1 /* 2 * 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2007 Intel Corporation 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 * Authors: 25 * Yaozu (Eddie) Dong <Eddie.dong@intel.com> 26 * Port from Qemu. 27 */ 28 #include <linux/mm.h> 29 #include <linux/bitops.h> 30 #include "irq.h" 31 32 #include <linux/kvm_host.h> 33 #include "trace.h" 34 35 static void pic_clear_isr(struct kvm_kpic_state *s, int irq) 36 { 37 s->isr &= ~(1 << irq); 38 s->isr_ack |= (1 << irq); 39 if (s != &s->pics_state->pics[0]) 40 irq += 8; 41 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq); 42 } 43 44 void kvm_pic_clear_isr_ack(struct kvm *kvm) 45 { 46 struct kvm_pic *s = pic_irqchip(kvm); 47 spin_lock(&s->lock); 48 s->pics[0].isr_ack = 0xff; 49 s->pics[1].isr_ack = 0xff; 50 spin_unlock(&s->lock); 51 } 52 53 /* 54 * set irq level. If an edge is detected, then the IRR is set to 1 55 */ 56 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) 57 { 58 int mask, ret = 1; 59 mask = 1 << irq; 60 if (s->elcr & mask) /* level triggered */ 61 if (level) { 62 ret = !(s->irr & mask); 63 s->irr |= mask; 64 s->last_irr |= mask; 65 } else { 66 s->irr &= ~mask; 67 s->last_irr &= ~mask; 68 } 69 else /* edge triggered */ 70 if (level) { 71 if ((s->last_irr & mask) == 0) { 72 ret = !(s->irr & mask); 73 s->irr |= mask; 74 } 75 s->last_irr |= mask; 76 } else 77 s->last_irr &= ~mask; 78 79 return (s->imr & mask) ? -1 : ret; 80 } 81 82 /* 83 * return the highest priority found in mask (highest = smallest 84 * number). Return 8 if no irq 85 */ 86 static inline int get_priority(struct kvm_kpic_state *s, int mask) 87 { 88 int priority; 89 if (mask == 0) 90 return 8; 91 priority = 0; 92 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 93 priority++; 94 return priority; 95 } 96 97 /* 98 * return the pic wanted interrupt. return -1 if none 99 */ 100 static int pic_get_irq(struct kvm_kpic_state *s) 101 { 102 int mask, cur_priority, priority; 103 104 mask = s->irr & ~s->imr; 105 priority = get_priority(s, mask); 106 if (priority == 8) 107 return -1; 108 /* 109 * compute current priority. If special fully nested mode on the 110 * master, the IRQ coming from the slave is not taken into account 111 * for the priority computation. 112 */ 113 mask = s->isr; 114 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 115 mask &= ~(1 << 2); 116 cur_priority = get_priority(s, mask); 117 if (priority < cur_priority) 118 /* 119 * higher priority found: an irq should be generated 120 */ 121 return (priority + s->priority_add) & 7; 122 else 123 return -1; 124 } 125 126 /* 127 * raise irq to CPU if necessary. must be called every time the active 128 * irq may change 129 */ 130 static void pic_update_irq(struct kvm_pic *s) 131 { 132 int irq2, irq; 133 134 irq2 = pic_get_irq(&s->pics[1]); 135 if (irq2 >= 0) { 136 /* 137 * if irq request by slave pic, signal master PIC 138 */ 139 pic_set_irq1(&s->pics[0], 2, 1); 140 pic_set_irq1(&s->pics[0], 2, 0); 141 } 142 irq = pic_get_irq(&s->pics[0]); 143 if (irq >= 0) 144 s->irq_request(s->irq_request_opaque, 1); 145 else 146 s->irq_request(s->irq_request_opaque, 0); 147 } 148 149 void kvm_pic_update_irq(struct kvm_pic *s) 150 { 151 spin_lock(&s->lock); 152 pic_update_irq(s); 153 spin_unlock(&s->lock); 154 } 155 156 int kvm_pic_set_irq(void *opaque, int irq, int level) 157 { 158 struct kvm_pic *s = opaque; 159 int ret = -1; 160 161 spin_lock(&s->lock); 162 if (irq >= 0 && irq < PIC_NUM_PINS) { 163 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 164 pic_update_irq(s); 165 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, 166 s->pics[irq >> 3].imr, ret == 0); 167 } 168 spin_unlock(&s->lock); 169 170 return ret; 171 } 172 173 /* 174 * acknowledge interrupt 'irq' 175 */ 176 static inline void pic_intack(struct kvm_kpic_state *s, int irq) 177 { 178 s->isr |= 1 << irq; 179 if (s->auto_eoi) { 180 if (s->rotate_on_auto_eoi) 181 s->priority_add = (irq + 1) & 7; 182 pic_clear_isr(s, irq); 183 } 184 /* 185 * We don't clear a level sensitive interrupt here 186 */ 187 if (!(s->elcr & (1 << irq))) 188 s->irr &= ~(1 << irq); 189 } 190 191 int kvm_pic_read_irq(struct kvm *kvm) 192 { 193 int irq, irq2, intno; 194 struct kvm_pic *s = pic_irqchip(kvm); 195 196 spin_lock(&s->lock); 197 irq = pic_get_irq(&s->pics[0]); 198 if (irq >= 0) { 199 pic_intack(&s->pics[0], irq); 200 if (irq == 2) { 201 irq2 = pic_get_irq(&s->pics[1]); 202 if (irq2 >= 0) 203 pic_intack(&s->pics[1], irq2); 204 else 205 /* 206 * spurious IRQ on slave controller 207 */ 208 irq2 = 7; 209 intno = s->pics[1].irq_base + irq2; 210 irq = irq2 + 8; 211 } else 212 intno = s->pics[0].irq_base + irq; 213 } else { 214 /* 215 * spurious IRQ on host controller 216 */ 217 irq = 7; 218 intno = s->pics[0].irq_base + irq; 219 } 220 pic_update_irq(s); 221 spin_unlock(&s->lock); 222 223 return intno; 224 } 225 226 void kvm_pic_reset(struct kvm_kpic_state *s) 227 { 228 int irq; 229 struct kvm *kvm = s->pics_state->irq_request_opaque; 230 struct kvm_vcpu *vcpu0 = kvm->bsp_vcpu; 231 u8 irr = s->irr, isr = s->imr; 232 233 s->last_irr = 0; 234 s->irr = 0; 235 s->imr = 0; 236 s->isr = 0; 237 s->isr_ack = 0xff; 238 s->priority_add = 0; 239 s->irq_base = 0; 240 s->read_reg_select = 0; 241 s->poll = 0; 242 s->special_mask = 0; 243 s->init_state = 0; 244 s->auto_eoi = 0; 245 s->rotate_on_auto_eoi = 0; 246 s->special_fully_nested_mode = 0; 247 s->init4 = 0; 248 249 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { 250 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) 251 if (irr & (1 << irq) || isr & (1 << irq)) { 252 pic_clear_isr(s, irq); 253 } 254 } 255 } 256 257 static void pic_ioport_write(void *opaque, u32 addr, u32 val) 258 { 259 struct kvm_kpic_state *s = opaque; 260 int priority, cmd, irq; 261 262 addr &= 1; 263 if (addr == 0) { 264 if (val & 0x10) { 265 kvm_pic_reset(s); /* init */ 266 /* 267 * deassert a pending interrupt 268 */ 269 s->pics_state->irq_request(s->pics_state-> 270 irq_request_opaque, 0); 271 s->init_state = 1; 272 s->init4 = val & 1; 273 if (val & 0x02) 274 printk(KERN_ERR "single mode not supported"); 275 if (val & 0x08) 276 printk(KERN_ERR 277 "level sensitive irq not supported"); 278 } else if (val & 0x08) { 279 if (val & 0x04) 280 s->poll = 1; 281 if (val & 0x02) 282 s->read_reg_select = val & 1; 283 if (val & 0x40) 284 s->special_mask = (val >> 5) & 1; 285 } else { 286 cmd = val >> 5; 287 switch (cmd) { 288 case 0: 289 case 4: 290 s->rotate_on_auto_eoi = cmd >> 2; 291 break; 292 case 1: /* end of interrupt */ 293 case 5: 294 priority = get_priority(s, s->isr); 295 if (priority != 8) { 296 irq = (priority + s->priority_add) & 7; 297 pic_clear_isr(s, irq); 298 if (cmd == 5) 299 s->priority_add = (irq + 1) & 7; 300 pic_update_irq(s->pics_state); 301 } 302 break; 303 case 3: 304 irq = val & 7; 305 pic_clear_isr(s, irq); 306 pic_update_irq(s->pics_state); 307 break; 308 case 6: 309 s->priority_add = (val + 1) & 7; 310 pic_update_irq(s->pics_state); 311 break; 312 case 7: 313 irq = val & 7; 314 s->priority_add = (irq + 1) & 7; 315 pic_clear_isr(s, irq); 316 pic_update_irq(s->pics_state); 317 break; 318 default: 319 break; /* no operation */ 320 } 321 } 322 } else 323 switch (s->init_state) { 324 case 0: /* normal mode */ 325 s->imr = val; 326 pic_update_irq(s->pics_state); 327 break; 328 case 1: 329 s->irq_base = val & 0xf8; 330 s->init_state = 2; 331 break; 332 case 2: 333 if (s->init4) 334 s->init_state = 3; 335 else 336 s->init_state = 0; 337 break; 338 case 3: 339 s->special_fully_nested_mode = (val >> 4) & 1; 340 s->auto_eoi = (val >> 1) & 1; 341 s->init_state = 0; 342 break; 343 } 344 } 345 346 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) 347 { 348 int ret; 349 350 ret = pic_get_irq(s); 351 if (ret >= 0) { 352 if (addr1 >> 7) { 353 s->pics_state->pics[0].isr &= ~(1 << 2); 354 s->pics_state->pics[0].irr &= ~(1 << 2); 355 } 356 s->irr &= ~(1 << ret); 357 pic_clear_isr(s, ret); 358 if (addr1 >> 7 || ret != 2) 359 pic_update_irq(s->pics_state); 360 } else { 361 ret = 0x07; 362 pic_update_irq(s->pics_state); 363 } 364 365 return ret; 366 } 367 368 static u32 pic_ioport_read(void *opaque, u32 addr1) 369 { 370 struct kvm_kpic_state *s = opaque; 371 unsigned int addr; 372 int ret; 373 374 addr = addr1; 375 addr &= 1; 376 if (s->poll) { 377 ret = pic_poll_read(s, addr1); 378 s->poll = 0; 379 } else 380 if (addr == 0) 381 if (s->read_reg_select) 382 ret = s->isr; 383 else 384 ret = s->irr; 385 else 386 ret = s->imr; 387 return ret; 388 } 389 390 static void elcr_ioport_write(void *opaque, u32 addr, u32 val) 391 { 392 struct kvm_kpic_state *s = opaque; 393 s->elcr = val & s->elcr_mask; 394 } 395 396 static u32 elcr_ioport_read(void *opaque, u32 addr1) 397 { 398 struct kvm_kpic_state *s = opaque; 399 return s->elcr; 400 } 401 402 static int picdev_in_range(gpa_t addr) 403 { 404 switch (addr) { 405 case 0x20: 406 case 0x21: 407 case 0xa0: 408 case 0xa1: 409 case 0x4d0: 410 case 0x4d1: 411 return 1; 412 default: 413 return 0; 414 } 415 } 416 417 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev) 418 { 419 return container_of(dev, struct kvm_pic, dev); 420 } 421 422 static int picdev_write(struct kvm_io_device *this, 423 gpa_t addr, int len, const void *val) 424 { 425 struct kvm_pic *s = to_pic(this); 426 unsigned char data = *(unsigned char *)val; 427 if (!picdev_in_range(addr)) 428 return -EOPNOTSUPP; 429 430 if (len != 1) { 431 if (printk_ratelimit()) 432 printk(KERN_ERR "PIC: non byte write\n"); 433 return 0; 434 } 435 spin_lock(&s->lock); 436 switch (addr) { 437 case 0x20: 438 case 0x21: 439 case 0xa0: 440 case 0xa1: 441 pic_ioport_write(&s->pics[addr >> 7], addr, data); 442 break; 443 case 0x4d0: 444 case 0x4d1: 445 elcr_ioport_write(&s->pics[addr & 1], addr, data); 446 break; 447 } 448 spin_unlock(&s->lock); 449 return 0; 450 } 451 452 static int picdev_read(struct kvm_io_device *this, 453 gpa_t addr, int len, void *val) 454 { 455 struct kvm_pic *s = to_pic(this); 456 unsigned char data = 0; 457 if (!picdev_in_range(addr)) 458 return -EOPNOTSUPP; 459 460 if (len != 1) { 461 if (printk_ratelimit()) 462 printk(KERN_ERR "PIC: non byte read\n"); 463 return 0; 464 } 465 spin_lock(&s->lock); 466 switch (addr) { 467 case 0x20: 468 case 0x21: 469 case 0xa0: 470 case 0xa1: 471 data = pic_ioport_read(&s->pics[addr >> 7], addr); 472 break; 473 case 0x4d0: 474 case 0x4d1: 475 data = elcr_ioport_read(&s->pics[addr & 1], addr); 476 break; 477 } 478 *(unsigned char *)val = data; 479 spin_unlock(&s->lock); 480 return 0; 481 } 482 483 /* 484 * callback when PIC0 irq status changed 485 */ 486 static void pic_irq_request(void *opaque, int level) 487 { 488 struct kvm *kvm = opaque; 489 struct kvm_vcpu *vcpu = kvm->bsp_vcpu; 490 struct kvm_pic *s = pic_irqchip(kvm); 491 int irq = pic_get_irq(&s->pics[0]); 492 493 s->output = level; 494 if (vcpu && level && (s->pics[0].isr_ack & (1 << irq))) { 495 s->pics[0].isr_ack &= ~(1 << irq); 496 kvm_vcpu_kick(vcpu); 497 } 498 } 499 500 static const struct kvm_io_device_ops picdev_ops = { 501 .read = picdev_read, 502 .write = picdev_write, 503 }; 504 505 struct kvm_pic *kvm_create_pic(struct kvm *kvm) 506 { 507 struct kvm_pic *s; 508 int ret; 509 510 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); 511 if (!s) 512 return NULL; 513 spin_lock_init(&s->lock); 514 s->kvm = kvm; 515 s->pics[0].elcr_mask = 0xf8; 516 s->pics[1].elcr_mask = 0xde; 517 s->irq_request = pic_irq_request; 518 s->irq_request_opaque = kvm; 519 s->pics[0].pics_state = s; 520 s->pics[1].pics_state = s; 521 522 /* 523 * Initialize PIO device 524 */ 525 kvm_iodevice_init(&s->dev, &picdev_ops); 526 ret = kvm_io_bus_register_dev(kvm, &kvm->pio_bus, &s->dev); 527 if (ret < 0) { 528 kfree(s); 529 return NULL; 530 } 531 532 return s; 533 } 534