1 /* 2 * 8259 interrupt controller emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2007 Intel Corporation 6 * Copyright 2009 Red Hat, Inc. and/or its affiliates. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * Authors: 26 * Yaozu (Eddie) Dong <Eddie.dong@intel.com> 27 * Port from Qemu. 28 */ 29 #include <linux/mm.h> 30 #include <linux/slab.h> 31 #include <linux/bitops.h> 32 #include "irq.h" 33 34 #include <linux/kvm_host.h> 35 #include "trace.h" 36 37 static void pic_irq_request(struct kvm *kvm, int level); 38 39 static void pic_lock(struct kvm_pic *s) 40 __acquires(&s->lock) 41 { 42 spin_lock(&s->lock); 43 } 44 45 static void pic_unlock(struct kvm_pic *s) 46 __releases(&s->lock) 47 { 48 bool wakeup = s->wakeup_needed; 49 struct kvm_vcpu *vcpu, *found = NULL; 50 int i; 51 52 s->wakeup_needed = false; 53 54 spin_unlock(&s->lock); 55 56 if (wakeup) { 57 kvm_for_each_vcpu(i, vcpu, s->kvm) { 58 if (kvm_apic_accept_pic_intr(vcpu)) { 59 found = vcpu; 60 break; 61 } 62 } 63 64 if (!found) 65 return; 66 67 kvm_make_request(KVM_REQ_EVENT, found); 68 kvm_vcpu_kick(found); 69 } 70 } 71 72 static void pic_clear_isr(struct kvm_kpic_state *s, int irq) 73 { 74 s->isr &= ~(1 << irq); 75 if (s != &s->pics_state->pics[0]) 76 irq += 8; 77 /* 78 * We are dropping lock while calling ack notifiers since ack 79 * notifier callbacks for assigned devices call into PIC recursively. 80 * Other interrupt may be delivered to PIC while lock is dropped but 81 * it should be safe since PIC state is already updated at this stage. 82 */ 83 pic_unlock(s->pics_state); 84 kvm_notify_acked_irq(s->pics_state->kvm, SELECT_PIC(irq), irq); 85 pic_lock(s->pics_state); 86 } 87 88 /* 89 * set irq level. If an edge is detected, then the IRR is set to 1 90 */ 91 static inline int pic_set_irq1(struct kvm_kpic_state *s, int irq, int level) 92 { 93 int mask, ret = 1; 94 mask = 1 << irq; 95 if (s->elcr & mask) /* level triggered */ 96 if (level) { 97 ret = !(s->irr & mask); 98 s->irr |= mask; 99 s->last_irr |= mask; 100 } else { 101 s->irr &= ~mask; 102 s->last_irr &= ~mask; 103 } 104 else /* edge triggered */ 105 if (level) { 106 if ((s->last_irr & mask) == 0) { 107 ret = !(s->irr & mask); 108 s->irr |= mask; 109 } 110 s->last_irr |= mask; 111 } else 112 s->last_irr &= ~mask; 113 114 return (s->imr & mask) ? -1 : ret; 115 } 116 117 /* 118 * return the highest priority found in mask (highest = smallest 119 * number). Return 8 if no irq 120 */ 121 static inline int get_priority(struct kvm_kpic_state *s, int mask) 122 { 123 int priority; 124 if (mask == 0) 125 return 8; 126 priority = 0; 127 while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0) 128 priority++; 129 return priority; 130 } 131 132 /* 133 * return the pic wanted interrupt. return -1 if none 134 */ 135 static int pic_get_irq(struct kvm_kpic_state *s) 136 { 137 int mask, cur_priority, priority; 138 139 mask = s->irr & ~s->imr; 140 priority = get_priority(s, mask); 141 if (priority == 8) 142 return -1; 143 /* 144 * compute current priority. If special fully nested mode on the 145 * master, the IRQ coming from the slave is not taken into account 146 * for the priority computation. 147 */ 148 mask = s->isr; 149 if (s->special_fully_nested_mode && s == &s->pics_state->pics[0]) 150 mask &= ~(1 << 2); 151 cur_priority = get_priority(s, mask); 152 if (priority < cur_priority) 153 /* 154 * higher priority found: an irq should be generated 155 */ 156 return (priority + s->priority_add) & 7; 157 else 158 return -1; 159 } 160 161 /* 162 * raise irq to CPU if necessary. must be called every time the active 163 * irq may change 164 */ 165 static void pic_update_irq(struct kvm_pic *s) 166 { 167 int irq2, irq; 168 169 irq2 = pic_get_irq(&s->pics[1]); 170 if (irq2 >= 0) { 171 /* 172 * if irq request by slave pic, signal master PIC 173 */ 174 pic_set_irq1(&s->pics[0], 2, 1); 175 pic_set_irq1(&s->pics[0], 2, 0); 176 } 177 irq = pic_get_irq(&s->pics[0]); 178 pic_irq_request(s->kvm, irq >= 0); 179 } 180 181 void kvm_pic_update_irq(struct kvm_pic *s) 182 { 183 pic_lock(s); 184 pic_update_irq(s); 185 pic_unlock(s); 186 } 187 188 int kvm_pic_set_irq(void *opaque, int irq, int level) 189 { 190 struct kvm_pic *s = opaque; 191 int ret = -1; 192 193 pic_lock(s); 194 if (irq >= 0 && irq < PIC_NUM_PINS) { 195 ret = pic_set_irq1(&s->pics[irq >> 3], irq & 7, level); 196 pic_update_irq(s); 197 trace_kvm_pic_set_irq(irq >> 3, irq & 7, s->pics[irq >> 3].elcr, 198 s->pics[irq >> 3].imr, ret == 0); 199 } 200 pic_unlock(s); 201 202 return ret; 203 } 204 205 /* 206 * acknowledge interrupt 'irq' 207 */ 208 static inline void pic_intack(struct kvm_kpic_state *s, int irq) 209 { 210 s->isr |= 1 << irq; 211 /* 212 * We don't clear a level sensitive interrupt here 213 */ 214 if (!(s->elcr & (1 << irq))) 215 s->irr &= ~(1 << irq); 216 217 if (s->auto_eoi) { 218 if (s->rotate_on_auto_eoi) 219 s->priority_add = (irq + 1) & 7; 220 pic_clear_isr(s, irq); 221 } 222 223 } 224 225 int kvm_pic_read_irq(struct kvm *kvm) 226 { 227 int irq, irq2, intno; 228 struct kvm_pic *s = pic_irqchip(kvm); 229 230 pic_lock(s); 231 irq = pic_get_irq(&s->pics[0]); 232 if (irq >= 0) { 233 pic_intack(&s->pics[0], irq); 234 if (irq == 2) { 235 irq2 = pic_get_irq(&s->pics[1]); 236 if (irq2 >= 0) 237 pic_intack(&s->pics[1], irq2); 238 else 239 /* 240 * spurious IRQ on slave controller 241 */ 242 irq2 = 7; 243 intno = s->pics[1].irq_base + irq2; 244 irq = irq2 + 8; 245 } else 246 intno = s->pics[0].irq_base + irq; 247 } else { 248 /* 249 * spurious IRQ on host controller 250 */ 251 irq = 7; 252 intno = s->pics[0].irq_base + irq; 253 } 254 pic_update_irq(s); 255 pic_unlock(s); 256 257 return intno; 258 } 259 260 void kvm_pic_reset(struct kvm_kpic_state *s) 261 { 262 int irq; 263 struct kvm_vcpu *vcpu0 = s->pics_state->kvm->bsp_vcpu; 264 u8 irr = s->irr, isr = s->imr; 265 266 s->last_irr = 0; 267 s->irr = 0; 268 s->imr = 0; 269 s->isr = 0; 270 s->priority_add = 0; 271 s->irq_base = 0; 272 s->read_reg_select = 0; 273 s->poll = 0; 274 s->special_mask = 0; 275 s->init_state = 0; 276 s->auto_eoi = 0; 277 s->rotate_on_auto_eoi = 0; 278 s->special_fully_nested_mode = 0; 279 s->init4 = 0; 280 281 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) { 282 if (vcpu0 && kvm_apic_accept_pic_intr(vcpu0)) 283 if (irr & (1 << irq) || isr & (1 << irq)) { 284 pic_clear_isr(s, irq); 285 } 286 } 287 } 288 289 static void pic_ioport_write(void *opaque, u32 addr, u32 val) 290 { 291 struct kvm_kpic_state *s = opaque; 292 int priority, cmd, irq; 293 294 addr &= 1; 295 if (addr == 0) { 296 if (val & 0x10) { 297 s->init4 = val & 1; 298 s->last_irr = 0; 299 s->imr = 0; 300 s->priority_add = 0; 301 s->special_mask = 0; 302 s->read_reg_select = 0; 303 if (!s->init4) { 304 s->special_fully_nested_mode = 0; 305 s->auto_eoi = 0; 306 } 307 s->init_state = 1; 308 if (val & 0x02) 309 printk(KERN_ERR "single mode not supported"); 310 if (val & 0x08) 311 printk(KERN_ERR 312 "level sensitive irq not supported"); 313 } else if (val & 0x08) { 314 if (val & 0x04) 315 s->poll = 1; 316 if (val & 0x02) 317 s->read_reg_select = val & 1; 318 if (val & 0x40) 319 s->special_mask = (val >> 5) & 1; 320 } else { 321 cmd = val >> 5; 322 switch (cmd) { 323 case 0: 324 case 4: 325 s->rotate_on_auto_eoi = cmd >> 2; 326 break; 327 case 1: /* end of interrupt */ 328 case 5: 329 priority = get_priority(s, s->isr); 330 if (priority != 8) { 331 irq = (priority + s->priority_add) & 7; 332 if (cmd == 5) 333 s->priority_add = (irq + 1) & 7; 334 pic_clear_isr(s, irq); 335 pic_update_irq(s->pics_state); 336 } 337 break; 338 case 3: 339 irq = val & 7; 340 pic_clear_isr(s, irq); 341 pic_update_irq(s->pics_state); 342 break; 343 case 6: 344 s->priority_add = (val + 1) & 7; 345 pic_update_irq(s->pics_state); 346 break; 347 case 7: 348 irq = val & 7; 349 s->priority_add = (irq + 1) & 7; 350 pic_clear_isr(s, irq); 351 pic_update_irq(s->pics_state); 352 break; 353 default: 354 break; /* no operation */ 355 } 356 } 357 } else 358 switch (s->init_state) { 359 case 0: { /* normal mode */ 360 u8 imr_diff = s->imr ^ val, 361 off = (s == &s->pics_state->pics[0]) ? 0 : 8; 362 s->imr = val; 363 for (irq = 0; irq < PIC_NUM_PINS/2; irq++) 364 if (imr_diff & (1 << irq)) 365 kvm_fire_mask_notifiers( 366 s->pics_state->kvm, 367 SELECT_PIC(irq + off), 368 irq + off, 369 !!(s->imr & (1 << irq))); 370 pic_update_irq(s->pics_state); 371 break; 372 } 373 case 1: 374 s->irq_base = val & 0xf8; 375 s->init_state = 2; 376 break; 377 case 2: 378 if (s->init4) 379 s->init_state = 3; 380 else 381 s->init_state = 0; 382 break; 383 case 3: 384 s->special_fully_nested_mode = (val >> 4) & 1; 385 s->auto_eoi = (val >> 1) & 1; 386 s->init_state = 0; 387 break; 388 } 389 } 390 391 static u32 pic_poll_read(struct kvm_kpic_state *s, u32 addr1) 392 { 393 int ret; 394 395 ret = pic_get_irq(s); 396 if (ret >= 0) { 397 if (addr1 >> 7) { 398 s->pics_state->pics[0].isr &= ~(1 << 2); 399 s->pics_state->pics[0].irr &= ~(1 << 2); 400 } 401 s->irr &= ~(1 << ret); 402 pic_clear_isr(s, ret); 403 if (addr1 >> 7 || ret != 2) 404 pic_update_irq(s->pics_state); 405 } else { 406 ret = 0x07; 407 pic_update_irq(s->pics_state); 408 } 409 410 return ret; 411 } 412 413 static u32 pic_ioport_read(void *opaque, u32 addr1) 414 { 415 struct kvm_kpic_state *s = opaque; 416 unsigned int addr; 417 int ret; 418 419 addr = addr1; 420 addr &= 1; 421 if (s->poll) { 422 ret = pic_poll_read(s, addr1); 423 s->poll = 0; 424 } else 425 if (addr == 0) 426 if (s->read_reg_select) 427 ret = s->isr; 428 else 429 ret = s->irr; 430 else 431 ret = s->imr; 432 return ret; 433 } 434 435 static void elcr_ioport_write(void *opaque, u32 addr, u32 val) 436 { 437 struct kvm_kpic_state *s = opaque; 438 s->elcr = val & s->elcr_mask; 439 } 440 441 static u32 elcr_ioport_read(void *opaque, u32 addr1) 442 { 443 struct kvm_kpic_state *s = opaque; 444 return s->elcr; 445 } 446 447 static int picdev_in_range(gpa_t addr) 448 { 449 switch (addr) { 450 case 0x20: 451 case 0x21: 452 case 0xa0: 453 case 0xa1: 454 case 0x4d0: 455 case 0x4d1: 456 return 1; 457 default: 458 return 0; 459 } 460 } 461 462 static inline struct kvm_pic *to_pic(struct kvm_io_device *dev) 463 { 464 return container_of(dev, struct kvm_pic, dev); 465 } 466 467 static int picdev_write(struct kvm_io_device *this, 468 gpa_t addr, int len, const void *val) 469 { 470 struct kvm_pic *s = to_pic(this); 471 unsigned char data = *(unsigned char *)val; 472 if (!picdev_in_range(addr)) 473 return -EOPNOTSUPP; 474 475 if (len != 1) { 476 if (printk_ratelimit()) 477 printk(KERN_ERR "PIC: non byte write\n"); 478 return 0; 479 } 480 pic_lock(s); 481 switch (addr) { 482 case 0x20: 483 case 0x21: 484 case 0xa0: 485 case 0xa1: 486 pic_ioport_write(&s->pics[addr >> 7], addr, data); 487 break; 488 case 0x4d0: 489 case 0x4d1: 490 elcr_ioport_write(&s->pics[addr & 1], addr, data); 491 break; 492 } 493 pic_unlock(s); 494 return 0; 495 } 496 497 static int picdev_read(struct kvm_io_device *this, 498 gpa_t addr, int len, void *val) 499 { 500 struct kvm_pic *s = to_pic(this); 501 unsigned char data = 0; 502 if (!picdev_in_range(addr)) 503 return -EOPNOTSUPP; 504 505 if (len != 1) { 506 if (printk_ratelimit()) 507 printk(KERN_ERR "PIC: non byte read\n"); 508 return 0; 509 } 510 pic_lock(s); 511 switch (addr) { 512 case 0x20: 513 case 0x21: 514 case 0xa0: 515 case 0xa1: 516 data = pic_ioport_read(&s->pics[addr >> 7], addr); 517 break; 518 case 0x4d0: 519 case 0x4d1: 520 data = elcr_ioport_read(&s->pics[addr & 1], addr); 521 break; 522 } 523 *(unsigned char *)val = data; 524 pic_unlock(s); 525 return 0; 526 } 527 528 /* 529 * callback when PIC0 irq status changed 530 */ 531 static void pic_irq_request(struct kvm *kvm, int level) 532 { 533 struct kvm_pic *s = pic_irqchip(kvm); 534 535 if (!s->output) 536 s->wakeup_needed = true; 537 s->output = level; 538 } 539 540 static const struct kvm_io_device_ops picdev_ops = { 541 .read = picdev_read, 542 .write = picdev_write, 543 }; 544 545 struct kvm_pic *kvm_create_pic(struct kvm *kvm) 546 { 547 struct kvm_pic *s; 548 int ret; 549 550 s = kzalloc(sizeof(struct kvm_pic), GFP_KERNEL); 551 if (!s) 552 return NULL; 553 spin_lock_init(&s->lock); 554 s->kvm = kvm; 555 s->pics[0].elcr_mask = 0xf8; 556 s->pics[1].elcr_mask = 0xde; 557 s->pics[0].pics_state = s; 558 s->pics[1].pics_state = s; 559 560 /* 561 * Initialize PIO device 562 */ 563 kvm_iodevice_init(&s->dev, &picdev_ops); 564 mutex_lock(&kvm->slots_lock); 565 ret = kvm_io_bus_register_dev(kvm, KVM_PIO_BUS, &s->dev); 566 mutex_unlock(&kvm->slots_lock); 567 if (ret < 0) { 568 kfree(s); 569 return NULL; 570 } 571 572 return s; 573 } 574 575 void kvm_destroy_pic(struct kvm *kvm) 576 { 577 struct kvm_pic *vpic = kvm->arch.vpic; 578 579 if (vpic) { 580 kvm_io_bus_unregister_dev(kvm, KVM_PIO_BUS, &vpic->dev); 581 kvm->arch.vpic = NULL; 582 kfree(vpic); 583 } 584 } 585