1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kvm_host.h> 14 #include <linux/export.h> 15 #include <linux/vmalloc.h> 16 #include <linux/uaccess.h> 17 #include <linux/sched/stat.h> 18 19 #include <asm/processor.h> 20 #include <asm/user.h> 21 #include <asm/fpu/xstate.h> 22 #include <asm/sgx.h> 23 #include <asm/cpuid.h> 24 #include "cpuid.h" 25 #include "lapic.h" 26 #include "mmu.h" 27 #include "trace.h" 28 #include "pmu.h" 29 #include "xen.h" 30 31 /* 32 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 33 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 34 */ 35 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 36 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 37 38 u32 xstate_required_size(u64 xstate_bv, bool compacted) 39 { 40 int feature_bit = 0; 41 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 42 43 xstate_bv &= XFEATURE_MASK_EXTEND; 44 while (xstate_bv) { 45 if (xstate_bv & 0x1) { 46 u32 eax, ebx, ecx, edx, offset; 47 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 48 /* ECX[1]: 64B alignment in compacted form */ 49 if (compacted) 50 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 51 else 52 offset = ebx; 53 ret = max(ret, offset + eax); 54 } 55 56 xstate_bv >>= 1; 57 feature_bit++; 58 } 59 60 return ret; 61 } 62 63 #define F feature_bit 64 65 /* Scattered Flag - For features that are scattered by cpufeatures.h. */ 66 #define SF(name) \ 67 ({ \ 68 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 69 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ 70 }) 71 72 /* 73 * Magic value used by KVM when querying userspace-provided CPUID entries and 74 * doesn't care about the CPIUD index because the index of the function in 75 * question is not significant. Note, this magic value must have at least one 76 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 77 * to avoid false positives when processing guest CPUID input. 78 */ 79 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 80 81 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 82 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 83 { 84 struct kvm_cpuid_entry2 *e; 85 int i; 86 87 for (i = 0; i < nent; i++) { 88 e = &entries[i]; 89 90 if (e->function != function) 91 continue; 92 93 /* 94 * If the index isn't significant, use the first entry with a 95 * matching function. It's userspace's responsibilty to not 96 * provide "duplicate" entries in all cases. 97 */ 98 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 99 return e; 100 101 102 /* 103 * Similarly, use the first matching entry if KVM is doing a 104 * lookup (as opposed to emulating CPUID) for a function that's 105 * architecturally defined as not having a significant index. 106 */ 107 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 108 /* 109 * Direct lookups from KVM should not diverge from what 110 * KVM defines internally (the architectural behavior). 111 */ 112 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 113 return e; 114 } 115 } 116 117 return NULL; 118 } 119 120 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 121 struct kvm_cpuid_entry2 *entries, 122 int nent) 123 { 124 struct kvm_cpuid_entry2 *best; 125 u64 xfeatures; 126 127 /* 128 * The existing code assumes virtual address is 48-bit or 57-bit in the 129 * canonical address checks; exit if it is ever changed. 130 */ 131 best = cpuid_entry2_find(entries, nent, 0x80000008, 132 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 133 if (best) { 134 int vaddr_bits = (best->eax & 0xff00) >> 8; 135 136 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 137 return -EINVAL; 138 } 139 140 /* 141 * Exposing dynamic xfeatures to the guest requires additional 142 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 143 */ 144 best = cpuid_entry2_find(entries, nent, 0xd, 0); 145 if (!best) 146 return 0; 147 148 xfeatures = best->eax | ((u64)best->edx << 32); 149 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 150 if (!xfeatures) 151 return 0; 152 153 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 154 } 155 156 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 157 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 158 int nent) 159 { 160 struct kvm_cpuid_entry2 *orig; 161 int i; 162 163 if (nent != vcpu->arch.cpuid_nent) 164 return -EINVAL; 165 166 for (i = 0; i < nent; i++) { 167 orig = &vcpu->arch.cpuid_entries[i]; 168 if (e2[i].function != orig->function || 169 e2[i].index != orig->index || 170 e2[i].flags != orig->flags || 171 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 172 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 173 return -EINVAL; 174 } 175 176 return 0; 177 } 178 179 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 180 const char *sig) 181 { 182 struct kvm_hypervisor_cpuid cpuid = {}; 183 struct kvm_cpuid_entry2 *entry; 184 u32 base; 185 186 for_each_possible_hypervisor_cpuid_base(base) { 187 entry = kvm_find_cpuid_entry(vcpu, base); 188 189 if (entry) { 190 u32 signature[3]; 191 192 signature[0] = entry->ebx; 193 signature[1] = entry->ecx; 194 signature[2] = entry->edx; 195 196 if (!memcmp(signature, sig, sizeof(signature))) { 197 cpuid.base = base; 198 cpuid.limit = entry->eax; 199 break; 200 } 201 } 202 } 203 204 return cpuid; 205 } 206 207 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 208 struct kvm_cpuid_entry2 *entries, int nent) 209 { 210 u32 base = vcpu->arch.kvm_cpuid.base; 211 212 if (!base) 213 return NULL; 214 215 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 216 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 217 } 218 219 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 220 { 221 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 222 vcpu->arch.cpuid_nent); 223 } 224 225 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 226 { 227 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 228 229 /* 230 * save the feature bitmap to avoid cpuid lookup for every PV 231 * operation 232 */ 233 if (best) 234 vcpu->arch.pv_cpuid.features = best->eax; 235 } 236 237 /* 238 * Calculate guest's supported XCR0 taking into account guest CPUID data and 239 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 240 */ 241 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 242 { 243 struct kvm_cpuid_entry2 *best; 244 245 best = cpuid_entry2_find(entries, nent, 0xd, 0); 246 if (!best) 247 return 0; 248 249 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 250 } 251 252 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 253 int nent) 254 { 255 struct kvm_cpuid_entry2 *best; 256 257 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 258 if (best) { 259 /* Update OSXSAVE bit */ 260 if (boot_cpu_has(X86_FEATURE_XSAVE)) 261 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 262 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 263 264 cpuid_entry_change(best, X86_FEATURE_APIC, 265 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 266 } 267 268 best = cpuid_entry2_find(entries, nent, 7, 0); 269 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 270 cpuid_entry_change(best, X86_FEATURE_OSPKE, 271 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 272 273 best = cpuid_entry2_find(entries, nent, 0xD, 0); 274 if (best) 275 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 276 277 best = cpuid_entry2_find(entries, nent, 0xD, 1); 278 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 279 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 280 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 281 282 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 283 if (kvm_hlt_in_guest(vcpu->kvm) && best && 284 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 285 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 286 287 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 288 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 289 if (best) 290 cpuid_entry_change(best, X86_FEATURE_MWAIT, 291 vcpu->arch.ia32_misc_enable_msr & 292 MSR_IA32_MISC_ENABLE_MWAIT); 293 } 294 } 295 296 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 297 { 298 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 299 } 300 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 301 302 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) 303 { 304 struct kvm_cpuid_entry2 *entry; 305 306 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, 307 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 308 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 309 } 310 311 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 312 { 313 struct kvm_lapic *apic = vcpu->arch.apic; 314 struct kvm_cpuid_entry2 *best; 315 316 best = kvm_find_cpuid_entry(vcpu, 1); 317 if (best && apic) { 318 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 319 apic->lapic_timer.timer_mode_mask = 3 << 17; 320 else 321 apic->lapic_timer.timer_mode_mask = 1 << 17; 322 323 kvm_apic_set_version(vcpu); 324 } 325 326 vcpu->arch.guest_supported_xcr0 = 327 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 328 329 /* 330 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if 331 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't 332 * supported by the host. 333 */ 334 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 | 335 XFEATURE_MASK_FPSSE; 336 337 kvm_update_pv_runtime(vcpu); 338 339 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 340 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 341 342 kvm_pmu_refresh(vcpu); 343 vcpu->arch.cr4_guest_rsvd_bits = 344 __cr4_reserved_bits(guest_cpuid_has, vcpu); 345 346 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, 347 vcpu->arch.cpuid_nent)); 348 349 /* Invoke the vendor callback only after the above state is updated. */ 350 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 351 352 /* 353 * Except for the MMU, which needs to do its thing any vendor specific 354 * adjustments to the reserved GPA bits. 355 */ 356 kvm_mmu_after_set_cpuid(vcpu); 357 } 358 359 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 360 { 361 struct kvm_cpuid_entry2 *best; 362 363 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 364 if (!best || best->eax < 0x80000008) 365 goto not_found; 366 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 367 if (best) 368 return best->eax & 0xff; 369 not_found: 370 return 36; 371 } 372 373 /* 374 * This "raw" version returns the reserved GPA bits without any adjustments for 375 * encryption technologies that usurp bits. The raw mask should be used if and 376 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 377 */ 378 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 379 { 380 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 381 } 382 383 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 384 int nent) 385 { 386 int r; 387 388 __kvm_update_cpuid_runtime(vcpu, e2, nent); 389 390 /* 391 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 392 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 393 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 394 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 395 * the core vCPU model on the fly. It would've been better to forbid any 396 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 397 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 398 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 399 * whether the supplied CPUID data is equal to what's already set. 400 */ 401 if (kvm_vcpu_has_run(vcpu)) { 402 r = kvm_cpuid_check_equal(vcpu, e2, nent); 403 if (r) 404 return r; 405 406 kvfree(e2); 407 return 0; 408 } 409 410 if (kvm_cpuid_has_hyperv(e2, nent)) { 411 r = kvm_hv_vcpu_init(vcpu); 412 if (r) 413 return r; 414 } 415 416 r = kvm_check_cpuid(vcpu, e2, nent); 417 if (r) 418 return r; 419 420 kvfree(vcpu->arch.cpuid_entries); 421 vcpu->arch.cpuid_entries = e2; 422 vcpu->arch.cpuid_nent = nent; 423 424 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 425 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 426 kvm_vcpu_after_set_cpuid(vcpu); 427 428 return 0; 429 } 430 431 /* when an old userspace process fills a new kernel module */ 432 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 433 struct kvm_cpuid *cpuid, 434 struct kvm_cpuid_entry __user *entries) 435 { 436 int r, i; 437 struct kvm_cpuid_entry *e = NULL; 438 struct kvm_cpuid_entry2 *e2 = NULL; 439 440 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 441 return -E2BIG; 442 443 if (cpuid->nent) { 444 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 445 if (IS_ERR(e)) 446 return PTR_ERR(e); 447 448 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 449 if (!e2) { 450 r = -ENOMEM; 451 goto out_free_cpuid; 452 } 453 } 454 for (i = 0; i < cpuid->nent; i++) { 455 e2[i].function = e[i].function; 456 e2[i].eax = e[i].eax; 457 e2[i].ebx = e[i].ebx; 458 e2[i].ecx = e[i].ecx; 459 e2[i].edx = e[i].edx; 460 e2[i].index = 0; 461 e2[i].flags = 0; 462 e2[i].padding[0] = 0; 463 e2[i].padding[1] = 0; 464 e2[i].padding[2] = 0; 465 } 466 467 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 468 if (r) 469 kvfree(e2); 470 471 out_free_cpuid: 472 kvfree(e); 473 474 return r; 475 } 476 477 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 478 struct kvm_cpuid2 *cpuid, 479 struct kvm_cpuid_entry2 __user *entries) 480 { 481 struct kvm_cpuid_entry2 *e2 = NULL; 482 int r; 483 484 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 485 return -E2BIG; 486 487 if (cpuid->nent) { 488 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 489 if (IS_ERR(e2)) 490 return PTR_ERR(e2); 491 } 492 493 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 494 if (r) 495 kvfree(e2); 496 497 return r; 498 } 499 500 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 501 struct kvm_cpuid2 *cpuid, 502 struct kvm_cpuid_entry2 __user *entries) 503 { 504 int r; 505 506 r = -E2BIG; 507 if (cpuid->nent < vcpu->arch.cpuid_nent) 508 goto out; 509 r = -EFAULT; 510 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 511 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 512 goto out; 513 return 0; 514 515 out: 516 cpuid->nent = vcpu->arch.cpuid_nent; 517 return r; 518 } 519 520 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 521 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 522 { 523 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 524 struct kvm_cpuid_entry2 entry; 525 526 reverse_cpuid_check(leaf); 527 528 cpuid_count(cpuid.function, cpuid.index, 529 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 530 531 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 532 } 533 534 static __always_inline 535 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) 536 { 537 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ 538 BUILD_BUG_ON(leaf < NCAPINTS); 539 540 kvm_cpu_caps[leaf] = mask; 541 542 __kvm_cpu_cap_mask(leaf); 543 } 544 545 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 546 { 547 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ 548 BUILD_BUG_ON(leaf >= NCAPINTS); 549 550 kvm_cpu_caps[leaf] &= mask; 551 552 __kvm_cpu_cap_mask(leaf); 553 } 554 555 void kvm_set_cpu_caps(void) 556 { 557 #ifdef CONFIG_X86_64 558 unsigned int f_gbpages = F(GBPAGES); 559 unsigned int f_lm = F(LM); 560 unsigned int f_xfd = F(XFD); 561 #else 562 unsigned int f_gbpages = 0; 563 unsigned int f_lm = 0; 564 unsigned int f_xfd = 0; 565 #endif 566 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 567 568 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 569 sizeof(boot_cpu_data.x86_capability)); 570 571 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 572 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 573 574 kvm_cpu_cap_mask(CPUID_1_ECX, 575 /* 576 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 577 * advertised to guests via CPUID! 578 */ 579 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 580 0 /* DS-CPL, VMX, SMX, EST */ | 581 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 582 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 583 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 584 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 585 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 586 F(F16C) | F(RDRAND) 587 ); 588 /* KVM emulates x2apic in software irrespective of host support. */ 589 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 590 591 kvm_cpu_cap_mask(CPUID_1_EDX, 592 F(FPU) | F(VME) | F(DE) | F(PSE) | 593 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 594 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 595 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 596 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 597 0 /* Reserved, DS, ACPI */ | F(MMX) | 598 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 599 0 /* HTT, TM, Reserved, PBE */ 600 ); 601 602 kvm_cpu_cap_mask(CPUID_7_0_EBX, 603 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 604 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 605 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 606 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 607 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 608 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 609 F(AVX512VL)); 610 611 kvm_cpu_cap_mask(CPUID_7_ECX, 612 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 613 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 614 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 615 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 616 F(SGX_LC) | F(BUS_LOCK_DETECT) 617 ); 618 /* Set LA57 based on hardware capability. */ 619 if (cpuid_ecx(7) & F(LA57)) 620 kvm_cpu_cap_set(X86_FEATURE_LA57); 621 622 /* 623 * PKU not yet implemented for shadow paging and requires OSPKE 624 * to be set on the host. Clear it if that is not the case 625 */ 626 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 627 kvm_cpu_cap_clear(X86_FEATURE_PKU); 628 629 kvm_cpu_cap_mask(CPUID_7_EDX, 630 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 631 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 632 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 633 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 634 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) 635 ); 636 637 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 638 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 639 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 640 641 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 642 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 643 if (boot_cpu_has(X86_FEATURE_STIBP)) 644 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 645 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 646 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 647 648 kvm_cpu_cap_mask(CPUID_7_1_EAX, 649 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | 650 F(FZRM) | F(FSRS) | F(FSRC) | 651 F(AMX_FP16) | F(AVX_IFMA) 652 ); 653 654 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, 655 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) 656 ); 657 658 kvm_cpu_cap_mask(CPUID_D_1_EAX, 659 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 660 ); 661 662 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, 663 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) 664 ); 665 666 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 667 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 668 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 669 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 670 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 671 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 672 ); 673 674 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 675 F(FPU) | F(VME) | F(DE) | F(PSE) | 676 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 677 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 678 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 679 F(PAT) | F(PSE36) | 0 /* Reserved */ | 680 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 681 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 682 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 683 ); 684 685 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 686 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 687 688 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, 689 SF(CONSTANT_TSC) 690 ); 691 692 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 693 F(CLZERO) | F(XSAVEERPTR) | 694 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 695 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 696 F(AMD_PSFD) 697 ); 698 699 /* 700 * AMD has separate bits for each SPEC_CTRL bit. 701 * arch/x86/kernel/cpu/bugs.c is kind enough to 702 * record that in cpufeatures so use them. 703 */ 704 if (boot_cpu_has(X86_FEATURE_IBPB)) 705 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 706 if (boot_cpu_has(X86_FEATURE_IBRS)) 707 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 708 if (boot_cpu_has(X86_FEATURE_STIBP)) 709 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 710 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 711 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 712 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 713 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 714 /* 715 * The preference is to use SPEC CTRL MSR instead of the 716 * VIRT_SPEC MSR. 717 */ 718 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 719 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 720 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 721 722 /* 723 * Hide all SVM features by default, SVM will set the cap bits for 724 * features it emulates and/or exposes for L1. 725 */ 726 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 727 728 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 729 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 730 F(SME_COHERENT)); 731 732 kvm_cpu_cap_mask(CPUID_8000_0021_EAX, 733 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | 734 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ 735 ); 736 737 /* 738 * Synthesize "LFENCE is serializing" into the AMD-defined entry in 739 * KVM's supported CPUID if the feature is reported as supported by the 740 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long 741 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most 742 * CPUs that support SSE2. On CPUs that don't support AMD's leaf, 743 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing 744 * the mask with the raw host CPUID, and reporting support in AMD's 745 * leaf can make it easier for userspace to detect the feature. 746 */ 747 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 748 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); 749 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 750 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 751 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); 752 753 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 754 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 755 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 756 F(PMM) | F(PMM_EN) 757 ); 758 759 /* 760 * Hide RDTSCP and RDPID if either feature is reported as supported but 761 * probing MSR_TSC_AUX failed. This is purely a sanity check and 762 * should never happen, but the guest will likely crash if RDTSCP or 763 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 764 * the past. For example, the sanity check may fire if this instance of 765 * KVM is running as L1 on top of an older, broken KVM. 766 */ 767 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 768 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 769 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 770 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 771 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 772 } 773 } 774 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 775 776 struct kvm_cpuid_array { 777 struct kvm_cpuid_entry2 *entries; 778 int maxnent; 779 int nent; 780 }; 781 782 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 783 { 784 if (array->nent >= array->maxnent) 785 return NULL; 786 787 return &array->entries[array->nent++]; 788 } 789 790 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 791 u32 function, u32 index) 792 { 793 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 794 795 if (!entry) 796 return NULL; 797 798 memset(entry, 0, sizeof(*entry)); 799 entry->function = function; 800 entry->index = index; 801 switch (function & 0xC0000000) { 802 case 0x40000000: 803 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 804 return entry; 805 806 case 0x80000000: 807 /* 808 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 809 * would result in out-of-bounds calls to do_host_cpuid. 810 */ 811 { 812 static int max_cpuid_80000000; 813 if (!READ_ONCE(max_cpuid_80000000)) 814 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 815 if (function > READ_ONCE(max_cpuid_80000000)) 816 return entry; 817 } 818 break; 819 820 default: 821 break; 822 } 823 824 cpuid_count(entry->function, entry->index, 825 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 826 827 if (cpuid_function_is_indexed(function)) 828 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 829 830 return entry; 831 } 832 833 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 834 { 835 struct kvm_cpuid_entry2 *entry; 836 837 if (array->nent >= array->maxnent) 838 return -E2BIG; 839 840 entry = &array->entries[array->nent]; 841 entry->function = func; 842 entry->index = 0; 843 entry->flags = 0; 844 845 switch (func) { 846 case 0: 847 entry->eax = 7; 848 ++array->nent; 849 break; 850 case 1: 851 entry->ecx = F(MOVBE); 852 ++array->nent; 853 break; 854 case 7: 855 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 856 entry->eax = 0; 857 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 858 entry->ecx = F(RDPID); 859 ++array->nent; 860 break; 861 default: 862 break; 863 } 864 865 return 0; 866 } 867 868 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 869 { 870 struct kvm_cpuid_entry2 *entry; 871 int r, i, max_idx; 872 873 /* all calls to cpuid_count() should be made on the same cpu */ 874 get_cpu(); 875 876 r = -E2BIG; 877 878 entry = do_host_cpuid(array, function, 0); 879 if (!entry) 880 goto out; 881 882 switch (function) { 883 case 0: 884 /* Limited to the highest leaf implemented in KVM. */ 885 entry->eax = min(entry->eax, 0x1fU); 886 break; 887 case 1: 888 cpuid_entry_override(entry, CPUID_1_EDX); 889 cpuid_entry_override(entry, CPUID_1_ECX); 890 break; 891 case 2: 892 /* 893 * On ancient CPUs, function 2 entries are STATEFUL. That is, 894 * CPUID(function=2, index=0) may return different results each 895 * time, with the least-significant byte in EAX enumerating the 896 * number of times software should do CPUID(2, 0). 897 * 898 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 899 * idiotic. Intel's SDM states that EAX & 0xff "will always 900 * return 01H. Software should ignore this value and not 901 * interpret it as an informational descriptor", while AMD's 902 * APM states that CPUID(2) is reserved. 903 * 904 * WARN if a frankenstein CPU that supports virtualization and 905 * a stateful CPUID.0x2 is encountered. 906 */ 907 WARN_ON_ONCE((entry->eax & 0xff) > 1); 908 break; 909 /* functions 4 and 0x8000001d have additional index. */ 910 case 4: 911 case 0x8000001d: 912 /* 913 * Read entries until the cache type in the previous entry is 914 * zero, i.e. indicates an invalid entry. 915 */ 916 for (i = 1; entry->eax & 0x1f; ++i) { 917 entry = do_host_cpuid(array, function, i); 918 if (!entry) 919 goto out; 920 } 921 break; 922 case 6: /* Thermal management */ 923 entry->eax = 0x4; /* allow ARAT */ 924 entry->ebx = 0; 925 entry->ecx = 0; 926 entry->edx = 0; 927 break; 928 /* function 7 has additional index. */ 929 case 7: 930 entry->eax = min(entry->eax, 1u); 931 cpuid_entry_override(entry, CPUID_7_0_EBX); 932 cpuid_entry_override(entry, CPUID_7_ECX); 933 cpuid_entry_override(entry, CPUID_7_EDX); 934 935 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 936 if (entry->eax == 1) { 937 entry = do_host_cpuid(array, function, 1); 938 if (!entry) 939 goto out; 940 941 cpuid_entry_override(entry, CPUID_7_1_EAX); 942 cpuid_entry_override(entry, CPUID_7_1_EDX); 943 entry->ebx = 0; 944 entry->ecx = 0; 945 } 946 break; 947 case 0xa: { /* Architectural Performance Monitoring */ 948 union cpuid10_eax eax; 949 union cpuid10_edx edx; 950 951 if (!static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 952 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 953 break; 954 } 955 956 eax.split.version_id = kvm_pmu_cap.version; 957 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 958 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 959 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 960 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 961 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 962 963 if (kvm_pmu_cap.version) 964 edx.split.anythread_deprecated = 1; 965 edx.split.reserved1 = 0; 966 edx.split.reserved2 = 0; 967 968 entry->eax = eax.full; 969 entry->ebx = kvm_pmu_cap.events_mask; 970 entry->ecx = 0; 971 entry->edx = edx.full; 972 break; 973 } 974 case 0x1f: 975 case 0xb: 976 /* 977 * No topology; a valid topology is indicated by the presence 978 * of subleaf 1. 979 */ 980 entry->eax = entry->ebx = entry->ecx = 0; 981 break; 982 case 0xd: { 983 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 984 u64 permitted_xss = kvm_caps.supported_xss; 985 986 entry->eax &= permitted_xcr0; 987 entry->ebx = xstate_required_size(permitted_xcr0, false); 988 entry->ecx = entry->ebx; 989 entry->edx &= permitted_xcr0 >> 32; 990 if (!permitted_xcr0) 991 break; 992 993 entry = do_host_cpuid(array, function, 1); 994 if (!entry) 995 goto out; 996 997 cpuid_entry_override(entry, CPUID_D_1_EAX); 998 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 999 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1000 true); 1001 else { 1002 WARN_ON_ONCE(permitted_xss != 0); 1003 entry->ebx = 0; 1004 } 1005 entry->ecx &= permitted_xss; 1006 entry->edx &= permitted_xss >> 32; 1007 1008 for (i = 2; i < 64; ++i) { 1009 bool s_state; 1010 if (permitted_xcr0 & BIT_ULL(i)) 1011 s_state = false; 1012 else if (permitted_xss & BIT_ULL(i)) 1013 s_state = true; 1014 else 1015 continue; 1016 1017 entry = do_host_cpuid(array, function, i); 1018 if (!entry) 1019 goto out; 1020 1021 /* 1022 * The supported check above should have filtered out 1023 * invalid sub-leafs. Only valid sub-leafs should 1024 * reach this point, and they should have a non-zero 1025 * save state size. Furthermore, check whether the 1026 * processor agrees with permitted_xcr0/permitted_xss 1027 * on whether this is an XCR0- or IA32_XSS-managed area. 1028 */ 1029 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1030 --array->nent; 1031 continue; 1032 } 1033 1034 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1035 entry->ecx &= ~BIT_ULL(2); 1036 entry->edx = 0; 1037 } 1038 break; 1039 } 1040 case 0x12: 1041 /* Intel SGX */ 1042 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1043 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1044 break; 1045 } 1046 1047 /* 1048 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1049 * and max enclave sizes. The SGX sub-features and MISCSELECT 1050 * are restricted by kernel and KVM capabilities (like most 1051 * feature flags), while enclave size is unrestricted. 1052 */ 1053 cpuid_entry_override(entry, CPUID_12_EAX); 1054 entry->ebx &= SGX_MISC_EXINFO; 1055 1056 entry = do_host_cpuid(array, function, 1); 1057 if (!entry) 1058 goto out; 1059 1060 /* 1061 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1062 * feature flags. Advertise all supported flags, including 1063 * privileged attributes that require explicit opt-in from 1064 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1065 * expected to derive it from supported XCR0. 1066 */ 1067 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1068 entry->ebx &= 0; 1069 break; 1070 /* Intel PT */ 1071 case 0x14: 1072 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1073 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1074 break; 1075 } 1076 1077 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1078 if (!do_host_cpuid(array, function, i)) 1079 goto out; 1080 } 1081 break; 1082 /* Intel AMX TILE */ 1083 case 0x1d: 1084 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1085 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1086 break; 1087 } 1088 1089 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1090 if (!do_host_cpuid(array, function, i)) 1091 goto out; 1092 } 1093 break; 1094 case 0x1e: /* TMUL information */ 1095 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1096 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1097 break; 1098 } 1099 break; 1100 case KVM_CPUID_SIGNATURE: { 1101 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1102 entry->eax = KVM_CPUID_FEATURES; 1103 entry->ebx = sigptr[0]; 1104 entry->ecx = sigptr[1]; 1105 entry->edx = sigptr[2]; 1106 break; 1107 } 1108 case KVM_CPUID_FEATURES: 1109 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1110 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1111 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1112 (1 << KVM_FEATURE_ASYNC_PF) | 1113 (1 << KVM_FEATURE_PV_EOI) | 1114 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1115 (1 << KVM_FEATURE_PV_UNHALT) | 1116 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1117 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1118 (1 << KVM_FEATURE_PV_SEND_IPI) | 1119 (1 << KVM_FEATURE_POLL_CONTROL) | 1120 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1121 (1 << KVM_FEATURE_ASYNC_PF_INT); 1122 1123 if (sched_info_on()) 1124 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1125 1126 entry->ebx = 0; 1127 entry->ecx = 0; 1128 entry->edx = 0; 1129 break; 1130 case 0x80000000: 1131 entry->eax = min(entry->eax, 0x80000021); 1132 /* 1133 * Serializing LFENCE is reported in a multitude of ways, and 1134 * NullSegClearsBase is not reported in CPUID on Zen2; help 1135 * userspace by providing the CPUID leaf ourselves. 1136 * 1137 * However, only do it if the host has CPUID leaf 0x8000001d. 1138 * QEMU thinks that it can query the host blindly for that 1139 * CPUID leaf if KVM reports that it supports 0x8000001d or 1140 * above. The processor merrily returns values from the 1141 * highest Intel leaf which QEMU tries to use as the guest's 1142 * 0x8000001d. Even worse, this can result in an infinite 1143 * loop if said highest leaf has no subleaves indexed by ECX. 1144 */ 1145 if (entry->eax >= 0x8000001d && 1146 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1147 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1148 entry->eax = max(entry->eax, 0x80000021); 1149 break; 1150 case 0x80000001: 1151 entry->ebx &= ~GENMASK(27, 16); 1152 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1153 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1154 break; 1155 case 0x80000006: 1156 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1157 entry->edx &= ~GENMASK(17, 16); 1158 break; 1159 case 0x80000007: /* Advanced power management */ 1160 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1161 1162 /* mask against host */ 1163 entry->edx &= boot_cpu_data.x86_power; 1164 entry->eax = entry->ebx = entry->ecx = 0; 1165 break; 1166 case 0x80000008: { 1167 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1168 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1169 unsigned phys_as = entry->eax & 0xff; 1170 1171 /* 1172 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1173 * the guest operates in the same PA space as the host, i.e. 1174 * reductions in MAXPHYADDR for memory encryption affect shadow 1175 * paging, too. 1176 * 1177 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1178 * provided, use the raw bare metal MAXPHYADDR as reductions to 1179 * the HPAs do not affect GPAs. 1180 */ 1181 if (!tdp_enabled) 1182 g_phys_as = boot_cpu_data.x86_phys_bits; 1183 else if (!g_phys_as) 1184 g_phys_as = phys_as; 1185 1186 entry->eax = g_phys_as | (virt_as << 8); 1187 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1188 entry->edx = 0; 1189 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1190 break; 1191 } 1192 case 0x8000000A: 1193 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1194 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1195 break; 1196 } 1197 entry->eax = 1; /* SVM revision 1 */ 1198 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1199 ASID emulation to nested SVM */ 1200 entry->ecx = 0; /* Reserved */ 1201 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1202 break; 1203 case 0x80000019: 1204 entry->ecx = entry->edx = 0; 1205 break; 1206 case 0x8000001a: 1207 entry->eax &= GENMASK(2, 0); 1208 entry->ebx = entry->ecx = entry->edx = 0; 1209 break; 1210 case 0x8000001e: 1211 /* Do not return host topology information. */ 1212 entry->eax = entry->ebx = entry->ecx = 0; 1213 entry->edx = 0; /* reserved */ 1214 break; 1215 case 0x8000001F: 1216 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1217 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1218 } else { 1219 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1220 /* Clear NumVMPL since KVM does not support VMPL. */ 1221 entry->ebx &= ~GENMASK(31, 12); 1222 /* 1223 * Enumerate '0' for "PA bits reduction", the adjusted 1224 * MAXPHYADDR is enumerated directly (see 0x80000008). 1225 */ 1226 entry->ebx &= ~GENMASK(11, 6); 1227 } 1228 break; 1229 case 0x80000020: 1230 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1231 break; 1232 case 0x80000021: 1233 entry->ebx = entry->ecx = entry->edx = 0; 1234 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1235 break; 1236 /*Add support for Centaur's CPUID instruction*/ 1237 case 0xC0000000: 1238 /*Just support up to 0xC0000004 now*/ 1239 entry->eax = min(entry->eax, 0xC0000004); 1240 break; 1241 case 0xC0000001: 1242 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1243 break; 1244 case 3: /* Processor serial number */ 1245 case 5: /* MONITOR/MWAIT */ 1246 case 0xC0000002: 1247 case 0xC0000003: 1248 case 0xC0000004: 1249 default: 1250 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1251 break; 1252 } 1253 1254 r = 0; 1255 1256 out: 1257 put_cpu(); 1258 1259 return r; 1260 } 1261 1262 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1263 unsigned int type) 1264 { 1265 if (type == KVM_GET_EMULATED_CPUID) 1266 return __do_cpuid_func_emulated(array, func); 1267 1268 return __do_cpuid_func(array, func); 1269 } 1270 1271 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1272 1273 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1274 unsigned int type) 1275 { 1276 u32 limit; 1277 int r; 1278 1279 if (func == CENTAUR_CPUID_SIGNATURE && 1280 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1281 return 0; 1282 1283 r = do_cpuid_func(array, func, type); 1284 if (r) 1285 return r; 1286 1287 limit = array->entries[array->nent - 1].eax; 1288 for (func = func + 1; func <= limit; ++func) { 1289 r = do_cpuid_func(array, func, type); 1290 if (r) 1291 break; 1292 } 1293 1294 return r; 1295 } 1296 1297 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1298 __u32 num_entries, unsigned int ioctl_type) 1299 { 1300 int i; 1301 __u32 pad[3]; 1302 1303 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1304 return false; 1305 1306 /* 1307 * We want to make sure that ->padding is being passed clean from 1308 * userspace in case we want to use it for something in the future. 1309 * 1310 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1311 * have to give ourselves satisfied only with the emulated side. /me 1312 * sheds a tear. 1313 */ 1314 for (i = 0; i < num_entries; i++) { 1315 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1316 return true; 1317 1318 if (pad[0] || pad[1] || pad[2]) 1319 return true; 1320 } 1321 return false; 1322 } 1323 1324 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1325 struct kvm_cpuid_entry2 __user *entries, 1326 unsigned int type) 1327 { 1328 static const u32 funcs[] = { 1329 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1330 }; 1331 1332 struct kvm_cpuid_array array = { 1333 .nent = 0, 1334 }; 1335 int r, i; 1336 1337 if (cpuid->nent < 1) 1338 return -E2BIG; 1339 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1340 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1341 1342 if (sanity_check_entries(entries, cpuid->nent, type)) 1343 return -EINVAL; 1344 1345 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1346 if (!array.entries) 1347 return -ENOMEM; 1348 1349 array.maxnent = cpuid->nent; 1350 1351 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1352 r = get_cpuid_func(&array, funcs[i], type); 1353 if (r) 1354 goto out_free; 1355 } 1356 cpuid->nent = array.nent; 1357 1358 if (copy_to_user(entries, array.entries, 1359 array.nent * sizeof(struct kvm_cpuid_entry2))) 1360 r = -EFAULT; 1361 1362 out_free: 1363 kvfree(array.entries); 1364 return r; 1365 } 1366 1367 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1368 u32 function, u32 index) 1369 { 1370 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1371 function, index); 1372 } 1373 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1374 1375 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1376 u32 function) 1377 { 1378 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1379 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1380 } 1381 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1382 1383 /* 1384 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1385 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1386 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1387 * range. Centaur/VIA follows Intel semantics. 1388 * 1389 * A leaf is considered out-of-range if its function is higher than the maximum 1390 * supported leaf of its associated class or if its associated class does not 1391 * exist. 1392 * 1393 * There are three primary classes to be considered, with their respective 1394 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1395 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1396 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1397 * 1398 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1399 * - Hypervisor: 0x40000000 - 0x4fffffff 1400 * - Extended: 0x80000000 - 0xbfffffff 1401 * - Centaur: 0xc0000000 - 0xcfffffff 1402 * 1403 * The Hypervisor class is further subdivided into sub-classes that each act as 1404 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1405 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1406 * CPUID sub-classes are: 1407 * 1408 * - HyperV: 0x40000000 - 0x400000ff 1409 * - KVM: 0x40000100 - 0x400001ff 1410 */ 1411 static struct kvm_cpuid_entry2 * 1412 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1413 { 1414 struct kvm_cpuid_entry2 *basic, *class; 1415 u32 function = *fn_ptr; 1416 1417 basic = kvm_find_cpuid_entry(vcpu, 0); 1418 if (!basic) 1419 return NULL; 1420 1421 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1422 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1423 return NULL; 1424 1425 if (function >= 0x40000000 && function <= 0x4fffffff) 1426 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1427 else if (function >= 0xc0000000) 1428 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1429 else 1430 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1431 1432 if (class && function <= class->eax) 1433 return NULL; 1434 1435 /* 1436 * Leaf specific adjustments are also applied when redirecting to the 1437 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1438 * entry for CPUID.0xb.index (see below), then the output value for EDX 1439 * needs to be pulled from CPUID.0xb.1. 1440 */ 1441 *fn_ptr = basic->eax; 1442 1443 /* 1444 * The class does not exist or the requested function is out of range; 1445 * the effective CPUID entry is the max basic leaf. Note, the index of 1446 * the original requested leaf is observed! 1447 */ 1448 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1449 } 1450 1451 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1452 u32 *ecx, u32 *edx, bool exact_only) 1453 { 1454 u32 orig_function = *eax, function = *eax, index = *ecx; 1455 struct kvm_cpuid_entry2 *entry; 1456 bool exact, used_max_basic = false; 1457 1458 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1459 exact = !!entry; 1460 1461 if (!entry && !exact_only) { 1462 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1463 used_max_basic = !!entry; 1464 } 1465 1466 if (entry) { 1467 *eax = entry->eax; 1468 *ebx = entry->ebx; 1469 *ecx = entry->ecx; 1470 *edx = entry->edx; 1471 if (function == 7 && index == 0) { 1472 u64 data; 1473 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1474 (data & TSX_CTRL_CPUID_CLEAR)) 1475 *ebx &= ~(F(RTM) | F(HLE)); 1476 } else if (function == 0x80000007) { 1477 if (kvm_hv_invtsc_suppressed(vcpu)) 1478 *edx &= ~SF(CONSTANT_TSC); 1479 } 1480 } else { 1481 *eax = *ebx = *ecx = *edx = 0; 1482 /* 1483 * When leaf 0BH or 1FH is defined, CL is pass-through 1484 * and EDX is always the x2APIC ID, even for undefined 1485 * subleaves. Index 1 will exist iff the leaf is 1486 * implemented, so we pass through CL iff leaf 1 1487 * exists. EDX can be copied from any existing index. 1488 */ 1489 if (function == 0xb || function == 0x1f) { 1490 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1491 if (entry) { 1492 *ecx = index & 0xff; 1493 *edx = entry->edx; 1494 } 1495 } 1496 } 1497 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1498 used_max_basic); 1499 return exact; 1500 } 1501 EXPORT_SYMBOL_GPL(kvm_cpuid); 1502 1503 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1504 { 1505 u32 eax, ebx, ecx, edx; 1506 1507 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1508 return 1; 1509 1510 eax = kvm_rax_read(vcpu); 1511 ecx = kvm_rcx_read(vcpu); 1512 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1513 kvm_rax_write(vcpu, eax); 1514 kvm_rbx_write(vcpu, ebx); 1515 kvm_rcx_write(vcpu, ecx); 1516 kvm_rdx_write(vcpu, edx); 1517 return kvm_skip_emulated_instruction(vcpu); 1518 } 1519 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1520