1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kvm_host.h> 14 #include "linux/lockdep.h" 15 #include <linux/export.h> 16 #include <linux/vmalloc.h> 17 #include <linux/uaccess.h> 18 #include <linux/sched/stat.h> 19 20 #include <asm/processor.h> 21 #include <asm/user.h> 22 #include <asm/fpu/xstate.h> 23 #include <asm/sgx.h> 24 #include <asm/cpuid.h> 25 #include "cpuid.h" 26 #include "lapic.h" 27 #include "mmu.h" 28 #include "trace.h" 29 #include "pmu.h" 30 #include "xen.h" 31 32 /* 33 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 34 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 35 */ 36 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 37 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 38 39 u32 xstate_required_size(u64 xstate_bv, bool compacted) 40 { 41 int feature_bit = 0; 42 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 43 44 xstate_bv &= XFEATURE_MASK_EXTEND; 45 while (xstate_bv) { 46 if (xstate_bv & 0x1) { 47 u32 eax, ebx, ecx, edx, offset; 48 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 49 /* ECX[1]: 64B alignment in compacted form */ 50 if (compacted) 51 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 52 else 53 offset = ebx; 54 ret = max(ret, offset + eax); 55 } 56 57 xstate_bv >>= 1; 58 feature_bit++; 59 } 60 61 return ret; 62 } 63 64 #define F feature_bit 65 66 /* Scattered Flag - For features that are scattered by cpufeatures.h. */ 67 #define SF(name) \ 68 ({ \ 69 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 70 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ 71 }) 72 73 /* 74 * Magic value used by KVM when querying userspace-provided CPUID entries and 75 * doesn't care about the CPIUD index because the index of the function in 76 * question is not significant. Note, this magic value must have at least one 77 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 78 * to avoid false positives when processing guest CPUID input. 79 */ 80 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 81 82 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 83 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 84 { 85 struct kvm_cpuid_entry2 *e; 86 int i; 87 88 /* 89 * KVM has a semi-arbitrary rule that querying the guest's CPUID model 90 * with IRQs disabled is disallowed. The CPUID model can legitimately 91 * have over one hundred entries, i.e. the lookup is slow, and IRQs are 92 * typically disabled in KVM only when KVM is in a performance critical 93 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break 94 * if this rule is violated, this assertion is purely to flag potential 95 * performance issues. If this fires, consider moving the lookup out 96 * of the hotpath, e.g. by caching information during CPUID updates. 97 */ 98 lockdep_assert_irqs_enabled(); 99 100 for (i = 0; i < nent; i++) { 101 e = &entries[i]; 102 103 if (e->function != function) 104 continue; 105 106 /* 107 * If the index isn't significant, use the first entry with a 108 * matching function. It's userspace's responsibilty to not 109 * provide "duplicate" entries in all cases. 110 */ 111 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 112 return e; 113 114 115 /* 116 * Similarly, use the first matching entry if KVM is doing a 117 * lookup (as opposed to emulating CPUID) for a function that's 118 * architecturally defined as not having a significant index. 119 */ 120 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 121 /* 122 * Direct lookups from KVM should not diverge from what 123 * KVM defines internally (the architectural behavior). 124 */ 125 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 126 return e; 127 } 128 } 129 130 return NULL; 131 } 132 133 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 134 struct kvm_cpuid_entry2 *entries, 135 int nent) 136 { 137 struct kvm_cpuid_entry2 *best; 138 u64 xfeatures; 139 140 /* 141 * The existing code assumes virtual address is 48-bit or 57-bit in the 142 * canonical address checks; exit if it is ever changed. 143 */ 144 best = cpuid_entry2_find(entries, nent, 0x80000008, 145 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 146 if (best) { 147 int vaddr_bits = (best->eax & 0xff00) >> 8; 148 149 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 150 return -EINVAL; 151 } 152 153 /* 154 * Exposing dynamic xfeatures to the guest requires additional 155 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 156 */ 157 best = cpuid_entry2_find(entries, nent, 0xd, 0); 158 if (!best) 159 return 0; 160 161 xfeatures = best->eax | ((u64)best->edx << 32); 162 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 163 if (!xfeatures) 164 return 0; 165 166 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 167 } 168 169 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 170 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 171 int nent) 172 { 173 struct kvm_cpuid_entry2 *orig; 174 int i; 175 176 if (nent != vcpu->arch.cpuid_nent) 177 return -EINVAL; 178 179 for (i = 0; i < nent; i++) { 180 orig = &vcpu->arch.cpuid_entries[i]; 181 if (e2[i].function != orig->function || 182 e2[i].index != orig->index || 183 e2[i].flags != orig->flags || 184 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 185 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 186 return -EINVAL; 187 } 188 189 return 0; 190 } 191 192 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 193 const char *sig) 194 { 195 struct kvm_hypervisor_cpuid cpuid = {}; 196 struct kvm_cpuid_entry2 *entry; 197 u32 base; 198 199 for_each_possible_hypervisor_cpuid_base(base) { 200 entry = kvm_find_cpuid_entry(vcpu, base); 201 202 if (entry) { 203 u32 signature[3]; 204 205 signature[0] = entry->ebx; 206 signature[1] = entry->ecx; 207 signature[2] = entry->edx; 208 209 if (!memcmp(signature, sig, sizeof(signature))) { 210 cpuid.base = base; 211 cpuid.limit = entry->eax; 212 break; 213 } 214 } 215 } 216 217 return cpuid; 218 } 219 220 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 221 struct kvm_cpuid_entry2 *entries, int nent) 222 { 223 u32 base = vcpu->arch.kvm_cpuid.base; 224 225 if (!base) 226 return NULL; 227 228 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 229 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 230 } 231 232 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 233 { 234 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 235 vcpu->arch.cpuid_nent); 236 } 237 238 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 239 { 240 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 241 242 /* 243 * save the feature bitmap to avoid cpuid lookup for every PV 244 * operation 245 */ 246 if (best) 247 vcpu->arch.pv_cpuid.features = best->eax; 248 } 249 250 /* 251 * Calculate guest's supported XCR0 taking into account guest CPUID data and 252 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 253 */ 254 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 255 { 256 struct kvm_cpuid_entry2 *best; 257 258 best = cpuid_entry2_find(entries, nent, 0xd, 0); 259 if (!best) 260 return 0; 261 262 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 263 } 264 265 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 266 int nent) 267 { 268 struct kvm_cpuid_entry2 *best; 269 270 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 271 if (best) { 272 /* Update OSXSAVE bit */ 273 if (boot_cpu_has(X86_FEATURE_XSAVE)) 274 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 275 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 276 277 cpuid_entry_change(best, X86_FEATURE_APIC, 278 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 279 } 280 281 best = cpuid_entry2_find(entries, nent, 7, 0); 282 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 283 cpuid_entry_change(best, X86_FEATURE_OSPKE, 284 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 285 286 best = cpuid_entry2_find(entries, nent, 0xD, 0); 287 if (best) 288 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 289 290 best = cpuid_entry2_find(entries, nent, 0xD, 1); 291 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 292 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 293 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 294 295 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 296 if (kvm_hlt_in_guest(vcpu->kvm) && best && 297 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 298 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 299 300 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 301 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 302 if (best) 303 cpuid_entry_change(best, X86_FEATURE_MWAIT, 304 vcpu->arch.ia32_misc_enable_msr & 305 MSR_IA32_MISC_ENABLE_MWAIT); 306 } 307 } 308 309 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 310 { 311 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 312 } 313 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 314 315 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) 316 { 317 struct kvm_cpuid_entry2 *entry; 318 319 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, 320 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 321 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 322 } 323 324 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 325 { 326 struct kvm_lapic *apic = vcpu->arch.apic; 327 struct kvm_cpuid_entry2 *best; 328 bool allow_gbpages; 329 330 BUILD_BUG_ON(KVM_NR_GOVERNED_FEATURES > KVM_MAX_NR_GOVERNED_FEATURES); 331 bitmap_zero(vcpu->arch.governed_features.enabled, 332 KVM_MAX_NR_GOVERNED_FEATURES); 333 334 /* 335 * If TDP is enabled, let the guest use GBPAGES if they're supported in 336 * hardware. The hardware page walker doesn't let KVM disable GBPAGES, 337 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA 338 * walk for performance and complexity reasons. Not to mention KVM 339 * _can't_ solve the problem because GVA->GPA walks aren't visible to 340 * KVM once a TDP translation is installed. Mimic hardware behavior so 341 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. 342 * If TDP is disabled, honor *only* guest CPUID as KVM has full control 343 * and can install smaller shadow pages if the host lacks 1GiB support. 344 */ 345 allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : 346 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES); 347 if (allow_gbpages) 348 kvm_governed_feature_set(vcpu, X86_FEATURE_GBPAGES); 349 350 best = kvm_find_cpuid_entry(vcpu, 1); 351 if (best && apic) { 352 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 353 apic->lapic_timer.timer_mode_mask = 3 << 17; 354 else 355 apic->lapic_timer.timer_mode_mask = 1 << 17; 356 357 kvm_apic_set_version(vcpu); 358 } 359 360 vcpu->arch.guest_supported_xcr0 = 361 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 362 363 kvm_update_pv_runtime(vcpu); 364 365 vcpu->arch.is_amd_compatible = guest_cpuid_is_amd_or_hygon(vcpu); 366 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 367 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 368 369 kvm_pmu_refresh(vcpu); 370 vcpu->arch.cr4_guest_rsvd_bits = 371 __cr4_reserved_bits(guest_cpuid_has, vcpu); 372 373 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, 374 vcpu->arch.cpuid_nent)); 375 376 /* Invoke the vendor callback only after the above state is updated. */ 377 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 378 379 /* 380 * Except for the MMU, which needs to do its thing any vendor specific 381 * adjustments to the reserved GPA bits. 382 */ 383 kvm_mmu_after_set_cpuid(vcpu); 384 } 385 386 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 387 { 388 struct kvm_cpuid_entry2 *best; 389 390 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 391 if (!best || best->eax < 0x80000008) 392 goto not_found; 393 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 394 if (best) 395 return best->eax & 0xff; 396 not_found: 397 return 36; 398 } 399 400 /* 401 * This "raw" version returns the reserved GPA bits without any adjustments for 402 * encryption technologies that usurp bits. The raw mask should be used if and 403 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 404 */ 405 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 406 { 407 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 408 } 409 410 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 411 int nent) 412 { 413 int r; 414 415 __kvm_update_cpuid_runtime(vcpu, e2, nent); 416 417 /* 418 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 419 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 420 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 421 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 422 * the core vCPU model on the fly. It would've been better to forbid any 423 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 424 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 425 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 426 * whether the supplied CPUID data is equal to what's already set. 427 */ 428 if (kvm_vcpu_has_run(vcpu)) { 429 r = kvm_cpuid_check_equal(vcpu, e2, nent); 430 if (r) 431 return r; 432 433 kvfree(e2); 434 return 0; 435 } 436 437 if (kvm_cpuid_has_hyperv(e2, nent)) { 438 r = kvm_hv_vcpu_init(vcpu); 439 if (r) 440 return r; 441 } 442 443 r = kvm_check_cpuid(vcpu, e2, nent); 444 if (r) 445 return r; 446 447 kvfree(vcpu->arch.cpuid_entries); 448 vcpu->arch.cpuid_entries = e2; 449 vcpu->arch.cpuid_nent = nent; 450 451 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 452 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 453 kvm_vcpu_after_set_cpuid(vcpu); 454 455 return 0; 456 } 457 458 /* when an old userspace process fills a new kernel module */ 459 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 460 struct kvm_cpuid *cpuid, 461 struct kvm_cpuid_entry __user *entries) 462 { 463 int r, i; 464 struct kvm_cpuid_entry *e = NULL; 465 struct kvm_cpuid_entry2 *e2 = NULL; 466 467 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 468 return -E2BIG; 469 470 if (cpuid->nent) { 471 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 472 if (IS_ERR(e)) 473 return PTR_ERR(e); 474 475 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 476 if (!e2) { 477 r = -ENOMEM; 478 goto out_free_cpuid; 479 } 480 } 481 for (i = 0; i < cpuid->nent; i++) { 482 e2[i].function = e[i].function; 483 e2[i].eax = e[i].eax; 484 e2[i].ebx = e[i].ebx; 485 e2[i].ecx = e[i].ecx; 486 e2[i].edx = e[i].edx; 487 e2[i].index = 0; 488 e2[i].flags = 0; 489 e2[i].padding[0] = 0; 490 e2[i].padding[1] = 0; 491 e2[i].padding[2] = 0; 492 } 493 494 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 495 if (r) 496 kvfree(e2); 497 498 out_free_cpuid: 499 kvfree(e); 500 501 return r; 502 } 503 504 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 505 struct kvm_cpuid2 *cpuid, 506 struct kvm_cpuid_entry2 __user *entries) 507 { 508 struct kvm_cpuid_entry2 *e2 = NULL; 509 int r; 510 511 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 512 return -E2BIG; 513 514 if (cpuid->nent) { 515 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 516 if (IS_ERR(e2)) 517 return PTR_ERR(e2); 518 } 519 520 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 521 if (r) 522 kvfree(e2); 523 524 return r; 525 } 526 527 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 528 struct kvm_cpuid2 *cpuid, 529 struct kvm_cpuid_entry2 __user *entries) 530 { 531 if (cpuid->nent < vcpu->arch.cpuid_nent) 532 return -E2BIG; 533 534 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 535 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 536 return -EFAULT; 537 538 cpuid->nent = vcpu->arch.cpuid_nent; 539 return 0; 540 } 541 542 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 543 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 544 { 545 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 546 struct kvm_cpuid_entry2 entry; 547 548 reverse_cpuid_check(leaf); 549 550 cpuid_count(cpuid.function, cpuid.index, 551 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 552 553 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 554 } 555 556 static __always_inline 557 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) 558 { 559 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ 560 BUILD_BUG_ON(leaf < NCAPINTS); 561 562 kvm_cpu_caps[leaf] = mask; 563 564 __kvm_cpu_cap_mask(leaf); 565 } 566 567 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 568 { 569 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ 570 BUILD_BUG_ON(leaf >= NCAPINTS); 571 572 kvm_cpu_caps[leaf] &= mask; 573 574 __kvm_cpu_cap_mask(leaf); 575 } 576 577 void kvm_set_cpu_caps(void) 578 { 579 #ifdef CONFIG_X86_64 580 unsigned int f_gbpages = F(GBPAGES); 581 unsigned int f_lm = F(LM); 582 unsigned int f_xfd = F(XFD); 583 #else 584 unsigned int f_gbpages = 0; 585 unsigned int f_lm = 0; 586 unsigned int f_xfd = 0; 587 #endif 588 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 589 590 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 591 sizeof(boot_cpu_data.x86_capability)); 592 593 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 594 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 595 596 kvm_cpu_cap_mask(CPUID_1_ECX, 597 /* 598 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 599 * advertised to guests via CPUID! 600 */ 601 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 602 0 /* DS-CPL, VMX, SMX, EST */ | 603 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 604 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 605 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 606 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 607 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 608 F(F16C) | F(RDRAND) 609 ); 610 /* KVM emulates x2apic in software irrespective of host support. */ 611 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 612 613 kvm_cpu_cap_mask(CPUID_1_EDX, 614 F(FPU) | F(VME) | F(DE) | F(PSE) | 615 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 616 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 617 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 618 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 619 0 /* Reserved, DS, ACPI */ | F(MMX) | 620 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 621 0 /* HTT, TM, Reserved, PBE */ 622 ); 623 624 kvm_cpu_cap_mask(CPUID_7_0_EBX, 625 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 626 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 627 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 628 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 629 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 630 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 631 F(AVX512VL)); 632 633 kvm_cpu_cap_mask(CPUID_7_ECX, 634 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 635 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 636 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 637 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 638 F(SGX_LC) | F(BUS_LOCK_DETECT) 639 ); 640 /* Set LA57 based on hardware capability. */ 641 if (cpuid_ecx(7) & F(LA57)) 642 kvm_cpu_cap_set(X86_FEATURE_LA57); 643 644 /* 645 * PKU not yet implemented for shadow paging and requires OSPKE 646 * to be set on the host. Clear it if that is not the case 647 */ 648 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 649 kvm_cpu_cap_clear(X86_FEATURE_PKU); 650 651 kvm_cpu_cap_mask(CPUID_7_EDX, 652 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 653 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 654 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 655 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 656 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) 657 ); 658 659 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 660 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 661 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 662 663 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 664 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 665 if (boot_cpu_has(X86_FEATURE_STIBP)) 666 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 667 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 668 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 669 670 kvm_cpu_cap_mask(CPUID_7_1_EAX, 671 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | 672 F(FZRM) | F(FSRS) | F(FSRC) | 673 F(AMX_FP16) | F(AVX_IFMA) 674 ); 675 676 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, 677 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) | 678 F(AMX_COMPLEX) 679 ); 680 681 kvm_cpu_cap_init_kvm_defined(CPUID_7_2_EDX, 682 F(INTEL_PSFD) | F(IPRED_CTRL) | F(RRSBA_CTRL) | F(DDPD_U) | 683 F(BHI_CTRL) | F(MCDT_NO) 684 ); 685 686 kvm_cpu_cap_mask(CPUID_D_1_EAX, 687 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 688 ); 689 690 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, 691 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) 692 ); 693 694 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 695 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 696 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 697 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 698 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 699 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 700 ); 701 702 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 703 F(FPU) | F(VME) | F(DE) | F(PSE) | 704 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 705 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 706 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 707 F(PAT) | F(PSE36) | 0 /* Reserved */ | 708 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 709 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 710 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 711 ); 712 713 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 714 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 715 716 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, 717 SF(CONSTANT_TSC) 718 ); 719 720 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 721 F(CLZERO) | F(XSAVEERPTR) | 722 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 723 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 724 F(AMD_PSFD) 725 ); 726 727 /* 728 * AMD has separate bits for each SPEC_CTRL bit. 729 * arch/x86/kernel/cpu/bugs.c is kind enough to 730 * record that in cpufeatures so use them. 731 */ 732 if (boot_cpu_has(X86_FEATURE_IBPB)) 733 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 734 if (boot_cpu_has(X86_FEATURE_IBRS)) 735 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 736 if (boot_cpu_has(X86_FEATURE_STIBP)) 737 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 738 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 739 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 740 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 741 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 742 /* 743 * The preference is to use SPEC CTRL MSR instead of the 744 * VIRT_SPEC MSR. 745 */ 746 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 747 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 748 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 749 750 /* 751 * Hide all SVM features by default, SVM will set the cap bits for 752 * features it emulates and/or exposes for L1. 753 */ 754 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 755 756 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 757 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 758 F(SME_COHERENT)); 759 760 kvm_cpu_cap_mask(CPUID_8000_0021_EAX, 761 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | 762 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ 763 ); 764 765 if (cpu_feature_enabled(X86_FEATURE_SRSO_NO)) 766 kvm_cpu_cap_set(X86_FEATURE_SRSO_NO); 767 768 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, 769 F(PERFMON_V2) 770 ); 771 772 /* 773 * Synthesize "LFENCE is serializing" into the AMD-defined entry in 774 * KVM's supported CPUID if the feature is reported as supported by the 775 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long 776 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most 777 * CPUs that support SSE2. On CPUs that don't support AMD's leaf, 778 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing 779 * the mask with the raw host CPUID, and reporting support in AMD's 780 * leaf can make it easier for userspace to detect the feature. 781 */ 782 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 783 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); 784 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 785 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 786 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); 787 788 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 789 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 790 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 791 F(PMM) | F(PMM_EN) 792 ); 793 794 /* 795 * Hide RDTSCP and RDPID if either feature is reported as supported but 796 * probing MSR_TSC_AUX failed. This is purely a sanity check and 797 * should never happen, but the guest will likely crash if RDTSCP or 798 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 799 * the past. For example, the sanity check may fire if this instance of 800 * KVM is running as L1 on top of an older, broken KVM. 801 */ 802 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 803 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 804 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 805 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 806 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 807 } 808 } 809 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 810 811 struct kvm_cpuid_array { 812 struct kvm_cpuid_entry2 *entries; 813 int maxnent; 814 int nent; 815 }; 816 817 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 818 { 819 if (array->nent >= array->maxnent) 820 return NULL; 821 822 return &array->entries[array->nent++]; 823 } 824 825 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 826 u32 function, u32 index) 827 { 828 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 829 830 if (!entry) 831 return NULL; 832 833 memset(entry, 0, sizeof(*entry)); 834 entry->function = function; 835 entry->index = index; 836 switch (function & 0xC0000000) { 837 case 0x40000000: 838 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 839 return entry; 840 841 case 0x80000000: 842 /* 843 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 844 * would result in out-of-bounds calls to do_host_cpuid. 845 */ 846 { 847 static int max_cpuid_80000000; 848 if (!READ_ONCE(max_cpuid_80000000)) 849 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 850 if (function > READ_ONCE(max_cpuid_80000000)) 851 return entry; 852 } 853 break; 854 855 default: 856 break; 857 } 858 859 cpuid_count(entry->function, entry->index, 860 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 861 862 if (cpuid_function_is_indexed(function)) 863 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 864 865 return entry; 866 } 867 868 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 869 { 870 struct kvm_cpuid_entry2 *entry; 871 872 if (array->nent >= array->maxnent) 873 return -E2BIG; 874 875 entry = &array->entries[array->nent]; 876 entry->function = func; 877 entry->index = 0; 878 entry->flags = 0; 879 880 switch (func) { 881 case 0: 882 entry->eax = 7; 883 ++array->nent; 884 break; 885 case 1: 886 entry->ecx = F(MOVBE); 887 ++array->nent; 888 break; 889 case 7: 890 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 891 entry->eax = 0; 892 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 893 entry->ecx = F(RDPID); 894 ++array->nent; 895 break; 896 default: 897 break; 898 } 899 900 return 0; 901 } 902 903 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 904 { 905 struct kvm_cpuid_entry2 *entry; 906 int r, i, max_idx; 907 908 /* all calls to cpuid_count() should be made on the same cpu */ 909 get_cpu(); 910 911 r = -E2BIG; 912 913 entry = do_host_cpuid(array, function, 0); 914 if (!entry) 915 goto out; 916 917 switch (function) { 918 case 0: 919 /* Limited to the highest leaf implemented in KVM. */ 920 entry->eax = min(entry->eax, 0x1fU); 921 break; 922 case 1: 923 cpuid_entry_override(entry, CPUID_1_EDX); 924 cpuid_entry_override(entry, CPUID_1_ECX); 925 break; 926 case 2: 927 /* 928 * On ancient CPUs, function 2 entries are STATEFUL. That is, 929 * CPUID(function=2, index=0) may return different results each 930 * time, with the least-significant byte in EAX enumerating the 931 * number of times software should do CPUID(2, 0). 932 * 933 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 934 * idiotic. Intel's SDM states that EAX & 0xff "will always 935 * return 01H. Software should ignore this value and not 936 * interpret it as an informational descriptor", while AMD's 937 * APM states that CPUID(2) is reserved. 938 * 939 * WARN if a frankenstein CPU that supports virtualization and 940 * a stateful CPUID.0x2 is encountered. 941 */ 942 WARN_ON_ONCE((entry->eax & 0xff) > 1); 943 break; 944 /* functions 4 and 0x8000001d have additional index. */ 945 case 4: 946 case 0x8000001d: 947 /* 948 * Read entries until the cache type in the previous entry is 949 * zero, i.e. indicates an invalid entry. 950 */ 951 for (i = 1; entry->eax & 0x1f; ++i) { 952 entry = do_host_cpuid(array, function, i); 953 if (!entry) 954 goto out; 955 } 956 break; 957 case 6: /* Thermal management */ 958 entry->eax = 0x4; /* allow ARAT */ 959 entry->ebx = 0; 960 entry->ecx = 0; 961 entry->edx = 0; 962 break; 963 /* function 7 has additional index. */ 964 case 7: 965 max_idx = entry->eax = min(entry->eax, 2u); 966 cpuid_entry_override(entry, CPUID_7_0_EBX); 967 cpuid_entry_override(entry, CPUID_7_ECX); 968 cpuid_entry_override(entry, CPUID_7_EDX); 969 970 /* KVM only supports up to 0x7.2, capped above via min(). */ 971 if (max_idx >= 1) { 972 entry = do_host_cpuid(array, function, 1); 973 if (!entry) 974 goto out; 975 976 cpuid_entry_override(entry, CPUID_7_1_EAX); 977 cpuid_entry_override(entry, CPUID_7_1_EDX); 978 entry->ebx = 0; 979 entry->ecx = 0; 980 } 981 if (max_idx >= 2) { 982 entry = do_host_cpuid(array, function, 2); 983 if (!entry) 984 goto out; 985 986 cpuid_entry_override(entry, CPUID_7_2_EDX); 987 entry->ecx = 0; 988 entry->ebx = 0; 989 entry->eax = 0; 990 } 991 break; 992 case 0xa: { /* Architectural Performance Monitoring */ 993 union cpuid10_eax eax; 994 union cpuid10_edx edx; 995 996 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 997 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 998 break; 999 } 1000 1001 eax.split.version_id = kvm_pmu_cap.version; 1002 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 1003 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 1004 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 1005 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 1006 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 1007 1008 if (kvm_pmu_cap.version) 1009 edx.split.anythread_deprecated = 1; 1010 edx.split.reserved1 = 0; 1011 edx.split.reserved2 = 0; 1012 1013 entry->eax = eax.full; 1014 entry->ebx = kvm_pmu_cap.events_mask; 1015 entry->ecx = 0; 1016 entry->edx = edx.full; 1017 break; 1018 } 1019 case 0x1f: 1020 case 0xb: 1021 /* 1022 * No topology; a valid topology is indicated by the presence 1023 * of subleaf 1. 1024 */ 1025 entry->eax = entry->ebx = entry->ecx = 0; 1026 break; 1027 case 0xd: { 1028 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 1029 u64 permitted_xss = kvm_caps.supported_xss; 1030 1031 entry->eax &= permitted_xcr0; 1032 entry->ebx = xstate_required_size(permitted_xcr0, false); 1033 entry->ecx = entry->ebx; 1034 entry->edx &= permitted_xcr0 >> 32; 1035 if (!permitted_xcr0) 1036 break; 1037 1038 entry = do_host_cpuid(array, function, 1); 1039 if (!entry) 1040 goto out; 1041 1042 cpuid_entry_override(entry, CPUID_D_1_EAX); 1043 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 1044 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1045 true); 1046 else { 1047 WARN_ON_ONCE(permitted_xss != 0); 1048 entry->ebx = 0; 1049 } 1050 entry->ecx &= permitted_xss; 1051 entry->edx &= permitted_xss >> 32; 1052 1053 for (i = 2; i < 64; ++i) { 1054 bool s_state; 1055 if (permitted_xcr0 & BIT_ULL(i)) 1056 s_state = false; 1057 else if (permitted_xss & BIT_ULL(i)) 1058 s_state = true; 1059 else 1060 continue; 1061 1062 entry = do_host_cpuid(array, function, i); 1063 if (!entry) 1064 goto out; 1065 1066 /* 1067 * The supported check above should have filtered out 1068 * invalid sub-leafs. Only valid sub-leafs should 1069 * reach this point, and they should have a non-zero 1070 * save state size. Furthermore, check whether the 1071 * processor agrees with permitted_xcr0/permitted_xss 1072 * on whether this is an XCR0- or IA32_XSS-managed area. 1073 */ 1074 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1075 --array->nent; 1076 continue; 1077 } 1078 1079 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1080 entry->ecx &= ~BIT_ULL(2); 1081 entry->edx = 0; 1082 } 1083 break; 1084 } 1085 case 0x12: 1086 /* Intel SGX */ 1087 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1088 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1089 break; 1090 } 1091 1092 /* 1093 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1094 * and max enclave sizes. The SGX sub-features and MISCSELECT 1095 * are restricted by kernel and KVM capabilities (like most 1096 * feature flags), while enclave size is unrestricted. 1097 */ 1098 cpuid_entry_override(entry, CPUID_12_EAX); 1099 entry->ebx &= SGX_MISC_EXINFO; 1100 1101 entry = do_host_cpuid(array, function, 1); 1102 if (!entry) 1103 goto out; 1104 1105 /* 1106 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1107 * feature flags. Advertise all supported flags, including 1108 * privileged attributes that require explicit opt-in from 1109 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1110 * expected to derive it from supported XCR0. 1111 */ 1112 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1113 entry->ebx &= 0; 1114 break; 1115 /* Intel PT */ 1116 case 0x14: 1117 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1118 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1119 break; 1120 } 1121 1122 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1123 if (!do_host_cpuid(array, function, i)) 1124 goto out; 1125 } 1126 break; 1127 /* Intel AMX TILE */ 1128 case 0x1d: 1129 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1130 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1131 break; 1132 } 1133 1134 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1135 if (!do_host_cpuid(array, function, i)) 1136 goto out; 1137 } 1138 break; 1139 case 0x1e: /* TMUL information */ 1140 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1141 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1142 break; 1143 } 1144 break; 1145 case KVM_CPUID_SIGNATURE: { 1146 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1147 entry->eax = KVM_CPUID_FEATURES; 1148 entry->ebx = sigptr[0]; 1149 entry->ecx = sigptr[1]; 1150 entry->edx = sigptr[2]; 1151 break; 1152 } 1153 case KVM_CPUID_FEATURES: 1154 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1155 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1156 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1157 (1 << KVM_FEATURE_ASYNC_PF) | 1158 (1 << KVM_FEATURE_PV_EOI) | 1159 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1160 (1 << KVM_FEATURE_PV_UNHALT) | 1161 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1162 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1163 (1 << KVM_FEATURE_PV_SEND_IPI) | 1164 (1 << KVM_FEATURE_POLL_CONTROL) | 1165 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1166 (1 << KVM_FEATURE_ASYNC_PF_INT); 1167 1168 if (sched_info_on()) 1169 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1170 1171 entry->ebx = 0; 1172 entry->ecx = 0; 1173 entry->edx = 0; 1174 break; 1175 case 0x80000000: 1176 entry->eax = min(entry->eax, 0x80000022); 1177 /* 1178 * Serializing LFENCE is reported in a multitude of ways, and 1179 * NullSegClearsBase is not reported in CPUID on Zen2; help 1180 * userspace by providing the CPUID leaf ourselves. 1181 * 1182 * However, only do it if the host has CPUID leaf 0x8000001d. 1183 * QEMU thinks that it can query the host blindly for that 1184 * CPUID leaf if KVM reports that it supports 0x8000001d or 1185 * above. The processor merrily returns values from the 1186 * highest Intel leaf which QEMU tries to use as the guest's 1187 * 0x8000001d. Even worse, this can result in an infinite 1188 * loop if said highest leaf has no subleaves indexed by ECX. 1189 */ 1190 if (entry->eax >= 0x8000001d && 1191 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1192 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1193 entry->eax = max(entry->eax, 0x80000021); 1194 break; 1195 case 0x80000001: 1196 entry->ebx &= ~GENMASK(27, 16); 1197 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1198 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1199 break; 1200 case 0x80000005: 1201 /* Pass host L1 cache and TLB info. */ 1202 break; 1203 case 0x80000006: 1204 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1205 entry->edx &= ~GENMASK(17, 16); 1206 break; 1207 case 0x80000007: /* Advanced power management */ 1208 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1209 1210 /* mask against host */ 1211 entry->edx &= boot_cpu_data.x86_power; 1212 entry->eax = entry->ebx = entry->ecx = 0; 1213 break; 1214 case 0x80000008: { 1215 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1216 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1217 unsigned phys_as = entry->eax & 0xff; 1218 1219 /* 1220 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1221 * the guest operates in the same PA space as the host, i.e. 1222 * reductions in MAXPHYADDR for memory encryption affect shadow 1223 * paging, too. 1224 * 1225 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1226 * provided, use the raw bare metal MAXPHYADDR as reductions to 1227 * the HPAs do not affect GPAs. 1228 */ 1229 if (!tdp_enabled) 1230 g_phys_as = boot_cpu_data.x86_phys_bits; 1231 else if (!g_phys_as) 1232 g_phys_as = phys_as; 1233 1234 entry->eax = g_phys_as | (virt_as << 8); 1235 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1236 entry->edx = 0; 1237 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1238 break; 1239 } 1240 case 0x8000000A: 1241 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1242 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1243 break; 1244 } 1245 entry->eax = 1; /* SVM revision 1 */ 1246 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1247 ASID emulation to nested SVM */ 1248 entry->ecx = 0; /* Reserved */ 1249 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1250 break; 1251 case 0x80000019: 1252 entry->ecx = entry->edx = 0; 1253 break; 1254 case 0x8000001a: 1255 entry->eax &= GENMASK(2, 0); 1256 entry->ebx = entry->ecx = entry->edx = 0; 1257 break; 1258 case 0x8000001e: 1259 /* Do not return host topology information. */ 1260 entry->eax = entry->ebx = entry->ecx = 0; 1261 entry->edx = 0; /* reserved */ 1262 break; 1263 case 0x8000001F: 1264 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1265 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1266 } else { 1267 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1268 /* Clear NumVMPL since KVM does not support VMPL. */ 1269 entry->ebx &= ~GENMASK(31, 12); 1270 /* 1271 * Enumerate '0' for "PA bits reduction", the adjusted 1272 * MAXPHYADDR is enumerated directly (see 0x80000008). 1273 */ 1274 entry->ebx &= ~GENMASK(11, 6); 1275 } 1276 break; 1277 case 0x80000020: 1278 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1279 break; 1280 case 0x80000021: 1281 entry->ebx = entry->ecx = entry->edx = 0; 1282 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1283 break; 1284 /* AMD Extended Performance Monitoring and Debug */ 1285 case 0x80000022: { 1286 union cpuid_0x80000022_ebx ebx; 1287 1288 entry->ecx = entry->edx = 0; 1289 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { 1290 entry->eax = entry->ebx; 1291 break; 1292 } 1293 1294 cpuid_entry_override(entry, CPUID_8000_0022_EAX); 1295 1296 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 1297 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; 1298 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) 1299 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; 1300 else 1301 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; 1302 1303 entry->ebx = ebx.full; 1304 break; 1305 } 1306 /*Add support for Centaur's CPUID instruction*/ 1307 case 0xC0000000: 1308 /*Just support up to 0xC0000004 now*/ 1309 entry->eax = min(entry->eax, 0xC0000004); 1310 break; 1311 case 0xC0000001: 1312 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1313 break; 1314 case 3: /* Processor serial number */ 1315 case 5: /* MONITOR/MWAIT */ 1316 case 0xC0000002: 1317 case 0xC0000003: 1318 case 0xC0000004: 1319 default: 1320 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1321 break; 1322 } 1323 1324 r = 0; 1325 1326 out: 1327 put_cpu(); 1328 1329 return r; 1330 } 1331 1332 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1333 unsigned int type) 1334 { 1335 if (type == KVM_GET_EMULATED_CPUID) 1336 return __do_cpuid_func_emulated(array, func); 1337 1338 return __do_cpuid_func(array, func); 1339 } 1340 1341 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1342 1343 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1344 unsigned int type) 1345 { 1346 u32 limit; 1347 int r; 1348 1349 if (func == CENTAUR_CPUID_SIGNATURE && 1350 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1351 return 0; 1352 1353 r = do_cpuid_func(array, func, type); 1354 if (r) 1355 return r; 1356 1357 limit = array->entries[array->nent - 1].eax; 1358 for (func = func + 1; func <= limit; ++func) { 1359 r = do_cpuid_func(array, func, type); 1360 if (r) 1361 break; 1362 } 1363 1364 return r; 1365 } 1366 1367 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1368 __u32 num_entries, unsigned int ioctl_type) 1369 { 1370 int i; 1371 __u32 pad[3]; 1372 1373 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1374 return false; 1375 1376 /* 1377 * We want to make sure that ->padding is being passed clean from 1378 * userspace in case we want to use it for something in the future. 1379 * 1380 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1381 * have to give ourselves satisfied only with the emulated side. /me 1382 * sheds a tear. 1383 */ 1384 for (i = 0; i < num_entries; i++) { 1385 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1386 return true; 1387 1388 if (pad[0] || pad[1] || pad[2]) 1389 return true; 1390 } 1391 return false; 1392 } 1393 1394 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1395 struct kvm_cpuid_entry2 __user *entries, 1396 unsigned int type) 1397 { 1398 static const u32 funcs[] = { 1399 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1400 }; 1401 1402 struct kvm_cpuid_array array = { 1403 .nent = 0, 1404 }; 1405 int r, i; 1406 1407 if (cpuid->nent < 1) 1408 return -E2BIG; 1409 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1410 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1411 1412 if (sanity_check_entries(entries, cpuid->nent, type)) 1413 return -EINVAL; 1414 1415 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1416 if (!array.entries) 1417 return -ENOMEM; 1418 1419 array.maxnent = cpuid->nent; 1420 1421 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1422 r = get_cpuid_func(&array, funcs[i], type); 1423 if (r) 1424 goto out_free; 1425 } 1426 cpuid->nent = array.nent; 1427 1428 if (copy_to_user(entries, array.entries, 1429 array.nent * sizeof(struct kvm_cpuid_entry2))) 1430 r = -EFAULT; 1431 1432 out_free: 1433 kvfree(array.entries); 1434 return r; 1435 } 1436 1437 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1438 u32 function, u32 index) 1439 { 1440 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1441 function, index); 1442 } 1443 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1444 1445 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1446 u32 function) 1447 { 1448 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1449 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1450 } 1451 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1452 1453 /* 1454 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1455 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1456 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1457 * range. Centaur/VIA follows Intel semantics. 1458 * 1459 * A leaf is considered out-of-range if its function is higher than the maximum 1460 * supported leaf of its associated class or if its associated class does not 1461 * exist. 1462 * 1463 * There are three primary classes to be considered, with their respective 1464 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1465 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1466 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1467 * 1468 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1469 * - Hypervisor: 0x40000000 - 0x4fffffff 1470 * - Extended: 0x80000000 - 0xbfffffff 1471 * - Centaur: 0xc0000000 - 0xcfffffff 1472 * 1473 * The Hypervisor class is further subdivided into sub-classes that each act as 1474 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1475 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1476 * CPUID sub-classes are: 1477 * 1478 * - HyperV: 0x40000000 - 0x400000ff 1479 * - KVM: 0x40000100 - 0x400001ff 1480 */ 1481 static struct kvm_cpuid_entry2 * 1482 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1483 { 1484 struct kvm_cpuid_entry2 *basic, *class; 1485 u32 function = *fn_ptr; 1486 1487 basic = kvm_find_cpuid_entry(vcpu, 0); 1488 if (!basic) 1489 return NULL; 1490 1491 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1492 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1493 return NULL; 1494 1495 if (function >= 0x40000000 && function <= 0x4fffffff) 1496 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1497 else if (function >= 0xc0000000) 1498 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1499 else 1500 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1501 1502 if (class && function <= class->eax) 1503 return NULL; 1504 1505 /* 1506 * Leaf specific adjustments are also applied when redirecting to the 1507 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1508 * entry for CPUID.0xb.index (see below), then the output value for EDX 1509 * needs to be pulled from CPUID.0xb.1. 1510 */ 1511 *fn_ptr = basic->eax; 1512 1513 /* 1514 * The class does not exist or the requested function is out of range; 1515 * the effective CPUID entry is the max basic leaf. Note, the index of 1516 * the original requested leaf is observed! 1517 */ 1518 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1519 } 1520 1521 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1522 u32 *ecx, u32 *edx, bool exact_only) 1523 { 1524 u32 orig_function = *eax, function = *eax, index = *ecx; 1525 struct kvm_cpuid_entry2 *entry; 1526 bool exact, used_max_basic = false; 1527 1528 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1529 exact = !!entry; 1530 1531 if (!entry && !exact_only) { 1532 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1533 used_max_basic = !!entry; 1534 } 1535 1536 if (entry) { 1537 *eax = entry->eax; 1538 *ebx = entry->ebx; 1539 *ecx = entry->ecx; 1540 *edx = entry->edx; 1541 if (function == 7 && index == 0) { 1542 u64 data; 1543 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1544 (data & TSX_CTRL_CPUID_CLEAR)) 1545 *ebx &= ~(F(RTM) | F(HLE)); 1546 } else if (function == 0x80000007) { 1547 if (kvm_hv_invtsc_suppressed(vcpu)) 1548 *edx &= ~SF(CONSTANT_TSC); 1549 } 1550 } else { 1551 *eax = *ebx = *ecx = *edx = 0; 1552 /* 1553 * When leaf 0BH or 1FH is defined, CL is pass-through 1554 * and EDX is always the x2APIC ID, even for undefined 1555 * subleaves. Index 1 will exist iff the leaf is 1556 * implemented, so we pass through CL iff leaf 1 1557 * exists. EDX can be copied from any existing index. 1558 */ 1559 if (function == 0xb || function == 0x1f) { 1560 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1561 if (entry) { 1562 *ecx = index & 0xff; 1563 *edx = entry->edx; 1564 } 1565 } 1566 } 1567 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1568 used_max_basic); 1569 return exact; 1570 } 1571 EXPORT_SYMBOL_GPL(kvm_cpuid); 1572 1573 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1574 { 1575 u32 eax, ebx, ecx, edx; 1576 1577 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1578 return 1; 1579 1580 eax = kvm_rax_read(vcpu); 1581 ecx = kvm_rcx_read(vcpu); 1582 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1583 kvm_rax_write(vcpu, eax); 1584 kvm_rbx_write(vcpu, ebx); 1585 kvm_rcx_write(vcpu, ecx); 1586 kvm_rdx_write(vcpu, edx); 1587 return kvm_skip_emulated_instruction(vcpu); 1588 } 1589 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1590