1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kvm_host.h> 14 #include "linux/lockdep.h" 15 #include <linux/export.h> 16 #include <linux/vmalloc.h> 17 #include <linux/uaccess.h> 18 #include <linux/sched/stat.h> 19 20 #include <asm/processor.h> 21 #include <asm/user.h> 22 #include <asm/fpu/xstate.h> 23 #include <asm/sgx.h> 24 #include <asm/cpuid.h> 25 #include "cpuid.h" 26 #include "lapic.h" 27 #include "mmu.h" 28 #include "trace.h" 29 #include "pmu.h" 30 #include "xen.h" 31 32 /* 33 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 34 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 35 */ 36 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 37 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 38 39 u32 xstate_required_size(u64 xstate_bv, bool compacted) 40 { 41 int feature_bit = 0; 42 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 43 44 xstate_bv &= XFEATURE_MASK_EXTEND; 45 while (xstate_bv) { 46 if (xstate_bv & 0x1) { 47 u32 eax, ebx, ecx, edx, offset; 48 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 49 /* ECX[1]: 64B alignment in compacted form */ 50 if (compacted) 51 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 52 else 53 offset = ebx; 54 ret = max(ret, offset + eax); 55 } 56 57 xstate_bv >>= 1; 58 feature_bit++; 59 } 60 61 return ret; 62 } 63 64 #define F feature_bit 65 66 /* Scattered Flag - For features that are scattered by cpufeatures.h. */ 67 #define SF(name) \ 68 ({ \ 69 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 70 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ 71 }) 72 73 /* 74 * Magic value used by KVM when querying userspace-provided CPUID entries and 75 * doesn't care about the CPIUD index because the index of the function in 76 * question is not significant. Note, this magic value must have at least one 77 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 78 * to avoid false positives when processing guest CPUID input. 79 */ 80 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 81 82 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 83 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 84 { 85 struct kvm_cpuid_entry2 *e; 86 int i; 87 88 /* 89 * KVM has a semi-arbitrary rule that querying the guest's CPUID model 90 * with IRQs disabled is disallowed. The CPUID model can legitimately 91 * have over one hundred entries, i.e. the lookup is slow, and IRQs are 92 * typically disabled in KVM only when KVM is in a performance critical 93 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break 94 * if this rule is violated, this assertion is purely to flag potential 95 * performance issues. If this fires, consider moving the lookup out 96 * of the hotpath, e.g. by caching information during CPUID updates. 97 */ 98 lockdep_assert_irqs_enabled(); 99 100 for (i = 0; i < nent; i++) { 101 e = &entries[i]; 102 103 if (e->function != function) 104 continue; 105 106 /* 107 * If the index isn't significant, use the first entry with a 108 * matching function. It's userspace's responsibilty to not 109 * provide "duplicate" entries in all cases. 110 */ 111 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 112 return e; 113 114 115 /* 116 * Similarly, use the first matching entry if KVM is doing a 117 * lookup (as opposed to emulating CPUID) for a function that's 118 * architecturally defined as not having a significant index. 119 */ 120 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 121 /* 122 * Direct lookups from KVM should not diverge from what 123 * KVM defines internally (the architectural behavior). 124 */ 125 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 126 return e; 127 } 128 } 129 130 return NULL; 131 } 132 133 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 134 struct kvm_cpuid_entry2 *entries, 135 int nent) 136 { 137 struct kvm_cpuid_entry2 *best; 138 u64 xfeatures; 139 140 /* 141 * The existing code assumes virtual address is 48-bit or 57-bit in the 142 * canonical address checks; exit if it is ever changed. 143 */ 144 best = cpuid_entry2_find(entries, nent, 0x80000008, 145 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 146 if (best) { 147 int vaddr_bits = (best->eax & 0xff00) >> 8; 148 149 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 150 return -EINVAL; 151 } 152 153 /* 154 * Exposing dynamic xfeatures to the guest requires additional 155 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 156 */ 157 best = cpuid_entry2_find(entries, nent, 0xd, 0); 158 if (!best) 159 return 0; 160 161 xfeatures = best->eax | ((u64)best->edx << 32); 162 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 163 if (!xfeatures) 164 return 0; 165 166 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 167 } 168 169 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 170 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 171 int nent) 172 { 173 struct kvm_cpuid_entry2 *orig; 174 int i; 175 176 if (nent != vcpu->arch.cpuid_nent) 177 return -EINVAL; 178 179 for (i = 0; i < nent; i++) { 180 orig = &vcpu->arch.cpuid_entries[i]; 181 if (e2[i].function != orig->function || 182 e2[i].index != orig->index || 183 e2[i].flags != orig->flags || 184 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 185 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 186 return -EINVAL; 187 } 188 189 return 0; 190 } 191 192 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 193 const char *sig) 194 { 195 struct kvm_hypervisor_cpuid cpuid = {}; 196 struct kvm_cpuid_entry2 *entry; 197 u32 base; 198 199 for_each_possible_hypervisor_cpuid_base(base) { 200 entry = kvm_find_cpuid_entry(vcpu, base); 201 202 if (entry) { 203 u32 signature[3]; 204 205 signature[0] = entry->ebx; 206 signature[1] = entry->ecx; 207 signature[2] = entry->edx; 208 209 if (!memcmp(signature, sig, sizeof(signature))) { 210 cpuid.base = base; 211 cpuid.limit = entry->eax; 212 break; 213 } 214 } 215 } 216 217 return cpuid; 218 } 219 220 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 221 struct kvm_cpuid_entry2 *entries, int nent) 222 { 223 u32 base = vcpu->arch.kvm_cpuid.base; 224 225 if (!base) 226 return NULL; 227 228 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 229 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 230 } 231 232 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 233 { 234 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 235 vcpu->arch.cpuid_nent); 236 } 237 238 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 239 { 240 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 241 242 /* 243 * save the feature bitmap to avoid cpuid lookup for every PV 244 * operation 245 */ 246 if (best) 247 vcpu->arch.pv_cpuid.features = best->eax; 248 } 249 250 /* 251 * Calculate guest's supported XCR0 taking into account guest CPUID data and 252 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 253 */ 254 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 255 { 256 struct kvm_cpuid_entry2 *best; 257 258 best = cpuid_entry2_find(entries, nent, 0xd, 0); 259 if (!best) 260 return 0; 261 262 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 263 } 264 265 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 266 int nent) 267 { 268 struct kvm_cpuid_entry2 *best; 269 270 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 271 if (best) { 272 /* Update OSXSAVE bit */ 273 if (boot_cpu_has(X86_FEATURE_XSAVE)) 274 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 275 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 276 277 cpuid_entry_change(best, X86_FEATURE_APIC, 278 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 279 } 280 281 best = cpuid_entry2_find(entries, nent, 7, 0); 282 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 283 cpuid_entry_change(best, X86_FEATURE_OSPKE, 284 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 285 286 best = cpuid_entry2_find(entries, nent, 0xD, 0); 287 if (best) 288 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 289 290 best = cpuid_entry2_find(entries, nent, 0xD, 1); 291 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 292 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 293 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 294 295 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 296 if (kvm_hlt_in_guest(vcpu->kvm) && best && 297 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 298 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 299 300 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 301 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 302 if (best) 303 cpuid_entry_change(best, X86_FEATURE_MWAIT, 304 vcpu->arch.ia32_misc_enable_msr & 305 MSR_IA32_MISC_ENABLE_MWAIT); 306 } 307 } 308 309 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 310 { 311 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 312 } 313 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 314 315 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) 316 { 317 struct kvm_cpuid_entry2 *entry; 318 319 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, 320 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 321 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 322 } 323 324 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 325 { 326 struct kvm_lapic *apic = vcpu->arch.apic; 327 struct kvm_cpuid_entry2 *best; 328 bool allow_gbpages; 329 330 BUILD_BUG_ON(KVM_NR_GOVERNED_FEATURES > KVM_MAX_NR_GOVERNED_FEATURES); 331 bitmap_zero(vcpu->arch.governed_features.enabled, 332 KVM_MAX_NR_GOVERNED_FEATURES); 333 334 /* 335 * If TDP is enabled, let the guest use GBPAGES if they're supported in 336 * hardware. The hardware page walker doesn't let KVM disable GBPAGES, 337 * i.e. won't treat them as reserved, and KVM doesn't redo the GVA->GPA 338 * walk for performance and complexity reasons. Not to mention KVM 339 * _can't_ solve the problem because GVA->GPA walks aren't visible to 340 * KVM once a TDP translation is installed. Mimic hardware behavior so 341 * that KVM's is at least consistent, i.e. doesn't randomly inject #PF. 342 * If TDP is disabled, honor *only* guest CPUID as KVM has full control 343 * and can install smaller shadow pages if the host lacks 1GiB support. 344 */ 345 allow_gbpages = tdp_enabled ? boot_cpu_has(X86_FEATURE_GBPAGES) : 346 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES); 347 if (allow_gbpages) 348 kvm_governed_feature_set(vcpu, X86_FEATURE_GBPAGES); 349 350 best = kvm_find_cpuid_entry(vcpu, 1); 351 if (best && apic) { 352 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 353 apic->lapic_timer.timer_mode_mask = 3 << 17; 354 else 355 apic->lapic_timer.timer_mode_mask = 1 << 17; 356 357 kvm_apic_set_version(vcpu); 358 } 359 360 vcpu->arch.guest_supported_xcr0 = 361 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 362 363 /* 364 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if 365 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't 366 * supported by the host. 367 */ 368 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 | 369 XFEATURE_MASK_FPSSE; 370 371 kvm_update_pv_runtime(vcpu); 372 373 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 374 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 375 376 kvm_pmu_refresh(vcpu); 377 vcpu->arch.cr4_guest_rsvd_bits = 378 __cr4_reserved_bits(guest_cpuid_has, vcpu); 379 380 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, 381 vcpu->arch.cpuid_nent)); 382 383 /* Invoke the vendor callback only after the above state is updated. */ 384 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 385 386 /* 387 * Except for the MMU, which needs to do its thing any vendor specific 388 * adjustments to the reserved GPA bits. 389 */ 390 kvm_mmu_after_set_cpuid(vcpu); 391 } 392 393 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 394 { 395 struct kvm_cpuid_entry2 *best; 396 397 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 398 if (!best || best->eax < 0x80000008) 399 goto not_found; 400 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 401 if (best) 402 return best->eax & 0xff; 403 not_found: 404 return 36; 405 } 406 407 /* 408 * This "raw" version returns the reserved GPA bits without any adjustments for 409 * encryption technologies that usurp bits. The raw mask should be used if and 410 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 411 */ 412 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 413 { 414 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 415 } 416 417 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 418 int nent) 419 { 420 int r; 421 422 __kvm_update_cpuid_runtime(vcpu, e2, nent); 423 424 /* 425 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 426 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 427 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 428 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 429 * the core vCPU model on the fly. It would've been better to forbid any 430 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 431 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 432 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 433 * whether the supplied CPUID data is equal to what's already set. 434 */ 435 if (kvm_vcpu_has_run(vcpu)) { 436 r = kvm_cpuid_check_equal(vcpu, e2, nent); 437 if (r) 438 return r; 439 440 kvfree(e2); 441 return 0; 442 } 443 444 if (kvm_cpuid_has_hyperv(e2, nent)) { 445 r = kvm_hv_vcpu_init(vcpu); 446 if (r) 447 return r; 448 } 449 450 r = kvm_check_cpuid(vcpu, e2, nent); 451 if (r) 452 return r; 453 454 kvfree(vcpu->arch.cpuid_entries); 455 vcpu->arch.cpuid_entries = e2; 456 vcpu->arch.cpuid_nent = nent; 457 458 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 459 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 460 kvm_vcpu_after_set_cpuid(vcpu); 461 462 return 0; 463 } 464 465 /* when an old userspace process fills a new kernel module */ 466 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 467 struct kvm_cpuid *cpuid, 468 struct kvm_cpuid_entry __user *entries) 469 { 470 int r, i; 471 struct kvm_cpuid_entry *e = NULL; 472 struct kvm_cpuid_entry2 *e2 = NULL; 473 474 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 475 return -E2BIG; 476 477 if (cpuid->nent) { 478 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 479 if (IS_ERR(e)) 480 return PTR_ERR(e); 481 482 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 483 if (!e2) { 484 r = -ENOMEM; 485 goto out_free_cpuid; 486 } 487 } 488 for (i = 0; i < cpuid->nent; i++) { 489 e2[i].function = e[i].function; 490 e2[i].eax = e[i].eax; 491 e2[i].ebx = e[i].ebx; 492 e2[i].ecx = e[i].ecx; 493 e2[i].edx = e[i].edx; 494 e2[i].index = 0; 495 e2[i].flags = 0; 496 e2[i].padding[0] = 0; 497 e2[i].padding[1] = 0; 498 e2[i].padding[2] = 0; 499 } 500 501 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 502 if (r) 503 kvfree(e2); 504 505 out_free_cpuid: 506 kvfree(e); 507 508 return r; 509 } 510 511 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 512 struct kvm_cpuid2 *cpuid, 513 struct kvm_cpuid_entry2 __user *entries) 514 { 515 struct kvm_cpuid_entry2 *e2 = NULL; 516 int r; 517 518 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 519 return -E2BIG; 520 521 if (cpuid->nent) { 522 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 523 if (IS_ERR(e2)) 524 return PTR_ERR(e2); 525 } 526 527 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 528 if (r) 529 kvfree(e2); 530 531 return r; 532 } 533 534 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 535 struct kvm_cpuid2 *cpuid, 536 struct kvm_cpuid_entry2 __user *entries) 537 { 538 if (cpuid->nent < vcpu->arch.cpuid_nent) 539 return -E2BIG; 540 541 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 542 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 543 return -EFAULT; 544 545 cpuid->nent = vcpu->arch.cpuid_nent; 546 return 0; 547 } 548 549 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 550 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 551 { 552 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 553 struct kvm_cpuid_entry2 entry; 554 555 reverse_cpuid_check(leaf); 556 557 cpuid_count(cpuid.function, cpuid.index, 558 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 559 560 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 561 } 562 563 static __always_inline 564 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) 565 { 566 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ 567 BUILD_BUG_ON(leaf < NCAPINTS); 568 569 kvm_cpu_caps[leaf] = mask; 570 571 __kvm_cpu_cap_mask(leaf); 572 } 573 574 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 575 { 576 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ 577 BUILD_BUG_ON(leaf >= NCAPINTS); 578 579 kvm_cpu_caps[leaf] &= mask; 580 581 __kvm_cpu_cap_mask(leaf); 582 } 583 584 void kvm_set_cpu_caps(void) 585 { 586 #ifdef CONFIG_X86_64 587 unsigned int f_gbpages = F(GBPAGES); 588 unsigned int f_lm = F(LM); 589 unsigned int f_xfd = F(XFD); 590 #else 591 unsigned int f_gbpages = 0; 592 unsigned int f_lm = 0; 593 unsigned int f_xfd = 0; 594 #endif 595 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 596 597 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 598 sizeof(boot_cpu_data.x86_capability)); 599 600 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 601 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 602 603 kvm_cpu_cap_mask(CPUID_1_ECX, 604 /* 605 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 606 * advertised to guests via CPUID! 607 */ 608 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 609 0 /* DS-CPL, VMX, SMX, EST */ | 610 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 611 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 612 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 613 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 614 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 615 F(F16C) | F(RDRAND) 616 ); 617 /* KVM emulates x2apic in software irrespective of host support. */ 618 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 619 620 kvm_cpu_cap_mask(CPUID_1_EDX, 621 F(FPU) | F(VME) | F(DE) | F(PSE) | 622 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 623 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 624 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 625 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 626 0 /* Reserved, DS, ACPI */ | F(MMX) | 627 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 628 0 /* HTT, TM, Reserved, PBE */ 629 ); 630 631 kvm_cpu_cap_mask(CPUID_7_0_EBX, 632 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 633 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 634 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 635 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 636 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 637 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 638 F(AVX512VL)); 639 640 kvm_cpu_cap_mask(CPUID_7_ECX, 641 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 642 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 643 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 644 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 645 F(SGX_LC) | F(BUS_LOCK_DETECT) 646 ); 647 /* Set LA57 based on hardware capability. */ 648 if (cpuid_ecx(7) & F(LA57)) 649 kvm_cpu_cap_set(X86_FEATURE_LA57); 650 651 /* 652 * PKU not yet implemented for shadow paging and requires OSPKE 653 * to be set on the host. Clear it if that is not the case 654 */ 655 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 656 kvm_cpu_cap_clear(X86_FEATURE_PKU); 657 658 kvm_cpu_cap_mask(CPUID_7_EDX, 659 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 660 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 661 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 662 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 663 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) 664 ); 665 666 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 667 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 668 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 669 670 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 671 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 672 if (boot_cpu_has(X86_FEATURE_STIBP)) 673 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 674 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 675 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 676 677 kvm_cpu_cap_mask(CPUID_7_1_EAX, 678 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | 679 F(FZRM) | F(FSRS) | F(FSRC) | 680 F(AMX_FP16) | F(AVX_IFMA) 681 ); 682 683 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, 684 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) | 685 F(AMX_COMPLEX) 686 ); 687 688 kvm_cpu_cap_mask(CPUID_D_1_EAX, 689 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 690 ); 691 692 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, 693 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) 694 ); 695 696 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 697 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 698 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 699 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 700 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 701 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 702 ); 703 704 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 705 F(FPU) | F(VME) | F(DE) | F(PSE) | 706 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 707 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 708 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 709 F(PAT) | F(PSE36) | 0 /* Reserved */ | 710 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 711 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 712 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 713 ); 714 715 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 716 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 717 718 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, 719 SF(CONSTANT_TSC) 720 ); 721 722 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 723 F(CLZERO) | F(XSAVEERPTR) | 724 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 725 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 726 F(AMD_PSFD) 727 ); 728 729 /* 730 * AMD has separate bits for each SPEC_CTRL bit. 731 * arch/x86/kernel/cpu/bugs.c is kind enough to 732 * record that in cpufeatures so use them. 733 */ 734 if (boot_cpu_has(X86_FEATURE_IBPB)) 735 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 736 if (boot_cpu_has(X86_FEATURE_IBRS)) 737 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 738 if (boot_cpu_has(X86_FEATURE_STIBP)) 739 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 740 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 741 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 742 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 743 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 744 /* 745 * The preference is to use SPEC CTRL MSR instead of the 746 * VIRT_SPEC MSR. 747 */ 748 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 749 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 750 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 751 752 /* 753 * Hide all SVM features by default, SVM will set the cap bits for 754 * features it emulates and/or exposes for L1. 755 */ 756 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 757 758 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 759 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 760 F(SME_COHERENT)); 761 762 kvm_cpu_cap_mask(CPUID_8000_0021_EAX, 763 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | 764 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ 765 ); 766 767 if (cpu_feature_enabled(X86_FEATURE_SRSO_NO)) 768 kvm_cpu_cap_set(X86_FEATURE_SRSO_NO); 769 770 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, 771 F(PERFMON_V2) 772 ); 773 774 /* 775 * Synthesize "LFENCE is serializing" into the AMD-defined entry in 776 * KVM's supported CPUID if the feature is reported as supported by the 777 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long 778 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most 779 * CPUs that support SSE2. On CPUs that don't support AMD's leaf, 780 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing 781 * the mask with the raw host CPUID, and reporting support in AMD's 782 * leaf can make it easier for userspace to detect the feature. 783 */ 784 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 785 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); 786 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 787 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 788 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); 789 790 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 791 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 792 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 793 F(PMM) | F(PMM_EN) 794 ); 795 796 /* 797 * Hide RDTSCP and RDPID if either feature is reported as supported but 798 * probing MSR_TSC_AUX failed. This is purely a sanity check and 799 * should never happen, but the guest will likely crash if RDTSCP or 800 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 801 * the past. For example, the sanity check may fire if this instance of 802 * KVM is running as L1 on top of an older, broken KVM. 803 */ 804 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 805 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 806 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 807 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 808 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 809 } 810 } 811 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 812 813 struct kvm_cpuid_array { 814 struct kvm_cpuid_entry2 *entries; 815 int maxnent; 816 int nent; 817 }; 818 819 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 820 { 821 if (array->nent >= array->maxnent) 822 return NULL; 823 824 return &array->entries[array->nent++]; 825 } 826 827 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 828 u32 function, u32 index) 829 { 830 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 831 832 if (!entry) 833 return NULL; 834 835 memset(entry, 0, sizeof(*entry)); 836 entry->function = function; 837 entry->index = index; 838 switch (function & 0xC0000000) { 839 case 0x40000000: 840 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 841 return entry; 842 843 case 0x80000000: 844 /* 845 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 846 * would result in out-of-bounds calls to do_host_cpuid. 847 */ 848 { 849 static int max_cpuid_80000000; 850 if (!READ_ONCE(max_cpuid_80000000)) 851 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 852 if (function > READ_ONCE(max_cpuid_80000000)) 853 return entry; 854 } 855 break; 856 857 default: 858 break; 859 } 860 861 cpuid_count(entry->function, entry->index, 862 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 863 864 if (cpuid_function_is_indexed(function)) 865 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 866 867 return entry; 868 } 869 870 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 871 { 872 struct kvm_cpuid_entry2 *entry; 873 874 if (array->nent >= array->maxnent) 875 return -E2BIG; 876 877 entry = &array->entries[array->nent]; 878 entry->function = func; 879 entry->index = 0; 880 entry->flags = 0; 881 882 switch (func) { 883 case 0: 884 entry->eax = 7; 885 ++array->nent; 886 break; 887 case 1: 888 entry->ecx = F(MOVBE); 889 ++array->nent; 890 break; 891 case 7: 892 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 893 entry->eax = 0; 894 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 895 entry->ecx = F(RDPID); 896 ++array->nent; 897 break; 898 default: 899 break; 900 } 901 902 return 0; 903 } 904 905 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 906 { 907 struct kvm_cpuid_entry2 *entry; 908 int r, i, max_idx; 909 910 /* all calls to cpuid_count() should be made on the same cpu */ 911 get_cpu(); 912 913 r = -E2BIG; 914 915 entry = do_host_cpuid(array, function, 0); 916 if (!entry) 917 goto out; 918 919 switch (function) { 920 case 0: 921 /* Limited to the highest leaf implemented in KVM. */ 922 entry->eax = min(entry->eax, 0x1fU); 923 break; 924 case 1: 925 cpuid_entry_override(entry, CPUID_1_EDX); 926 cpuid_entry_override(entry, CPUID_1_ECX); 927 break; 928 case 2: 929 /* 930 * On ancient CPUs, function 2 entries are STATEFUL. That is, 931 * CPUID(function=2, index=0) may return different results each 932 * time, with the least-significant byte in EAX enumerating the 933 * number of times software should do CPUID(2, 0). 934 * 935 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 936 * idiotic. Intel's SDM states that EAX & 0xff "will always 937 * return 01H. Software should ignore this value and not 938 * interpret it as an informational descriptor", while AMD's 939 * APM states that CPUID(2) is reserved. 940 * 941 * WARN if a frankenstein CPU that supports virtualization and 942 * a stateful CPUID.0x2 is encountered. 943 */ 944 WARN_ON_ONCE((entry->eax & 0xff) > 1); 945 break; 946 /* functions 4 and 0x8000001d have additional index. */ 947 case 4: 948 case 0x8000001d: 949 /* 950 * Read entries until the cache type in the previous entry is 951 * zero, i.e. indicates an invalid entry. 952 */ 953 for (i = 1; entry->eax & 0x1f; ++i) { 954 entry = do_host_cpuid(array, function, i); 955 if (!entry) 956 goto out; 957 } 958 break; 959 case 6: /* Thermal management */ 960 entry->eax = 0x4; /* allow ARAT */ 961 entry->ebx = 0; 962 entry->ecx = 0; 963 entry->edx = 0; 964 break; 965 /* function 7 has additional index. */ 966 case 7: 967 entry->eax = min(entry->eax, 1u); 968 cpuid_entry_override(entry, CPUID_7_0_EBX); 969 cpuid_entry_override(entry, CPUID_7_ECX); 970 cpuid_entry_override(entry, CPUID_7_EDX); 971 972 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 973 if (entry->eax == 1) { 974 entry = do_host_cpuid(array, function, 1); 975 if (!entry) 976 goto out; 977 978 cpuid_entry_override(entry, CPUID_7_1_EAX); 979 cpuid_entry_override(entry, CPUID_7_1_EDX); 980 entry->ebx = 0; 981 entry->ecx = 0; 982 } 983 break; 984 case 0xa: { /* Architectural Performance Monitoring */ 985 union cpuid10_eax eax; 986 union cpuid10_edx edx; 987 988 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 989 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 990 break; 991 } 992 993 eax.split.version_id = kvm_pmu_cap.version; 994 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 995 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 996 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 997 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 998 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 999 1000 if (kvm_pmu_cap.version) 1001 edx.split.anythread_deprecated = 1; 1002 edx.split.reserved1 = 0; 1003 edx.split.reserved2 = 0; 1004 1005 entry->eax = eax.full; 1006 entry->ebx = kvm_pmu_cap.events_mask; 1007 entry->ecx = 0; 1008 entry->edx = edx.full; 1009 break; 1010 } 1011 case 0x1f: 1012 case 0xb: 1013 /* 1014 * No topology; a valid topology is indicated by the presence 1015 * of subleaf 1. 1016 */ 1017 entry->eax = entry->ebx = entry->ecx = 0; 1018 break; 1019 case 0xd: { 1020 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 1021 u64 permitted_xss = kvm_caps.supported_xss; 1022 1023 entry->eax &= permitted_xcr0; 1024 entry->ebx = xstate_required_size(permitted_xcr0, false); 1025 entry->ecx = entry->ebx; 1026 entry->edx &= permitted_xcr0 >> 32; 1027 if (!permitted_xcr0) 1028 break; 1029 1030 entry = do_host_cpuid(array, function, 1); 1031 if (!entry) 1032 goto out; 1033 1034 cpuid_entry_override(entry, CPUID_D_1_EAX); 1035 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 1036 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1037 true); 1038 else { 1039 WARN_ON_ONCE(permitted_xss != 0); 1040 entry->ebx = 0; 1041 } 1042 entry->ecx &= permitted_xss; 1043 entry->edx &= permitted_xss >> 32; 1044 1045 for (i = 2; i < 64; ++i) { 1046 bool s_state; 1047 if (permitted_xcr0 & BIT_ULL(i)) 1048 s_state = false; 1049 else if (permitted_xss & BIT_ULL(i)) 1050 s_state = true; 1051 else 1052 continue; 1053 1054 entry = do_host_cpuid(array, function, i); 1055 if (!entry) 1056 goto out; 1057 1058 /* 1059 * The supported check above should have filtered out 1060 * invalid sub-leafs. Only valid sub-leafs should 1061 * reach this point, and they should have a non-zero 1062 * save state size. Furthermore, check whether the 1063 * processor agrees with permitted_xcr0/permitted_xss 1064 * on whether this is an XCR0- or IA32_XSS-managed area. 1065 */ 1066 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1067 --array->nent; 1068 continue; 1069 } 1070 1071 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1072 entry->ecx &= ~BIT_ULL(2); 1073 entry->edx = 0; 1074 } 1075 break; 1076 } 1077 case 0x12: 1078 /* Intel SGX */ 1079 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1080 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1081 break; 1082 } 1083 1084 /* 1085 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1086 * and max enclave sizes. The SGX sub-features and MISCSELECT 1087 * are restricted by kernel and KVM capabilities (like most 1088 * feature flags), while enclave size is unrestricted. 1089 */ 1090 cpuid_entry_override(entry, CPUID_12_EAX); 1091 entry->ebx &= SGX_MISC_EXINFO; 1092 1093 entry = do_host_cpuid(array, function, 1); 1094 if (!entry) 1095 goto out; 1096 1097 /* 1098 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1099 * feature flags. Advertise all supported flags, including 1100 * privileged attributes that require explicit opt-in from 1101 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1102 * expected to derive it from supported XCR0. 1103 */ 1104 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1105 entry->ebx &= 0; 1106 break; 1107 /* Intel PT */ 1108 case 0x14: 1109 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1110 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1111 break; 1112 } 1113 1114 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1115 if (!do_host_cpuid(array, function, i)) 1116 goto out; 1117 } 1118 break; 1119 /* Intel AMX TILE */ 1120 case 0x1d: 1121 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1122 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1123 break; 1124 } 1125 1126 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1127 if (!do_host_cpuid(array, function, i)) 1128 goto out; 1129 } 1130 break; 1131 case 0x1e: /* TMUL information */ 1132 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1133 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1134 break; 1135 } 1136 break; 1137 case KVM_CPUID_SIGNATURE: { 1138 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1139 entry->eax = KVM_CPUID_FEATURES; 1140 entry->ebx = sigptr[0]; 1141 entry->ecx = sigptr[1]; 1142 entry->edx = sigptr[2]; 1143 break; 1144 } 1145 case KVM_CPUID_FEATURES: 1146 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1147 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1148 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1149 (1 << KVM_FEATURE_ASYNC_PF) | 1150 (1 << KVM_FEATURE_PV_EOI) | 1151 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1152 (1 << KVM_FEATURE_PV_UNHALT) | 1153 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1154 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1155 (1 << KVM_FEATURE_PV_SEND_IPI) | 1156 (1 << KVM_FEATURE_POLL_CONTROL) | 1157 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1158 (1 << KVM_FEATURE_ASYNC_PF_INT); 1159 1160 if (sched_info_on()) 1161 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1162 1163 entry->ebx = 0; 1164 entry->ecx = 0; 1165 entry->edx = 0; 1166 break; 1167 case 0x80000000: 1168 entry->eax = min(entry->eax, 0x80000022); 1169 /* 1170 * Serializing LFENCE is reported in a multitude of ways, and 1171 * NullSegClearsBase is not reported in CPUID on Zen2; help 1172 * userspace by providing the CPUID leaf ourselves. 1173 * 1174 * However, only do it if the host has CPUID leaf 0x8000001d. 1175 * QEMU thinks that it can query the host blindly for that 1176 * CPUID leaf if KVM reports that it supports 0x8000001d or 1177 * above. The processor merrily returns values from the 1178 * highest Intel leaf which QEMU tries to use as the guest's 1179 * 0x8000001d. Even worse, this can result in an infinite 1180 * loop if said highest leaf has no subleaves indexed by ECX. 1181 */ 1182 if (entry->eax >= 0x8000001d && 1183 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1184 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1185 entry->eax = max(entry->eax, 0x80000021); 1186 break; 1187 case 0x80000001: 1188 entry->ebx &= ~GENMASK(27, 16); 1189 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1190 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1191 break; 1192 case 0x80000005: 1193 /* Pass host L1 cache and TLB info. */ 1194 break; 1195 case 0x80000006: 1196 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1197 entry->edx &= ~GENMASK(17, 16); 1198 break; 1199 case 0x80000007: /* Advanced power management */ 1200 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1201 1202 /* mask against host */ 1203 entry->edx &= boot_cpu_data.x86_power; 1204 entry->eax = entry->ebx = entry->ecx = 0; 1205 break; 1206 case 0x80000008: { 1207 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1208 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1209 unsigned phys_as = entry->eax & 0xff; 1210 1211 /* 1212 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1213 * the guest operates in the same PA space as the host, i.e. 1214 * reductions in MAXPHYADDR for memory encryption affect shadow 1215 * paging, too. 1216 * 1217 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1218 * provided, use the raw bare metal MAXPHYADDR as reductions to 1219 * the HPAs do not affect GPAs. 1220 */ 1221 if (!tdp_enabled) 1222 g_phys_as = boot_cpu_data.x86_phys_bits; 1223 else if (!g_phys_as) 1224 g_phys_as = phys_as; 1225 1226 entry->eax = g_phys_as | (virt_as << 8); 1227 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1228 entry->edx = 0; 1229 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1230 break; 1231 } 1232 case 0x8000000A: 1233 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1234 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1235 break; 1236 } 1237 entry->eax = 1; /* SVM revision 1 */ 1238 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1239 ASID emulation to nested SVM */ 1240 entry->ecx = 0; /* Reserved */ 1241 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1242 break; 1243 case 0x80000019: 1244 entry->ecx = entry->edx = 0; 1245 break; 1246 case 0x8000001a: 1247 entry->eax &= GENMASK(2, 0); 1248 entry->ebx = entry->ecx = entry->edx = 0; 1249 break; 1250 case 0x8000001e: 1251 /* Do not return host topology information. */ 1252 entry->eax = entry->ebx = entry->ecx = 0; 1253 entry->edx = 0; /* reserved */ 1254 break; 1255 case 0x8000001F: 1256 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1257 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1258 } else { 1259 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1260 /* Clear NumVMPL since KVM does not support VMPL. */ 1261 entry->ebx &= ~GENMASK(31, 12); 1262 /* 1263 * Enumerate '0' for "PA bits reduction", the adjusted 1264 * MAXPHYADDR is enumerated directly (see 0x80000008). 1265 */ 1266 entry->ebx &= ~GENMASK(11, 6); 1267 } 1268 break; 1269 case 0x80000020: 1270 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1271 break; 1272 case 0x80000021: 1273 entry->ebx = entry->ecx = entry->edx = 0; 1274 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1275 break; 1276 /* AMD Extended Performance Monitoring and Debug */ 1277 case 0x80000022: { 1278 union cpuid_0x80000022_ebx ebx; 1279 1280 entry->ecx = entry->edx = 0; 1281 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { 1282 entry->eax = entry->ebx; 1283 break; 1284 } 1285 1286 cpuid_entry_override(entry, CPUID_8000_0022_EAX); 1287 1288 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 1289 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; 1290 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) 1291 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; 1292 else 1293 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; 1294 1295 entry->ebx = ebx.full; 1296 break; 1297 } 1298 /*Add support for Centaur's CPUID instruction*/ 1299 case 0xC0000000: 1300 /*Just support up to 0xC0000004 now*/ 1301 entry->eax = min(entry->eax, 0xC0000004); 1302 break; 1303 case 0xC0000001: 1304 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1305 break; 1306 case 3: /* Processor serial number */ 1307 case 5: /* MONITOR/MWAIT */ 1308 case 0xC0000002: 1309 case 0xC0000003: 1310 case 0xC0000004: 1311 default: 1312 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1313 break; 1314 } 1315 1316 r = 0; 1317 1318 out: 1319 put_cpu(); 1320 1321 return r; 1322 } 1323 1324 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1325 unsigned int type) 1326 { 1327 if (type == KVM_GET_EMULATED_CPUID) 1328 return __do_cpuid_func_emulated(array, func); 1329 1330 return __do_cpuid_func(array, func); 1331 } 1332 1333 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1334 1335 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1336 unsigned int type) 1337 { 1338 u32 limit; 1339 int r; 1340 1341 if (func == CENTAUR_CPUID_SIGNATURE && 1342 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1343 return 0; 1344 1345 r = do_cpuid_func(array, func, type); 1346 if (r) 1347 return r; 1348 1349 limit = array->entries[array->nent - 1].eax; 1350 for (func = func + 1; func <= limit; ++func) { 1351 r = do_cpuid_func(array, func, type); 1352 if (r) 1353 break; 1354 } 1355 1356 return r; 1357 } 1358 1359 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1360 __u32 num_entries, unsigned int ioctl_type) 1361 { 1362 int i; 1363 __u32 pad[3]; 1364 1365 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1366 return false; 1367 1368 /* 1369 * We want to make sure that ->padding is being passed clean from 1370 * userspace in case we want to use it for something in the future. 1371 * 1372 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1373 * have to give ourselves satisfied only with the emulated side. /me 1374 * sheds a tear. 1375 */ 1376 for (i = 0; i < num_entries; i++) { 1377 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1378 return true; 1379 1380 if (pad[0] || pad[1] || pad[2]) 1381 return true; 1382 } 1383 return false; 1384 } 1385 1386 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1387 struct kvm_cpuid_entry2 __user *entries, 1388 unsigned int type) 1389 { 1390 static const u32 funcs[] = { 1391 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1392 }; 1393 1394 struct kvm_cpuid_array array = { 1395 .nent = 0, 1396 }; 1397 int r, i; 1398 1399 if (cpuid->nent < 1) 1400 return -E2BIG; 1401 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1402 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1403 1404 if (sanity_check_entries(entries, cpuid->nent, type)) 1405 return -EINVAL; 1406 1407 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1408 if (!array.entries) 1409 return -ENOMEM; 1410 1411 array.maxnent = cpuid->nent; 1412 1413 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1414 r = get_cpuid_func(&array, funcs[i], type); 1415 if (r) 1416 goto out_free; 1417 } 1418 cpuid->nent = array.nent; 1419 1420 if (copy_to_user(entries, array.entries, 1421 array.nent * sizeof(struct kvm_cpuid_entry2))) 1422 r = -EFAULT; 1423 1424 out_free: 1425 kvfree(array.entries); 1426 return r; 1427 } 1428 1429 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1430 u32 function, u32 index) 1431 { 1432 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1433 function, index); 1434 } 1435 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1436 1437 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1438 u32 function) 1439 { 1440 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1441 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1442 } 1443 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1444 1445 /* 1446 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1447 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1448 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1449 * range. Centaur/VIA follows Intel semantics. 1450 * 1451 * A leaf is considered out-of-range if its function is higher than the maximum 1452 * supported leaf of its associated class or if its associated class does not 1453 * exist. 1454 * 1455 * There are three primary classes to be considered, with their respective 1456 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1457 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1458 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1459 * 1460 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1461 * - Hypervisor: 0x40000000 - 0x4fffffff 1462 * - Extended: 0x80000000 - 0xbfffffff 1463 * - Centaur: 0xc0000000 - 0xcfffffff 1464 * 1465 * The Hypervisor class is further subdivided into sub-classes that each act as 1466 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1467 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1468 * CPUID sub-classes are: 1469 * 1470 * - HyperV: 0x40000000 - 0x400000ff 1471 * - KVM: 0x40000100 - 0x400001ff 1472 */ 1473 static struct kvm_cpuid_entry2 * 1474 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1475 { 1476 struct kvm_cpuid_entry2 *basic, *class; 1477 u32 function = *fn_ptr; 1478 1479 basic = kvm_find_cpuid_entry(vcpu, 0); 1480 if (!basic) 1481 return NULL; 1482 1483 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1484 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1485 return NULL; 1486 1487 if (function >= 0x40000000 && function <= 0x4fffffff) 1488 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1489 else if (function >= 0xc0000000) 1490 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1491 else 1492 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1493 1494 if (class && function <= class->eax) 1495 return NULL; 1496 1497 /* 1498 * Leaf specific adjustments are also applied when redirecting to the 1499 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1500 * entry for CPUID.0xb.index (see below), then the output value for EDX 1501 * needs to be pulled from CPUID.0xb.1. 1502 */ 1503 *fn_ptr = basic->eax; 1504 1505 /* 1506 * The class does not exist or the requested function is out of range; 1507 * the effective CPUID entry is the max basic leaf. Note, the index of 1508 * the original requested leaf is observed! 1509 */ 1510 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1511 } 1512 1513 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1514 u32 *ecx, u32 *edx, bool exact_only) 1515 { 1516 u32 orig_function = *eax, function = *eax, index = *ecx; 1517 struct kvm_cpuid_entry2 *entry; 1518 bool exact, used_max_basic = false; 1519 1520 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1521 exact = !!entry; 1522 1523 if (!entry && !exact_only) { 1524 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1525 used_max_basic = !!entry; 1526 } 1527 1528 if (entry) { 1529 *eax = entry->eax; 1530 *ebx = entry->ebx; 1531 *ecx = entry->ecx; 1532 *edx = entry->edx; 1533 if (function == 7 && index == 0) { 1534 u64 data; 1535 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1536 (data & TSX_CTRL_CPUID_CLEAR)) 1537 *ebx &= ~(F(RTM) | F(HLE)); 1538 } else if (function == 0x80000007) { 1539 if (kvm_hv_invtsc_suppressed(vcpu)) 1540 *edx &= ~SF(CONSTANT_TSC); 1541 } 1542 } else { 1543 *eax = *ebx = *ecx = *edx = 0; 1544 /* 1545 * When leaf 0BH or 1FH is defined, CL is pass-through 1546 * and EDX is always the x2APIC ID, even for undefined 1547 * subleaves. Index 1 will exist iff the leaf is 1548 * implemented, so we pass through CL iff leaf 1 1549 * exists. EDX can be copied from any existing index. 1550 */ 1551 if (function == 0xb || function == 0x1f) { 1552 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1553 if (entry) { 1554 *ecx = index & 0xff; 1555 *edx = entry->edx; 1556 } 1557 } 1558 } 1559 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1560 used_max_basic); 1561 return exact; 1562 } 1563 EXPORT_SYMBOL_GPL(kvm_cpuid); 1564 1565 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1566 { 1567 u32 eax, ebx, ecx, edx; 1568 1569 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1570 return 1; 1571 1572 eax = kvm_rax_read(vcpu); 1573 ecx = kvm_rcx_read(vcpu); 1574 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1575 kvm_rax_write(vcpu, eax); 1576 kvm_rbx_write(vcpu, ebx); 1577 kvm_rcx_write(vcpu, ecx); 1578 kvm_rdx_write(vcpu, edx); 1579 return kvm_skip_emulated_instruction(vcpu); 1580 } 1581 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1582