1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include "cpuid.h" 22 #include "lapic.h" 23 #include "mmu.h" 24 #include "trace.h" 25 #include "pmu.h" 26 27 /* 28 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 29 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 30 */ 31 u32 kvm_cpu_caps[NCAPINTS] __read_mostly; 32 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 33 34 static u32 xstate_required_size(u64 xstate_bv, bool compacted) 35 { 36 int feature_bit = 0; 37 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 38 39 xstate_bv &= XFEATURE_MASK_EXTEND; 40 while (xstate_bv) { 41 if (xstate_bv & 0x1) { 42 u32 eax, ebx, ecx, edx, offset; 43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 44 offset = compacted ? ret : ebx; 45 ret = max(ret, offset + eax); 46 } 47 48 xstate_bv >>= 1; 49 feature_bit++; 50 } 51 52 return ret; 53 } 54 55 #define F feature_bit 56 57 static int kvm_check_cpuid(struct kvm_vcpu *vcpu) 58 { 59 struct kvm_cpuid_entry2 *best; 60 61 /* 62 * The existing code assumes virtual address is 48-bit or 57-bit in the 63 * canonical address checks; exit if it is ever changed. 64 */ 65 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 66 if (best) { 67 int vaddr_bits = (best->eax & 0xff00) >> 8; 68 69 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 70 return -EINVAL; 71 } 72 73 return 0; 74 } 75 76 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 77 { 78 struct kvm_cpuid_entry2 *best; 79 80 best = kvm_find_cpuid_entry(vcpu, 1, 0); 81 if (best) { 82 /* Update OSXSAVE bit */ 83 if (boot_cpu_has(X86_FEATURE_XSAVE)) 84 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 85 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 86 87 cpuid_entry_change(best, X86_FEATURE_APIC, 88 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 89 } 90 91 best = kvm_find_cpuid_entry(vcpu, 7, 0); 92 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 93 cpuid_entry_change(best, X86_FEATURE_OSPKE, 94 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 95 96 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 97 if (best) 98 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 99 100 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 101 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 102 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 103 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 104 105 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 106 if (kvm_hlt_in_guest(vcpu->kvm) && best && 107 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 108 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 109 110 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 111 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 112 if (best) 113 cpuid_entry_change(best, X86_FEATURE_MWAIT, 114 vcpu->arch.ia32_misc_enable_msr & 115 MSR_IA32_MISC_ENABLE_MWAIT); 116 } 117 } 118 119 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 120 { 121 struct kvm_lapic *apic = vcpu->arch.apic; 122 struct kvm_cpuid_entry2 *best; 123 124 kvm_x86_ops.vcpu_after_set_cpuid(vcpu); 125 126 best = kvm_find_cpuid_entry(vcpu, 1, 0); 127 if (best && apic) { 128 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 129 apic->lapic_timer.timer_mode_mask = 3 << 17; 130 else 131 apic->lapic_timer.timer_mode_mask = 1 << 17; 132 133 kvm_apic_set_version(vcpu); 134 } 135 136 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 137 if (!best) 138 vcpu->arch.guest_supported_xcr0 = 0; 139 else 140 vcpu->arch.guest_supported_xcr0 = 141 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 142 143 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 144 kvm_mmu_reset_context(vcpu); 145 146 kvm_pmu_refresh(vcpu); 147 vcpu->arch.cr4_guest_rsvd_bits = 148 __cr4_reserved_bits(guest_cpuid_has, vcpu); 149 kvm_x86_ops.update_exception_bitmap(vcpu); 150 } 151 152 static int is_efer_nx(void) 153 { 154 return host_efer & EFER_NX; 155 } 156 157 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) 158 { 159 int i; 160 struct kvm_cpuid_entry2 *e, *entry; 161 162 entry = NULL; 163 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 164 e = &vcpu->arch.cpuid_entries[i]; 165 if (e->function == 0x80000001) { 166 entry = e; 167 break; 168 } 169 } 170 if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { 171 cpuid_entry_clear(entry, X86_FEATURE_NX); 172 printk(KERN_INFO "kvm: guest NX capability removed\n"); 173 } 174 } 175 176 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 177 { 178 struct kvm_cpuid_entry2 *best; 179 180 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 181 if (!best || best->eax < 0x80000008) 182 goto not_found; 183 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 184 if (best) 185 return best->eax & 0xff; 186 not_found: 187 return 36; 188 } 189 EXPORT_SYMBOL_GPL(cpuid_query_maxphyaddr); 190 191 /* when an old userspace process fills a new kernel module */ 192 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 193 struct kvm_cpuid *cpuid, 194 struct kvm_cpuid_entry __user *entries) 195 { 196 int r, i; 197 struct kvm_cpuid_entry *cpuid_entries = NULL; 198 199 r = -E2BIG; 200 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 201 goto out; 202 if (cpuid->nent) { 203 cpuid_entries = vmemdup_user(entries, 204 array_size(sizeof(struct kvm_cpuid_entry), 205 cpuid->nent)); 206 if (IS_ERR(cpuid_entries)) { 207 r = PTR_ERR(cpuid_entries); 208 goto out; 209 } 210 } 211 for (i = 0; i < cpuid->nent; i++) { 212 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function; 213 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax; 214 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx; 215 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx; 216 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx; 217 vcpu->arch.cpuid_entries[i].index = 0; 218 vcpu->arch.cpuid_entries[i].flags = 0; 219 vcpu->arch.cpuid_entries[i].padding[0] = 0; 220 vcpu->arch.cpuid_entries[i].padding[1] = 0; 221 vcpu->arch.cpuid_entries[i].padding[2] = 0; 222 } 223 vcpu->arch.cpuid_nent = cpuid->nent; 224 r = kvm_check_cpuid(vcpu); 225 if (r) { 226 vcpu->arch.cpuid_nent = 0; 227 kvfree(cpuid_entries); 228 goto out; 229 } 230 231 cpuid_fix_nx_cap(vcpu); 232 kvm_update_cpuid_runtime(vcpu); 233 kvm_vcpu_after_set_cpuid(vcpu); 234 235 kvfree(cpuid_entries); 236 out: 237 return r; 238 } 239 240 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 241 struct kvm_cpuid2 *cpuid, 242 struct kvm_cpuid_entry2 __user *entries) 243 { 244 int r; 245 246 r = -E2BIG; 247 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 248 goto out; 249 r = -EFAULT; 250 if (copy_from_user(&vcpu->arch.cpuid_entries, entries, 251 cpuid->nent * sizeof(struct kvm_cpuid_entry2))) 252 goto out; 253 vcpu->arch.cpuid_nent = cpuid->nent; 254 r = kvm_check_cpuid(vcpu); 255 if (r) { 256 vcpu->arch.cpuid_nent = 0; 257 goto out; 258 } 259 260 kvm_update_cpuid_runtime(vcpu); 261 kvm_vcpu_after_set_cpuid(vcpu); 262 out: 263 return r; 264 } 265 266 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 267 struct kvm_cpuid2 *cpuid, 268 struct kvm_cpuid_entry2 __user *entries) 269 { 270 int r; 271 272 r = -E2BIG; 273 if (cpuid->nent < vcpu->arch.cpuid_nent) 274 goto out; 275 r = -EFAULT; 276 if (copy_to_user(entries, &vcpu->arch.cpuid_entries, 277 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 278 goto out; 279 return 0; 280 281 out: 282 cpuid->nent = vcpu->arch.cpuid_nent; 283 return r; 284 } 285 286 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 287 { 288 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 289 struct kvm_cpuid_entry2 entry; 290 291 reverse_cpuid_check(leaf); 292 kvm_cpu_caps[leaf] &= mask; 293 294 cpuid_count(cpuid.function, cpuid.index, 295 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 296 297 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 298 } 299 300 void kvm_set_cpu_caps(void) 301 { 302 unsigned int f_nx = is_efer_nx() ? F(NX) : 0; 303 #ifdef CONFIG_X86_64 304 unsigned int f_gbpages = F(GBPAGES); 305 unsigned int f_lm = F(LM); 306 #else 307 unsigned int f_gbpages = 0; 308 unsigned int f_lm = 0; 309 #endif 310 311 BUILD_BUG_ON(sizeof(kvm_cpu_caps) > 312 sizeof(boot_cpu_data.x86_capability)); 313 314 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 315 sizeof(kvm_cpu_caps)); 316 317 kvm_cpu_cap_mask(CPUID_1_ECX, 318 /* 319 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 320 * advertised to guests via CPUID! 321 */ 322 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 323 0 /* DS-CPL, VMX, SMX, EST */ | 324 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 325 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 326 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 327 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 328 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 329 F(F16C) | F(RDRAND) 330 ); 331 /* KVM emulates x2apic in software irrespective of host support. */ 332 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 333 334 kvm_cpu_cap_mask(CPUID_1_EDX, 335 F(FPU) | F(VME) | F(DE) | F(PSE) | 336 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 337 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 338 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 339 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 340 0 /* Reserved, DS, ACPI */ | F(MMX) | 341 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 342 0 /* HTT, TM, Reserved, PBE */ 343 ); 344 345 kvm_cpu_cap_mask(CPUID_7_0_EBX, 346 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 347 F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 348 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 349 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 350 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 351 ); 352 353 kvm_cpu_cap_mask(CPUID_7_ECX, 354 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 355 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 356 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 357 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ 358 ); 359 /* Set LA57 based on hardware capability. */ 360 if (cpuid_ecx(7) & F(LA57)) 361 kvm_cpu_cap_set(X86_FEATURE_LA57); 362 363 /* 364 * PKU not yet implemented for shadow paging and requires OSPKE 365 * to be set on the host. Clear it if that is not the case 366 */ 367 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 368 kvm_cpu_cap_clear(X86_FEATURE_PKU); 369 370 kvm_cpu_cap_mask(CPUID_7_EDX, 371 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 372 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 373 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) 374 ); 375 376 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 377 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 378 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 379 380 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 381 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 382 if (boot_cpu_has(X86_FEATURE_STIBP)) 383 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 384 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 385 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 386 387 kvm_cpu_cap_mask(CPUID_7_1_EAX, 388 F(AVX512_BF16) 389 ); 390 391 kvm_cpu_cap_mask(CPUID_D_1_EAX, 392 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) 393 ); 394 395 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 396 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 397 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 398 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 399 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 400 F(TOPOEXT) | F(PERFCTR_CORE) 401 ); 402 403 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 404 F(FPU) | F(VME) | F(DE) | F(PSE) | 405 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 406 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 407 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 408 F(PAT) | F(PSE36) | 0 /* Reserved */ | 409 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 410 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 411 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 412 ); 413 414 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 415 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 416 417 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 418 F(CLZERO) | F(XSAVEERPTR) | 419 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 420 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) 421 ); 422 423 /* 424 * AMD has separate bits for each SPEC_CTRL bit. 425 * arch/x86/kernel/cpu/bugs.c is kind enough to 426 * record that in cpufeatures so use them. 427 */ 428 if (boot_cpu_has(X86_FEATURE_IBPB)) 429 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 430 if (boot_cpu_has(X86_FEATURE_IBRS)) 431 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 432 if (boot_cpu_has(X86_FEATURE_STIBP)) 433 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 434 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 435 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 436 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 437 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 438 /* 439 * The preference is to use SPEC CTRL MSR instead of the 440 * VIRT_SPEC MSR. 441 */ 442 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 443 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 444 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 445 446 /* 447 * Hide all SVM features by default, SVM will set the cap bits for 448 * features it emulates and/or exposes for L1. 449 */ 450 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 451 452 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 453 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 454 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 455 F(PMM) | F(PMM_EN) 456 ); 457 } 458 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 459 460 struct kvm_cpuid_array { 461 struct kvm_cpuid_entry2 *entries; 462 int maxnent; 463 int nent; 464 }; 465 466 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 467 u32 function, u32 index) 468 { 469 struct kvm_cpuid_entry2 *entry; 470 471 if (array->nent >= array->maxnent) 472 return NULL; 473 474 entry = &array->entries[array->nent++]; 475 476 entry->function = function; 477 entry->index = index; 478 entry->flags = 0; 479 480 cpuid_count(entry->function, entry->index, 481 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 482 483 switch (function) { 484 case 4: 485 case 7: 486 case 0xb: 487 case 0xd: 488 case 0xf: 489 case 0x10: 490 case 0x12: 491 case 0x14: 492 case 0x17: 493 case 0x18: 494 case 0x1f: 495 case 0x8000001d: 496 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 497 break; 498 } 499 500 return entry; 501 } 502 503 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 504 { 505 struct kvm_cpuid_entry2 *entry; 506 507 if (array->nent >= array->maxnent) 508 return -E2BIG; 509 510 entry = &array->entries[array->nent]; 511 entry->function = func; 512 entry->index = 0; 513 entry->flags = 0; 514 515 switch (func) { 516 case 0: 517 entry->eax = 7; 518 ++array->nent; 519 break; 520 case 1: 521 entry->ecx = F(MOVBE); 522 ++array->nent; 523 break; 524 case 7: 525 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 526 entry->eax = 0; 527 entry->ecx = F(RDPID); 528 ++array->nent; 529 default: 530 break; 531 } 532 533 return 0; 534 } 535 536 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 537 { 538 struct kvm_cpuid_entry2 *entry; 539 int r, i, max_idx; 540 541 /* all calls to cpuid_count() should be made on the same cpu */ 542 get_cpu(); 543 544 r = -E2BIG; 545 546 entry = do_host_cpuid(array, function, 0); 547 if (!entry) 548 goto out; 549 550 switch (function) { 551 case 0: 552 /* Limited to the highest leaf implemented in KVM. */ 553 entry->eax = min(entry->eax, 0x1fU); 554 break; 555 case 1: 556 cpuid_entry_override(entry, CPUID_1_EDX); 557 cpuid_entry_override(entry, CPUID_1_ECX); 558 break; 559 case 2: 560 /* 561 * On ancient CPUs, function 2 entries are STATEFUL. That is, 562 * CPUID(function=2, index=0) may return different results each 563 * time, with the least-significant byte in EAX enumerating the 564 * number of times software should do CPUID(2, 0). 565 * 566 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 567 * idiotic. Intel's SDM states that EAX & 0xff "will always 568 * return 01H. Software should ignore this value and not 569 * interpret it as an informational descriptor", while AMD's 570 * APM states that CPUID(2) is reserved. 571 * 572 * WARN if a frankenstein CPU that supports virtualization and 573 * a stateful CPUID.0x2 is encountered. 574 */ 575 WARN_ON_ONCE((entry->eax & 0xff) > 1); 576 break; 577 /* functions 4 and 0x8000001d have additional index. */ 578 case 4: 579 case 0x8000001d: 580 /* 581 * Read entries until the cache type in the previous entry is 582 * zero, i.e. indicates an invalid entry. 583 */ 584 for (i = 1; entry->eax & 0x1f; ++i) { 585 entry = do_host_cpuid(array, function, i); 586 if (!entry) 587 goto out; 588 } 589 break; 590 case 6: /* Thermal management */ 591 entry->eax = 0x4; /* allow ARAT */ 592 entry->ebx = 0; 593 entry->ecx = 0; 594 entry->edx = 0; 595 break; 596 /* function 7 has additional index. */ 597 case 7: 598 entry->eax = min(entry->eax, 1u); 599 cpuid_entry_override(entry, CPUID_7_0_EBX); 600 cpuid_entry_override(entry, CPUID_7_ECX); 601 cpuid_entry_override(entry, CPUID_7_EDX); 602 603 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 604 if (entry->eax == 1) { 605 entry = do_host_cpuid(array, function, 1); 606 if (!entry) 607 goto out; 608 609 cpuid_entry_override(entry, CPUID_7_1_EAX); 610 entry->ebx = 0; 611 entry->ecx = 0; 612 entry->edx = 0; 613 } 614 break; 615 case 9: 616 break; 617 case 0xa: { /* Architectural Performance Monitoring */ 618 struct x86_pmu_capability cap; 619 union cpuid10_eax eax; 620 union cpuid10_edx edx; 621 622 perf_get_x86_pmu_capability(&cap); 623 624 /* 625 * Only support guest architectural pmu on a host 626 * with architectural pmu. 627 */ 628 if (!cap.version) 629 memset(&cap, 0, sizeof(cap)); 630 631 eax.split.version_id = min(cap.version, 2); 632 eax.split.num_counters = cap.num_counters_gp; 633 eax.split.bit_width = cap.bit_width_gp; 634 eax.split.mask_length = cap.events_mask_len; 635 636 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 637 edx.split.bit_width_fixed = cap.bit_width_fixed; 638 edx.split.reserved = 0; 639 640 entry->eax = eax.full; 641 entry->ebx = cap.events_mask; 642 entry->ecx = 0; 643 entry->edx = edx.full; 644 break; 645 } 646 /* 647 * Per Intel's SDM, the 0x1f is a superset of 0xb, 648 * thus they can be handled by common code. 649 */ 650 case 0x1f: 651 case 0xb: 652 /* 653 * Populate entries until the level type (ECX[15:8]) of the 654 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 655 * the starting entry, filled by the primary do_host_cpuid(). 656 */ 657 for (i = 1; entry->ecx & 0xff00; ++i) { 658 entry = do_host_cpuid(array, function, i); 659 if (!entry) 660 goto out; 661 } 662 break; 663 case 0xd: 664 entry->eax &= supported_xcr0; 665 entry->ebx = xstate_required_size(supported_xcr0, false); 666 entry->ecx = entry->ebx; 667 entry->edx &= supported_xcr0 >> 32; 668 if (!supported_xcr0) 669 break; 670 671 entry = do_host_cpuid(array, function, 1); 672 if (!entry) 673 goto out; 674 675 cpuid_entry_override(entry, CPUID_D_1_EAX); 676 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 677 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 678 true); 679 else { 680 WARN_ON_ONCE(supported_xss != 0); 681 entry->ebx = 0; 682 } 683 entry->ecx &= supported_xss; 684 entry->edx &= supported_xss >> 32; 685 686 for (i = 2; i < 64; ++i) { 687 bool s_state; 688 if (supported_xcr0 & BIT_ULL(i)) 689 s_state = false; 690 else if (supported_xss & BIT_ULL(i)) 691 s_state = true; 692 else 693 continue; 694 695 entry = do_host_cpuid(array, function, i); 696 if (!entry) 697 goto out; 698 699 /* 700 * The supported check above should have filtered out 701 * invalid sub-leafs. Only valid sub-leafs should 702 * reach this point, and they should have a non-zero 703 * save state size. Furthermore, check whether the 704 * processor agrees with supported_xcr0/supported_xss 705 * on whether this is an XCR0- or IA32_XSS-managed area. 706 */ 707 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 708 --array->nent; 709 continue; 710 } 711 entry->edx = 0; 712 } 713 break; 714 /* Intel PT */ 715 case 0x14: 716 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 717 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 718 break; 719 } 720 721 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 722 if (!do_host_cpuid(array, function, i)) 723 goto out; 724 } 725 break; 726 case KVM_CPUID_SIGNATURE: { 727 static const char signature[12] = "KVMKVMKVM\0\0"; 728 const u32 *sigptr = (const u32 *)signature; 729 entry->eax = KVM_CPUID_FEATURES; 730 entry->ebx = sigptr[0]; 731 entry->ecx = sigptr[1]; 732 entry->edx = sigptr[2]; 733 break; 734 } 735 case KVM_CPUID_FEATURES: 736 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 737 (1 << KVM_FEATURE_NOP_IO_DELAY) | 738 (1 << KVM_FEATURE_CLOCKSOURCE2) | 739 (1 << KVM_FEATURE_ASYNC_PF) | 740 (1 << KVM_FEATURE_PV_EOI) | 741 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 742 (1 << KVM_FEATURE_PV_UNHALT) | 743 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 744 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 745 (1 << KVM_FEATURE_PV_SEND_IPI) | 746 (1 << KVM_FEATURE_POLL_CONTROL) | 747 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 748 (1 << KVM_FEATURE_ASYNC_PF_INT); 749 750 if (sched_info_on()) 751 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 752 753 entry->ebx = 0; 754 entry->ecx = 0; 755 entry->edx = 0; 756 break; 757 case 0x80000000: 758 entry->eax = min(entry->eax, 0x8000001f); 759 break; 760 case 0x80000001: 761 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 762 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 763 break; 764 case 0x80000006: 765 /* L2 cache and TLB: pass through host info. */ 766 break; 767 case 0x80000007: /* Advanced power management */ 768 /* invariant TSC is CPUID.80000007H:EDX[8] */ 769 entry->edx &= (1 << 8); 770 /* mask against host */ 771 entry->edx &= boot_cpu_data.x86_power; 772 entry->eax = entry->ebx = entry->ecx = 0; 773 break; 774 case 0x80000008: { 775 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 776 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 777 unsigned phys_as = entry->eax & 0xff; 778 779 if (!g_phys_as) 780 g_phys_as = phys_as; 781 entry->eax = g_phys_as | (virt_as << 8); 782 entry->edx = 0; 783 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 784 break; 785 } 786 case 0x8000000A: 787 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 788 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 789 break; 790 } 791 entry->eax = 1; /* SVM revision 1 */ 792 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 793 ASID emulation to nested SVM */ 794 entry->ecx = 0; /* Reserved */ 795 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 796 break; 797 case 0x80000019: 798 entry->ecx = entry->edx = 0; 799 break; 800 case 0x8000001a: 801 case 0x8000001e: 802 break; 803 /* Support memory encryption cpuid if host supports it */ 804 case 0x8000001F: 805 if (!boot_cpu_has(X86_FEATURE_SEV)) 806 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 807 break; 808 /*Add support for Centaur's CPUID instruction*/ 809 case 0xC0000000: 810 /*Just support up to 0xC0000004 now*/ 811 entry->eax = min(entry->eax, 0xC0000004); 812 break; 813 case 0xC0000001: 814 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 815 break; 816 case 3: /* Processor serial number */ 817 case 5: /* MONITOR/MWAIT */ 818 case 0xC0000002: 819 case 0xC0000003: 820 case 0xC0000004: 821 default: 822 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 823 break; 824 } 825 826 r = 0; 827 828 out: 829 put_cpu(); 830 831 return r; 832 } 833 834 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 835 unsigned int type) 836 { 837 if (type == KVM_GET_EMULATED_CPUID) 838 return __do_cpuid_func_emulated(array, func); 839 840 return __do_cpuid_func(array, func); 841 } 842 843 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 844 845 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 846 unsigned int type) 847 { 848 u32 limit; 849 int r; 850 851 if (func == CENTAUR_CPUID_SIGNATURE && 852 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 853 return 0; 854 855 r = do_cpuid_func(array, func, type); 856 if (r) 857 return r; 858 859 limit = array->entries[array->nent - 1].eax; 860 for (func = func + 1; func <= limit; ++func) { 861 r = do_cpuid_func(array, func, type); 862 if (r) 863 break; 864 } 865 866 return r; 867 } 868 869 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 870 __u32 num_entries, unsigned int ioctl_type) 871 { 872 int i; 873 __u32 pad[3]; 874 875 if (ioctl_type != KVM_GET_EMULATED_CPUID) 876 return false; 877 878 /* 879 * We want to make sure that ->padding is being passed clean from 880 * userspace in case we want to use it for something in the future. 881 * 882 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 883 * have to give ourselves satisfied only with the emulated side. /me 884 * sheds a tear. 885 */ 886 for (i = 0; i < num_entries; i++) { 887 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 888 return true; 889 890 if (pad[0] || pad[1] || pad[2]) 891 return true; 892 } 893 return false; 894 } 895 896 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 897 struct kvm_cpuid_entry2 __user *entries, 898 unsigned int type) 899 { 900 static const u32 funcs[] = { 901 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 902 }; 903 904 struct kvm_cpuid_array array = { 905 .nent = 0, 906 }; 907 int r, i; 908 909 if (cpuid->nent < 1) 910 return -E2BIG; 911 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 912 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 913 914 if (sanity_check_entries(entries, cpuid->nent, type)) 915 return -EINVAL; 916 917 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 918 cpuid->nent)); 919 if (!array.entries) 920 return -ENOMEM; 921 922 array.maxnent = cpuid->nent; 923 924 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 925 r = get_cpuid_func(&array, funcs[i], type); 926 if (r) 927 goto out_free; 928 } 929 cpuid->nent = array.nent; 930 931 if (copy_to_user(entries, array.entries, 932 array.nent * sizeof(struct kvm_cpuid_entry2))) 933 r = -EFAULT; 934 935 out_free: 936 vfree(array.entries); 937 return r; 938 } 939 940 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 941 u32 function, u32 index) 942 { 943 struct kvm_cpuid_entry2 *e; 944 int i; 945 946 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 947 e = &vcpu->arch.cpuid_entries[i]; 948 949 if (e->function == function && (e->index == index || 950 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) 951 return e; 952 } 953 return NULL; 954 } 955 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 956 957 /* 958 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 959 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 960 * returns all zeroes for any undefined leaf, whether or not the leaf is in 961 * range. Centaur/VIA follows Intel semantics. 962 * 963 * A leaf is considered out-of-range if its function is higher than the maximum 964 * supported leaf of its associated class or if its associated class does not 965 * exist. 966 * 967 * There are three primary classes to be considered, with their respective 968 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 969 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 970 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 971 * 972 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 973 * - Hypervisor: 0x40000000 - 0x4fffffff 974 * - Extended: 0x80000000 - 0xbfffffff 975 * - Centaur: 0xc0000000 - 0xcfffffff 976 * 977 * The Hypervisor class is further subdivided into sub-classes that each act as 978 * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu 979 * is advertising support for both HyperV and KVM, the resulting Hypervisor 980 * CPUID sub-classes are: 981 * 982 * - HyperV: 0x40000000 - 0x400000ff 983 * - KVM: 0x40000100 - 0x400001ff 984 */ 985 static struct kvm_cpuid_entry2 * 986 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 987 { 988 struct kvm_cpuid_entry2 *basic, *class; 989 u32 function = *fn_ptr; 990 991 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 992 if (!basic) 993 return NULL; 994 995 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 996 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 997 return NULL; 998 999 if (function >= 0x40000000 && function <= 0x4fffffff) 1000 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1001 else if (function >= 0xc0000000) 1002 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1003 else 1004 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1005 1006 if (class && function <= class->eax) 1007 return NULL; 1008 1009 /* 1010 * Leaf specific adjustments are also applied when redirecting to the 1011 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1012 * entry for CPUID.0xb.index (see below), then the output value for EDX 1013 * needs to be pulled from CPUID.0xb.1. 1014 */ 1015 *fn_ptr = basic->eax; 1016 1017 /* 1018 * The class does not exist or the requested function is out of range; 1019 * the effective CPUID entry is the max basic leaf. Note, the index of 1020 * the original requested leaf is observed! 1021 */ 1022 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1023 } 1024 1025 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1026 u32 *ecx, u32 *edx, bool exact_only) 1027 { 1028 u32 orig_function = *eax, function = *eax, index = *ecx; 1029 struct kvm_cpuid_entry2 *entry; 1030 bool exact, used_max_basic = false; 1031 1032 entry = kvm_find_cpuid_entry(vcpu, function, index); 1033 exact = !!entry; 1034 1035 if (!entry && !exact_only) { 1036 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1037 used_max_basic = !!entry; 1038 } 1039 1040 if (entry) { 1041 *eax = entry->eax; 1042 *ebx = entry->ebx; 1043 *ecx = entry->ecx; 1044 *edx = entry->edx; 1045 if (function == 7 && index == 0) { 1046 u64 data; 1047 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1048 (data & TSX_CTRL_CPUID_CLEAR)) 1049 *ebx &= ~(F(RTM) | F(HLE)); 1050 } 1051 } else { 1052 *eax = *ebx = *ecx = *edx = 0; 1053 /* 1054 * When leaf 0BH or 1FH is defined, CL is pass-through 1055 * and EDX is always the x2APIC ID, even for undefined 1056 * subleaves. Index 1 will exist iff the leaf is 1057 * implemented, so we pass through CL iff leaf 1 1058 * exists. EDX can be copied from any existing index. 1059 */ 1060 if (function == 0xb || function == 0x1f) { 1061 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1062 if (entry) { 1063 *ecx = index & 0xff; 1064 *edx = entry->edx; 1065 } 1066 } 1067 } 1068 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1069 used_max_basic); 1070 return exact; 1071 } 1072 EXPORT_SYMBOL_GPL(kvm_cpuid); 1073 1074 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1075 { 1076 u32 eax, ebx, ecx, edx; 1077 1078 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1079 return 1; 1080 1081 eax = kvm_rax_read(vcpu); 1082 ecx = kvm_rcx_read(vcpu); 1083 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1084 kvm_rax_write(vcpu, eax); 1085 kvm_rbx_write(vcpu, ebx); 1086 kvm_rcx_write(vcpu, ecx); 1087 kvm_rdx_write(vcpu, edx); 1088 return kvm_skip_emulated_instruction(vcpu); 1089 } 1090 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1091