1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include "cpuid.h" 22 #include "lapic.h" 23 #include "mmu.h" 24 #include "trace.h" 25 #include "pmu.h" 26 27 /* 28 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 29 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 30 */ 31 u32 kvm_cpu_caps[NCAPINTS] __read_mostly; 32 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 33 34 static u32 xstate_required_size(u64 xstate_bv, bool compacted) 35 { 36 int feature_bit = 0; 37 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 38 39 xstate_bv &= XFEATURE_MASK_EXTEND; 40 while (xstate_bv) { 41 if (xstate_bv & 0x1) { 42 u32 eax, ebx, ecx, edx, offset; 43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 44 offset = compacted ? ret : ebx; 45 ret = max(ret, offset + eax); 46 } 47 48 xstate_bv >>= 1; 49 feature_bit++; 50 } 51 52 return ret; 53 } 54 55 #define F feature_bit 56 57 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 58 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 59 { 60 struct kvm_cpuid_entry2 *e; 61 int i; 62 63 for (i = 0; i < nent; i++) { 64 e = &entries[i]; 65 66 if (e->function == function && (e->index == index || 67 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) 68 return e; 69 } 70 71 return NULL; 72 } 73 74 static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) 75 { 76 struct kvm_cpuid_entry2 *best; 77 78 /* 79 * The existing code assumes virtual address is 48-bit or 57-bit in the 80 * canonical address checks; exit if it is ever changed. 81 */ 82 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 83 if (best) { 84 int vaddr_bits = (best->eax & 0xff00) >> 8; 85 86 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 87 return -EINVAL; 88 } 89 90 return 0; 91 } 92 93 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 94 { 95 struct kvm_cpuid_entry2 *best; 96 97 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 98 99 /* 100 * save the feature bitmap to avoid cpuid lookup for every PV 101 * operation 102 */ 103 if (best) 104 vcpu->arch.pv_cpuid.features = best->eax; 105 } 106 107 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 108 { 109 struct kvm_cpuid_entry2 *best; 110 111 best = kvm_find_cpuid_entry(vcpu, 1, 0); 112 if (best) { 113 /* Update OSXSAVE bit */ 114 if (boot_cpu_has(X86_FEATURE_XSAVE)) 115 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 116 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 117 118 cpuid_entry_change(best, X86_FEATURE_APIC, 119 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 120 } 121 122 best = kvm_find_cpuid_entry(vcpu, 7, 0); 123 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 124 cpuid_entry_change(best, X86_FEATURE_OSPKE, 125 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 126 127 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 128 if (best) 129 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 130 131 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 132 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 133 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 134 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 135 136 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 137 if (kvm_hlt_in_guest(vcpu->kvm) && best && 138 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 139 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 140 141 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 142 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 143 if (best) 144 cpuid_entry_change(best, X86_FEATURE_MWAIT, 145 vcpu->arch.ia32_misc_enable_msr & 146 MSR_IA32_MISC_ENABLE_MWAIT); 147 } 148 } 149 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 150 151 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 152 { 153 struct kvm_lapic *apic = vcpu->arch.apic; 154 struct kvm_cpuid_entry2 *best; 155 156 best = kvm_find_cpuid_entry(vcpu, 1, 0); 157 if (best && apic) { 158 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 159 apic->lapic_timer.timer_mode_mask = 3 << 17; 160 else 161 apic->lapic_timer.timer_mode_mask = 1 << 17; 162 163 kvm_apic_set_version(vcpu); 164 } 165 166 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 167 if (!best) 168 vcpu->arch.guest_supported_xcr0 = 0; 169 else 170 vcpu->arch.guest_supported_xcr0 = 171 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 172 173 kvm_update_pv_runtime(vcpu); 174 175 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 176 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 177 178 kvm_pmu_refresh(vcpu); 179 vcpu->arch.cr4_guest_rsvd_bits = 180 __cr4_reserved_bits(guest_cpuid_has, vcpu); 181 182 kvm_hv_set_cpuid(vcpu); 183 184 /* Invoke the vendor callback only after the above state is updated. */ 185 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 186 187 /* 188 * Except for the MMU, which needs to be reset after any vendor 189 * specific adjustments to the reserved GPA bits. 190 */ 191 kvm_mmu_reset_context(vcpu); 192 } 193 194 static int is_efer_nx(void) 195 { 196 return host_efer & EFER_NX; 197 } 198 199 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) 200 { 201 int i; 202 struct kvm_cpuid_entry2 *e, *entry; 203 204 entry = NULL; 205 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 206 e = &vcpu->arch.cpuid_entries[i]; 207 if (e->function == 0x80000001) { 208 entry = e; 209 break; 210 } 211 } 212 if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { 213 cpuid_entry_clear(entry, X86_FEATURE_NX); 214 printk(KERN_INFO "kvm: guest NX capability removed\n"); 215 } 216 } 217 218 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 219 { 220 struct kvm_cpuid_entry2 *best; 221 222 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 223 if (!best || best->eax < 0x80000008) 224 goto not_found; 225 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 226 if (best) 227 return best->eax & 0xff; 228 not_found: 229 return 36; 230 } 231 232 /* 233 * This "raw" version returns the reserved GPA bits without any adjustments for 234 * encryption technologies that usurp bits. The raw mask should be used if and 235 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 236 */ 237 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 238 { 239 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 240 } 241 242 /* when an old userspace process fills a new kernel module */ 243 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 244 struct kvm_cpuid *cpuid, 245 struct kvm_cpuid_entry __user *entries) 246 { 247 int r, i; 248 struct kvm_cpuid_entry *e = NULL; 249 struct kvm_cpuid_entry2 *e2 = NULL; 250 251 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 252 return -E2BIG; 253 254 if (cpuid->nent) { 255 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 256 if (IS_ERR(e)) 257 return PTR_ERR(e); 258 259 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 260 if (!e2) { 261 r = -ENOMEM; 262 goto out_free_cpuid; 263 } 264 } 265 for (i = 0; i < cpuid->nent; i++) { 266 e2[i].function = e[i].function; 267 e2[i].eax = e[i].eax; 268 e2[i].ebx = e[i].ebx; 269 e2[i].ecx = e[i].ecx; 270 e2[i].edx = e[i].edx; 271 e2[i].index = 0; 272 e2[i].flags = 0; 273 e2[i].padding[0] = 0; 274 e2[i].padding[1] = 0; 275 e2[i].padding[2] = 0; 276 } 277 278 r = kvm_check_cpuid(e2, cpuid->nent); 279 if (r) { 280 kvfree(e2); 281 goto out_free_cpuid; 282 } 283 284 kvfree(vcpu->arch.cpuid_entries); 285 vcpu->arch.cpuid_entries = e2; 286 vcpu->arch.cpuid_nent = cpuid->nent; 287 288 cpuid_fix_nx_cap(vcpu); 289 kvm_update_cpuid_runtime(vcpu); 290 kvm_vcpu_after_set_cpuid(vcpu); 291 292 out_free_cpuid: 293 kvfree(e); 294 295 return r; 296 } 297 298 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 299 struct kvm_cpuid2 *cpuid, 300 struct kvm_cpuid_entry2 __user *entries) 301 { 302 struct kvm_cpuid_entry2 *e2 = NULL; 303 int r; 304 305 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 306 return -E2BIG; 307 308 if (cpuid->nent) { 309 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 310 if (IS_ERR(e2)) 311 return PTR_ERR(e2); 312 } 313 314 r = kvm_check_cpuid(e2, cpuid->nent); 315 if (r) { 316 kvfree(e2); 317 return r; 318 } 319 320 kvfree(vcpu->arch.cpuid_entries); 321 vcpu->arch.cpuid_entries = e2; 322 vcpu->arch.cpuid_nent = cpuid->nent; 323 324 kvm_update_cpuid_runtime(vcpu); 325 kvm_vcpu_after_set_cpuid(vcpu); 326 327 return 0; 328 } 329 330 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 331 struct kvm_cpuid2 *cpuid, 332 struct kvm_cpuid_entry2 __user *entries) 333 { 334 int r; 335 336 r = -E2BIG; 337 if (cpuid->nent < vcpu->arch.cpuid_nent) 338 goto out; 339 r = -EFAULT; 340 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 341 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 342 goto out; 343 return 0; 344 345 out: 346 cpuid->nent = vcpu->arch.cpuid_nent; 347 return r; 348 } 349 350 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 351 { 352 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 353 struct kvm_cpuid_entry2 entry; 354 355 reverse_cpuid_check(leaf); 356 kvm_cpu_caps[leaf] &= mask; 357 358 cpuid_count(cpuid.function, cpuid.index, 359 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 360 361 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 362 } 363 364 void kvm_set_cpu_caps(void) 365 { 366 unsigned int f_nx = is_efer_nx() ? F(NX) : 0; 367 #ifdef CONFIG_X86_64 368 unsigned int f_gbpages = F(GBPAGES); 369 unsigned int f_lm = F(LM); 370 #else 371 unsigned int f_gbpages = 0; 372 unsigned int f_lm = 0; 373 #endif 374 375 BUILD_BUG_ON(sizeof(kvm_cpu_caps) > 376 sizeof(boot_cpu_data.x86_capability)); 377 378 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 379 sizeof(kvm_cpu_caps)); 380 381 kvm_cpu_cap_mask(CPUID_1_ECX, 382 /* 383 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 384 * advertised to guests via CPUID! 385 */ 386 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 387 0 /* DS-CPL, VMX, SMX, EST */ | 388 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 389 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 390 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 391 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 392 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 393 F(F16C) | F(RDRAND) 394 ); 395 /* KVM emulates x2apic in software irrespective of host support. */ 396 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 397 398 kvm_cpu_cap_mask(CPUID_1_EDX, 399 F(FPU) | F(VME) | F(DE) | F(PSE) | 400 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 401 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 402 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 403 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 404 0 /* Reserved, DS, ACPI */ | F(MMX) | 405 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 406 0 /* HTT, TM, Reserved, PBE */ 407 ); 408 409 kvm_cpu_cap_mask(CPUID_7_0_EBX, 410 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 411 F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 412 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 413 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 414 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 415 ); 416 417 kvm_cpu_cap_mask(CPUID_7_ECX, 418 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 419 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 420 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 421 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ 422 ); 423 /* Set LA57 based on hardware capability. */ 424 if (cpuid_ecx(7) & F(LA57)) 425 kvm_cpu_cap_set(X86_FEATURE_LA57); 426 427 /* 428 * PKU not yet implemented for shadow paging and requires OSPKE 429 * to be set on the host. Clear it if that is not the case 430 */ 431 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 432 kvm_cpu_cap_clear(X86_FEATURE_PKU); 433 434 kvm_cpu_cap_mask(CPUID_7_EDX, 435 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 436 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 437 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 438 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) 439 ); 440 441 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 442 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 443 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 444 445 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 446 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 447 if (boot_cpu_has(X86_FEATURE_STIBP)) 448 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 449 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 450 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 451 452 kvm_cpu_cap_mask(CPUID_7_1_EAX, 453 F(AVX_VNNI) | F(AVX512_BF16) 454 ); 455 456 kvm_cpu_cap_mask(CPUID_D_1_EAX, 457 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) 458 ); 459 460 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 461 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 462 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 463 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 464 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 465 F(TOPOEXT) | F(PERFCTR_CORE) 466 ); 467 468 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 469 F(FPU) | F(VME) | F(DE) | F(PSE) | 470 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 471 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 472 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 473 F(PAT) | F(PSE36) | 0 /* Reserved */ | 474 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 475 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 476 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 477 ); 478 479 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 480 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 481 482 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 483 F(CLZERO) | F(XSAVEERPTR) | 484 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 485 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) 486 ); 487 488 /* 489 * AMD has separate bits for each SPEC_CTRL bit. 490 * arch/x86/kernel/cpu/bugs.c is kind enough to 491 * record that in cpufeatures so use them. 492 */ 493 if (boot_cpu_has(X86_FEATURE_IBPB)) 494 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 495 if (boot_cpu_has(X86_FEATURE_IBRS)) 496 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 497 if (boot_cpu_has(X86_FEATURE_STIBP)) 498 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 499 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 500 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 501 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 502 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 503 /* 504 * The preference is to use SPEC CTRL MSR instead of the 505 * VIRT_SPEC MSR. 506 */ 507 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 508 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 509 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 510 511 /* 512 * Hide all SVM features by default, SVM will set the cap bits for 513 * features it emulates and/or exposes for L1. 514 */ 515 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 516 517 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 518 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 519 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 520 F(PMM) | F(PMM_EN) 521 ); 522 } 523 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 524 525 struct kvm_cpuid_array { 526 struct kvm_cpuid_entry2 *entries; 527 int maxnent; 528 int nent; 529 }; 530 531 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 532 u32 function, u32 index) 533 { 534 struct kvm_cpuid_entry2 *entry; 535 536 if (array->nent >= array->maxnent) 537 return NULL; 538 539 entry = &array->entries[array->nent++]; 540 541 entry->function = function; 542 entry->index = index; 543 entry->flags = 0; 544 545 cpuid_count(entry->function, entry->index, 546 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 547 548 switch (function) { 549 case 4: 550 case 7: 551 case 0xb: 552 case 0xd: 553 case 0xf: 554 case 0x10: 555 case 0x12: 556 case 0x14: 557 case 0x17: 558 case 0x18: 559 case 0x1f: 560 case 0x8000001d: 561 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 562 break; 563 } 564 565 return entry; 566 } 567 568 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 569 { 570 struct kvm_cpuid_entry2 *entry; 571 572 if (array->nent >= array->maxnent) 573 return -E2BIG; 574 575 entry = &array->entries[array->nent]; 576 entry->function = func; 577 entry->index = 0; 578 entry->flags = 0; 579 580 switch (func) { 581 case 0: 582 entry->eax = 7; 583 ++array->nent; 584 break; 585 case 1: 586 entry->ecx = F(MOVBE); 587 ++array->nent; 588 break; 589 case 7: 590 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 591 entry->eax = 0; 592 entry->ecx = F(RDPID); 593 ++array->nent; 594 default: 595 break; 596 } 597 598 return 0; 599 } 600 601 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 602 { 603 struct kvm_cpuid_entry2 *entry; 604 int r, i, max_idx; 605 606 /* all calls to cpuid_count() should be made on the same cpu */ 607 get_cpu(); 608 609 r = -E2BIG; 610 611 entry = do_host_cpuid(array, function, 0); 612 if (!entry) 613 goto out; 614 615 switch (function) { 616 case 0: 617 /* Limited to the highest leaf implemented in KVM. */ 618 entry->eax = min(entry->eax, 0x1fU); 619 break; 620 case 1: 621 cpuid_entry_override(entry, CPUID_1_EDX); 622 cpuid_entry_override(entry, CPUID_1_ECX); 623 break; 624 case 2: 625 /* 626 * On ancient CPUs, function 2 entries are STATEFUL. That is, 627 * CPUID(function=2, index=0) may return different results each 628 * time, with the least-significant byte in EAX enumerating the 629 * number of times software should do CPUID(2, 0). 630 * 631 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 632 * idiotic. Intel's SDM states that EAX & 0xff "will always 633 * return 01H. Software should ignore this value and not 634 * interpret it as an informational descriptor", while AMD's 635 * APM states that CPUID(2) is reserved. 636 * 637 * WARN if a frankenstein CPU that supports virtualization and 638 * a stateful CPUID.0x2 is encountered. 639 */ 640 WARN_ON_ONCE((entry->eax & 0xff) > 1); 641 break; 642 /* functions 4 and 0x8000001d have additional index. */ 643 case 4: 644 case 0x8000001d: 645 /* 646 * Read entries until the cache type in the previous entry is 647 * zero, i.e. indicates an invalid entry. 648 */ 649 for (i = 1; entry->eax & 0x1f; ++i) { 650 entry = do_host_cpuid(array, function, i); 651 if (!entry) 652 goto out; 653 } 654 break; 655 case 6: /* Thermal management */ 656 entry->eax = 0x4; /* allow ARAT */ 657 entry->ebx = 0; 658 entry->ecx = 0; 659 entry->edx = 0; 660 break; 661 /* function 7 has additional index. */ 662 case 7: 663 entry->eax = min(entry->eax, 1u); 664 cpuid_entry_override(entry, CPUID_7_0_EBX); 665 cpuid_entry_override(entry, CPUID_7_ECX); 666 cpuid_entry_override(entry, CPUID_7_EDX); 667 668 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 669 if (entry->eax == 1) { 670 entry = do_host_cpuid(array, function, 1); 671 if (!entry) 672 goto out; 673 674 cpuid_entry_override(entry, CPUID_7_1_EAX); 675 entry->ebx = 0; 676 entry->ecx = 0; 677 entry->edx = 0; 678 } 679 break; 680 case 9: 681 break; 682 case 0xa: { /* Architectural Performance Monitoring */ 683 struct x86_pmu_capability cap; 684 union cpuid10_eax eax; 685 union cpuid10_edx edx; 686 687 perf_get_x86_pmu_capability(&cap); 688 689 /* 690 * Only support guest architectural pmu on a host 691 * with architectural pmu. 692 */ 693 if (!cap.version) 694 memset(&cap, 0, sizeof(cap)); 695 696 eax.split.version_id = min(cap.version, 2); 697 eax.split.num_counters = cap.num_counters_gp; 698 eax.split.bit_width = cap.bit_width_gp; 699 eax.split.mask_length = cap.events_mask_len; 700 701 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 702 edx.split.bit_width_fixed = cap.bit_width_fixed; 703 edx.split.anythread_deprecated = 1; 704 edx.split.reserved1 = 0; 705 edx.split.reserved2 = 0; 706 707 entry->eax = eax.full; 708 entry->ebx = cap.events_mask; 709 entry->ecx = 0; 710 entry->edx = edx.full; 711 break; 712 } 713 /* 714 * Per Intel's SDM, the 0x1f is a superset of 0xb, 715 * thus they can be handled by common code. 716 */ 717 case 0x1f: 718 case 0xb: 719 /* 720 * Populate entries until the level type (ECX[15:8]) of the 721 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 722 * the starting entry, filled by the primary do_host_cpuid(). 723 */ 724 for (i = 1; entry->ecx & 0xff00; ++i) { 725 entry = do_host_cpuid(array, function, i); 726 if (!entry) 727 goto out; 728 } 729 break; 730 case 0xd: 731 entry->eax &= supported_xcr0; 732 entry->ebx = xstate_required_size(supported_xcr0, false); 733 entry->ecx = entry->ebx; 734 entry->edx &= supported_xcr0 >> 32; 735 if (!supported_xcr0) 736 break; 737 738 entry = do_host_cpuid(array, function, 1); 739 if (!entry) 740 goto out; 741 742 cpuid_entry_override(entry, CPUID_D_1_EAX); 743 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 744 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 745 true); 746 else { 747 WARN_ON_ONCE(supported_xss != 0); 748 entry->ebx = 0; 749 } 750 entry->ecx &= supported_xss; 751 entry->edx &= supported_xss >> 32; 752 753 for (i = 2; i < 64; ++i) { 754 bool s_state; 755 if (supported_xcr0 & BIT_ULL(i)) 756 s_state = false; 757 else if (supported_xss & BIT_ULL(i)) 758 s_state = true; 759 else 760 continue; 761 762 entry = do_host_cpuid(array, function, i); 763 if (!entry) 764 goto out; 765 766 /* 767 * The supported check above should have filtered out 768 * invalid sub-leafs. Only valid sub-leafs should 769 * reach this point, and they should have a non-zero 770 * save state size. Furthermore, check whether the 771 * processor agrees with supported_xcr0/supported_xss 772 * on whether this is an XCR0- or IA32_XSS-managed area. 773 */ 774 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 775 --array->nent; 776 continue; 777 } 778 entry->edx = 0; 779 } 780 break; 781 /* Intel PT */ 782 case 0x14: 783 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 784 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 785 break; 786 } 787 788 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 789 if (!do_host_cpuid(array, function, i)) 790 goto out; 791 } 792 break; 793 case KVM_CPUID_SIGNATURE: { 794 static const char signature[12] = "KVMKVMKVM\0\0"; 795 const u32 *sigptr = (const u32 *)signature; 796 entry->eax = KVM_CPUID_FEATURES; 797 entry->ebx = sigptr[0]; 798 entry->ecx = sigptr[1]; 799 entry->edx = sigptr[2]; 800 break; 801 } 802 case KVM_CPUID_FEATURES: 803 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 804 (1 << KVM_FEATURE_NOP_IO_DELAY) | 805 (1 << KVM_FEATURE_CLOCKSOURCE2) | 806 (1 << KVM_FEATURE_ASYNC_PF) | 807 (1 << KVM_FEATURE_PV_EOI) | 808 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 809 (1 << KVM_FEATURE_PV_UNHALT) | 810 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 811 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 812 (1 << KVM_FEATURE_PV_SEND_IPI) | 813 (1 << KVM_FEATURE_POLL_CONTROL) | 814 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 815 (1 << KVM_FEATURE_ASYNC_PF_INT); 816 817 if (sched_info_on()) 818 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 819 820 entry->ebx = 0; 821 entry->ecx = 0; 822 entry->edx = 0; 823 break; 824 case 0x80000000: 825 entry->eax = min(entry->eax, 0x8000001f); 826 break; 827 case 0x80000001: 828 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 829 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 830 break; 831 case 0x80000006: 832 /* L2 cache and TLB: pass through host info. */ 833 break; 834 case 0x80000007: /* Advanced power management */ 835 /* invariant TSC is CPUID.80000007H:EDX[8] */ 836 entry->edx &= (1 << 8); 837 /* mask against host */ 838 entry->edx &= boot_cpu_data.x86_power; 839 entry->eax = entry->ebx = entry->ecx = 0; 840 break; 841 case 0x80000008: { 842 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 843 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 844 unsigned phys_as = entry->eax & 0xff; 845 846 if (!g_phys_as) 847 g_phys_as = phys_as; 848 entry->eax = g_phys_as | (virt_as << 8); 849 entry->edx = 0; 850 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 851 break; 852 } 853 case 0x8000000A: 854 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 855 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 856 break; 857 } 858 entry->eax = 1; /* SVM revision 1 */ 859 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 860 ASID emulation to nested SVM */ 861 entry->ecx = 0; /* Reserved */ 862 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 863 break; 864 case 0x80000019: 865 entry->ecx = entry->edx = 0; 866 break; 867 case 0x8000001a: 868 case 0x8000001e: 869 break; 870 /* Support memory encryption cpuid if host supports it */ 871 case 0x8000001F: 872 if (!boot_cpu_has(X86_FEATURE_SEV)) 873 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 874 break; 875 /*Add support for Centaur's CPUID instruction*/ 876 case 0xC0000000: 877 /*Just support up to 0xC0000004 now*/ 878 entry->eax = min(entry->eax, 0xC0000004); 879 break; 880 case 0xC0000001: 881 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 882 break; 883 case 3: /* Processor serial number */ 884 case 5: /* MONITOR/MWAIT */ 885 case 0xC0000002: 886 case 0xC0000003: 887 case 0xC0000004: 888 default: 889 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 890 break; 891 } 892 893 r = 0; 894 895 out: 896 put_cpu(); 897 898 return r; 899 } 900 901 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 902 unsigned int type) 903 { 904 if (type == KVM_GET_EMULATED_CPUID) 905 return __do_cpuid_func_emulated(array, func); 906 907 return __do_cpuid_func(array, func); 908 } 909 910 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 911 912 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 913 unsigned int type) 914 { 915 u32 limit; 916 int r; 917 918 if (func == CENTAUR_CPUID_SIGNATURE && 919 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 920 return 0; 921 922 r = do_cpuid_func(array, func, type); 923 if (r) 924 return r; 925 926 limit = array->entries[array->nent - 1].eax; 927 for (func = func + 1; func <= limit; ++func) { 928 r = do_cpuid_func(array, func, type); 929 if (r) 930 break; 931 } 932 933 return r; 934 } 935 936 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 937 __u32 num_entries, unsigned int ioctl_type) 938 { 939 int i; 940 __u32 pad[3]; 941 942 if (ioctl_type != KVM_GET_EMULATED_CPUID) 943 return false; 944 945 /* 946 * We want to make sure that ->padding is being passed clean from 947 * userspace in case we want to use it for something in the future. 948 * 949 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 950 * have to give ourselves satisfied only with the emulated side. /me 951 * sheds a tear. 952 */ 953 for (i = 0; i < num_entries; i++) { 954 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 955 return true; 956 957 if (pad[0] || pad[1] || pad[2]) 958 return true; 959 } 960 return false; 961 } 962 963 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 964 struct kvm_cpuid_entry2 __user *entries, 965 unsigned int type) 966 { 967 static const u32 funcs[] = { 968 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 969 }; 970 971 struct kvm_cpuid_array array = { 972 .nent = 0, 973 }; 974 int r, i; 975 976 if (cpuid->nent < 1) 977 return -E2BIG; 978 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 979 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 980 981 if (sanity_check_entries(entries, cpuid->nent, type)) 982 return -EINVAL; 983 984 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 985 cpuid->nent)); 986 if (!array.entries) 987 return -ENOMEM; 988 989 array.maxnent = cpuid->nent; 990 991 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 992 r = get_cpuid_func(&array, funcs[i], type); 993 if (r) 994 goto out_free; 995 } 996 cpuid->nent = array.nent; 997 998 if (copy_to_user(entries, array.entries, 999 array.nent * sizeof(struct kvm_cpuid_entry2))) 1000 r = -EFAULT; 1001 1002 out_free: 1003 vfree(array.entries); 1004 return r; 1005 } 1006 1007 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1008 u32 function, u32 index) 1009 { 1010 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1011 function, index); 1012 } 1013 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1014 1015 /* 1016 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1017 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1018 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1019 * range. Centaur/VIA follows Intel semantics. 1020 * 1021 * A leaf is considered out-of-range if its function is higher than the maximum 1022 * supported leaf of its associated class or if its associated class does not 1023 * exist. 1024 * 1025 * There are three primary classes to be considered, with their respective 1026 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1027 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1028 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1029 * 1030 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1031 * - Hypervisor: 0x40000000 - 0x4fffffff 1032 * - Extended: 0x80000000 - 0xbfffffff 1033 * - Centaur: 0xc0000000 - 0xcfffffff 1034 * 1035 * The Hypervisor class is further subdivided into sub-classes that each act as 1036 * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu 1037 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1038 * CPUID sub-classes are: 1039 * 1040 * - HyperV: 0x40000000 - 0x400000ff 1041 * - KVM: 0x40000100 - 0x400001ff 1042 */ 1043 static struct kvm_cpuid_entry2 * 1044 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1045 { 1046 struct kvm_cpuid_entry2 *basic, *class; 1047 u32 function = *fn_ptr; 1048 1049 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1050 if (!basic) 1051 return NULL; 1052 1053 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1054 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1055 return NULL; 1056 1057 if (function >= 0x40000000 && function <= 0x4fffffff) 1058 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1059 else if (function >= 0xc0000000) 1060 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1061 else 1062 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1063 1064 if (class && function <= class->eax) 1065 return NULL; 1066 1067 /* 1068 * Leaf specific adjustments are also applied when redirecting to the 1069 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1070 * entry for CPUID.0xb.index (see below), then the output value for EDX 1071 * needs to be pulled from CPUID.0xb.1. 1072 */ 1073 *fn_ptr = basic->eax; 1074 1075 /* 1076 * The class does not exist or the requested function is out of range; 1077 * the effective CPUID entry is the max basic leaf. Note, the index of 1078 * the original requested leaf is observed! 1079 */ 1080 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1081 } 1082 1083 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1084 u32 *ecx, u32 *edx, bool exact_only) 1085 { 1086 u32 orig_function = *eax, function = *eax, index = *ecx; 1087 struct kvm_cpuid_entry2 *entry; 1088 bool exact, used_max_basic = false; 1089 1090 entry = kvm_find_cpuid_entry(vcpu, function, index); 1091 exact = !!entry; 1092 1093 if (!entry && !exact_only) { 1094 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1095 used_max_basic = !!entry; 1096 } 1097 1098 if (entry) { 1099 *eax = entry->eax; 1100 *ebx = entry->ebx; 1101 *ecx = entry->ecx; 1102 *edx = entry->edx; 1103 if (function == 7 && index == 0) { 1104 u64 data; 1105 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1106 (data & TSX_CTRL_CPUID_CLEAR)) 1107 *ebx &= ~(F(RTM) | F(HLE)); 1108 } 1109 } else { 1110 *eax = *ebx = *ecx = *edx = 0; 1111 /* 1112 * When leaf 0BH or 1FH is defined, CL is pass-through 1113 * and EDX is always the x2APIC ID, even for undefined 1114 * subleaves. Index 1 will exist iff the leaf is 1115 * implemented, so we pass through CL iff leaf 1 1116 * exists. EDX can be copied from any existing index. 1117 */ 1118 if (function == 0xb || function == 0x1f) { 1119 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1120 if (entry) { 1121 *ecx = index & 0xff; 1122 *edx = entry->edx; 1123 } 1124 } 1125 } 1126 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1127 used_max_basic); 1128 return exact; 1129 } 1130 EXPORT_SYMBOL_GPL(kvm_cpuid); 1131 1132 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1133 { 1134 u32 eax, ebx, ecx, edx; 1135 1136 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1137 return 1; 1138 1139 eax = kvm_rax_read(vcpu); 1140 ecx = kvm_rcx_read(vcpu); 1141 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1142 kvm_rax_write(vcpu, eax); 1143 kvm_rbx_write(vcpu, ebx); 1144 kvm_rcx_write(vcpu, ecx); 1145 kvm_rdx_write(vcpu, edx); 1146 return kvm_skip_emulated_instruction(vcpu); 1147 } 1148 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1149