1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include <asm/sgx.h> 22 #include "cpuid.h" 23 #include "lapic.h" 24 #include "mmu.h" 25 #include "trace.h" 26 #include "pmu.h" 27 28 /* 29 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 30 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 31 */ 32 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 33 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 34 35 static u32 xstate_required_size(u64 xstate_bv, bool compacted) 36 { 37 int feature_bit = 0; 38 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 39 40 xstate_bv &= XFEATURE_MASK_EXTEND; 41 while (xstate_bv) { 42 if (xstate_bv & 0x1) { 43 u32 eax, ebx, ecx, edx, offset; 44 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 45 offset = compacted ? ret : ebx; 46 ret = max(ret, offset + eax); 47 } 48 49 xstate_bv >>= 1; 50 feature_bit++; 51 } 52 53 return ret; 54 } 55 56 #define F feature_bit 57 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0) 58 59 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 60 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 61 { 62 struct kvm_cpuid_entry2 *e; 63 int i; 64 65 for (i = 0; i < nent; i++) { 66 e = &entries[i]; 67 68 if (e->function == function && (e->index == index || 69 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) 70 return e; 71 } 72 73 return NULL; 74 } 75 76 static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) 77 { 78 struct kvm_cpuid_entry2 *best; 79 80 /* 81 * The existing code assumes virtual address is 48-bit or 57-bit in the 82 * canonical address checks; exit if it is ever changed. 83 */ 84 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 85 if (best) { 86 int vaddr_bits = (best->eax & 0xff00) >> 8; 87 88 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 89 return -EINVAL; 90 } 91 92 return 0; 93 } 94 95 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 96 { 97 struct kvm_cpuid_entry2 *best; 98 99 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 100 101 /* 102 * save the feature bitmap to avoid cpuid lookup for every PV 103 * operation 104 */ 105 if (best) 106 vcpu->arch.pv_cpuid.features = best->eax; 107 } 108 109 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 110 { 111 struct kvm_cpuid_entry2 *best; 112 113 best = kvm_find_cpuid_entry(vcpu, 1, 0); 114 if (best) { 115 /* Update OSXSAVE bit */ 116 if (boot_cpu_has(X86_FEATURE_XSAVE)) 117 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 118 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 119 120 cpuid_entry_change(best, X86_FEATURE_APIC, 121 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 122 } 123 124 best = kvm_find_cpuid_entry(vcpu, 7, 0); 125 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 126 cpuid_entry_change(best, X86_FEATURE_OSPKE, 127 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 128 129 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 130 if (best) 131 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 132 133 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 134 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 135 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 136 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 137 138 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 139 if (kvm_hlt_in_guest(vcpu->kvm) && best && 140 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 141 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 142 143 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 144 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 145 if (best) 146 cpuid_entry_change(best, X86_FEATURE_MWAIT, 147 vcpu->arch.ia32_misc_enable_msr & 148 MSR_IA32_MISC_ENABLE_MWAIT); 149 } 150 } 151 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 152 153 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 154 { 155 struct kvm_lapic *apic = vcpu->arch.apic; 156 struct kvm_cpuid_entry2 *best; 157 158 best = kvm_find_cpuid_entry(vcpu, 1, 0); 159 if (best && apic) { 160 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 161 apic->lapic_timer.timer_mode_mask = 3 << 17; 162 else 163 apic->lapic_timer.timer_mode_mask = 1 << 17; 164 165 kvm_apic_set_version(vcpu); 166 } 167 168 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 169 if (!best) 170 vcpu->arch.guest_supported_xcr0 = 0; 171 else 172 vcpu->arch.guest_supported_xcr0 = 173 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 174 175 /* 176 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 177 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 178 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 179 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 180 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 181 * '1' even on CPUs that don't support XSAVE. 182 */ 183 best = kvm_find_cpuid_entry(vcpu, 0x12, 0x1); 184 if (best) { 185 best->ecx &= vcpu->arch.guest_supported_xcr0 & 0xffffffff; 186 best->edx &= vcpu->arch.guest_supported_xcr0 >> 32; 187 best->ecx |= XFEATURE_MASK_FPSSE; 188 } 189 190 kvm_update_pv_runtime(vcpu); 191 192 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 193 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 194 195 kvm_pmu_refresh(vcpu); 196 vcpu->arch.cr4_guest_rsvd_bits = 197 __cr4_reserved_bits(guest_cpuid_has, vcpu); 198 199 kvm_hv_set_cpuid(vcpu); 200 201 /* Invoke the vendor callback only after the above state is updated. */ 202 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 203 204 /* 205 * Except for the MMU, which needs to do its thing any vendor specific 206 * adjustments to the reserved GPA bits. 207 */ 208 kvm_mmu_after_set_cpuid(vcpu); 209 } 210 211 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 212 { 213 struct kvm_cpuid_entry2 *best; 214 215 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 216 if (!best || best->eax < 0x80000008) 217 goto not_found; 218 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 219 if (best) 220 return best->eax & 0xff; 221 not_found: 222 return 36; 223 } 224 225 /* 226 * This "raw" version returns the reserved GPA bits without any adjustments for 227 * encryption technologies that usurp bits. The raw mask should be used if and 228 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 229 */ 230 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 231 { 232 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 233 } 234 235 /* when an old userspace process fills a new kernel module */ 236 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 237 struct kvm_cpuid *cpuid, 238 struct kvm_cpuid_entry __user *entries) 239 { 240 int r, i; 241 struct kvm_cpuid_entry *e = NULL; 242 struct kvm_cpuid_entry2 *e2 = NULL; 243 244 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 245 return -E2BIG; 246 247 if (cpuid->nent) { 248 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 249 if (IS_ERR(e)) 250 return PTR_ERR(e); 251 252 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 253 if (!e2) { 254 r = -ENOMEM; 255 goto out_free_cpuid; 256 } 257 } 258 for (i = 0; i < cpuid->nent; i++) { 259 e2[i].function = e[i].function; 260 e2[i].eax = e[i].eax; 261 e2[i].ebx = e[i].ebx; 262 e2[i].ecx = e[i].ecx; 263 e2[i].edx = e[i].edx; 264 e2[i].index = 0; 265 e2[i].flags = 0; 266 e2[i].padding[0] = 0; 267 e2[i].padding[1] = 0; 268 e2[i].padding[2] = 0; 269 } 270 271 r = kvm_check_cpuid(e2, cpuid->nent); 272 if (r) { 273 kvfree(e2); 274 goto out_free_cpuid; 275 } 276 277 kvfree(vcpu->arch.cpuid_entries); 278 vcpu->arch.cpuid_entries = e2; 279 vcpu->arch.cpuid_nent = cpuid->nent; 280 281 kvm_update_cpuid_runtime(vcpu); 282 kvm_vcpu_after_set_cpuid(vcpu); 283 284 out_free_cpuid: 285 kvfree(e); 286 287 return r; 288 } 289 290 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 291 struct kvm_cpuid2 *cpuid, 292 struct kvm_cpuid_entry2 __user *entries) 293 { 294 struct kvm_cpuid_entry2 *e2 = NULL; 295 int r; 296 297 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 298 return -E2BIG; 299 300 if (cpuid->nent) { 301 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 302 if (IS_ERR(e2)) 303 return PTR_ERR(e2); 304 } 305 306 r = kvm_check_cpuid(e2, cpuid->nent); 307 if (r) { 308 kvfree(e2); 309 return r; 310 } 311 312 kvfree(vcpu->arch.cpuid_entries); 313 vcpu->arch.cpuid_entries = e2; 314 vcpu->arch.cpuid_nent = cpuid->nent; 315 316 kvm_update_cpuid_runtime(vcpu); 317 kvm_vcpu_after_set_cpuid(vcpu); 318 319 return 0; 320 } 321 322 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 323 struct kvm_cpuid2 *cpuid, 324 struct kvm_cpuid_entry2 __user *entries) 325 { 326 int r; 327 328 r = -E2BIG; 329 if (cpuid->nent < vcpu->arch.cpuid_nent) 330 goto out; 331 r = -EFAULT; 332 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 333 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 334 goto out; 335 return 0; 336 337 out: 338 cpuid->nent = vcpu->arch.cpuid_nent; 339 return r; 340 } 341 342 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 343 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 344 { 345 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 346 struct kvm_cpuid_entry2 entry; 347 348 reverse_cpuid_check(leaf); 349 350 cpuid_count(cpuid.function, cpuid.index, 351 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 352 353 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 354 } 355 356 static __always_inline 357 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask) 358 { 359 /* Use kvm_cpu_cap_mask for non-scattered leafs. */ 360 BUILD_BUG_ON(leaf < NCAPINTS); 361 362 kvm_cpu_caps[leaf] = mask; 363 364 __kvm_cpu_cap_mask(leaf); 365 } 366 367 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 368 { 369 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */ 370 BUILD_BUG_ON(leaf >= NCAPINTS); 371 372 kvm_cpu_caps[leaf] &= mask; 373 374 __kvm_cpu_cap_mask(leaf); 375 } 376 377 void kvm_set_cpu_caps(void) 378 { 379 #ifdef CONFIG_X86_64 380 unsigned int f_gbpages = F(GBPAGES); 381 unsigned int f_lm = F(LM); 382 #else 383 unsigned int f_gbpages = 0; 384 unsigned int f_lm = 0; 385 #endif 386 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 387 388 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 389 sizeof(boot_cpu_data.x86_capability)); 390 391 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 392 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 393 394 kvm_cpu_cap_mask(CPUID_1_ECX, 395 /* 396 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 397 * advertised to guests via CPUID! 398 */ 399 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 400 0 /* DS-CPL, VMX, SMX, EST */ | 401 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 402 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 403 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 404 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 405 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 406 F(F16C) | F(RDRAND) 407 ); 408 /* KVM emulates x2apic in software irrespective of host support. */ 409 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 410 411 kvm_cpu_cap_mask(CPUID_1_EDX, 412 F(FPU) | F(VME) | F(DE) | F(PSE) | 413 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 414 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 415 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 416 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 417 0 /* Reserved, DS, ACPI */ | F(MMX) | 418 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 419 0 /* HTT, TM, Reserved, PBE */ 420 ); 421 422 kvm_cpu_cap_mask(CPUID_7_0_EBX, 423 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 424 F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 425 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 426 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 427 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 428 ); 429 430 kvm_cpu_cap_mask(CPUID_7_ECX, 431 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 432 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 433 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 434 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 435 F(SGX_LC) | F(BUS_LOCK_DETECT) 436 ); 437 /* Set LA57 based on hardware capability. */ 438 if (cpuid_ecx(7) & F(LA57)) 439 kvm_cpu_cap_set(X86_FEATURE_LA57); 440 441 /* 442 * PKU not yet implemented for shadow paging and requires OSPKE 443 * to be set on the host. Clear it if that is not the case 444 */ 445 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 446 kvm_cpu_cap_clear(X86_FEATURE_PKU); 447 448 kvm_cpu_cap_mask(CPUID_7_EDX, 449 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 450 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 451 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 452 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) 453 ); 454 455 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 456 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 457 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 458 459 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 460 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 461 if (boot_cpu_has(X86_FEATURE_STIBP)) 462 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 463 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 464 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 465 466 kvm_cpu_cap_mask(CPUID_7_1_EAX, 467 F(AVX_VNNI) | F(AVX512_BF16) 468 ); 469 470 kvm_cpu_cap_mask(CPUID_D_1_EAX, 471 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) 472 ); 473 474 kvm_cpu_cap_init_scattered(CPUID_12_EAX, 475 SF(SGX1) | SF(SGX2) 476 ); 477 478 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 479 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 480 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 481 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 482 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 483 F(TOPOEXT) | F(PERFCTR_CORE) 484 ); 485 486 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 487 F(FPU) | F(VME) | F(DE) | F(PSE) | 488 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 489 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 490 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 491 F(PAT) | F(PSE36) | 0 /* Reserved */ | 492 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 493 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 494 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 495 ); 496 497 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 498 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 499 500 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 501 F(CLZERO) | F(XSAVEERPTR) | 502 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 503 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) 504 ); 505 506 /* 507 * AMD has separate bits for each SPEC_CTRL bit. 508 * arch/x86/kernel/cpu/bugs.c is kind enough to 509 * record that in cpufeatures so use them. 510 */ 511 if (boot_cpu_has(X86_FEATURE_IBPB)) 512 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 513 if (boot_cpu_has(X86_FEATURE_IBRS)) 514 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 515 if (boot_cpu_has(X86_FEATURE_STIBP)) 516 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 517 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 518 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 519 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 520 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 521 /* 522 * The preference is to use SPEC CTRL MSR instead of the 523 * VIRT_SPEC MSR. 524 */ 525 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 526 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 527 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 528 529 /* 530 * Hide all SVM features by default, SVM will set the cap bits for 531 * features it emulates and/or exposes for L1. 532 */ 533 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 534 535 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 536 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 537 F(SME_COHERENT)); 538 539 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 540 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 541 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 542 F(PMM) | F(PMM_EN) 543 ); 544 545 /* 546 * Hide RDTSCP and RDPID if either feature is reported as supported but 547 * probing MSR_TSC_AUX failed. This is purely a sanity check and 548 * should never happen, but the guest will likely crash if RDTSCP or 549 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 550 * the past. For example, the sanity check may fire if this instance of 551 * KVM is running as L1 on top of an older, broken KVM. 552 */ 553 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 554 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 555 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 556 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 557 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 558 } 559 } 560 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 561 562 struct kvm_cpuid_array { 563 struct kvm_cpuid_entry2 *entries; 564 int maxnent; 565 int nent; 566 }; 567 568 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 569 u32 function, u32 index) 570 { 571 struct kvm_cpuid_entry2 *entry; 572 573 if (array->nent >= array->maxnent) 574 return NULL; 575 576 entry = &array->entries[array->nent++]; 577 578 entry->function = function; 579 entry->index = index; 580 entry->flags = 0; 581 582 cpuid_count(entry->function, entry->index, 583 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 584 585 switch (function) { 586 case 4: 587 case 7: 588 case 0xb: 589 case 0xd: 590 case 0xf: 591 case 0x10: 592 case 0x12: 593 case 0x14: 594 case 0x17: 595 case 0x18: 596 case 0x1f: 597 case 0x8000001d: 598 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 599 break; 600 } 601 602 return entry; 603 } 604 605 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 606 { 607 struct kvm_cpuid_entry2 *entry; 608 609 if (array->nent >= array->maxnent) 610 return -E2BIG; 611 612 entry = &array->entries[array->nent]; 613 entry->function = func; 614 entry->index = 0; 615 entry->flags = 0; 616 617 switch (func) { 618 case 0: 619 entry->eax = 7; 620 ++array->nent; 621 break; 622 case 1: 623 entry->ecx = F(MOVBE); 624 ++array->nent; 625 break; 626 case 7: 627 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 628 entry->eax = 0; 629 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 630 entry->ecx = F(RDPID); 631 ++array->nent; 632 break; 633 default: 634 break; 635 } 636 637 return 0; 638 } 639 640 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 641 { 642 struct kvm_cpuid_entry2 *entry; 643 int r, i, max_idx; 644 645 /* all calls to cpuid_count() should be made on the same cpu */ 646 get_cpu(); 647 648 r = -E2BIG; 649 650 entry = do_host_cpuid(array, function, 0); 651 if (!entry) 652 goto out; 653 654 switch (function) { 655 case 0: 656 /* Limited to the highest leaf implemented in KVM. */ 657 entry->eax = min(entry->eax, 0x1fU); 658 break; 659 case 1: 660 cpuid_entry_override(entry, CPUID_1_EDX); 661 cpuid_entry_override(entry, CPUID_1_ECX); 662 break; 663 case 2: 664 /* 665 * On ancient CPUs, function 2 entries are STATEFUL. That is, 666 * CPUID(function=2, index=0) may return different results each 667 * time, with the least-significant byte in EAX enumerating the 668 * number of times software should do CPUID(2, 0). 669 * 670 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 671 * idiotic. Intel's SDM states that EAX & 0xff "will always 672 * return 01H. Software should ignore this value and not 673 * interpret it as an informational descriptor", while AMD's 674 * APM states that CPUID(2) is reserved. 675 * 676 * WARN if a frankenstein CPU that supports virtualization and 677 * a stateful CPUID.0x2 is encountered. 678 */ 679 WARN_ON_ONCE((entry->eax & 0xff) > 1); 680 break; 681 /* functions 4 and 0x8000001d have additional index. */ 682 case 4: 683 case 0x8000001d: 684 /* 685 * Read entries until the cache type in the previous entry is 686 * zero, i.e. indicates an invalid entry. 687 */ 688 for (i = 1; entry->eax & 0x1f; ++i) { 689 entry = do_host_cpuid(array, function, i); 690 if (!entry) 691 goto out; 692 } 693 break; 694 case 6: /* Thermal management */ 695 entry->eax = 0x4; /* allow ARAT */ 696 entry->ebx = 0; 697 entry->ecx = 0; 698 entry->edx = 0; 699 break; 700 /* function 7 has additional index. */ 701 case 7: 702 entry->eax = min(entry->eax, 1u); 703 cpuid_entry_override(entry, CPUID_7_0_EBX); 704 cpuid_entry_override(entry, CPUID_7_ECX); 705 cpuid_entry_override(entry, CPUID_7_EDX); 706 707 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 708 if (entry->eax == 1) { 709 entry = do_host_cpuid(array, function, 1); 710 if (!entry) 711 goto out; 712 713 cpuid_entry_override(entry, CPUID_7_1_EAX); 714 entry->ebx = 0; 715 entry->ecx = 0; 716 entry->edx = 0; 717 } 718 break; 719 case 9: 720 break; 721 case 0xa: { /* Architectural Performance Monitoring */ 722 struct x86_pmu_capability cap; 723 union cpuid10_eax eax; 724 union cpuid10_edx edx; 725 726 perf_get_x86_pmu_capability(&cap); 727 728 /* 729 * Only support guest architectural pmu on a host 730 * with architectural pmu. 731 */ 732 if (!cap.version) 733 memset(&cap, 0, sizeof(cap)); 734 735 eax.split.version_id = min(cap.version, 2); 736 eax.split.num_counters = cap.num_counters_gp; 737 eax.split.bit_width = cap.bit_width_gp; 738 eax.split.mask_length = cap.events_mask_len; 739 740 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 741 edx.split.bit_width_fixed = cap.bit_width_fixed; 742 if (cap.version) 743 edx.split.anythread_deprecated = 1; 744 edx.split.reserved1 = 0; 745 edx.split.reserved2 = 0; 746 747 entry->eax = eax.full; 748 entry->ebx = cap.events_mask; 749 entry->ecx = 0; 750 entry->edx = edx.full; 751 break; 752 } 753 /* 754 * Per Intel's SDM, the 0x1f is a superset of 0xb, 755 * thus they can be handled by common code. 756 */ 757 case 0x1f: 758 case 0xb: 759 /* 760 * Populate entries until the level type (ECX[15:8]) of the 761 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 762 * the starting entry, filled by the primary do_host_cpuid(). 763 */ 764 for (i = 1; entry->ecx & 0xff00; ++i) { 765 entry = do_host_cpuid(array, function, i); 766 if (!entry) 767 goto out; 768 } 769 break; 770 case 0xd: 771 entry->eax &= supported_xcr0; 772 entry->ebx = xstate_required_size(supported_xcr0, false); 773 entry->ecx = entry->ebx; 774 entry->edx &= supported_xcr0 >> 32; 775 if (!supported_xcr0) 776 break; 777 778 entry = do_host_cpuid(array, function, 1); 779 if (!entry) 780 goto out; 781 782 cpuid_entry_override(entry, CPUID_D_1_EAX); 783 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 784 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 785 true); 786 else { 787 WARN_ON_ONCE(supported_xss != 0); 788 entry->ebx = 0; 789 } 790 entry->ecx &= supported_xss; 791 entry->edx &= supported_xss >> 32; 792 793 for (i = 2; i < 64; ++i) { 794 bool s_state; 795 if (supported_xcr0 & BIT_ULL(i)) 796 s_state = false; 797 else if (supported_xss & BIT_ULL(i)) 798 s_state = true; 799 else 800 continue; 801 802 entry = do_host_cpuid(array, function, i); 803 if (!entry) 804 goto out; 805 806 /* 807 * The supported check above should have filtered out 808 * invalid sub-leafs. Only valid sub-leafs should 809 * reach this point, and they should have a non-zero 810 * save state size. Furthermore, check whether the 811 * processor agrees with supported_xcr0/supported_xss 812 * on whether this is an XCR0- or IA32_XSS-managed area. 813 */ 814 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 815 --array->nent; 816 continue; 817 } 818 entry->edx = 0; 819 } 820 break; 821 case 0x12: 822 /* Intel SGX */ 823 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 824 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 825 break; 826 } 827 828 /* 829 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 830 * and max enclave sizes. The SGX sub-features and MISCSELECT 831 * are restricted by kernel and KVM capabilities (like most 832 * feature flags), while enclave size is unrestricted. 833 */ 834 cpuid_entry_override(entry, CPUID_12_EAX); 835 entry->ebx &= SGX_MISC_EXINFO; 836 837 entry = do_host_cpuid(array, function, 1); 838 if (!entry) 839 goto out; 840 841 /* 842 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 843 * feature flags. Advertise all supported flags, including 844 * privileged attributes that require explicit opt-in from 845 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 846 * expected to derive it from supported XCR0. 847 */ 848 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | 849 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY | 850 SGX_ATTR_KSS; 851 entry->ebx &= 0; 852 break; 853 /* Intel PT */ 854 case 0x14: 855 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 856 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 857 break; 858 } 859 860 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 861 if (!do_host_cpuid(array, function, i)) 862 goto out; 863 } 864 break; 865 case KVM_CPUID_SIGNATURE: { 866 static const char signature[12] = "KVMKVMKVM\0\0"; 867 const u32 *sigptr = (const u32 *)signature; 868 entry->eax = KVM_CPUID_FEATURES; 869 entry->ebx = sigptr[0]; 870 entry->ecx = sigptr[1]; 871 entry->edx = sigptr[2]; 872 break; 873 } 874 case KVM_CPUID_FEATURES: 875 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 876 (1 << KVM_FEATURE_NOP_IO_DELAY) | 877 (1 << KVM_FEATURE_CLOCKSOURCE2) | 878 (1 << KVM_FEATURE_ASYNC_PF) | 879 (1 << KVM_FEATURE_PV_EOI) | 880 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 881 (1 << KVM_FEATURE_PV_UNHALT) | 882 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 883 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 884 (1 << KVM_FEATURE_PV_SEND_IPI) | 885 (1 << KVM_FEATURE_POLL_CONTROL) | 886 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 887 (1 << KVM_FEATURE_ASYNC_PF_INT); 888 889 if (sched_info_on()) 890 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 891 892 entry->ebx = 0; 893 entry->ecx = 0; 894 entry->edx = 0; 895 break; 896 case 0x80000000: 897 entry->eax = min(entry->eax, 0x8000001f); 898 break; 899 case 0x80000001: 900 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 901 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 902 break; 903 case 0x80000006: 904 /* L2 cache and TLB: pass through host info. */ 905 break; 906 case 0x80000007: /* Advanced power management */ 907 /* invariant TSC is CPUID.80000007H:EDX[8] */ 908 entry->edx &= (1 << 8); 909 /* mask against host */ 910 entry->edx &= boot_cpu_data.x86_power; 911 entry->eax = entry->ebx = entry->ecx = 0; 912 break; 913 case 0x80000008: { 914 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 915 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 916 unsigned phys_as = entry->eax & 0xff; 917 918 /* 919 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 920 * the guest operates in the same PA space as the host, i.e. 921 * reductions in MAXPHYADDR for memory encryption affect shadow 922 * paging, too. 923 * 924 * If TDP is enabled but an explicit guest MAXPHYADDR is not 925 * provided, use the raw bare metal MAXPHYADDR as reductions to 926 * the HPAs do not affect GPAs. 927 */ 928 if (!tdp_enabled) 929 g_phys_as = boot_cpu_data.x86_phys_bits; 930 else if (!g_phys_as) 931 g_phys_as = phys_as; 932 933 entry->eax = g_phys_as | (virt_as << 8); 934 entry->edx = 0; 935 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 936 break; 937 } 938 case 0x8000000A: 939 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 940 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 941 break; 942 } 943 entry->eax = 1; /* SVM revision 1 */ 944 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 945 ASID emulation to nested SVM */ 946 entry->ecx = 0; /* Reserved */ 947 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 948 break; 949 case 0x80000019: 950 entry->ecx = entry->edx = 0; 951 break; 952 case 0x8000001a: 953 case 0x8000001e: 954 break; 955 case 0x8000001F: 956 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 957 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 958 } else { 959 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 960 961 /* 962 * Enumerate '0' for "PA bits reduction", the adjusted 963 * MAXPHYADDR is enumerated directly (see 0x80000008). 964 */ 965 entry->ebx &= ~GENMASK(11, 6); 966 } 967 break; 968 /*Add support for Centaur's CPUID instruction*/ 969 case 0xC0000000: 970 /*Just support up to 0xC0000004 now*/ 971 entry->eax = min(entry->eax, 0xC0000004); 972 break; 973 case 0xC0000001: 974 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 975 break; 976 case 3: /* Processor serial number */ 977 case 5: /* MONITOR/MWAIT */ 978 case 0xC0000002: 979 case 0xC0000003: 980 case 0xC0000004: 981 default: 982 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 983 break; 984 } 985 986 r = 0; 987 988 out: 989 put_cpu(); 990 991 return r; 992 } 993 994 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 995 unsigned int type) 996 { 997 if (type == KVM_GET_EMULATED_CPUID) 998 return __do_cpuid_func_emulated(array, func); 999 1000 return __do_cpuid_func(array, func); 1001 } 1002 1003 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1004 1005 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1006 unsigned int type) 1007 { 1008 u32 limit; 1009 int r; 1010 1011 if (func == CENTAUR_CPUID_SIGNATURE && 1012 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1013 return 0; 1014 1015 r = do_cpuid_func(array, func, type); 1016 if (r) 1017 return r; 1018 1019 limit = array->entries[array->nent - 1].eax; 1020 for (func = func + 1; func <= limit; ++func) { 1021 r = do_cpuid_func(array, func, type); 1022 if (r) 1023 break; 1024 } 1025 1026 return r; 1027 } 1028 1029 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1030 __u32 num_entries, unsigned int ioctl_type) 1031 { 1032 int i; 1033 __u32 pad[3]; 1034 1035 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1036 return false; 1037 1038 /* 1039 * We want to make sure that ->padding is being passed clean from 1040 * userspace in case we want to use it for something in the future. 1041 * 1042 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1043 * have to give ourselves satisfied only with the emulated side. /me 1044 * sheds a tear. 1045 */ 1046 for (i = 0; i < num_entries; i++) { 1047 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1048 return true; 1049 1050 if (pad[0] || pad[1] || pad[2]) 1051 return true; 1052 } 1053 return false; 1054 } 1055 1056 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1057 struct kvm_cpuid_entry2 __user *entries, 1058 unsigned int type) 1059 { 1060 static const u32 funcs[] = { 1061 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1062 }; 1063 1064 struct kvm_cpuid_array array = { 1065 .nent = 0, 1066 }; 1067 int r, i; 1068 1069 if (cpuid->nent < 1) 1070 return -E2BIG; 1071 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1072 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1073 1074 if (sanity_check_entries(entries, cpuid->nent, type)) 1075 return -EINVAL; 1076 1077 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 1078 cpuid->nent)); 1079 if (!array.entries) 1080 return -ENOMEM; 1081 1082 array.maxnent = cpuid->nent; 1083 1084 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1085 r = get_cpuid_func(&array, funcs[i], type); 1086 if (r) 1087 goto out_free; 1088 } 1089 cpuid->nent = array.nent; 1090 1091 if (copy_to_user(entries, array.entries, 1092 array.nent * sizeof(struct kvm_cpuid_entry2))) 1093 r = -EFAULT; 1094 1095 out_free: 1096 vfree(array.entries); 1097 return r; 1098 } 1099 1100 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1101 u32 function, u32 index) 1102 { 1103 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1104 function, index); 1105 } 1106 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1107 1108 /* 1109 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1110 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1111 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1112 * range. Centaur/VIA follows Intel semantics. 1113 * 1114 * A leaf is considered out-of-range if its function is higher than the maximum 1115 * supported leaf of its associated class or if its associated class does not 1116 * exist. 1117 * 1118 * There are three primary classes to be considered, with their respective 1119 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1120 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1121 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1122 * 1123 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1124 * - Hypervisor: 0x40000000 - 0x4fffffff 1125 * - Extended: 0x80000000 - 0xbfffffff 1126 * - Centaur: 0xc0000000 - 0xcfffffff 1127 * 1128 * The Hypervisor class is further subdivided into sub-classes that each act as 1129 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1130 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1131 * CPUID sub-classes are: 1132 * 1133 * - HyperV: 0x40000000 - 0x400000ff 1134 * - KVM: 0x40000100 - 0x400001ff 1135 */ 1136 static struct kvm_cpuid_entry2 * 1137 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1138 { 1139 struct kvm_cpuid_entry2 *basic, *class; 1140 u32 function = *fn_ptr; 1141 1142 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1143 if (!basic) 1144 return NULL; 1145 1146 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1147 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1148 return NULL; 1149 1150 if (function >= 0x40000000 && function <= 0x4fffffff) 1151 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1152 else if (function >= 0xc0000000) 1153 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1154 else 1155 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1156 1157 if (class && function <= class->eax) 1158 return NULL; 1159 1160 /* 1161 * Leaf specific adjustments are also applied when redirecting to the 1162 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1163 * entry for CPUID.0xb.index (see below), then the output value for EDX 1164 * needs to be pulled from CPUID.0xb.1. 1165 */ 1166 *fn_ptr = basic->eax; 1167 1168 /* 1169 * The class does not exist or the requested function is out of range; 1170 * the effective CPUID entry is the max basic leaf. Note, the index of 1171 * the original requested leaf is observed! 1172 */ 1173 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1174 } 1175 1176 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1177 u32 *ecx, u32 *edx, bool exact_only) 1178 { 1179 u32 orig_function = *eax, function = *eax, index = *ecx; 1180 struct kvm_cpuid_entry2 *entry; 1181 bool exact, used_max_basic = false; 1182 1183 entry = kvm_find_cpuid_entry(vcpu, function, index); 1184 exact = !!entry; 1185 1186 if (!entry && !exact_only) { 1187 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1188 used_max_basic = !!entry; 1189 } 1190 1191 if (entry) { 1192 *eax = entry->eax; 1193 *ebx = entry->ebx; 1194 *ecx = entry->ecx; 1195 *edx = entry->edx; 1196 if (function == 7 && index == 0) { 1197 u64 data; 1198 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1199 (data & TSX_CTRL_CPUID_CLEAR)) 1200 *ebx &= ~(F(RTM) | F(HLE)); 1201 } 1202 } else { 1203 *eax = *ebx = *ecx = *edx = 0; 1204 /* 1205 * When leaf 0BH or 1FH is defined, CL is pass-through 1206 * and EDX is always the x2APIC ID, even for undefined 1207 * subleaves. Index 1 will exist iff the leaf is 1208 * implemented, so we pass through CL iff leaf 1 1209 * exists. EDX can be copied from any existing index. 1210 */ 1211 if (function == 0xb || function == 0x1f) { 1212 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1213 if (entry) { 1214 *ecx = index & 0xff; 1215 *edx = entry->edx; 1216 } 1217 } 1218 } 1219 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1220 used_max_basic); 1221 return exact; 1222 } 1223 EXPORT_SYMBOL_GPL(kvm_cpuid); 1224 1225 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1226 { 1227 u32 eax, ebx, ecx, edx; 1228 1229 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1230 return 1; 1231 1232 eax = kvm_rax_read(vcpu); 1233 ecx = kvm_rcx_read(vcpu); 1234 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1235 kvm_rax_write(vcpu, eax); 1236 kvm_rbx_write(vcpu, ebx); 1237 kvm_rcx_write(vcpu, ecx); 1238 kvm_rdx_write(vcpu, edx); 1239 return kvm_skip_emulated_instruction(vcpu); 1240 } 1241 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1242