1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include <asm/sgx.h> 22 #include "cpuid.h" 23 #include "lapic.h" 24 #include "mmu.h" 25 #include "trace.h" 26 #include "pmu.h" 27 28 /* 29 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 30 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 31 */ 32 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 33 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 34 35 u32 xstate_required_size(u64 xstate_bv, bool compacted) 36 { 37 int feature_bit = 0; 38 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 39 40 xstate_bv &= XFEATURE_MASK_EXTEND; 41 while (xstate_bv) { 42 if (xstate_bv & 0x1) { 43 u32 eax, ebx, ecx, edx, offset; 44 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 45 /* ECX[1]: 64B alignment in compacted form */ 46 if (compacted) 47 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 48 else 49 offset = ebx; 50 ret = max(ret, offset + eax); 51 } 52 53 xstate_bv >>= 1; 54 feature_bit++; 55 } 56 57 return ret; 58 } 59 60 /* 61 * This one is tied to SSB in the user API, and not 62 * visible in /proc/cpuinfo. 63 */ 64 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ 65 66 #define F feature_bit 67 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0) 68 69 70 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 71 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 72 { 73 struct kvm_cpuid_entry2 *e; 74 int i; 75 76 for (i = 0; i < nent; i++) { 77 e = &entries[i]; 78 79 if (e->function == function && 80 (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)) 81 return e; 82 } 83 84 return NULL; 85 } 86 87 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 88 struct kvm_cpuid_entry2 *entries, 89 int nent) 90 { 91 struct kvm_cpuid_entry2 *best; 92 u64 xfeatures; 93 94 /* 95 * The existing code assumes virtual address is 48-bit or 57-bit in the 96 * canonical address checks; exit if it is ever changed. 97 */ 98 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 99 if (best) { 100 int vaddr_bits = (best->eax & 0xff00) >> 8; 101 102 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 103 return -EINVAL; 104 } 105 106 /* 107 * Exposing dynamic xfeatures to the guest requires additional 108 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 109 */ 110 best = cpuid_entry2_find(entries, nent, 0xd, 0); 111 if (!best) 112 return 0; 113 114 xfeatures = best->eax | ((u64)best->edx << 32); 115 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 116 if (!xfeatures) 117 return 0; 118 119 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 120 } 121 122 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 123 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 124 int nent) 125 { 126 struct kvm_cpuid_entry2 *orig; 127 int i; 128 129 if (nent != vcpu->arch.cpuid_nent) 130 return -EINVAL; 131 132 for (i = 0; i < nent; i++) { 133 orig = &vcpu->arch.cpuid_entries[i]; 134 if (e2[i].function != orig->function || 135 e2[i].index != orig->index || 136 e2[i].flags != orig->flags || 137 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 138 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 139 return -EINVAL; 140 } 141 142 return 0; 143 } 144 145 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu) 146 { 147 u32 function; 148 struct kvm_cpuid_entry2 *entry; 149 150 vcpu->arch.kvm_cpuid_base = 0; 151 152 for_each_possible_hypervisor_cpuid_base(function) { 153 entry = kvm_find_cpuid_entry(vcpu, function, 0); 154 155 if (entry) { 156 u32 signature[3]; 157 158 signature[0] = entry->ebx; 159 signature[1] = entry->ecx; 160 signature[2] = entry->edx; 161 162 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE)); 163 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) { 164 vcpu->arch.kvm_cpuid_base = function; 165 break; 166 } 167 } 168 } 169 } 170 171 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 172 struct kvm_cpuid_entry2 *entries, int nent) 173 { 174 u32 base = vcpu->arch.kvm_cpuid_base; 175 176 if (!base) 177 return NULL; 178 179 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 0); 180 } 181 182 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 183 { 184 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 185 vcpu->arch.cpuid_nent); 186 } 187 188 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 189 { 190 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 191 192 /* 193 * save the feature bitmap to avoid cpuid lookup for every PV 194 * operation 195 */ 196 if (best) 197 vcpu->arch.pv_cpuid.features = best->eax; 198 } 199 200 /* 201 * Calculate guest's supported XCR0 taking into account guest CPUID data and 202 * supported_xcr0 (comprised of host configuration and KVM_SUPPORTED_XCR0). 203 */ 204 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 205 { 206 struct kvm_cpuid_entry2 *best; 207 208 best = cpuid_entry2_find(entries, nent, 0xd, 0); 209 if (!best) 210 return 0; 211 212 return (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 213 } 214 215 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 216 int nent) 217 { 218 struct kvm_cpuid_entry2 *best; 219 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent); 220 221 best = cpuid_entry2_find(entries, nent, 1, 0); 222 if (best) { 223 /* Update OSXSAVE bit */ 224 if (boot_cpu_has(X86_FEATURE_XSAVE)) 225 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 226 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 227 228 cpuid_entry_change(best, X86_FEATURE_APIC, 229 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 230 } 231 232 best = cpuid_entry2_find(entries, nent, 7, 0); 233 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 234 cpuid_entry_change(best, X86_FEATURE_OSPKE, 235 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 236 237 best = cpuid_entry2_find(entries, nent, 0xD, 0); 238 if (best) 239 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 240 241 best = cpuid_entry2_find(entries, nent, 0xD, 1); 242 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 243 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 244 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 245 246 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 247 if (kvm_hlt_in_guest(vcpu->kvm) && best && 248 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 249 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 250 251 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 252 best = cpuid_entry2_find(entries, nent, 0x1, 0); 253 if (best) 254 cpuid_entry_change(best, X86_FEATURE_MWAIT, 255 vcpu->arch.ia32_misc_enable_msr & 256 MSR_IA32_MISC_ENABLE_MWAIT); 257 } 258 259 /* 260 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 261 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 262 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 263 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 264 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 265 * '1' even on CPUs that don't support XSAVE. 266 */ 267 best = cpuid_entry2_find(entries, nent, 0x12, 0x1); 268 if (best) { 269 best->ecx &= guest_supported_xcr0 & 0xffffffff; 270 best->edx &= guest_supported_xcr0 >> 32; 271 best->ecx |= XFEATURE_MASK_FPSSE; 272 } 273 } 274 275 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 276 { 277 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 278 } 279 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 280 281 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 282 { 283 struct kvm_lapic *apic = vcpu->arch.apic; 284 struct kvm_cpuid_entry2 *best; 285 286 best = kvm_find_cpuid_entry(vcpu, 1, 0); 287 if (best && apic) { 288 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 289 apic->lapic_timer.timer_mode_mask = 3 << 17; 290 else 291 apic->lapic_timer.timer_mode_mask = 1 << 17; 292 293 kvm_apic_set_version(vcpu); 294 } 295 296 vcpu->arch.guest_supported_xcr0 = 297 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 298 299 kvm_update_pv_runtime(vcpu); 300 301 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 302 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 303 304 kvm_pmu_refresh(vcpu); 305 vcpu->arch.cr4_guest_rsvd_bits = 306 __cr4_reserved_bits(guest_cpuid_has, vcpu); 307 308 kvm_hv_set_cpuid(vcpu); 309 310 /* Invoke the vendor callback only after the above state is updated. */ 311 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 312 313 /* 314 * Except for the MMU, which needs to do its thing any vendor specific 315 * adjustments to the reserved GPA bits. 316 */ 317 kvm_mmu_after_set_cpuid(vcpu); 318 } 319 320 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 321 { 322 struct kvm_cpuid_entry2 *best; 323 324 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 325 if (!best || best->eax < 0x80000008) 326 goto not_found; 327 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 328 if (best) 329 return best->eax & 0xff; 330 not_found: 331 return 36; 332 } 333 334 /* 335 * This "raw" version returns the reserved GPA bits without any adjustments for 336 * encryption technologies that usurp bits. The raw mask should be used if and 337 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 338 */ 339 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 340 { 341 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 342 } 343 344 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 345 int nent) 346 { 347 int r; 348 349 __kvm_update_cpuid_runtime(vcpu, e2, nent); 350 351 /* 352 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 353 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 354 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 355 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 356 * the core vCPU model on the fly. It would've been better to forbid any 357 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 358 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 359 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 360 * whether the supplied CPUID data is equal to what's already set. 361 */ 362 if (vcpu->arch.last_vmentry_cpu != -1) { 363 r = kvm_cpuid_check_equal(vcpu, e2, nent); 364 if (r) 365 return r; 366 367 kvfree(e2); 368 return 0; 369 } 370 371 r = kvm_check_cpuid(vcpu, e2, nent); 372 if (r) 373 return r; 374 375 kvfree(vcpu->arch.cpuid_entries); 376 vcpu->arch.cpuid_entries = e2; 377 vcpu->arch.cpuid_nent = nent; 378 379 kvm_update_kvm_cpuid_base(vcpu); 380 kvm_vcpu_after_set_cpuid(vcpu); 381 382 return 0; 383 } 384 385 /* when an old userspace process fills a new kernel module */ 386 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 387 struct kvm_cpuid *cpuid, 388 struct kvm_cpuid_entry __user *entries) 389 { 390 int r, i; 391 struct kvm_cpuid_entry *e = NULL; 392 struct kvm_cpuid_entry2 *e2 = NULL; 393 394 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 395 return -E2BIG; 396 397 if (cpuid->nent) { 398 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 399 if (IS_ERR(e)) 400 return PTR_ERR(e); 401 402 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 403 if (!e2) { 404 r = -ENOMEM; 405 goto out_free_cpuid; 406 } 407 } 408 for (i = 0; i < cpuid->nent; i++) { 409 e2[i].function = e[i].function; 410 e2[i].eax = e[i].eax; 411 e2[i].ebx = e[i].ebx; 412 e2[i].ecx = e[i].ecx; 413 e2[i].edx = e[i].edx; 414 e2[i].index = 0; 415 e2[i].flags = 0; 416 e2[i].padding[0] = 0; 417 e2[i].padding[1] = 0; 418 e2[i].padding[2] = 0; 419 } 420 421 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 422 if (r) 423 kvfree(e2); 424 425 out_free_cpuid: 426 kvfree(e); 427 428 return r; 429 } 430 431 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 432 struct kvm_cpuid2 *cpuid, 433 struct kvm_cpuid_entry2 __user *entries) 434 { 435 struct kvm_cpuid_entry2 *e2 = NULL; 436 int r; 437 438 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 439 return -E2BIG; 440 441 if (cpuid->nent) { 442 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 443 if (IS_ERR(e2)) 444 return PTR_ERR(e2); 445 } 446 447 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 448 if (r) 449 kvfree(e2); 450 451 return r; 452 } 453 454 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 455 struct kvm_cpuid2 *cpuid, 456 struct kvm_cpuid_entry2 __user *entries) 457 { 458 int r; 459 460 r = -E2BIG; 461 if (cpuid->nent < vcpu->arch.cpuid_nent) 462 goto out; 463 r = -EFAULT; 464 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 465 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 466 goto out; 467 return 0; 468 469 out: 470 cpuid->nent = vcpu->arch.cpuid_nent; 471 return r; 472 } 473 474 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 475 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 476 { 477 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 478 struct kvm_cpuid_entry2 entry; 479 480 reverse_cpuid_check(leaf); 481 482 cpuid_count(cpuid.function, cpuid.index, 483 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 484 485 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 486 } 487 488 static __always_inline 489 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask) 490 { 491 /* Use kvm_cpu_cap_mask for non-scattered leafs. */ 492 BUILD_BUG_ON(leaf < NCAPINTS); 493 494 kvm_cpu_caps[leaf] = mask; 495 496 __kvm_cpu_cap_mask(leaf); 497 } 498 499 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 500 { 501 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */ 502 BUILD_BUG_ON(leaf >= NCAPINTS); 503 504 kvm_cpu_caps[leaf] &= mask; 505 506 __kvm_cpu_cap_mask(leaf); 507 } 508 509 void kvm_set_cpu_caps(void) 510 { 511 #ifdef CONFIG_X86_64 512 unsigned int f_gbpages = F(GBPAGES); 513 unsigned int f_lm = F(LM); 514 unsigned int f_xfd = F(XFD); 515 #else 516 unsigned int f_gbpages = 0; 517 unsigned int f_lm = 0; 518 unsigned int f_xfd = 0; 519 #endif 520 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 521 522 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 523 sizeof(boot_cpu_data.x86_capability)); 524 525 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 526 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 527 528 kvm_cpu_cap_mask(CPUID_1_ECX, 529 /* 530 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 531 * advertised to guests via CPUID! 532 */ 533 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 534 0 /* DS-CPL, VMX, SMX, EST */ | 535 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 536 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 537 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 538 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 539 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 540 F(F16C) | F(RDRAND) 541 ); 542 /* KVM emulates x2apic in software irrespective of host support. */ 543 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 544 545 kvm_cpu_cap_mask(CPUID_1_EDX, 546 F(FPU) | F(VME) | F(DE) | F(PSE) | 547 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 548 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 549 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 550 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 551 0 /* Reserved, DS, ACPI */ | F(MMX) | 552 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 553 0 /* HTT, TM, Reserved, PBE */ 554 ); 555 556 kvm_cpu_cap_mask(CPUID_7_0_EBX, 557 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 558 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 559 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 560 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 561 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 562 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 563 F(AVX512VL)); 564 565 kvm_cpu_cap_mask(CPUID_7_ECX, 566 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 567 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 568 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 569 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 570 F(SGX_LC) | F(BUS_LOCK_DETECT) 571 ); 572 /* Set LA57 based on hardware capability. */ 573 if (cpuid_ecx(7) & F(LA57)) 574 kvm_cpu_cap_set(X86_FEATURE_LA57); 575 576 /* 577 * PKU not yet implemented for shadow paging and requires OSPKE 578 * to be set on the host. Clear it if that is not the case 579 */ 580 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 581 kvm_cpu_cap_clear(X86_FEATURE_PKU); 582 583 kvm_cpu_cap_mask(CPUID_7_EDX, 584 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 585 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 586 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 587 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 588 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) 589 ); 590 591 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 592 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 593 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 594 595 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 596 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 597 if (boot_cpu_has(X86_FEATURE_STIBP)) 598 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 599 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 600 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 601 602 kvm_cpu_cap_mask(CPUID_7_1_EAX, 603 F(AVX_VNNI) | F(AVX512_BF16) 604 ); 605 606 kvm_cpu_cap_mask(CPUID_D_1_EAX, 607 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 608 ); 609 610 kvm_cpu_cap_init_scattered(CPUID_12_EAX, 611 SF(SGX1) | SF(SGX2) 612 ); 613 614 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 615 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 616 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 617 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 618 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 619 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 620 ); 621 622 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 623 F(FPU) | F(VME) | F(DE) | F(PSE) | 624 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 625 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 626 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 627 F(PAT) | F(PSE36) | 0 /* Reserved */ | 628 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 629 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 630 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 631 ); 632 633 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 634 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 635 636 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 637 F(CLZERO) | F(XSAVEERPTR) | 638 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 639 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 640 __feature_bit(KVM_X86_FEATURE_PSFD) 641 ); 642 643 /* 644 * AMD has separate bits for each SPEC_CTRL bit. 645 * arch/x86/kernel/cpu/bugs.c is kind enough to 646 * record that in cpufeatures so use them. 647 */ 648 if (boot_cpu_has(X86_FEATURE_IBPB)) 649 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 650 if (boot_cpu_has(X86_FEATURE_IBRS)) 651 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 652 if (boot_cpu_has(X86_FEATURE_STIBP)) 653 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 654 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 655 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 656 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 657 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 658 /* 659 * The preference is to use SPEC CTRL MSR instead of the 660 * VIRT_SPEC MSR. 661 */ 662 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 663 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 664 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 665 666 /* 667 * Hide all SVM features by default, SVM will set the cap bits for 668 * features it emulates and/or exposes for L1. 669 */ 670 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 671 672 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 673 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 674 F(SME_COHERENT)); 675 676 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 677 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 678 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 679 F(PMM) | F(PMM_EN) 680 ); 681 682 /* 683 * Hide RDTSCP and RDPID if either feature is reported as supported but 684 * probing MSR_TSC_AUX failed. This is purely a sanity check and 685 * should never happen, but the guest will likely crash if RDTSCP or 686 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 687 * the past. For example, the sanity check may fire if this instance of 688 * KVM is running as L1 on top of an older, broken KVM. 689 */ 690 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 691 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 692 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 693 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 694 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 695 } 696 } 697 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 698 699 struct kvm_cpuid_array { 700 struct kvm_cpuid_entry2 *entries; 701 int maxnent; 702 int nent; 703 }; 704 705 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 706 u32 function, u32 index) 707 { 708 struct kvm_cpuid_entry2 *entry; 709 710 if (array->nent >= array->maxnent) 711 return NULL; 712 713 entry = &array->entries[array->nent++]; 714 715 entry->function = function; 716 entry->index = index; 717 entry->flags = 0; 718 719 cpuid_count(entry->function, entry->index, 720 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 721 722 switch (function) { 723 case 4: 724 case 7: 725 case 0xb: 726 case 0xd: 727 case 0xf: 728 case 0x10: 729 case 0x12: 730 case 0x14: 731 case 0x17: 732 case 0x18: 733 case 0x1d: 734 case 0x1e: 735 case 0x1f: 736 case 0x8000001d: 737 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 738 break; 739 } 740 741 return entry; 742 } 743 744 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 745 { 746 struct kvm_cpuid_entry2 *entry; 747 748 if (array->nent >= array->maxnent) 749 return -E2BIG; 750 751 entry = &array->entries[array->nent]; 752 entry->function = func; 753 entry->index = 0; 754 entry->flags = 0; 755 756 switch (func) { 757 case 0: 758 entry->eax = 7; 759 ++array->nent; 760 break; 761 case 1: 762 entry->ecx = F(MOVBE); 763 ++array->nent; 764 break; 765 case 7: 766 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 767 entry->eax = 0; 768 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 769 entry->ecx = F(RDPID); 770 ++array->nent; 771 break; 772 default: 773 break; 774 } 775 776 return 0; 777 } 778 779 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 780 { 781 struct kvm_cpuid_entry2 *entry; 782 int r, i, max_idx; 783 784 /* all calls to cpuid_count() should be made on the same cpu */ 785 get_cpu(); 786 787 r = -E2BIG; 788 789 entry = do_host_cpuid(array, function, 0); 790 if (!entry) 791 goto out; 792 793 switch (function) { 794 case 0: 795 /* Limited to the highest leaf implemented in KVM. */ 796 entry->eax = min(entry->eax, 0x1fU); 797 break; 798 case 1: 799 cpuid_entry_override(entry, CPUID_1_EDX); 800 cpuid_entry_override(entry, CPUID_1_ECX); 801 break; 802 case 2: 803 /* 804 * On ancient CPUs, function 2 entries are STATEFUL. That is, 805 * CPUID(function=2, index=0) may return different results each 806 * time, with the least-significant byte in EAX enumerating the 807 * number of times software should do CPUID(2, 0). 808 * 809 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 810 * idiotic. Intel's SDM states that EAX & 0xff "will always 811 * return 01H. Software should ignore this value and not 812 * interpret it as an informational descriptor", while AMD's 813 * APM states that CPUID(2) is reserved. 814 * 815 * WARN if a frankenstein CPU that supports virtualization and 816 * a stateful CPUID.0x2 is encountered. 817 */ 818 WARN_ON_ONCE((entry->eax & 0xff) > 1); 819 break; 820 /* functions 4 and 0x8000001d have additional index. */ 821 case 4: 822 case 0x8000001d: 823 /* 824 * Read entries until the cache type in the previous entry is 825 * zero, i.e. indicates an invalid entry. 826 */ 827 for (i = 1; entry->eax & 0x1f; ++i) { 828 entry = do_host_cpuid(array, function, i); 829 if (!entry) 830 goto out; 831 } 832 break; 833 case 6: /* Thermal management */ 834 entry->eax = 0x4; /* allow ARAT */ 835 entry->ebx = 0; 836 entry->ecx = 0; 837 entry->edx = 0; 838 break; 839 /* function 7 has additional index. */ 840 case 7: 841 entry->eax = min(entry->eax, 1u); 842 cpuid_entry_override(entry, CPUID_7_0_EBX); 843 cpuid_entry_override(entry, CPUID_7_ECX); 844 cpuid_entry_override(entry, CPUID_7_EDX); 845 846 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 847 if (entry->eax == 1) { 848 entry = do_host_cpuid(array, function, 1); 849 if (!entry) 850 goto out; 851 852 cpuid_entry_override(entry, CPUID_7_1_EAX); 853 entry->ebx = 0; 854 entry->ecx = 0; 855 entry->edx = 0; 856 } 857 break; 858 case 9: 859 break; 860 case 0xa: { /* Architectural Performance Monitoring */ 861 struct x86_pmu_capability cap; 862 union cpuid10_eax eax; 863 union cpuid10_edx edx; 864 865 perf_get_x86_pmu_capability(&cap); 866 867 /* 868 * The guest architecture pmu is only supported if the architecture 869 * pmu exists on the host and the module parameters allow it. 870 */ 871 if (!cap.version || !enable_pmu) 872 memset(&cap, 0, sizeof(cap)); 873 874 eax.split.version_id = min(cap.version, 2); 875 eax.split.num_counters = cap.num_counters_gp; 876 eax.split.bit_width = cap.bit_width_gp; 877 eax.split.mask_length = cap.events_mask_len; 878 879 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 880 edx.split.bit_width_fixed = cap.bit_width_fixed; 881 if (cap.version) 882 edx.split.anythread_deprecated = 1; 883 edx.split.reserved1 = 0; 884 edx.split.reserved2 = 0; 885 886 entry->eax = eax.full; 887 entry->ebx = cap.events_mask; 888 entry->ecx = 0; 889 entry->edx = edx.full; 890 break; 891 } 892 /* 893 * Per Intel's SDM, the 0x1f is a superset of 0xb, 894 * thus they can be handled by common code. 895 */ 896 case 0x1f: 897 case 0xb: 898 /* 899 * Populate entries until the level type (ECX[15:8]) of the 900 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 901 * the starting entry, filled by the primary do_host_cpuid(). 902 */ 903 for (i = 1; entry->ecx & 0xff00; ++i) { 904 entry = do_host_cpuid(array, function, i); 905 if (!entry) 906 goto out; 907 } 908 break; 909 case 0xd: { 910 u64 permitted_xcr0 = supported_xcr0 & xstate_get_guest_group_perm(); 911 u64 permitted_xss = supported_xss; 912 913 entry->eax &= permitted_xcr0; 914 entry->ebx = xstate_required_size(permitted_xcr0, false); 915 entry->ecx = entry->ebx; 916 entry->edx &= permitted_xcr0 >> 32; 917 if (!permitted_xcr0) 918 break; 919 920 entry = do_host_cpuid(array, function, 1); 921 if (!entry) 922 goto out; 923 924 cpuid_entry_override(entry, CPUID_D_1_EAX); 925 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 926 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 927 true); 928 else { 929 WARN_ON_ONCE(permitted_xss != 0); 930 entry->ebx = 0; 931 } 932 entry->ecx &= permitted_xss; 933 entry->edx &= permitted_xss >> 32; 934 935 for (i = 2; i < 64; ++i) { 936 bool s_state; 937 if (permitted_xcr0 & BIT_ULL(i)) 938 s_state = false; 939 else if (permitted_xss & BIT_ULL(i)) 940 s_state = true; 941 else 942 continue; 943 944 entry = do_host_cpuid(array, function, i); 945 if (!entry) 946 goto out; 947 948 /* 949 * The supported check above should have filtered out 950 * invalid sub-leafs. Only valid sub-leafs should 951 * reach this point, and they should have a non-zero 952 * save state size. Furthermore, check whether the 953 * processor agrees with permitted_xcr0/permitted_xss 954 * on whether this is an XCR0- or IA32_XSS-managed area. 955 */ 956 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 957 --array->nent; 958 continue; 959 } 960 961 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 962 entry->ecx &= ~BIT_ULL(2); 963 entry->edx = 0; 964 } 965 break; 966 } 967 case 0x12: 968 /* Intel SGX */ 969 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 970 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 971 break; 972 } 973 974 /* 975 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 976 * and max enclave sizes. The SGX sub-features and MISCSELECT 977 * are restricted by kernel and KVM capabilities (like most 978 * feature flags), while enclave size is unrestricted. 979 */ 980 cpuid_entry_override(entry, CPUID_12_EAX); 981 entry->ebx &= SGX_MISC_EXINFO; 982 983 entry = do_host_cpuid(array, function, 1); 984 if (!entry) 985 goto out; 986 987 /* 988 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 989 * feature flags. Advertise all supported flags, including 990 * privileged attributes that require explicit opt-in from 991 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 992 * expected to derive it from supported XCR0. 993 */ 994 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | 995 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY | 996 SGX_ATTR_KSS; 997 entry->ebx &= 0; 998 break; 999 /* Intel PT */ 1000 case 0x14: 1001 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1002 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1003 break; 1004 } 1005 1006 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1007 if (!do_host_cpuid(array, function, i)) 1008 goto out; 1009 } 1010 break; 1011 /* Intel AMX TILE */ 1012 case 0x1d: 1013 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1014 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1015 break; 1016 } 1017 1018 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1019 if (!do_host_cpuid(array, function, i)) 1020 goto out; 1021 } 1022 break; 1023 case 0x1e: /* TMUL information */ 1024 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1025 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1026 break; 1027 } 1028 break; 1029 case KVM_CPUID_SIGNATURE: { 1030 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1031 entry->eax = KVM_CPUID_FEATURES; 1032 entry->ebx = sigptr[0]; 1033 entry->ecx = sigptr[1]; 1034 entry->edx = sigptr[2]; 1035 break; 1036 } 1037 case KVM_CPUID_FEATURES: 1038 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1039 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1040 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1041 (1 << KVM_FEATURE_ASYNC_PF) | 1042 (1 << KVM_FEATURE_PV_EOI) | 1043 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1044 (1 << KVM_FEATURE_PV_UNHALT) | 1045 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1046 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1047 (1 << KVM_FEATURE_PV_SEND_IPI) | 1048 (1 << KVM_FEATURE_POLL_CONTROL) | 1049 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1050 (1 << KVM_FEATURE_ASYNC_PF_INT); 1051 1052 if (sched_info_on()) 1053 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1054 1055 entry->ebx = 0; 1056 entry->ecx = 0; 1057 entry->edx = 0; 1058 break; 1059 case 0x80000000: 1060 entry->eax = min(entry->eax, 0x8000001f); 1061 break; 1062 case 0x80000001: 1063 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1064 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1065 break; 1066 case 0x80000006: 1067 /* L2 cache and TLB: pass through host info. */ 1068 break; 1069 case 0x80000007: /* Advanced power management */ 1070 /* invariant TSC is CPUID.80000007H:EDX[8] */ 1071 entry->edx &= (1 << 8); 1072 /* mask against host */ 1073 entry->edx &= boot_cpu_data.x86_power; 1074 entry->eax = entry->ebx = entry->ecx = 0; 1075 break; 1076 case 0x80000008: { 1077 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1078 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1079 unsigned phys_as = entry->eax & 0xff; 1080 1081 /* 1082 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1083 * the guest operates in the same PA space as the host, i.e. 1084 * reductions in MAXPHYADDR for memory encryption affect shadow 1085 * paging, too. 1086 * 1087 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1088 * provided, use the raw bare metal MAXPHYADDR as reductions to 1089 * the HPAs do not affect GPAs. 1090 */ 1091 if (!tdp_enabled) 1092 g_phys_as = boot_cpu_data.x86_phys_bits; 1093 else if (!g_phys_as) 1094 g_phys_as = phys_as; 1095 1096 entry->eax = g_phys_as | (virt_as << 8); 1097 entry->edx = 0; 1098 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1099 break; 1100 } 1101 case 0x8000000A: 1102 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1103 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1104 break; 1105 } 1106 entry->eax = 1; /* SVM revision 1 */ 1107 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1108 ASID emulation to nested SVM */ 1109 entry->ecx = 0; /* Reserved */ 1110 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1111 break; 1112 case 0x80000019: 1113 entry->ecx = entry->edx = 0; 1114 break; 1115 case 0x8000001a: 1116 case 0x8000001e: 1117 break; 1118 case 0x8000001F: 1119 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1120 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1121 } else { 1122 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1123 1124 /* 1125 * Enumerate '0' for "PA bits reduction", the adjusted 1126 * MAXPHYADDR is enumerated directly (see 0x80000008). 1127 */ 1128 entry->ebx &= ~GENMASK(11, 6); 1129 } 1130 break; 1131 /*Add support for Centaur's CPUID instruction*/ 1132 case 0xC0000000: 1133 /*Just support up to 0xC0000004 now*/ 1134 entry->eax = min(entry->eax, 0xC0000004); 1135 break; 1136 case 0xC0000001: 1137 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1138 break; 1139 case 3: /* Processor serial number */ 1140 case 5: /* MONITOR/MWAIT */ 1141 case 0xC0000002: 1142 case 0xC0000003: 1143 case 0xC0000004: 1144 default: 1145 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1146 break; 1147 } 1148 1149 r = 0; 1150 1151 out: 1152 put_cpu(); 1153 1154 return r; 1155 } 1156 1157 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1158 unsigned int type) 1159 { 1160 if (type == KVM_GET_EMULATED_CPUID) 1161 return __do_cpuid_func_emulated(array, func); 1162 1163 return __do_cpuid_func(array, func); 1164 } 1165 1166 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1167 1168 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1169 unsigned int type) 1170 { 1171 u32 limit; 1172 int r; 1173 1174 if (func == CENTAUR_CPUID_SIGNATURE && 1175 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1176 return 0; 1177 1178 r = do_cpuid_func(array, func, type); 1179 if (r) 1180 return r; 1181 1182 limit = array->entries[array->nent - 1].eax; 1183 for (func = func + 1; func <= limit; ++func) { 1184 r = do_cpuid_func(array, func, type); 1185 if (r) 1186 break; 1187 } 1188 1189 return r; 1190 } 1191 1192 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1193 __u32 num_entries, unsigned int ioctl_type) 1194 { 1195 int i; 1196 __u32 pad[3]; 1197 1198 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1199 return false; 1200 1201 /* 1202 * We want to make sure that ->padding is being passed clean from 1203 * userspace in case we want to use it for something in the future. 1204 * 1205 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1206 * have to give ourselves satisfied only with the emulated side. /me 1207 * sheds a tear. 1208 */ 1209 for (i = 0; i < num_entries; i++) { 1210 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1211 return true; 1212 1213 if (pad[0] || pad[1] || pad[2]) 1214 return true; 1215 } 1216 return false; 1217 } 1218 1219 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1220 struct kvm_cpuid_entry2 __user *entries, 1221 unsigned int type) 1222 { 1223 static const u32 funcs[] = { 1224 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1225 }; 1226 1227 struct kvm_cpuid_array array = { 1228 .nent = 0, 1229 }; 1230 int r, i; 1231 1232 if (cpuid->nent < 1) 1233 return -E2BIG; 1234 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1235 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1236 1237 if (sanity_check_entries(entries, cpuid->nent, type)) 1238 return -EINVAL; 1239 1240 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 1241 cpuid->nent)); 1242 if (!array.entries) 1243 return -ENOMEM; 1244 1245 array.maxnent = cpuid->nent; 1246 1247 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1248 r = get_cpuid_func(&array, funcs[i], type); 1249 if (r) 1250 goto out_free; 1251 } 1252 cpuid->nent = array.nent; 1253 1254 if (copy_to_user(entries, array.entries, 1255 array.nent * sizeof(struct kvm_cpuid_entry2))) 1256 r = -EFAULT; 1257 1258 out_free: 1259 vfree(array.entries); 1260 return r; 1261 } 1262 1263 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1264 u32 function, u32 index) 1265 { 1266 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1267 function, index); 1268 } 1269 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1270 1271 /* 1272 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1273 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1274 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1275 * range. Centaur/VIA follows Intel semantics. 1276 * 1277 * A leaf is considered out-of-range if its function is higher than the maximum 1278 * supported leaf of its associated class or if its associated class does not 1279 * exist. 1280 * 1281 * There are three primary classes to be considered, with their respective 1282 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1283 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1284 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1285 * 1286 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1287 * - Hypervisor: 0x40000000 - 0x4fffffff 1288 * - Extended: 0x80000000 - 0xbfffffff 1289 * - Centaur: 0xc0000000 - 0xcfffffff 1290 * 1291 * The Hypervisor class is further subdivided into sub-classes that each act as 1292 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1293 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1294 * CPUID sub-classes are: 1295 * 1296 * - HyperV: 0x40000000 - 0x400000ff 1297 * - KVM: 0x40000100 - 0x400001ff 1298 */ 1299 static struct kvm_cpuid_entry2 * 1300 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1301 { 1302 struct kvm_cpuid_entry2 *basic, *class; 1303 u32 function = *fn_ptr; 1304 1305 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1306 if (!basic) 1307 return NULL; 1308 1309 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1310 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1311 return NULL; 1312 1313 if (function >= 0x40000000 && function <= 0x4fffffff) 1314 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1315 else if (function >= 0xc0000000) 1316 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1317 else 1318 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1319 1320 if (class && function <= class->eax) 1321 return NULL; 1322 1323 /* 1324 * Leaf specific adjustments are also applied when redirecting to the 1325 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1326 * entry for CPUID.0xb.index (see below), then the output value for EDX 1327 * needs to be pulled from CPUID.0xb.1. 1328 */ 1329 *fn_ptr = basic->eax; 1330 1331 /* 1332 * The class does not exist or the requested function is out of range; 1333 * the effective CPUID entry is the max basic leaf. Note, the index of 1334 * the original requested leaf is observed! 1335 */ 1336 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1337 } 1338 1339 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1340 u32 *ecx, u32 *edx, bool exact_only) 1341 { 1342 u32 orig_function = *eax, function = *eax, index = *ecx; 1343 struct kvm_cpuid_entry2 *entry; 1344 bool exact, used_max_basic = false; 1345 1346 entry = kvm_find_cpuid_entry(vcpu, function, index); 1347 exact = !!entry; 1348 1349 if (!entry && !exact_only) { 1350 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1351 used_max_basic = !!entry; 1352 } 1353 1354 if (entry) { 1355 *eax = entry->eax; 1356 *ebx = entry->ebx; 1357 *ecx = entry->ecx; 1358 *edx = entry->edx; 1359 if (function == 7 && index == 0) { 1360 u64 data; 1361 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1362 (data & TSX_CTRL_CPUID_CLEAR)) 1363 *ebx &= ~(F(RTM) | F(HLE)); 1364 } 1365 } else { 1366 *eax = *ebx = *ecx = *edx = 0; 1367 /* 1368 * When leaf 0BH or 1FH is defined, CL is pass-through 1369 * and EDX is always the x2APIC ID, even for undefined 1370 * subleaves. Index 1 will exist iff the leaf is 1371 * implemented, so we pass through CL iff leaf 1 1372 * exists. EDX can be copied from any existing index. 1373 */ 1374 if (function == 0xb || function == 0x1f) { 1375 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1376 if (entry) { 1377 *ecx = index & 0xff; 1378 *edx = entry->edx; 1379 } 1380 } 1381 } 1382 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1383 used_max_basic); 1384 return exact; 1385 } 1386 EXPORT_SYMBOL_GPL(kvm_cpuid); 1387 1388 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1389 { 1390 u32 eax, ebx, ecx, edx; 1391 1392 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1393 return 1; 1394 1395 eax = kvm_rax_read(vcpu); 1396 ecx = kvm_rcx_read(vcpu); 1397 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1398 kvm_rax_write(vcpu, eax); 1399 kvm_rbx_write(vcpu, ebx); 1400 kvm_rcx_write(vcpu, ecx); 1401 kvm_rdx_write(vcpu, edx); 1402 return kvm_skip_emulated_instruction(vcpu); 1403 } 1404 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1405