1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include <asm/sgx.h> 22 #include "cpuid.h" 23 #include "lapic.h" 24 #include "mmu.h" 25 #include "trace.h" 26 #include "pmu.h" 27 28 /* 29 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 30 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 31 */ 32 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 33 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 34 35 u32 xstate_required_size(u64 xstate_bv, bool compacted) 36 { 37 int feature_bit = 0; 38 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 39 40 xstate_bv &= XFEATURE_MASK_EXTEND; 41 while (xstate_bv) { 42 if (xstate_bv & 0x1) { 43 u32 eax, ebx, ecx, edx, offset; 44 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 45 /* ECX[1]: 64B alignment in compacted form */ 46 if (compacted) 47 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 48 else 49 offset = ebx; 50 ret = max(ret, offset + eax); 51 } 52 53 xstate_bv >>= 1; 54 feature_bit++; 55 } 56 57 return ret; 58 } 59 60 /* 61 * This one is tied to SSB in the user API, and not 62 * visible in /proc/cpuinfo. 63 */ 64 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ 65 66 #define F feature_bit 67 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0) 68 69 70 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 71 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 72 { 73 struct kvm_cpuid_entry2 *e; 74 int i; 75 76 for (i = 0; i < nent; i++) { 77 e = &entries[i]; 78 79 if (e->function == function && 80 (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)) 81 return e; 82 } 83 84 return NULL; 85 } 86 87 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 88 struct kvm_cpuid_entry2 *entries, 89 int nent) 90 { 91 struct kvm_cpuid_entry2 *best; 92 u64 xfeatures; 93 94 /* 95 * The existing code assumes virtual address is 48-bit or 57-bit in the 96 * canonical address checks; exit if it is ever changed. 97 */ 98 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 99 if (best) { 100 int vaddr_bits = (best->eax & 0xff00) >> 8; 101 102 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 103 return -EINVAL; 104 } 105 106 /* 107 * Exposing dynamic xfeatures to the guest requires additional 108 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 109 */ 110 best = cpuid_entry2_find(entries, nent, 0xd, 0); 111 if (!best) 112 return 0; 113 114 xfeatures = best->eax | ((u64)best->edx << 32); 115 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 116 if (!xfeatures) 117 return 0; 118 119 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 120 } 121 122 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 123 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 124 int nent) 125 { 126 struct kvm_cpuid_entry2 *orig; 127 int i; 128 129 if (nent != vcpu->arch.cpuid_nent) 130 return -EINVAL; 131 132 for (i = 0; i < nent; i++) { 133 orig = &vcpu->arch.cpuid_entries[i]; 134 if (e2[i].function != orig->function || 135 e2[i].index != orig->index || 136 e2[i].flags != orig->flags || 137 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 138 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 139 return -EINVAL; 140 } 141 142 return 0; 143 } 144 145 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu) 146 { 147 u32 function; 148 struct kvm_cpuid_entry2 *entry; 149 150 vcpu->arch.kvm_cpuid_base = 0; 151 152 for_each_possible_hypervisor_cpuid_base(function) { 153 entry = kvm_find_cpuid_entry(vcpu, function, 0); 154 155 if (entry) { 156 u32 signature[3]; 157 158 signature[0] = entry->ebx; 159 signature[1] = entry->ecx; 160 signature[2] = entry->edx; 161 162 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE)); 163 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) { 164 vcpu->arch.kvm_cpuid_base = function; 165 break; 166 } 167 } 168 } 169 } 170 171 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 172 struct kvm_cpuid_entry2 *entries, int nent) 173 { 174 u32 base = vcpu->arch.kvm_cpuid_base; 175 176 if (!base) 177 return NULL; 178 179 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 0); 180 } 181 182 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 183 { 184 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 185 vcpu->arch.cpuid_nent); 186 } 187 188 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 189 { 190 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 191 192 /* 193 * save the feature bitmap to avoid cpuid lookup for every PV 194 * operation 195 */ 196 if (best) 197 vcpu->arch.pv_cpuid.features = best->eax; 198 } 199 200 /* 201 * Calculate guest's supported XCR0 taking into account guest CPUID data and 202 * supported_xcr0 (comprised of host configuration and KVM_SUPPORTED_XCR0). 203 */ 204 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 205 { 206 struct kvm_cpuid_entry2 *best; 207 208 best = cpuid_entry2_find(entries, nent, 0xd, 0); 209 if (!best) 210 return 0; 211 212 return (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 213 } 214 215 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 216 int nent) 217 { 218 struct kvm_cpuid_entry2 *best; 219 u64 guest_supported_xcr0 = cpuid_get_supported_xcr0(entries, nent); 220 221 best = cpuid_entry2_find(entries, nent, 1, 0); 222 if (best) { 223 /* Update OSXSAVE bit */ 224 if (boot_cpu_has(X86_FEATURE_XSAVE)) 225 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 226 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 227 228 cpuid_entry_change(best, X86_FEATURE_APIC, 229 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 230 } 231 232 best = cpuid_entry2_find(entries, nent, 7, 0); 233 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 234 cpuid_entry_change(best, X86_FEATURE_OSPKE, 235 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 236 237 best = cpuid_entry2_find(entries, nent, 0xD, 0); 238 if (best) 239 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 240 241 best = cpuid_entry2_find(entries, nent, 0xD, 1); 242 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 243 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 244 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 245 246 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 247 if (kvm_hlt_in_guest(vcpu->kvm) && best && 248 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 249 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 250 251 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 252 best = cpuid_entry2_find(entries, nent, 0x1, 0); 253 if (best) 254 cpuid_entry_change(best, X86_FEATURE_MWAIT, 255 vcpu->arch.ia32_misc_enable_msr & 256 MSR_IA32_MISC_ENABLE_MWAIT); 257 } 258 259 /* 260 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 261 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 262 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 263 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 264 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 265 * '1' even on CPUs that don't support XSAVE. 266 */ 267 best = cpuid_entry2_find(entries, nent, 0x12, 0x1); 268 if (best) { 269 best->ecx &= guest_supported_xcr0 & 0xffffffff; 270 best->edx &= guest_supported_xcr0 >> 32; 271 best->ecx |= XFEATURE_MASK_FPSSE; 272 } 273 } 274 275 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 276 { 277 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 278 } 279 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 280 281 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 282 { 283 struct kvm_lapic *apic = vcpu->arch.apic; 284 struct kvm_cpuid_entry2 *best; 285 286 best = kvm_find_cpuid_entry(vcpu, 1, 0); 287 if (best && apic) { 288 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 289 apic->lapic_timer.timer_mode_mask = 3 << 17; 290 else 291 apic->lapic_timer.timer_mode_mask = 1 << 17; 292 293 kvm_apic_set_version(vcpu); 294 } 295 296 vcpu->arch.guest_supported_xcr0 = 297 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 298 299 kvm_update_pv_runtime(vcpu); 300 301 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 302 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 303 304 kvm_pmu_refresh(vcpu); 305 vcpu->arch.cr4_guest_rsvd_bits = 306 __cr4_reserved_bits(guest_cpuid_has, vcpu); 307 308 kvm_hv_set_cpuid(vcpu); 309 310 /* Invoke the vendor callback only after the above state is updated. */ 311 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 312 313 /* 314 * Except for the MMU, which needs to do its thing any vendor specific 315 * adjustments to the reserved GPA bits. 316 */ 317 kvm_mmu_after_set_cpuid(vcpu); 318 } 319 320 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 321 { 322 struct kvm_cpuid_entry2 *best; 323 324 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 325 if (!best || best->eax < 0x80000008) 326 goto not_found; 327 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 328 if (best) 329 return best->eax & 0xff; 330 not_found: 331 return 36; 332 } 333 334 /* 335 * This "raw" version returns the reserved GPA bits without any adjustments for 336 * encryption technologies that usurp bits. The raw mask should be used if and 337 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 338 */ 339 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 340 { 341 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 342 } 343 344 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 345 int nent) 346 { 347 int r; 348 349 __kvm_update_cpuid_runtime(vcpu, e2, nent); 350 351 /* 352 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 353 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 354 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 355 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 356 * the core vCPU model on the fly. It would've been better to forbid any 357 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 358 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 359 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 360 * whether the supplied CPUID data is equal to what's already set. 361 */ 362 if (vcpu->arch.last_vmentry_cpu != -1) { 363 r = kvm_cpuid_check_equal(vcpu, e2, nent); 364 if (r) 365 return r; 366 367 kvfree(e2); 368 return 0; 369 } 370 371 r = kvm_check_cpuid(vcpu, e2, nent); 372 if (r) 373 return r; 374 375 kvfree(vcpu->arch.cpuid_entries); 376 vcpu->arch.cpuid_entries = e2; 377 vcpu->arch.cpuid_nent = nent; 378 379 kvm_update_kvm_cpuid_base(vcpu); 380 kvm_vcpu_after_set_cpuid(vcpu); 381 382 return 0; 383 } 384 385 /* when an old userspace process fills a new kernel module */ 386 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 387 struct kvm_cpuid *cpuid, 388 struct kvm_cpuid_entry __user *entries) 389 { 390 int r, i; 391 struct kvm_cpuid_entry *e = NULL; 392 struct kvm_cpuid_entry2 *e2 = NULL; 393 394 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 395 return -E2BIG; 396 397 if (cpuid->nent) { 398 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 399 if (IS_ERR(e)) 400 return PTR_ERR(e); 401 402 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 403 if (!e2) { 404 r = -ENOMEM; 405 goto out_free_cpuid; 406 } 407 } 408 for (i = 0; i < cpuid->nent; i++) { 409 e2[i].function = e[i].function; 410 e2[i].eax = e[i].eax; 411 e2[i].ebx = e[i].ebx; 412 e2[i].ecx = e[i].ecx; 413 e2[i].edx = e[i].edx; 414 e2[i].index = 0; 415 e2[i].flags = 0; 416 e2[i].padding[0] = 0; 417 e2[i].padding[1] = 0; 418 e2[i].padding[2] = 0; 419 } 420 421 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 422 if (r) 423 kvfree(e2); 424 425 out_free_cpuid: 426 kvfree(e); 427 428 return r; 429 } 430 431 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 432 struct kvm_cpuid2 *cpuid, 433 struct kvm_cpuid_entry2 __user *entries) 434 { 435 struct kvm_cpuid_entry2 *e2 = NULL; 436 int r; 437 438 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 439 return -E2BIG; 440 441 if (cpuid->nent) { 442 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 443 if (IS_ERR(e2)) 444 return PTR_ERR(e2); 445 } 446 447 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 448 if (r) 449 kvfree(e2); 450 451 return r; 452 } 453 454 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 455 struct kvm_cpuid2 *cpuid, 456 struct kvm_cpuid_entry2 __user *entries) 457 { 458 int r; 459 460 r = -E2BIG; 461 if (cpuid->nent < vcpu->arch.cpuid_nent) 462 goto out; 463 r = -EFAULT; 464 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 465 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 466 goto out; 467 return 0; 468 469 out: 470 cpuid->nent = vcpu->arch.cpuid_nent; 471 return r; 472 } 473 474 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 475 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 476 { 477 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 478 struct kvm_cpuid_entry2 entry; 479 480 reverse_cpuid_check(leaf); 481 482 cpuid_count(cpuid.function, cpuid.index, 483 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 484 485 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 486 } 487 488 static __always_inline 489 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask) 490 { 491 /* Use kvm_cpu_cap_mask for non-scattered leafs. */ 492 BUILD_BUG_ON(leaf < NCAPINTS); 493 494 kvm_cpu_caps[leaf] = mask; 495 496 __kvm_cpu_cap_mask(leaf); 497 } 498 499 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 500 { 501 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */ 502 BUILD_BUG_ON(leaf >= NCAPINTS); 503 504 kvm_cpu_caps[leaf] &= mask; 505 506 __kvm_cpu_cap_mask(leaf); 507 } 508 509 void kvm_set_cpu_caps(void) 510 { 511 #ifdef CONFIG_X86_64 512 unsigned int f_gbpages = F(GBPAGES); 513 unsigned int f_lm = F(LM); 514 unsigned int f_xfd = F(XFD); 515 #else 516 unsigned int f_gbpages = 0; 517 unsigned int f_lm = 0; 518 unsigned int f_xfd = 0; 519 #endif 520 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 521 522 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 523 sizeof(boot_cpu_data.x86_capability)); 524 525 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 526 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 527 528 kvm_cpu_cap_mask(CPUID_1_ECX, 529 /* 530 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 531 * advertised to guests via CPUID! 532 */ 533 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 534 0 /* DS-CPL, VMX, SMX, EST */ | 535 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 536 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 537 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 538 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 539 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 540 F(F16C) | F(RDRAND) 541 ); 542 /* KVM emulates x2apic in software irrespective of host support. */ 543 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 544 545 kvm_cpu_cap_mask(CPUID_1_EDX, 546 F(FPU) | F(VME) | F(DE) | F(PSE) | 547 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 548 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 549 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 550 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 551 0 /* Reserved, DS, ACPI */ | F(MMX) | 552 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 553 0 /* HTT, TM, Reserved, PBE */ 554 ); 555 556 kvm_cpu_cap_mask(CPUID_7_0_EBX, 557 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 558 F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 559 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 560 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 561 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 562 ); 563 564 kvm_cpu_cap_mask(CPUID_7_ECX, 565 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 566 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 567 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 568 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 569 F(SGX_LC) | F(BUS_LOCK_DETECT) 570 ); 571 /* Set LA57 based on hardware capability. */ 572 if (cpuid_ecx(7) & F(LA57)) 573 kvm_cpu_cap_set(X86_FEATURE_LA57); 574 575 /* 576 * PKU not yet implemented for shadow paging and requires OSPKE 577 * to be set on the host. Clear it if that is not the case 578 */ 579 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 580 kvm_cpu_cap_clear(X86_FEATURE_PKU); 581 582 kvm_cpu_cap_mask(CPUID_7_EDX, 583 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 584 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 585 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 586 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 587 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) 588 ); 589 590 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 591 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 592 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 593 594 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 595 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 596 if (boot_cpu_has(X86_FEATURE_STIBP)) 597 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 598 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 599 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 600 601 kvm_cpu_cap_mask(CPUID_7_1_EAX, 602 F(AVX_VNNI) | F(AVX512_BF16) 603 ); 604 605 kvm_cpu_cap_mask(CPUID_D_1_EAX, 606 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 607 ); 608 609 kvm_cpu_cap_init_scattered(CPUID_12_EAX, 610 SF(SGX1) | SF(SGX2) 611 ); 612 613 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 614 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 615 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 616 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 617 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 618 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 619 ); 620 621 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 622 F(FPU) | F(VME) | F(DE) | F(PSE) | 623 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 624 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 625 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 626 F(PAT) | F(PSE36) | 0 /* Reserved */ | 627 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 628 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 629 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 630 ); 631 632 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 633 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 634 635 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 636 F(CLZERO) | F(XSAVEERPTR) | 637 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 638 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 639 __feature_bit(KVM_X86_FEATURE_PSFD) 640 ); 641 642 /* 643 * AMD has separate bits for each SPEC_CTRL bit. 644 * arch/x86/kernel/cpu/bugs.c is kind enough to 645 * record that in cpufeatures so use them. 646 */ 647 if (boot_cpu_has(X86_FEATURE_IBPB)) 648 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 649 if (boot_cpu_has(X86_FEATURE_IBRS)) 650 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 651 if (boot_cpu_has(X86_FEATURE_STIBP)) 652 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 653 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 654 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 655 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 656 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 657 /* 658 * The preference is to use SPEC CTRL MSR instead of the 659 * VIRT_SPEC MSR. 660 */ 661 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 662 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 663 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 664 665 /* 666 * Hide all SVM features by default, SVM will set the cap bits for 667 * features it emulates and/or exposes for L1. 668 */ 669 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 670 671 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 672 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 673 F(SME_COHERENT)); 674 675 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 676 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 677 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 678 F(PMM) | F(PMM_EN) 679 ); 680 681 /* 682 * Hide RDTSCP and RDPID if either feature is reported as supported but 683 * probing MSR_TSC_AUX failed. This is purely a sanity check and 684 * should never happen, but the guest will likely crash if RDTSCP or 685 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 686 * the past. For example, the sanity check may fire if this instance of 687 * KVM is running as L1 on top of an older, broken KVM. 688 */ 689 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 690 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 691 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 692 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 693 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 694 } 695 } 696 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 697 698 struct kvm_cpuid_array { 699 struct kvm_cpuid_entry2 *entries; 700 int maxnent; 701 int nent; 702 }; 703 704 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 705 u32 function, u32 index) 706 { 707 struct kvm_cpuid_entry2 *entry; 708 709 if (array->nent >= array->maxnent) 710 return NULL; 711 712 entry = &array->entries[array->nent++]; 713 714 entry->function = function; 715 entry->index = index; 716 entry->flags = 0; 717 718 cpuid_count(entry->function, entry->index, 719 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 720 721 switch (function) { 722 case 4: 723 case 7: 724 case 0xb: 725 case 0xd: 726 case 0xf: 727 case 0x10: 728 case 0x12: 729 case 0x14: 730 case 0x17: 731 case 0x18: 732 case 0x1d: 733 case 0x1e: 734 case 0x1f: 735 case 0x8000001d: 736 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 737 break; 738 } 739 740 return entry; 741 } 742 743 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 744 { 745 struct kvm_cpuid_entry2 *entry; 746 747 if (array->nent >= array->maxnent) 748 return -E2BIG; 749 750 entry = &array->entries[array->nent]; 751 entry->function = func; 752 entry->index = 0; 753 entry->flags = 0; 754 755 switch (func) { 756 case 0: 757 entry->eax = 7; 758 ++array->nent; 759 break; 760 case 1: 761 entry->ecx = F(MOVBE); 762 ++array->nent; 763 break; 764 case 7: 765 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 766 entry->eax = 0; 767 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 768 entry->ecx = F(RDPID); 769 ++array->nent; 770 break; 771 default: 772 break; 773 } 774 775 return 0; 776 } 777 778 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 779 { 780 struct kvm_cpuid_entry2 *entry; 781 int r, i, max_idx; 782 783 /* all calls to cpuid_count() should be made on the same cpu */ 784 get_cpu(); 785 786 r = -E2BIG; 787 788 entry = do_host_cpuid(array, function, 0); 789 if (!entry) 790 goto out; 791 792 switch (function) { 793 case 0: 794 /* Limited to the highest leaf implemented in KVM. */ 795 entry->eax = min(entry->eax, 0x1fU); 796 break; 797 case 1: 798 cpuid_entry_override(entry, CPUID_1_EDX); 799 cpuid_entry_override(entry, CPUID_1_ECX); 800 break; 801 case 2: 802 /* 803 * On ancient CPUs, function 2 entries are STATEFUL. That is, 804 * CPUID(function=2, index=0) may return different results each 805 * time, with the least-significant byte in EAX enumerating the 806 * number of times software should do CPUID(2, 0). 807 * 808 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 809 * idiotic. Intel's SDM states that EAX & 0xff "will always 810 * return 01H. Software should ignore this value and not 811 * interpret it as an informational descriptor", while AMD's 812 * APM states that CPUID(2) is reserved. 813 * 814 * WARN if a frankenstein CPU that supports virtualization and 815 * a stateful CPUID.0x2 is encountered. 816 */ 817 WARN_ON_ONCE((entry->eax & 0xff) > 1); 818 break; 819 /* functions 4 and 0x8000001d have additional index. */ 820 case 4: 821 case 0x8000001d: 822 /* 823 * Read entries until the cache type in the previous entry is 824 * zero, i.e. indicates an invalid entry. 825 */ 826 for (i = 1; entry->eax & 0x1f; ++i) { 827 entry = do_host_cpuid(array, function, i); 828 if (!entry) 829 goto out; 830 } 831 break; 832 case 6: /* Thermal management */ 833 entry->eax = 0x4; /* allow ARAT */ 834 entry->ebx = 0; 835 entry->ecx = 0; 836 entry->edx = 0; 837 break; 838 /* function 7 has additional index. */ 839 case 7: 840 entry->eax = min(entry->eax, 1u); 841 cpuid_entry_override(entry, CPUID_7_0_EBX); 842 cpuid_entry_override(entry, CPUID_7_ECX); 843 cpuid_entry_override(entry, CPUID_7_EDX); 844 845 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 846 if (entry->eax == 1) { 847 entry = do_host_cpuid(array, function, 1); 848 if (!entry) 849 goto out; 850 851 cpuid_entry_override(entry, CPUID_7_1_EAX); 852 entry->ebx = 0; 853 entry->ecx = 0; 854 entry->edx = 0; 855 } 856 break; 857 case 9: 858 break; 859 case 0xa: { /* Architectural Performance Monitoring */ 860 struct x86_pmu_capability cap; 861 union cpuid10_eax eax; 862 union cpuid10_edx edx; 863 864 perf_get_x86_pmu_capability(&cap); 865 866 /* 867 * The guest architecture pmu is only supported if the architecture 868 * pmu exists on the host and the module parameters allow it. 869 */ 870 if (!cap.version || !enable_pmu) 871 memset(&cap, 0, sizeof(cap)); 872 873 eax.split.version_id = min(cap.version, 2); 874 eax.split.num_counters = cap.num_counters_gp; 875 eax.split.bit_width = cap.bit_width_gp; 876 eax.split.mask_length = cap.events_mask_len; 877 878 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 879 edx.split.bit_width_fixed = cap.bit_width_fixed; 880 if (cap.version) 881 edx.split.anythread_deprecated = 1; 882 edx.split.reserved1 = 0; 883 edx.split.reserved2 = 0; 884 885 entry->eax = eax.full; 886 entry->ebx = cap.events_mask; 887 entry->ecx = 0; 888 entry->edx = edx.full; 889 break; 890 } 891 /* 892 * Per Intel's SDM, the 0x1f is a superset of 0xb, 893 * thus they can be handled by common code. 894 */ 895 case 0x1f: 896 case 0xb: 897 /* 898 * Populate entries until the level type (ECX[15:8]) of the 899 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 900 * the starting entry, filled by the primary do_host_cpuid(). 901 */ 902 for (i = 1; entry->ecx & 0xff00; ++i) { 903 entry = do_host_cpuid(array, function, i); 904 if (!entry) 905 goto out; 906 } 907 break; 908 case 0xd: { 909 u64 permitted_xcr0 = supported_xcr0 & xstate_get_guest_group_perm(); 910 u64 permitted_xss = supported_xss; 911 912 entry->eax &= permitted_xcr0; 913 entry->ebx = xstate_required_size(permitted_xcr0, false); 914 entry->ecx = entry->ebx; 915 entry->edx &= permitted_xcr0 >> 32; 916 if (!permitted_xcr0) 917 break; 918 919 entry = do_host_cpuid(array, function, 1); 920 if (!entry) 921 goto out; 922 923 cpuid_entry_override(entry, CPUID_D_1_EAX); 924 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 925 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 926 true); 927 else { 928 WARN_ON_ONCE(permitted_xss != 0); 929 entry->ebx = 0; 930 } 931 entry->ecx &= permitted_xss; 932 entry->edx &= permitted_xss >> 32; 933 934 for (i = 2; i < 64; ++i) { 935 bool s_state; 936 if (permitted_xcr0 & BIT_ULL(i)) 937 s_state = false; 938 else if (permitted_xss & BIT_ULL(i)) 939 s_state = true; 940 else 941 continue; 942 943 entry = do_host_cpuid(array, function, i); 944 if (!entry) 945 goto out; 946 947 /* 948 * The supported check above should have filtered out 949 * invalid sub-leafs. Only valid sub-leafs should 950 * reach this point, and they should have a non-zero 951 * save state size. Furthermore, check whether the 952 * processor agrees with permitted_xcr0/permitted_xss 953 * on whether this is an XCR0- or IA32_XSS-managed area. 954 */ 955 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 956 --array->nent; 957 continue; 958 } 959 960 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 961 entry->ecx &= ~BIT_ULL(2); 962 entry->edx = 0; 963 } 964 break; 965 } 966 case 0x12: 967 /* Intel SGX */ 968 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 969 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 970 break; 971 } 972 973 /* 974 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 975 * and max enclave sizes. The SGX sub-features and MISCSELECT 976 * are restricted by kernel and KVM capabilities (like most 977 * feature flags), while enclave size is unrestricted. 978 */ 979 cpuid_entry_override(entry, CPUID_12_EAX); 980 entry->ebx &= SGX_MISC_EXINFO; 981 982 entry = do_host_cpuid(array, function, 1); 983 if (!entry) 984 goto out; 985 986 /* 987 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 988 * feature flags. Advertise all supported flags, including 989 * privileged attributes that require explicit opt-in from 990 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 991 * expected to derive it from supported XCR0. 992 */ 993 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | 994 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY | 995 SGX_ATTR_KSS; 996 entry->ebx &= 0; 997 break; 998 /* Intel PT */ 999 case 0x14: 1000 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1001 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1002 break; 1003 } 1004 1005 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1006 if (!do_host_cpuid(array, function, i)) 1007 goto out; 1008 } 1009 break; 1010 /* Intel AMX TILE */ 1011 case 0x1d: 1012 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1013 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1014 break; 1015 } 1016 1017 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1018 if (!do_host_cpuid(array, function, i)) 1019 goto out; 1020 } 1021 break; 1022 case 0x1e: /* TMUL information */ 1023 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1024 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1025 break; 1026 } 1027 break; 1028 case KVM_CPUID_SIGNATURE: { 1029 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1030 entry->eax = KVM_CPUID_FEATURES; 1031 entry->ebx = sigptr[0]; 1032 entry->ecx = sigptr[1]; 1033 entry->edx = sigptr[2]; 1034 break; 1035 } 1036 case KVM_CPUID_FEATURES: 1037 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1038 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1039 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1040 (1 << KVM_FEATURE_ASYNC_PF) | 1041 (1 << KVM_FEATURE_PV_EOI) | 1042 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1043 (1 << KVM_FEATURE_PV_UNHALT) | 1044 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1045 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1046 (1 << KVM_FEATURE_PV_SEND_IPI) | 1047 (1 << KVM_FEATURE_POLL_CONTROL) | 1048 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1049 (1 << KVM_FEATURE_ASYNC_PF_INT); 1050 1051 if (sched_info_on()) 1052 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1053 1054 entry->ebx = 0; 1055 entry->ecx = 0; 1056 entry->edx = 0; 1057 break; 1058 case 0x80000000: 1059 entry->eax = min(entry->eax, 0x8000001f); 1060 break; 1061 case 0x80000001: 1062 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1063 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1064 break; 1065 case 0x80000006: 1066 /* L2 cache and TLB: pass through host info. */ 1067 break; 1068 case 0x80000007: /* Advanced power management */ 1069 /* invariant TSC is CPUID.80000007H:EDX[8] */ 1070 entry->edx &= (1 << 8); 1071 /* mask against host */ 1072 entry->edx &= boot_cpu_data.x86_power; 1073 entry->eax = entry->ebx = entry->ecx = 0; 1074 break; 1075 case 0x80000008: { 1076 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1077 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1078 unsigned phys_as = entry->eax & 0xff; 1079 1080 /* 1081 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1082 * the guest operates in the same PA space as the host, i.e. 1083 * reductions in MAXPHYADDR for memory encryption affect shadow 1084 * paging, too. 1085 * 1086 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1087 * provided, use the raw bare metal MAXPHYADDR as reductions to 1088 * the HPAs do not affect GPAs. 1089 */ 1090 if (!tdp_enabled) 1091 g_phys_as = boot_cpu_data.x86_phys_bits; 1092 else if (!g_phys_as) 1093 g_phys_as = phys_as; 1094 1095 entry->eax = g_phys_as | (virt_as << 8); 1096 entry->edx = 0; 1097 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1098 break; 1099 } 1100 case 0x8000000A: 1101 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1102 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1103 break; 1104 } 1105 entry->eax = 1; /* SVM revision 1 */ 1106 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1107 ASID emulation to nested SVM */ 1108 entry->ecx = 0; /* Reserved */ 1109 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1110 break; 1111 case 0x80000019: 1112 entry->ecx = entry->edx = 0; 1113 break; 1114 case 0x8000001a: 1115 case 0x8000001e: 1116 break; 1117 case 0x8000001F: 1118 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1119 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1120 } else { 1121 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1122 1123 /* 1124 * Enumerate '0' for "PA bits reduction", the adjusted 1125 * MAXPHYADDR is enumerated directly (see 0x80000008). 1126 */ 1127 entry->ebx &= ~GENMASK(11, 6); 1128 } 1129 break; 1130 /*Add support for Centaur's CPUID instruction*/ 1131 case 0xC0000000: 1132 /*Just support up to 0xC0000004 now*/ 1133 entry->eax = min(entry->eax, 0xC0000004); 1134 break; 1135 case 0xC0000001: 1136 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1137 break; 1138 case 3: /* Processor serial number */ 1139 case 5: /* MONITOR/MWAIT */ 1140 case 0xC0000002: 1141 case 0xC0000003: 1142 case 0xC0000004: 1143 default: 1144 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1145 break; 1146 } 1147 1148 r = 0; 1149 1150 out: 1151 put_cpu(); 1152 1153 return r; 1154 } 1155 1156 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1157 unsigned int type) 1158 { 1159 if (type == KVM_GET_EMULATED_CPUID) 1160 return __do_cpuid_func_emulated(array, func); 1161 1162 return __do_cpuid_func(array, func); 1163 } 1164 1165 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1166 1167 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1168 unsigned int type) 1169 { 1170 u32 limit; 1171 int r; 1172 1173 if (func == CENTAUR_CPUID_SIGNATURE && 1174 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1175 return 0; 1176 1177 r = do_cpuid_func(array, func, type); 1178 if (r) 1179 return r; 1180 1181 limit = array->entries[array->nent - 1].eax; 1182 for (func = func + 1; func <= limit; ++func) { 1183 r = do_cpuid_func(array, func, type); 1184 if (r) 1185 break; 1186 } 1187 1188 return r; 1189 } 1190 1191 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1192 __u32 num_entries, unsigned int ioctl_type) 1193 { 1194 int i; 1195 __u32 pad[3]; 1196 1197 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1198 return false; 1199 1200 /* 1201 * We want to make sure that ->padding is being passed clean from 1202 * userspace in case we want to use it for something in the future. 1203 * 1204 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1205 * have to give ourselves satisfied only with the emulated side. /me 1206 * sheds a tear. 1207 */ 1208 for (i = 0; i < num_entries; i++) { 1209 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1210 return true; 1211 1212 if (pad[0] || pad[1] || pad[2]) 1213 return true; 1214 } 1215 return false; 1216 } 1217 1218 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1219 struct kvm_cpuid_entry2 __user *entries, 1220 unsigned int type) 1221 { 1222 static const u32 funcs[] = { 1223 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1224 }; 1225 1226 struct kvm_cpuid_array array = { 1227 .nent = 0, 1228 }; 1229 int r, i; 1230 1231 if (cpuid->nent < 1) 1232 return -E2BIG; 1233 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1234 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1235 1236 if (sanity_check_entries(entries, cpuid->nent, type)) 1237 return -EINVAL; 1238 1239 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 1240 cpuid->nent)); 1241 if (!array.entries) 1242 return -ENOMEM; 1243 1244 array.maxnent = cpuid->nent; 1245 1246 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1247 r = get_cpuid_func(&array, funcs[i], type); 1248 if (r) 1249 goto out_free; 1250 } 1251 cpuid->nent = array.nent; 1252 1253 if (copy_to_user(entries, array.entries, 1254 array.nent * sizeof(struct kvm_cpuid_entry2))) 1255 r = -EFAULT; 1256 1257 out_free: 1258 vfree(array.entries); 1259 return r; 1260 } 1261 1262 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1263 u32 function, u32 index) 1264 { 1265 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1266 function, index); 1267 } 1268 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1269 1270 /* 1271 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1272 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1273 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1274 * range. Centaur/VIA follows Intel semantics. 1275 * 1276 * A leaf is considered out-of-range if its function is higher than the maximum 1277 * supported leaf of its associated class or if its associated class does not 1278 * exist. 1279 * 1280 * There are three primary classes to be considered, with their respective 1281 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1282 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1283 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1284 * 1285 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1286 * - Hypervisor: 0x40000000 - 0x4fffffff 1287 * - Extended: 0x80000000 - 0xbfffffff 1288 * - Centaur: 0xc0000000 - 0xcfffffff 1289 * 1290 * The Hypervisor class is further subdivided into sub-classes that each act as 1291 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1292 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1293 * CPUID sub-classes are: 1294 * 1295 * - HyperV: 0x40000000 - 0x400000ff 1296 * - KVM: 0x40000100 - 0x400001ff 1297 */ 1298 static struct kvm_cpuid_entry2 * 1299 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1300 { 1301 struct kvm_cpuid_entry2 *basic, *class; 1302 u32 function = *fn_ptr; 1303 1304 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1305 if (!basic) 1306 return NULL; 1307 1308 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1309 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1310 return NULL; 1311 1312 if (function >= 0x40000000 && function <= 0x4fffffff) 1313 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1314 else if (function >= 0xc0000000) 1315 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1316 else 1317 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1318 1319 if (class && function <= class->eax) 1320 return NULL; 1321 1322 /* 1323 * Leaf specific adjustments are also applied when redirecting to the 1324 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1325 * entry for CPUID.0xb.index (see below), then the output value for EDX 1326 * needs to be pulled from CPUID.0xb.1. 1327 */ 1328 *fn_ptr = basic->eax; 1329 1330 /* 1331 * The class does not exist or the requested function is out of range; 1332 * the effective CPUID entry is the max basic leaf. Note, the index of 1333 * the original requested leaf is observed! 1334 */ 1335 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1336 } 1337 1338 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1339 u32 *ecx, u32 *edx, bool exact_only) 1340 { 1341 u32 orig_function = *eax, function = *eax, index = *ecx; 1342 struct kvm_cpuid_entry2 *entry; 1343 bool exact, used_max_basic = false; 1344 1345 entry = kvm_find_cpuid_entry(vcpu, function, index); 1346 exact = !!entry; 1347 1348 if (!entry && !exact_only) { 1349 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1350 used_max_basic = !!entry; 1351 } 1352 1353 if (entry) { 1354 *eax = entry->eax; 1355 *ebx = entry->ebx; 1356 *ecx = entry->ecx; 1357 *edx = entry->edx; 1358 if (function == 7 && index == 0) { 1359 u64 data; 1360 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1361 (data & TSX_CTRL_CPUID_CLEAR)) 1362 *ebx &= ~(F(RTM) | F(HLE)); 1363 } 1364 } else { 1365 *eax = *ebx = *ecx = *edx = 0; 1366 /* 1367 * When leaf 0BH or 1FH is defined, CL is pass-through 1368 * and EDX is always the x2APIC ID, even for undefined 1369 * subleaves. Index 1 will exist iff the leaf is 1370 * implemented, so we pass through CL iff leaf 1 1371 * exists. EDX can be copied from any existing index. 1372 */ 1373 if (function == 0xb || function == 0x1f) { 1374 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1375 if (entry) { 1376 *ecx = index & 0xff; 1377 *edx = entry->edx; 1378 } 1379 } 1380 } 1381 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1382 used_max_basic); 1383 return exact; 1384 } 1385 EXPORT_SYMBOL_GPL(kvm_cpuid); 1386 1387 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1388 { 1389 u32 eax, ebx, ecx, edx; 1390 1391 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1392 return 1; 1393 1394 eax = kvm_rax_read(vcpu); 1395 ecx = kvm_rcx_read(vcpu); 1396 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1397 kvm_rax_write(vcpu, eax); 1398 kvm_rbx_write(vcpu, ebx); 1399 kvm_rcx_write(vcpu, ecx); 1400 kvm_rdx_write(vcpu, edx); 1401 return kvm_skip_emulated_instruction(vcpu); 1402 } 1403 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1404