1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 12 13 #include <linux/kvm_host.h> 14 #include <linux/export.h> 15 #include <linux/vmalloc.h> 16 #include <linux/uaccess.h> 17 #include <linux/sched/stat.h> 18 19 #include <asm/processor.h> 20 #include <asm/user.h> 21 #include <asm/fpu/xstate.h> 22 #include <asm/sgx.h> 23 #include <asm/cpuid.h> 24 #include "cpuid.h" 25 #include "lapic.h" 26 #include "mmu.h" 27 #include "trace.h" 28 #include "pmu.h" 29 #include "xen.h" 30 31 /* 32 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 33 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 34 */ 35 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 36 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 37 38 u32 xstate_required_size(u64 xstate_bv, bool compacted) 39 { 40 int feature_bit = 0; 41 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 42 43 xstate_bv &= XFEATURE_MASK_EXTEND; 44 while (xstate_bv) { 45 if (xstate_bv & 0x1) { 46 u32 eax, ebx, ecx, edx, offset; 47 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 48 /* ECX[1]: 64B alignment in compacted form */ 49 if (compacted) 50 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 51 else 52 offset = ebx; 53 ret = max(ret, offset + eax); 54 } 55 56 xstate_bv >>= 1; 57 feature_bit++; 58 } 59 60 return ret; 61 } 62 63 #define F feature_bit 64 65 /* Scattered Flag - For features that are scattered by cpufeatures.h. */ 66 #define SF(name) \ 67 ({ \ 68 BUILD_BUG_ON(X86_FEATURE_##name >= MAX_CPU_FEATURES); \ 69 (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0); \ 70 }) 71 72 /* 73 * Magic value used by KVM when querying userspace-provided CPUID entries and 74 * doesn't care about the CPIUD index because the index of the function in 75 * question is not significant. Note, this magic value must have at least one 76 * bit set in bits[63:32] and must be consumed as a u64 by cpuid_entry2_find() 77 * to avoid false positives when processing guest CPUID input. 78 */ 79 #define KVM_CPUID_INDEX_NOT_SIGNIFICANT -1ull 80 81 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 82 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u64 index) 83 { 84 struct kvm_cpuid_entry2 *e; 85 int i; 86 87 for (i = 0; i < nent; i++) { 88 e = &entries[i]; 89 90 if (e->function != function) 91 continue; 92 93 /* 94 * If the index isn't significant, use the first entry with a 95 * matching function. It's userspace's responsibilty to not 96 * provide "duplicate" entries in all cases. 97 */ 98 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) 99 return e; 100 101 102 /* 103 * Similarly, use the first matching entry if KVM is doing a 104 * lookup (as opposed to emulating CPUID) for a function that's 105 * architecturally defined as not having a significant index. 106 */ 107 if (index == KVM_CPUID_INDEX_NOT_SIGNIFICANT) { 108 /* 109 * Direct lookups from KVM should not diverge from what 110 * KVM defines internally (the architectural behavior). 111 */ 112 WARN_ON_ONCE(cpuid_function_is_indexed(function)); 113 return e; 114 } 115 } 116 117 return NULL; 118 } 119 120 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 121 struct kvm_cpuid_entry2 *entries, 122 int nent) 123 { 124 struct kvm_cpuid_entry2 *best; 125 u64 xfeatures; 126 127 /* 128 * The existing code assumes virtual address is 48-bit or 57-bit in the 129 * canonical address checks; exit if it is ever changed. 130 */ 131 best = cpuid_entry2_find(entries, nent, 0x80000008, 132 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 133 if (best) { 134 int vaddr_bits = (best->eax & 0xff00) >> 8; 135 136 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 137 return -EINVAL; 138 } 139 140 /* 141 * Exposing dynamic xfeatures to the guest requires additional 142 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 143 */ 144 best = cpuid_entry2_find(entries, nent, 0xd, 0); 145 if (!best) 146 return 0; 147 148 xfeatures = best->eax | ((u64)best->edx << 32); 149 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 150 if (!xfeatures) 151 return 0; 152 153 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 154 } 155 156 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 157 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 158 int nent) 159 { 160 struct kvm_cpuid_entry2 *orig; 161 int i; 162 163 if (nent != vcpu->arch.cpuid_nent) 164 return -EINVAL; 165 166 for (i = 0; i < nent; i++) { 167 orig = &vcpu->arch.cpuid_entries[i]; 168 if (e2[i].function != orig->function || 169 e2[i].index != orig->index || 170 e2[i].flags != orig->flags || 171 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 172 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 173 return -EINVAL; 174 } 175 176 return 0; 177 } 178 179 static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcpu, 180 const char *sig) 181 { 182 struct kvm_hypervisor_cpuid cpuid = {}; 183 struct kvm_cpuid_entry2 *entry; 184 u32 base; 185 186 for_each_possible_hypervisor_cpuid_base(base) { 187 entry = kvm_find_cpuid_entry(vcpu, base); 188 189 if (entry) { 190 u32 signature[3]; 191 192 signature[0] = entry->ebx; 193 signature[1] = entry->ecx; 194 signature[2] = entry->edx; 195 196 if (!memcmp(signature, sig, sizeof(signature))) { 197 cpuid.base = base; 198 cpuid.limit = entry->eax; 199 break; 200 } 201 } 202 } 203 204 return cpuid; 205 } 206 207 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 208 struct kvm_cpuid_entry2 *entries, int nent) 209 { 210 u32 base = vcpu->arch.kvm_cpuid.base; 211 212 if (!base) 213 return NULL; 214 215 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 216 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 217 } 218 219 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 220 { 221 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 222 vcpu->arch.cpuid_nent); 223 } 224 225 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 226 { 227 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 228 229 /* 230 * save the feature bitmap to avoid cpuid lookup for every PV 231 * operation 232 */ 233 if (best) 234 vcpu->arch.pv_cpuid.features = best->eax; 235 } 236 237 /* 238 * Calculate guest's supported XCR0 taking into account guest CPUID data and 239 * KVM's supported XCR0 (comprised of host's XCR0 and KVM_SUPPORTED_XCR0). 240 */ 241 static u64 cpuid_get_supported_xcr0(struct kvm_cpuid_entry2 *entries, int nent) 242 { 243 struct kvm_cpuid_entry2 *best; 244 245 best = cpuid_entry2_find(entries, nent, 0xd, 0); 246 if (!best) 247 return 0; 248 249 return (best->eax | ((u64)best->edx << 32)) & kvm_caps.supported_xcr0; 250 } 251 252 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 253 int nent) 254 { 255 struct kvm_cpuid_entry2 *best; 256 257 best = cpuid_entry2_find(entries, nent, 1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 258 if (best) { 259 /* Update OSXSAVE bit */ 260 if (boot_cpu_has(X86_FEATURE_XSAVE)) 261 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 262 kvm_is_cr4_bit_set(vcpu, X86_CR4_OSXSAVE)); 263 264 cpuid_entry_change(best, X86_FEATURE_APIC, 265 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 266 } 267 268 best = cpuid_entry2_find(entries, nent, 7, 0); 269 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 270 cpuid_entry_change(best, X86_FEATURE_OSPKE, 271 kvm_is_cr4_bit_set(vcpu, X86_CR4_PKE)); 272 273 best = cpuid_entry2_find(entries, nent, 0xD, 0); 274 if (best) 275 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 276 277 best = cpuid_entry2_find(entries, nent, 0xD, 1); 278 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 279 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 280 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 281 282 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 283 if (kvm_hlt_in_guest(vcpu->kvm) && best && 284 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 285 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 286 287 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 288 best = cpuid_entry2_find(entries, nent, 0x1, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 289 if (best) 290 cpuid_entry_change(best, X86_FEATURE_MWAIT, 291 vcpu->arch.ia32_misc_enable_msr & 292 MSR_IA32_MISC_ENABLE_MWAIT); 293 } 294 } 295 296 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 297 { 298 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 299 } 300 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 301 302 static bool kvm_cpuid_has_hyperv(struct kvm_cpuid_entry2 *entries, int nent) 303 { 304 struct kvm_cpuid_entry2 *entry; 305 306 entry = cpuid_entry2_find(entries, nent, HYPERV_CPUID_INTERFACE, 307 KVM_CPUID_INDEX_NOT_SIGNIFICANT); 308 return entry && entry->eax == HYPERV_CPUID_SIGNATURE_EAX; 309 } 310 311 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 312 { 313 struct kvm_lapic *apic = vcpu->arch.apic; 314 struct kvm_cpuid_entry2 *best; 315 316 best = kvm_find_cpuid_entry(vcpu, 1); 317 if (best && apic) { 318 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 319 apic->lapic_timer.timer_mode_mask = 3 << 17; 320 else 321 apic->lapic_timer.timer_mode_mask = 1 << 17; 322 323 kvm_apic_set_version(vcpu); 324 } 325 326 vcpu->arch.guest_supported_xcr0 = 327 cpuid_get_supported_xcr0(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 328 329 /* 330 * FP+SSE can always be saved/restored via KVM_{G,S}ET_XSAVE, even if 331 * XSAVE/XCRO are not exposed to the guest, and even if XSAVE isn't 332 * supported by the host. 333 */ 334 vcpu->arch.guest_fpu.fpstate->user_xfeatures = vcpu->arch.guest_supported_xcr0 | 335 XFEATURE_MASK_FPSSE; 336 337 kvm_update_pv_runtime(vcpu); 338 339 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 340 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 341 342 kvm_pmu_refresh(vcpu); 343 vcpu->arch.cr4_guest_rsvd_bits = 344 __cr4_reserved_bits(guest_cpuid_has, vcpu); 345 346 kvm_hv_set_cpuid(vcpu, kvm_cpuid_has_hyperv(vcpu->arch.cpuid_entries, 347 vcpu->arch.cpuid_nent)); 348 349 /* Invoke the vendor callback only after the above state is updated. */ 350 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 351 352 /* 353 * Except for the MMU, which needs to do its thing any vendor specific 354 * adjustments to the reserved GPA bits. 355 */ 356 kvm_mmu_after_set_cpuid(vcpu); 357 } 358 359 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 360 { 361 struct kvm_cpuid_entry2 *best; 362 363 best = kvm_find_cpuid_entry(vcpu, 0x80000000); 364 if (!best || best->eax < 0x80000008) 365 goto not_found; 366 best = kvm_find_cpuid_entry(vcpu, 0x80000008); 367 if (best) 368 return best->eax & 0xff; 369 not_found: 370 return 36; 371 } 372 373 /* 374 * This "raw" version returns the reserved GPA bits without any adjustments for 375 * encryption technologies that usurp bits. The raw mask should be used if and 376 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 377 */ 378 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 379 { 380 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 381 } 382 383 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 384 int nent) 385 { 386 int r; 387 388 __kvm_update_cpuid_runtime(vcpu, e2, nent); 389 390 /* 391 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 392 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 393 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 394 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 395 * the core vCPU model on the fly. It would've been better to forbid any 396 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 397 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 398 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 399 * whether the supplied CPUID data is equal to what's already set. 400 */ 401 if (kvm_vcpu_has_run(vcpu)) { 402 r = kvm_cpuid_check_equal(vcpu, e2, nent); 403 if (r) 404 return r; 405 406 kvfree(e2); 407 return 0; 408 } 409 410 if (kvm_cpuid_has_hyperv(e2, nent)) { 411 r = kvm_hv_vcpu_init(vcpu); 412 if (r) 413 return r; 414 } 415 416 r = kvm_check_cpuid(vcpu, e2, nent); 417 if (r) 418 return r; 419 420 kvfree(vcpu->arch.cpuid_entries); 421 vcpu->arch.cpuid_entries = e2; 422 vcpu->arch.cpuid_nent = nent; 423 424 vcpu->arch.kvm_cpuid = kvm_get_hypervisor_cpuid(vcpu, KVM_SIGNATURE); 425 vcpu->arch.xen.cpuid = kvm_get_hypervisor_cpuid(vcpu, XEN_SIGNATURE); 426 kvm_vcpu_after_set_cpuid(vcpu); 427 428 return 0; 429 } 430 431 /* when an old userspace process fills a new kernel module */ 432 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 433 struct kvm_cpuid *cpuid, 434 struct kvm_cpuid_entry __user *entries) 435 { 436 int r, i; 437 struct kvm_cpuid_entry *e = NULL; 438 struct kvm_cpuid_entry2 *e2 = NULL; 439 440 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 441 return -E2BIG; 442 443 if (cpuid->nent) { 444 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 445 if (IS_ERR(e)) 446 return PTR_ERR(e); 447 448 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 449 if (!e2) { 450 r = -ENOMEM; 451 goto out_free_cpuid; 452 } 453 } 454 for (i = 0; i < cpuid->nent; i++) { 455 e2[i].function = e[i].function; 456 e2[i].eax = e[i].eax; 457 e2[i].ebx = e[i].ebx; 458 e2[i].ecx = e[i].ecx; 459 e2[i].edx = e[i].edx; 460 e2[i].index = 0; 461 e2[i].flags = 0; 462 e2[i].padding[0] = 0; 463 e2[i].padding[1] = 0; 464 e2[i].padding[2] = 0; 465 } 466 467 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 468 if (r) 469 kvfree(e2); 470 471 out_free_cpuid: 472 kvfree(e); 473 474 return r; 475 } 476 477 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 478 struct kvm_cpuid2 *cpuid, 479 struct kvm_cpuid_entry2 __user *entries) 480 { 481 struct kvm_cpuid_entry2 *e2 = NULL; 482 int r; 483 484 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 485 return -E2BIG; 486 487 if (cpuid->nent) { 488 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 489 if (IS_ERR(e2)) 490 return PTR_ERR(e2); 491 } 492 493 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 494 if (r) 495 kvfree(e2); 496 497 return r; 498 } 499 500 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 501 struct kvm_cpuid2 *cpuid, 502 struct kvm_cpuid_entry2 __user *entries) 503 { 504 if (cpuid->nent < vcpu->arch.cpuid_nent) 505 return -E2BIG; 506 507 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 508 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 509 return -EFAULT; 510 511 cpuid->nent = vcpu->arch.cpuid_nent; 512 return 0; 513 } 514 515 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 516 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 517 { 518 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 519 struct kvm_cpuid_entry2 entry; 520 521 reverse_cpuid_check(leaf); 522 523 cpuid_count(cpuid.function, cpuid.index, 524 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 525 526 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 527 } 528 529 static __always_inline 530 void kvm_cpu_cap_init_kvm_defined(enum kvm_only_cpuid_leafs leaf, u32 mask) 531 { 532 /* Use kvm_cpu_cap_mask for leafs that aren't KVM-only. */ 533 BUILD_BUG_ON(leaf < NCAPINTS); 534 535 kvm_cpu_caps[leaf] = mask; 536 537 __kvm_cpu_cap_mask(leaf); 538 } 539 540 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 541 { 542 /* Use kvm_cpu_cap_init_kvm_defined for KVM-only leafs. */ 543 BUILD_BUG_ON(leaf >= NCAPINTS); 544 545 kvm_cpu_caps[leaf] &= mask; 546 547 __kvm_cpu_cap_mask(leaf); 548 } 549 550 void kvm_set_cpu_caps(void) 551 { 552 #ifdef CONFIG_X86_64 553 unsigned int f_gbpages = F(GBPAGES); 554 unsigned int f_lm = F(LM); 555 unsigned int f_xfd = F(XFD); 556 #else 557 unsigned int f_gbpages = 0; 558 unsigned int f_lm = 0; 559 unsigned int f_xfd = 0; 560 #endif 561 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 562 563 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 564 sizeof(boot_cpu_data.x86_capability)); 565 566 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 567 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 568 569 kvm_cpu_cap_mask(CPUID_1_ECX, 570 /* 571 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 572 * advertised to guests via CPUID! 573 */ 574 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 575 0 /* DS-CPL, VMX, SMX, EST */ | 576 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 577 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 578 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 579 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 580 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 581 F(F16C) | F(RDRAND) 582 ); 583 /* KVM emulates x2apic in software irrespective of host support. */ 584 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 585 586 kvm_cpu_cap_mask(CPUID_1_EDX, 587 F(FPU) | F(VME) | F(DE) | F(PSE) | 588 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 589 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 590 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 591 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 592 0 /* Reserved, DS, ACPI */ | F(MMX) | 593 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 594 0 /* HTT, TM, Reserved, PBE */ 595 ); 596 597 kvm_cpu_cap_mask(CPUID_7_0_EBX, 598 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | 599 F(FDP_EXCPTN_ONLY) | F(SMEP) | F(BMI2) | F(ERMS) | F(INVPCID) | 600 F(RTM) | F(ZERO_FCS_FDS) | 0 /*MPX*/ | F(AVX512F) | 601 F(AVX512DQ) | F(RDSEED) | F(ADX) | F(SMAP) | F(AVX512IFMA) | 602 F(CLFLUSHOPT) | F(CLWB) | 0 /*INTEL_PT*/ | F(AVX512PF) | 603 F(AVX512ER) | F(AVX512CD) | F(SHA_NI) | F(AVX512BW) | 604 F(AVX512VL)); 605 606 kvm_cpu_cap_mask(CPUID_7_ECX, 607 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 608 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 609 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 610 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 611 F(SGX_LC) | F(BUS_LOCK_DETECT) 612 ); 613 /* Set LA57 based on hardware capability. */ 614 if (cpuid_ecx(7) & F(LA57)) 615 kvm_cpu_cap_set(X86_FEATURE_LA57); 616 617 /* 618 * PKU not yet implemented for shadow paging and requires OSPKE 619 * to be set on the host. Clear it if that is not the case 620 */ 621 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 622 kvm_cpu_cap_clear(X86_FEATURE_PKU); 623 624 kvm_cpu_cap_mask(CPUID_7_EDX, 625 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 626 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 627 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 628 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 629 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) | F(FLUSH_L1D) 630 ); 631 632 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 633 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 634 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 635 636 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 637 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 638 if (boot_cpu_has(X86_FEATURE_STIBP)) 639 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 640 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 641 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 642 643 kvm_cpu_cap_mask(CPUID_7_1_EAX, 644 F(AVX_VNNI) | F(AVX512_BF16) | F(CMPCCXADD) | 645 F(FZRM) | F(FSRS) | F(FSRC) | 646 F(AMX_FP16) | F(AVX_IFMA) 647 ); 648 649 kvm_cpu_cap_init_kvm_defined(CPUID_7_1_EDX, 650 F(AVX_VNNI_INT8) | F(AVX_NE_CONVERT) | F(PREFETCHITI) 651 ); 652 653 kvm_cpu_cap_mask(CPUID_D_1_EAX, 654 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 655 ); 656 657 kvm_cpu_cap_init_kvm_defined(CPUID_12_EAX, 658 SF(SGX1) | SF(SGX2) | SF(SGX_EDECCSSA) 659 ); 660 661 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 662 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 663 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 664 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 665 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 666 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 667 ); 668 669 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 670 F(FPU) | F(VME) | F(DE) | F(PSE) | 671 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 672 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 673 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 674 F(PAT) | F(PSE36) | 0 /* Reserved */ | 675 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 676 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 677 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 678 ); 679 680 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 681 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 682 683 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0007_EDX, 684 SF(CONSTANT_TSC) 685 ); 686 687 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 688 F(CLZERO) | F(XSAVEERPTR) | 689 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 690 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 691 F(AMD_PSFD) 692 ); 693 694 /* 695 * AMD has separate bits for each SPEC_CTRL bit. 696 * arch/x86/kernel/cpu/bugs.c is kind enough to 697 * record that in cpufeatures so use them. 698 */ 699 if (boot_cpu_has(X86_FEATURE_IBPB)) 700 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 701 if (boot_cpu_has(X86_FEATURE_IBRS)) 702 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 703 if (boot_cpu_has(X86_FEATURE_STIBP)) 704 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 705 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 706 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 707 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 708 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 709 /* 710 * The preference is to use SPEC CTRL MSR instead of the 711 * VIRT_SPEC MSR. 712 */ 713 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 714 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 715 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 716 717 /* 718 * Hide all SVM features by default, SVM will set the cap bits for 719 * features it emulates and/or exposes for L1. 720 */ 721 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 722 723 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 724 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 725 F(SME_COHERENT)); 726 727 kvm_cpu_cap_mask(CPUID_8000_0021_EAX, 728 F(NO_NESTED_DATA_BP) | F(LFENCE_RDTSC) | 0 /* SmmPgCfgLock */ | 729 F(NULL_SEL_CLR_BASE) | F(AUTOIBRS) | 0 /* PrefetchCtlMsr */ 730 ); 731 732 if (cpu_feature_enabled(X86_FEATURE_SRSO_NO)) 733 kvm_cpu_cap_set(X86_FEATURE_SRSO_NO); 734 735 kvm_cpu_cap_init_kvm_defined(CPUID_8000_0022_EAX, 736 F(PERFMON_V2) 737 ); 738 739 /* 740 * Synthesize "LFENCE is serializing" into the AMD-defined entry in 741 * KVM's supported CPUID if the feature is reported as supported by the 742 * kernel. LFENCE_RDTSC was a Linux-defined synthetic feature long 743 * before AMD joined the bandwagon, e.g. LFENCE is serializing on most 744 * CPUs that support SSE2. On CPUs that don't support AMD's leaf, 745 * kvm_cpu_cap_mask() will unfortunately drop the flag due to ANDing 746 * the mask with the raw host CPUID, and reporting support in AMD's 747 * leaf can make it easier for userspace to detect the feature. 748 */ 749 if (cpu_feature_enabled(X86_FEATURE_LFENCE_RDTSC)) 750 kvm_cpu_cap_set(X86_FEATURE_LFENCE_RDTSC); 751 if (!static_cpu_has_bug(X86_BUG_NULL_SEG)) 752 kvm_cpu_cap_set(X86_FEATURE_NULL_SEL_CLR_BASE); 753 kvm_cpu_cap_set(X86_FEATURE_NO_SMM_CTL_MSR); 754 755 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 756 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 757 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 758 F(PMM) | F(PMM_EN) 759 ); 760 761 /* 762 * Hide RDTSCP and RDPID if either feature is reported as supported but 763 * probing MSR_TSC_AUX failed. This is purely a sanity check and 764 * should never happen, but the guest will likely crash if RDTSCP or 765 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 766 * the past. For example, the sanity check may fire if this instance of 767 * KVM is running as L1 on top of an older, broken KVM. 768 */ 769 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 770 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 771 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 772 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 773 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 774 } 775 } 776 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 777 778 struct kvm_cpuid_array { 779 struct kvm_cpuid_entry2 *entries; 780 int maxnent; 781 int nent; 782 }; 783 784 static struct kvm_cpuid_entry2 *get_next_cpuid(struct kvm_cpuid_array *array) 785 { 786 if (array->nent >= array->maxnent) 787 return NULL; 788 789 return &array->entries[array->nent++]; 790 } 791 792 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 793 u32 function, u32 index) 794 { 795 struct kvm_cpuid_entry2 *entry = get_next_cpuid(array); 796 797 if (!entry) 798 return NULL; 799 800 memset(entry, 0, sizeof(*entry)); 801 entry->function = function; 802 entry->index = index; 803 switch (function & 0xC0000000) { 804 case 0x40000000: 805 /* Hypervisor leaves are always synthesized by __do_cpuid_func. */ 806 return entry; 807 808 case 0x80000000: 809 /* 810 * 0x80000021 is sometimes synthesized by __do_cpuid_func, which 811 * would result in out-of-bounds calls to do_host_cpuid. 812 */ 813 { 814 static int max_cpuid_80000000; 815 if (!READ_ONCE(max_cpuid_80000000)) 816 WRITE_ONCE(max_cpuid_80000000, cpuid_eax(0x80000000)); 817 if (function > READ_ONCE(max_cpuid_80000000)) 818 return entry; 819 } 820 break; 821 822 default: 823 break; 824 } 825 826 cpuid_count(entry->function, entry->index, 827 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 828 829 if (cpuid_function_is_indexed(function)) 830 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 831 832 return entry; 833 } 834 835 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 836 { 837 struct kvm_cpuid_entry2 *entry; 838 839 if (array->nent >= array->maxnent) 840 return -E2BIG; 841 842 entry = &array->entries[array->nent]; 843 entry->function = func; 844 entry->index = 0; 845 entry->flags = 0; 846 847 switch (func) { 848 case 0: 849 entry->eax = 7; 850 ++array->nent; 851 break; 852 case 1: 853 entry->ecx = F(MOVBE); 854 ++array->nent; 855 break; 856 case 7: 857 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 858 entry->eax = 0; 859 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 860 entry->ecx = F(RDPID); 861 ++array->nent; 862 break; 863 default: 864 break; 865 } 866 867 return 0; 868 } 869 870 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 871 { 872 struct kvm_cpuid_entry2 *entry; 873 int r, i, max_idx; 874 875 /* all calls to cpuid_count() should be made on the same cpu */ 876 get_cpu(); 877 878 r = -E2BIG; 879 880 entry = do_host_cpuid(array, function, 0); 881 if (!entry) 882 goto out; 883 884 switch (function) { 885 case 0: 886 /* Limited to the highest leaf implemented in KVM. */ 887 entry->eax = min(entry->eax, 0x1fU); 888 break; 889 case 1: 890 cpuid_entry_override(entry, CPUID_1_EDX); 891 cpuid_entry_override(entry, CPUID_1_ECX); 892 break; 893 case 2: 894 /* 895 * On ancient CPUs, function 2 entries are STATEFUL. That is, 896 * CPUID(function=2, index=0) may return different results each 897 * time, with the least-significant byte in EAX enumerating the 898 * number of times software should do CPUID(2, 0). 899 * 900 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 901 * idiotic. Intel's SDM states that EAX & 0xff "will always 902 * return 01H. Software should ignore this value and not 903 * interpret it as an informational descriptor", while AMD's 904 * APM states that CPUID(2) is reserved. 905 * 906 * WARN if a frankenstein CPU that supports virtualization and 907 * a stateful CPUID.0x2 is encountered. 908 */ 909 WARN_ON_ONCE((entry->eax & 0xff) > 1); 910 break; 911 /* functions 4 and 0x8000001d have additional index. */ 912 case 4: 913 case 0x8000001d: 914 /* 915 * Read entries until the cache type in the previous entry is 916 * zero, i.e. indicates an invalid entry. 917 */ 918 for (i = 1; entry->eax & 0x1f; ++i) { 919 entry = do_host_cpuid(array, function, i); 920 if (!entry) 921 goto out; 922 } 923 break; 924 case 6: /* Thermal management */ 925 entry->eax = 0x4; /* allow ARAT */ 926 entry->ebx = 0; 927 entry->ecx = 0; 928 entry->edx = 0; 929 break; 930 /* function 7 has additional index. */ 931 case 7: 932 entry->eax = min(entry->eax, 1u); 933 cpuid_entry_override(entry, CPUID_7_0_EBX); 934 cpuid_entry_override(entry, CPUID_7_ECX); 935 cpuid_entry_override(entry, CPUID_7_EDX); 936 937 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 938 if (entry->eax == 1) { 939 entry = do_host_cpuid(array, function, 1); 940 if (!entry) 941 goto out; 942 943 cpuid_entry_override(entry, CPUID_7_1_EAX); 944 cpuid_entry_override(entry, CPUID_7_1_EDX); 945 entry->ebx = 0; 946 entry->ecx = 0; 947 } 948 break; 949 case 0xa: { /* Architectural Performance Monitoring */ 950 union cpuid10_eax eax; 951 union cpuid10_edx edx; 952 953 if (!enable_pmu || !static_cpu_has(X86_FEATURE_ARCH_PERFMON)) { 954 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 955 break; 956 } 957 958 eax.split.version_id = kvm_pmu_cap.version; 959 eax.split.num_counters = kvm_pmu_cap.num_counters_gp; 960 eax.split.bit_width = kvm_pmu_cap.bit_width_gp; 961 eax.split.mask_length = kvm_pmu_cap.events_mask_len; 962 edx.split.num_counters_fixed = kvm_pmu_cap.num_counters_fixed; 963 edx.split.bit_width_fixed = kvm_pmu_cap.bit_width_fixed; 964 965 if (kvm_pmu_cap.version) 966 edx.split.anythread_deprecated = 1; 967 edx.split.reserved1 = 0; 968 edx.split.reserved2 = 0; 969 970 entry->eax = eax.full; 971 entry->ebx = kvm_pmu_cap.events_mask; 972 entry->ecx = 0; 973 entry->edx = edx.full; 974 break; 975 } 976 case 0x1f: 977 case 0xb: 978 /* 979 * No topology; a valid topology is indicated by the presence 980 * of subleaf 1. 981 */ 982 entry->eax = entry->ebx = entry->ecx = 0; 983 break; 984 case 0xd: { 985 u64 permitted_xcr0 = kvm_get_filtered_xcr0(); 986 u64 permitted_xss = kvm_caps.supported_xss; 987 988 entry->eax &= permitted_xcr0; 989 entry->ebx = xstate_required_size(permitted_xcr0, false); 990 entry->ecx = entry->ebx; 991 entry->edx &= permitted_xcr0 >> 32; 992 if (!permitted_xcr0) 993 break; 994 995 entry = do_host_cpuid(array, function, 1); 996 if (!entry) 997 goto out; 998 999 cpuid_entry_override(entry, CPUID_D_1_EAX); 1000 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 1001 entry->ebx = xstate_required_size(permitted_xcr0 | permitted_xss, 1002 true); 1003 else { 1004 WARN_ON_ONCE(permitted_xss != 0); 1005 entry->ebx = 0; 1006 } 1007 entry->ecx &= permitted_xss; 1008 entry->edx &= permitted_xss >> 32; 1009 1010 for (i = 2; i < 64; ++i) { 1011 bool s_state; 1012 if (permitted_xcr0 & BIT_ULL(i)) 1013 s_state = false; 1014 else if (permitted_xss & BIT_ULL(i)) 1015 s_state = true; 1016 else 1017 continue; 1018 1019 entry = do_host_cpuid(array, function, i); 1020 if (!entry) 1021 goto out; 1022 1023 /* 1024 * The supported check above should have filtered out 1025 * invalid sub-leafs. Only valid sub-leafs should 1026 * reach this point, and they should have a non-zero 1027 * save state size. Furthermore, check whether the 1028 * processor agrees with permitted_xcr0/permitted_xss 1029 * on whether this is an XCR0- or IA32_XSS-managed area. 1030 */ 1031 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 1032 --array->nent; 1033 continue; 1034 } 1035 1036 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 1037 entry->ecx &= ~BIT_ULL(2); 1038 entry->edx = 0; 1039 } 1040 break; 1041 } 1042 case 0x12: 1043 /* Intel SGX */ 1044 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 1045 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1046 break; 1047 } 1048 1049 /* 1050 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 1051 * and max enclave sizes. The SGX sub-features and MISCSELECT 1052 * are restricted by kernel and KVM capabilities (like most 1053 * feature flags), while enclave size is unrestricted. 1054 */ 1055 cpuid_entry_override(entry, CPUID_12_EAX); 1056 entry->ebx &= SGX_MISC_EXINFO; 1057 1058 entry = do_host_cpuid(array, function, 1); 1059 if (!entry) 1060 goto out; 1061 1062 /* 1063 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 1064 * feature flags. Advertise all supported flags, including 1065 * privileged attributes that require explicit opt-in from 1066 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 1067 * expected to derive it from supported XCR0. 1068 */ 1069 entry->eax &= SGX_ATTR_PRIV_MASK | SGX_ATTR_UNPRIV_MASK; 1070 entry->ebx &= 0; 1071 break; 1072 /* Intel PT */ 1073 case 0x14: 1074 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 1075 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1076 break; 1077 } 1078 1079 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1080 if (!do_host_cpuid(array, function, i)) 1081 goto out; 1082 } 1083 break; 1084 /* Intel AMX TILE */ 1085 case 0x1d: 1086 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1087 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1088 break; 1089 } 1090 1091 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 1092 if (!do_host_cpuid(array, function, i)) 1093 goto out; 1094 } 1095 break; 1096 case 0x1e: /* TMUL information */ 1097 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1098 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1099 break; 1100 } 1101 break; 1102 case KVM_CPUID_SIGNATURE: { 1103 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1104 entry->eax = KVM_CPUID_FEATURES; 1105 entry->ebx = sigptr[0]; 1106 entry->ecx = sigptr[1]; 1107 entry->edx = sigptr[2]; 1108 break; 1109 } 1110 case KVM_CPUID_FEATURES: 1111 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1112 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1113 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1114 (1 << KVM_FEATURE_ASYNC_PF) | 1115 (1 << KVM_FEATURE_PV_EOI) | 1116 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1117 (1 << KVM_FEATURE_PV_UNHALT) | 1118 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1119 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1120 (1 << KVM_FEATURE_PV_SEND_IPI) | 1121 (1 << KVM_FEATURE_POLL_CONTROL) | 1122 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1123 (1 << KVM_FEATURE_ASYNC_PF_INT); 1124 1125 if (sched_info_on()) 1126 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1127 1128 entry->ebx = 0; 1129 entry->ecx = 0; 1130 entry->edx = 0; 1131 break; 1132 case 0x80000000: 1133 entry->eax = min(entry->eax, 0x80000022); 1134 /* 1135 * Serializing LFENCE is reported in a multitude of ways, and 1136 * NullSegClearsBase is not reported in CPUID on Zen2; help 1137 * userspace by providing the CPUID leaf ourselves. 1138 * 1139 * However, only do it if the host has CPUID leaf 0x8000001d. 1140 * QEMU thinks that it can query the host blindly for that 1141 * CPUID leaf if KVM reports that it supports 0x8000001d or 1142 * above. The processor merrily returns values from the 1143 * highest Intel leaf which QEMU tries to use as the guest's 1144 * 0x8000001d. Even worse, this can result in an infinite 1145 * loop if said highest leaf has no subleaves indexed by ECX. 1146 */ 1147 if (entry->eax >= 0x8000001d && 1148 (static_cpu_has(X86_FEATURE_LFENCE_RDTSC) 1149 || !static_cpu_has_bug(X86_BUG_NULL_SEG))) 1150 entry->eax = max(entry->eax, 0x80000021); 1151 break; 1152 case 0x80000001: 1153 entry->ebx &= ~GENMASK(27, 16); 1154 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1155 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1156 break; 1157 case 0x80000006: 1158 /* Drop reserved bits, pass host L2 cache and TLB info. */ 1159 entry->edx &= ~GENMASK(17, 16); 1160 break; 1161 case 0x80000007: /* Advanced power management */ 1162 cpuid_entry_override(entry, CPUID_8000_0007_EDX); 1163 1164 /* mask against host */ 1165 entry->edx &= boot_cpu_data.x86_power; 1166 entry->eax = entry->ebx = entry->ecx = 0; 1167 break; 1168 case 0x80000008: { 1169 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1170 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1171 unsigned phys_as = entry->eax & 0xff; 1172 1173 /* 1174 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1175 * the guest operates in the same PA space as the host, i.e. 1176 * reductions in MAXPHYADDR for memory encryption affect shadow 1177 * paging, too. 1178 * 1179 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1180 * provided, use the raw bare metal MAXPHYADDR as reductions to 1181 * the HPAs do not affect GPAs. 1182 */ 1183 if (!tdp_enabled) 1184 g_phys_as = boot_cpu_data.x86_phys_bits; 1185 else if (!g_phys_as) 1186 g_phys_as = phys_as; 1187 1188 entry->eax = g_phys_as | (virt_as << 8); 1189 entry->ecx &= ~(GENMASK(31, 16) | GENMASK(11, 8)); 1190 entry->edx = 0; 1191 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1192 break; 1193 } 1194 case 0x8000000A: 1195 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1196 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1197 break; 1198 } 1199 entry->eax = 1; /* SVM revision 1 */ 1200 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1201 ASID emulation to nested SVM */ 1202 entry->ecx = 0; /* Reserved */ 1203 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1204 break; 1205 case 0x80000019: 1206 entry->ecx = entry->edx = 0; 1207 break; 1208 case 0x8000001a: 1209 entry->eax &= GENMASK(2, 0); 1210 entry->ebx = entry->ecx = entry->edx = 0; 1211 break; 1212 case 0x8000001e: 1213 /* Do not return host topology information. */ 1214 entry->eax = entry->ebx = entry->ecx = 0; 1215 entry->edx = 0; /* reserved */ 1216 break; 1217 case 0x8000001F: 1218 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1219 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1220 } else { 1221 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1222 /* Clear NumVMPL since KVM does not support VMPL. */ 1223 entry->ebx &= ~GENMASK(31, 12); 1224 /* 1225 * Enumerate '0' for "PA bits reduction", the adjusted 1226 * MAXPHYADDR is enumerated directly (see 0x80000008). 1227 */ 1228 entry->ebx &= ~GENMASK(11, 6); 1229 } 1230 break; 1231 case 0x80000020: 1232 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1233 break; 1234 case 0x80000021: 1235 entry->ebx = entry->ecx = entry->edx = 0; 1236 cpuid_entry_override(entry, CPUID_8000_0021_EAX); 1237 break; 1238 /* AMD Extended Performance Monitoring and Debug */ 1239 case 0x80000022: { 1240 union cpuid_0x80000022_ebx ebx; 1241 1242 entry->ecx = entry->edx = 0; 1243 if (!enable_pmu || !kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) { 1244 entry->eax = entry->ebx; 1245 break; 1246 } 1247 1248 cpuid_entry_override(entry, CPUID_8000_0022_EAX); 1249 1250 if (kvm_cpu_cap_has(X86_FEATURE_PERFMON_V2)) 1251 ebx.split.num_core_pmc = kvm_pmu_cap.num_counters_gp; 1252 else if (kvm_cpu_cap_has(X86_FEATURE_PERFCTR_CORE)) 1253 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS_CORE; 1254 else 1255 ebx.split.num_core_pmc = AMD64_NUM_COUNTERS; 1256 1257 entry->ebx = ebx.full; 1258 break; 1259 } 1260 /*Add support for Centaur's CPUID instruction*/ 1261 case 0xC0000000: 1262 /*Just support up to 0xC0000004 now*/ 1263 entry->eax = min(entry->eax, 0xC0000004); 1264 break; 1265 case 0xC0000001: 1266 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1267 break; 1268 case 3: /* Processor serial number */ 1269 case 5: /* MONITOR/MWAIT */ 1270 case 0xC0000002: 1271 case 0xC0000003: 1272 case 0xC0000004: 1273 default: 1274 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1275 break; 1276 } 1277 1278 r = 0; 1279 1280 out: 1281 put_cpu(); 1282 1283 return r; 1284 } 1285 1286 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1287 unsigned int type) 1288 { 1289 if (type == KVM_GET_EMULATED_CPUID) 1290 return __do_cpuid_func_emulated(array, func); 1291 1292 return __do_cpuid_func(array, func); 1293 } 1294 1295 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1296 1297 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1298 unsigned int type) 1299 { 1300 u32 limit; 1301 int r; 1302 1303 if (func == CENTAUR_CPUID_SIGNATURE && 1304 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1305 return 0; 1306 1307 r = do_cpuid_func(array, func, type); 1308 if (r) 1309 return r; 1310 1311 limit = array->entries[array->nent - 1].eax; 1312 for (func = func + 1; func <= limit; ++func) { 1313 r = do_cpuid_func(array, func, type); 1314 if (r) 1315 break; 1316 } 1317 1318 return r; 1319 } 1320 1321 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1322 __u32 num_entries, unsigned int ioctl_type) 1323 { 1324 int i; 1325 __u32 pad[3]; 1326 1327 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1328 return false; 1329 1330 /* 1331 * We want to make sure that ->padding is being passed clean from 1332 * userspace in case we want to use it for something in the future. 1333 * 1334 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1335 * have to give ourselves satisfied only with the emulated side. /me 1336 * sheds a tear. 1337 */ 1338 for (i = 0; i < num_entries; i++) { 1339 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1340 return true; 1341 1342 if (pad[0] || pad[1] || pad[2]) 1343 return true; 1344 } 1345 return false; 1346 } 1347 1348 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1349 struct kvm_cpuid_entry2 __user *entries, 1350 unsigned int type) 1351 { 1352 static const u32 funcs[] = { 1353 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1354 }; 1355 1356 struct kvm_cpuid_array array = { 1357 .nent = 0, 1358 }; 1359 int r, i; 1360 1361 if (cpuid->nent < 1) 1362 return -E2BIG; 1363 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1364 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1365 1366 if (sanity_check_entries(entries, cpuid->nent, type)) 1367 return -EINVAL; 1368 1369 array.entries = kvcalloc(cpuid->nent, sizeof(struct kvm_cpuid_entry2), GFP_KERNEL); 1370 if (!array.entries) 1371 return -ENOMEM; 1372 1373 array.maxnent = cpuid->nent; 1374 1375 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1376 r = get_cpuid_func(&array, funcs[i], type); 1377 if (r) 1378 goto out_free; 1379 } 1380 cpuid->nent = array.nent; 1381 1382 if (copy_to_user(entries, array.entries, 1383 array.nent * sizeof(struct kvm_cpuid_entry2))) 1384 r = -EFAULT; 1385 1386 out_free: 1387 kvfree(array.entries); 1388 return r; 1389 } 1390 1391 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry_index(struct kvm_vcpu *vcpu, 1392 u32 function, u32 index) 1393 { 1394 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1395 function, index); 1396 } 1397 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry_index); 1398 1399 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1400 u32 function) 1401 { 1402 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1403 function, KVM_CPUID_INDEX_NOT_SIGNIFICANT); 1404 } 1405 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1406 1407 /* 1408 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1409 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1410 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1411 * range. Centaur/VIA follows Intel semantics. 1412 * 1413 * A leaf is considered out-of-range if its function is higher than the maximum 1414 * supported leaf of its associated class or if its associated class does not 1415 * exist. 1416 * 1417 * There are three primary classes to be considered, with their respective 1418 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1419 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1420 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1421 * 1422 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1423 * - Hypervisor: 0x40000000 - 0x4fffffff 1424 * - Extended: 0x80000000 - 0xbfffffff 1425 * - Centaur: 0xc0000000 - 0xcfffffff 1426 * 1427 * The Hypervisor class is further subdivided into sub-classes that each act as 1428 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1429 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1430 * CPUID sub-classes are: 1431 * 1432 * - HyperV: 0x40000000 - 0x400000ff 1433 * - KVM: 0x40000100 - 0x400001ff 1434 */ 1435 static struct kvm_cpuid_entry2 * 1436 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1437 { 1438 struct kvm_cpuid_entry2 *basic, *class; 1439 u32 function = *fn_ptr; 1440 1441 basic = kvm_find_cpuid_entry(vcpu, 0); 1442 if (!basic) 1443 return NULL; 1444 1445 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1446 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1447 return NULL; 1448 1449 if (function >= 0x40000000 && function <= 0x4fffffff) 1450 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00); 1451 else if (function >= 0xc0000000) 1452 class = kvm_find_cpuid_entry(vcpu, 0xc0000000); 1453 else 1454 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000); 1455 1456 if (class && function <= class->eax) 1457 return NULL; 1458 1459 /* 1460 * Leaf specific adjustments are also applied when redirecting to the 1461 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1462 * entry for CPUID.0xb.index (see below), then the output value for EDX 1463 * needs to be pulled from CPUID.0xb.1. 1464 */ 1465 *fn_ptr = basic->eax; 1466 1467 /* 1468 * The class does not exist or the requested function is out of range; 1469 * the effective CPUID entry is the max basic leaf. Note, the index of 1470 * the original requested leaf is observed! 1471 */ 1472 return kvm_find_cpuid_entry_index(vcpu, basic->eax, index); 1473 } 1474 1475 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1476 u32 *ecx, u32 *edx, bool exact_only) 1477 { 1478 u32 orig_function = *eax, function = *eax, index = *ecx; 1479 struct kvm_cpuid_entry2 *entry; 1480 bool exact, used_max_basic = false; 1481 1482 entry = kvm_find_cpuid_entry_index(vcpu, function, index); 1483 exact = !!entry; 1484 1485 if (!entry && !exact_only) { 1486 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1487 used_max_basic = !!entry; 1488 } 1489 1490 if (entry) { 1491 *eax = entry->eax; 1492 *ebx = entry->ebx; 1493 *ecx = entry->ecx; 1494 *edx = entry->edx; 1495 if (function == 7 && index == 0) { 1496 u64 data; 1497 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1498 (data & TSX_CTRL_CPUID_CLEAR)) 1499 *ebx &= ~(F(RTM) | F(HLE)); 1500 } else if (function == 0x80000007) { 1501 if (kvm_hv_invtsc_suppressed(vcpu)) 1502 *edx &= ~SF(CONSTANT_TSC); 1503 } 1504 } else { 1505 *eax = *ebx = *ecx = *edx = 0; 1506 /* 1507 * When leaf 0BH or 1FH is defined, CL is pass-through 1508 * and EDX is always the x2APIC ID, even for undefined 1509 * subleaves. Index 1 will exist iff the leaf is 1510 * implemented, so we pass through CL iff leaf 1 1511 * exists. EDX can be copied from any existing index. 1512 */ 1513 if (function == 0xb || function == 0x1f) { 1514 entry = kvm_find_cpuid_entry_index(vcpu, function, 1); 1515 if (entry) { 1516 *ecx = index & 0xff; 1517 *edx = entry->edx; 1518 } 1519 } 1520 } 1521 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1522 used_max_basic); 1523 return exact; 1524 } 1525 EXPORT_SYMBOL_GPL(kvm_cpuid); 1526 1527 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1528 { 1529 u32 eax, ebx, ecx, edx; 1530 1531 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1532 return 1; 1533 1534 eax = kvm_rax_read(vcpu); 1535 ecx = kvm_rcx_read(vcpu); 1536 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1537 kvm_rax_write(vcpu, eax); 1538 kvm_rbx_write(vcpu, ebx); 1539 kvm_rcx_write(vcpu, ecx); 1540 kvm_rdx_write(vcpu, edx); 1541 return kvm_skip_emulated_instruction(vcpu); 1542 } 1543 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1544