1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include <asm/sgx.h> 22 #include "cpuid.h" 23 #include "lapic.h" 24 #include "mmu.h" 25 #include "trace.h" 26 #include "pmu.h" 27 28 /* 29 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 30 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 31 */ 32 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 33 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 34 35 u32 xstate_required_size(u64 xstate_bv, bool compacted) 36 { 37 int feature_bit = 0; 38 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 39 40 xstate_bv &= XFEATURE_MASK_EXTEND; 41 while (xstate_bv) { 42 if (xstate_bv & 0x1) { 43 u32 eax, ebx, ecx, edx, offset; 44 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 45 /* ECX[1]: 64B alignment in compacted form */ 46 if (compacted) 47 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 48 else 49 offset = ebx; 50 ret = max(ret, offset + eax); 51 } 52 53 xstate_bv >>= 1; 54 feature_bit++; 55 } 56 57 return ret; 58 } 59 60 /* 61 * This one is tied to SSB in the user API, and not 62 * visible in /proc/cpuinfo. 63 */ 64 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ 65 66 #define F feature_bit 67 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0) 68 69 70 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 71 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 72 { 73 struct kvm_cpuid_entry2 *e; 74 int i; 75 76 for (i = 0; i < nent; i++) { 77 e = &entries[i]; 78 79 if (e->function == function && 80 (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)) 81 return e; 82 } 83 84 return NULL; 85 } 86 87 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 88 struct kvm_cpuid_entry2 *entries, 89 int nent) 90 { 91 struct kvm_cpuid_entry2 *best; 92 u64 xfeatures; 93 94 /* 95 * The existing code assumes virtual address is 48-bit or 57-bit in the 96 * canonical address checks; exit if it is ever changed. 97 */ 98 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 99 if (best) { 100 int vaddr_bits = (best->eax & 0xff00) >> 8; 101 102 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 103 return -EINVAL; 104 } 105 106 /* 107 * Exposing dynamic xfeatures to the guest requires additional 108 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 109 */ 110 best = cpuid_entry2_find(entries, nent, 0xd, 0); 111 if (!best) 112 return 0; 113 114 xfeatures = best->eax | ((u64)best->edx << 32); 115 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 116 if (!xfeatures) 117 return 0; 118 119 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 120 } 121 122 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu) 123 { 124 u32 function; 125 struct kvm_cpuid_entry2 *entry; 126 127 vcpu->arch.kvm_cpuid_base = 0; 128 129 for_each_possible_hypervisor_cpuid_base(function) { 130 entry = kvm_find_cpuid_entry(vcpu, function, 0); 131 132 if (entry) { 133 u32 signature[3]; 134 135 signature[0] = entry->ebx; 136 signature[1] = entry->ecx; 137 signature[2] = entry->edx; 138 139 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE)); 140 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) { 141 vcpu->arch.kvm_cpuid_base = function; 142 break; 143 } 144 } 145 } 146 } 147 148 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 149 { 150 u32 base = vcpu->arch.kvm_cpuid_base; 151 152 if (!base) 153 return NULL; 154 155 return kvm_find_cpuid_entry(vcpu, base | KVM_CPUID_FEATURES, 0); 156 } 157 158 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 159 { 160 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 161 162 /* 163 * save the feature bitmap to avoid cpuid lookup for every PV 164 * operation 165 */ 166 if (best) 167 vcpu->arch.pv_cpuid.features = best->eax; 168 } 169 170 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 171 { 172 struct kvm_cpuid_entry2 *best; 173 174 best = kvm_find_cpuid_entry(vcpu, 1, 0); 175 if (best) { 176 /* Update OSXSAVE bit */ 177 if (boot_cpu_has(X86_FEATURE_XSAVE)) 178 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 179 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 180 181 cpuid_entry_change(best, X86_FEATURE_APIC, 182 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 183 } 184 185 best = kvm_find_cpuid_entry(vcpu, 7, 0); 186 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 187 cpuid_entry_change(best, X86_FEATURE_OSPKE, 188 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 189 190 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 191 if (best) 192 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 193 194 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 195 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 196 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 197 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 198 199 best = kvm_find_kvm_cpuid_features(vcpu); 200 if (kvm_hlt_in_guest(vcpu->kvm) && best && 201 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 202 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 203 204 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 205 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 206 if (best) 207 cpuid_entry_change(best, X86_FEATURE_MWAIT, 208 vcpu->arch.ia32_misc_enable_msr & 209 MSR_IA32_MISC_ENABLE_MWAIT); 210 } 211 } 212 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 213 214 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 215 { 216 struct kvm_lapic *apic = vcpu->arch.apic; 217 struct kvm_cpuid_entry2 *best; 218 219 best = kvm_find_cpuid_entry(vcpu, 1, 0); 220 if (best && apic) { 221 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 222 apic->lapic_timer.timer_mode_mask = 3 << 17; 223 else 224 apic->lapic_timer.timer_mode_mask = 1 << 17; 225 226 kvm_apic_set_version(vcpu); 227 } 228 229 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 230 if (!best) 231 vcpu->arch.guest_supported_xcr0 = 0; 232 else 233 vcpu->arch.guest_supported_xcr0 = 234 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 235 236 /* 237 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 238 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 239 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 240 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 241 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 242 * '1' even on CPUs that don't support XSAVE. 243 */ 244 best = kvm_find_cpuid_entry(vcpu, 0x12, 0x1); 245 if (best) { 246 best->ecx &= vcpu->arch.guest_supported_xcr0 & 0xffffffff; 247 best->edx &= vcpu->arch.guest_supported_xcr0 >> 32; 248 best->ecx |= XFEATURE_MASK_FPSSE; 249 } 250 251 kvm_update_pv_runtime(vcpu); 252 253 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 254 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 255 256 kvm_pmu_refresh(vcpu); 257 vcpu->arch.cr4_guest_rsvd_bits = 258 __cr4_reserved_bits(guest_cpuid_has, vcpu); 259 260 kvm_hv_set_cpuid(vcpu); 261 262 /* Invoke the vendor callback only after the above state is updated. */ 263 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 264 265 /* 266 * Except for the MMU, which needs to do its thing any vendor specific 267 * adjustments to the reserved GPA bits. 268 */ 269 kvm_mmu_after_set_cpuid(vcpu); 270 } 271 272 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 273 { 274 struct kvm_cpuid_entry2 *best; 275 276 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 277 if (!best || best->eax < 0x80000008) 278 goto not_found; 279 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 280 if (best) 281 return best->eax & 0xff; 282 not_found: 283 return 36; 284 } 285 286 /* 287 * This "raw" version returns the reserved GPA bits without any adjustments for 288 * encryption technologies that usurp bits. The raw mask should be used if and 289 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 290 */ 291 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 292 { 293 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 294 } 295 296 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 297 int nent) 298 { 299 int r; 300 301 r = kvm_check_cpuid(vcpu, e2, nent); 302 if (r) 303 return r; 304 305 kvfree(vcpu->arch.cpuid_entries); 306 vcpu->arch.cpuid_entries = e2; 307 vcpu->arch.cpuid_nent = nent; 308 309 kvm_update_kvm_cpuid_base(vcpu); 310 kvm_update_cpuid_runtime(vcpu); 311 kvm_vcpu_after_set_cpuid(vcpu); 312 313 return 0; 314 } 315 316 /* when an old userspace process fills a new kernel module */ 317 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 318 struct kvm_cpuid *cpuid, 319 struct kvm_cpuid_entry __user *entries) 320 { 321 int r, i; 322 struct kvm_cpuid_entry *e = NULL; 323 struct kvm_cpuid_entry2 *e2 = NULL; 324 325 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 326 return -E2BIG; 327 328 if (cpuid->nent) { 329 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 330 if (IS_ERR(e)) 331 return PTR_ERR(e); 332 333 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 334 if (!e2) { 335 r = -ENOMEM; 336 goto out_free_cpuid; 337 } 338 } 339 for (i = 0; i < cpuid->nent; i++) { 340 e2[i].function = e[i].function; 341 e2[i].eax = e[i].eax; 342 e2[i].ebx = e[i].ebx; 343 e2[i].ecx = e[i].ecx; 344 e2[i].edx = e[i].edx; 345 e2[i].index = 0; 346 e2[i].flags = 0; 347 e2[i].padding[0] = 0; 348 e2[i].padding[1] = 0; 349 e2[i].padding[2] = 0; 350 } 351 352 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 353 if (r) 354 kvfree(e2); 355 356 out_free_cpuid: 357 kvfree(e); 358 359 return r; 360 } 361 362 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 363 struct kvm_cpuid2 *cpuid, 364 struct kvm_cpuid_entry2 __user *entries) 365 { 366 struct kvm_cpuid_entry2 *e2 = NULL; 367 int r; 368 369 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 370 return -E2BIG; 371 372 if (cpuid->nent) { 373 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 374 if (IS_ERR(e2)) 375 return PTR_ERR(e2); 376 } 377 378 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 379 if (r) 380 kvfree(e2); 381 382 return r; 383 } 384 385 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 386 struct kvm_cpuid2 *cpuid, 387 struct kvm_cpuid_entry2 __user *entries) 388 { 389 int r; 390 391 r = -E2BIG; 392 if (cpuid->nent < vcpu->arch.cpuid_nent) 393 goto out; 394 r = -EFAULT; 395 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 396 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 397 goto out; 398 return 0; 399 400 out: 401 cpuid->nent = vcpu->arch.cpuid_nent; 402 return r; 403 } 404 405 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 406 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 407 { 408 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 409 struct kvm_cpuid_entry2 entry; 410 411 reverse_cpuid_check(leaf); 412 413 cpuid_count(cpuid.function, cpuid.index, 414 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 415 416 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 417 } 418 419 static __always_inline 420 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask) 421 { 422 /* Use kvm_cpu_cap_mask for non-scattered leafs. */ 423 BUILD_BUG_ON(leaf < NCAPINTS); 424 425 kvm_cpu_caps[leaf] = mask; 426 427 __kvm_cpu_cap_mask(leaf); 428 } 429 430 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 431 { 432 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */ 433 BUILD_BUG_ON(leaf >= NCAPINTS); 434 435 kvm_cpu_caps[leaf] &= mask; 436 437 __kvm_cpu_cap_mask(leaf); 438 } 439 440 void kvm_set_cpu_caps(void) 441 { 442 #ifdef CONFIG_X86_64 443 unsigned int f_gbpages = F(GBPAGES); 444 unsigned int f_lm = F(LM); 445 unsigned int f_xfd = F(XFD); 446 #else 447 unsigned int f_gbpages = 0; 448 unsigned int f_lm = 0; 449 unsigned int f_xfd = 0; 450 #endif 451 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 452 453 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 454 sizeof(boot_cpu_data.x86_capability)); 455 456 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 457 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 458 459 kvm_cpu_cap_mask(CPUID_1_ECX, 460 /* 461 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 462 * advertised to guests via CPUID! 463 */ 464 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 465 0 /* DS-CPL, VMX, SMX, EST */ | 466 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 467 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 468 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 469 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 470 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 471 F(F16C) | F(RDRAND) 472 ); 473 /* KVM emulates x2apic in software irrespective of host support. */ 474 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 475 476 kvm_cpu_cap_mask(CPUID_1_EDX, 477 F(FPU) | F(VME) | F(DE) | F(PSE) | 478 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 479 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 480 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 481 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 482 0 /* Reserved, DS, ACPI */ | F(MMX) | 483 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 484 0 /* HTT, TM, Reserved, PBE */ 485 ); 486 487 kvm_cpu_cap_mask(CPUID_7_0_EBX, 488 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 489 F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 490 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 491 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 492 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 493 ); 494 495 kvm_cpu_cap_mask(CPUID_7_ECX, 496 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 497 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 498 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 499 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 500 F(SGX_LC) | F(BUS_LOCK_DETECT) 501 ); 502 /* Set LA57 based on hardware capability. */ 503 if (cpuid_ecx(7) & F(LA57)) 504 kvm_cpu_cap_set(X86_FEATURE_LA57); 505 506 /* 507 * PKU not yet implemented for shadow paging and requires OSPKE 508 * to be set on the host. Clear it if that is not the case 509 */ 510 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 511 kvm_cpu_cap_clear(X86_FEATURE_PKU); 512 513 kvm_cpu_cap_mask(CPUID_7_EDX, 514 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 515 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 516 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 517 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 518 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) 519 ); 520 521 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 522 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 523 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 524 525 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 526 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 527 if (boot_cpu_has(X86_FEATURE_STIBP)) 528 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 529 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 530 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 531 532 kvm_cpu_cap_mask(CPUID_7_1_EAX, 533 F(AVX_VNNI) | F(AVX512_BF16) 534 ); 535 536 kvm_cpu_cap_mask(CPUID_D_1_EAX, 537 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 538 ); 539 540 kvm_cpu_cap_init_scattered(CPUID_12_EAX, 541 SF(SGX1) | SF(SGX2) 542 ); 543 544 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 545 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 546 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 547 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 548 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 549 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 550 ); 551 552 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 553 F(FPU) | F(VME) | F(DE) | F(PSE) | 554 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 555 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 556 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 557 F(PAT) | F(PSE36) | 0 /* Reserved */ | 558 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 559 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 560 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 561 ); 562 563 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 564 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 565 566 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 567 F(CLZERO) | F(XSAVEERPTR) | 568 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 569 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 570 __feature_bit(KVM_X86_FEATURE_PSFD) 571 ); 572 573 /* 574 * AMD has separate bits for each SPEC_CTRL bit. 575 * arch/x86/kernel/cpu/bugs.c is kind enough to 576 * record that in cpufeatures so use them. 577 */ 578 if (boot_cpu_has(X86_FEATURE_IBPB)) 579 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 580 if (boot_cpu_has(X86_FEATURE_IBRS)) 581 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 582 if (boot_cpu_has(X86_FEATURE_STIBP)) 583 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 584 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 585 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 586 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 587 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 588 /* 589 * The preference is to use SPEC CTRL MSR instead of the 590 * VIRT_SPEC MSR. 591 */ 592 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 593 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 594 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 595 596 /* 597 * Hide all SVM features by default, SVM will set the cap bits for 598 * features it emulates and/or exposes for L1. 599 */ 600 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 601 602 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 603 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 604 F(SME_COHERENT)); 605 606 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 607 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 608 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 609 F(PMM) | F(PMM_EN) 610 ); 611 612 /* 613 * Hide RDTSCP and RDPID if either feature is reported as supported but 614 * probing MSR_TSC_AUX failed. This is purely a sanity check and 615 * should never happen, but the guest will likely crash if RDTSCP or 616 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 617 * the past. For example, the sanity check may fire if this instance of 618 * KVM is running as L1 on top of an older, broken KVM. 619 */ 620 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 621 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 622 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 623 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 624 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 625 } 626 } 627 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 628 629 struct kvm_cpuid_array { 630 struct kvm_cpuid_entry2 *entries; 631 int maxnent; 632 int nent; 633 }; 634 635 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 636 u32 function, u32 index) 637 { 638 struct kvm_cpuid_entry2 *entry; 639 640 if (array->nent >= array->maxnent) 641 return NULL; 642 643 entry = &array->entries[array->nent++]; 644 645 entry->function = function; 646 entry->index = index; 647 entry->flags = 0; 648 649 cpuid_count(entry->function, entry->index, 650 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 651 652 switch (function) { 653 case 4: 654 case 7: 655 case 0xb: 656 case 0xd: 657 case 0xf: 658 case 0x10: 659 case 0x12: 660 case 0x14: 661 case 0x17: 662 case 0x18: 663 case 0x1d: 664 case 0x1e: 665 case 0x1f: 666 case 0x8000001d: 667 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 668 break; 669 } 670 671 return entry; 672 } 673 674 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 675 { 676 struct kvm_cpuid_entry2 *entry; 677 678 if (array->nent >= array->maxnent) 679 return -E2BIG; 680 681 entry = &array->entries[array->nent]; 682 entry->function = func; 683 entry->index = 0; 684 entry->flags = 0; 685 686 switch (func) { 687 case 0: 688 entry->eax = 7; 689 ++array->nent; 690 break; 691 case 1: 692 entry->ecx = F(MOVBE); 693 ++array->nent; 694 break; 695 case 7: 696 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 697 entry->eax = 0; 698 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 699 entry->ecx = F(RDPID); 700 ++array->nent; 701 break; 702 default: 703 break; 704 } 705 706 return 0; 707 } 708 709 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 710 { 711 struct kvm_cpuid_entry2 *entry; 712 int r, i, max_idx; 713 714 /* all calls to cpuid_count() should be made on the same cpu */ 715 get_cpu(); 716 717 r = -E2BIG; 718 719 entry = do_host_cpuid(array, function, 0); 720 if (!entry) 721 goto out; 722 723 switch (function) { 724 case 0: 725 /* Limited to the highest leaf implemented in KVM. */ 726 entry->eax = min(entry->eax, 0x1fU); 727 break; 728 case 1: 729 cpuid_entry_override(entry, CPUID_1_EDX); 730 cpuid_entry_override(entry, CPUID_1_ECX); 731 break; 732 case 2: 733 /* 734 * On ancient CPUs, function 2 entries are STATEFUL. That is, 735 * CPUID(function=2, index=0) may return different results each 736 * time, with the least-significant byte in EAX enumerating the 737 * number of times software should do CPUID(2, 0). 738 * 739 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 740 * idiotic. Intel's SDM states that EAX & 0xff "will always 741 * return 01H. Software should ignore this value and not 742 * interpret it as an informational descriptor", while AMD's 743 * APM states that CPUID(2) is reserved. 744 * 745 * WARN if a frankenstein CPU that supports virtualization and 746 * a stateful CPUID.0x2 is encountered. 747 */ 748 WARN_ON_ONCE((entry->eax & 0xff) > 1); 749 break; 750 /* functions 4 and 0x8000001d have additional index. */ 751 case 4: 752 case 0x8000001d: 753 /* 754 * Read entries until the cache type in the previous entry is 755 * zero, i.e. indicates an invalid entry. 756 */ 757 for (i = 1; entry->eax & 0x1f; ++i) { 758 entry = do_host_cpuid(array, function, i); 759 if (!entry) 760 goto out; 761 } 762 break; 763 case 6: /* Thermal management */ 764 entry->eax = 0x4; /* allow ARAT */ 765 entry->ebx = 0; 766 entry->ecx = 0; 767 entry->edx = 0; 768 break; 769 /* function 7 has additional index. */ 770 case 7: 771 entry->eax = min(entry->eax, 1u); 772 cpuid_entry_override(entry, CPUID_7_0_EBX); 773 cpuid_entry_override(entry, CPUID_7_ECX); 774 cpuid_entry_override(entry, CPUID_7_EDX); 775 776 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 777 if (entry->eax == 1) { 778 entry = do_host_cpuid(array, function, 1); 779 if (!entry) 780 goto out; 781 782 cpuid_entry_override(entry, CPUID_7_1_EAX); 783 entry->ebx = 0; 784 entry->ecx = 0; 785 entry->edx = 0; 786 } 787 break; 788 case 9: 789 break; 790 case 0xa: { /* Architectural Performance Monitoring */ 791 struct x86_pmu_capability cap; 792 union cpuid10_eax eax; 793 union cpuid10_edx edx; 794 795 perf_get_x86_pmu_capability(&cap); 796 797 /* 798 * Only support guest architectural pmu on a host 799 * with architectural pmu. 800 */ 801 if (!cap.version) 802 memset(&cap, 0, sizeof(cap)); 803 804 eax.split.version_id = min(cap.version, 2); 805 eax.split.num_counters = cap.num_counters_gp; 806 eax.split.bit_width = cap.bit_width_gp; 807 eax.split.mask_length = cap.events_mask_len; 808 809 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 810 edx.split.bit_width_fixed = cap.bit_width_fixed; 811 if (cap.version) 812 edx.split.anythread_deprecated = 1; 813 edx.split.reserved1 = 0; 814 edx.split.reserved2 = 0; 815 816 entry->eax = eax.full; 817 entry->ebx = cap.events_mask; 818 entry->ecx = 0; 819 entry->edx = edx.full; 820 break; 821 } 822 /* 823 * Per Intel's SDM, the 0x1f is a superset of 0xb, 824 * thus they can be handled by common code. 825 */ 826 case 0x1f: 827 case 0xb: 828 /* 829 * Populate entries until the level type (ECX[15:8]) of the 830 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 831 * the starting entry, filled by the primary do_host_cpuid(). 832 */ 833 for (i = 1; entry->ecx & 0xff00; ++i) { 834 entry = do_host_cpuid(array, function, i); 835 if (!entry) 836 goto out; 837 } 838 break; 839 case 0xd: { 840 u64 guest_perm = xstate_get_guest_group_perm(); 841 842 entry->eax &= supported_xcr0 & guest_perm; 843 entry->ebx = xstate_required_size(supported_xcr0, false); 844 entry->ecx = entry->ebx; 845 entry->edx &= (supported_xcr0 & guest_perm) >> 32; 846 if (!supported_xcr0) 847 break; 848 849 entry = do_host_cpuid(array, function, 1); 850 if (!entry) 851 goto out; 852 853 cpuid_entry_override(entry, CPUID_D_1_EAX); 854 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 855 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 856 true); 857 else { 858 WARN_ON_ONCE(supported_xss != 0); 859 entry->ebx = 0; 860 } 861 entry->ecx &= supported_xss; 862 entry->edx &= supported_xss >> 32; 863 864 for (i = 2; i < 64; ++i) { 865 bool s_state; 866 if (supported_xcr0 & BIT_ULL(i)) 867 s_state = false; 868 else if (supported_xss & BIT_ULL(i)) 869 s_state = true; 870 else 871 continue; 872 873 entry = do_host_cpuid(array, function, i); 874 if (!entry) 875 goto out; 876 877 /* 878 * The supported check above should have filtered out 879 * invalid sub-leafs. Only valid sub-leafs should 880 * reach this point, and they should have a non-zero 881 * save state size. Furthermore, check whether the 882 * processor agrees with supported_xcr0/supported_xss 883 * on whether this is an XCR0- or IA32_XSS-managed area. 884 */ 885 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 886 --array->nent; 887 continue; 888 } 889 entry->edx = 0; 890 } 891 break; 892 } 893 case 0x12: 894 /* Intel SGX */ 895 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 896 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 897 break; 898 } 899 900 /* 901 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 902 * and max enclave sizes. The SGX sub-features and MISCSELECT 903 * are restricted by kernel and KVM capabilities (like most 904 * feature flags), while enclave size is unrestricted. 905 */ 906 cpuid_entry_override(entry, CPUID_12_EAX); 907 entry->ebx &= SGX_MISC_EXINFO; 908 909 entry = do_host_cpuid(array, function, 1); 910 if (!entry) 911 goto out; 912 913 /* 914 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 915 * feature flags. Advertise all supported flags, including 916 * privileged attributes that require explicit opt-in from 917 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 918 * expected to derive it from supported XCR0. 919 */ 920 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | 921 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY | 922 SGX_ATTR_KSS; 923 entry->ebx &= 0; 924 break; 925 /* Intel PT */ 926 case 0x14: 927 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 928 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 929 break; 930 } 931 932 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 933 if (!do_host_cpuid(array, function, i)) 934 goto out; 935 } 936 break; 937 /* Intel AMX TILE */ 938 case 0x1d: 939 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 940 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 941 break; 942 } 943 944 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 945 if (!do_host_cpuid(array, function, i)) 946 goto out; 947 } 948 break; 949 case 0x1e: /* TMUL information */ 950 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 951 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 952 break; 953 } 954 break; 955 case KVM_CPUID_SIGNATURE: { 956 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 957 entry->eax = KVM_CPUID_FEATURES; 958 entry->ebx = sigptr[0]; 959 entry->ecx = sigptr[1]; 960 entry->edx = sigptr[2]; 961 break; 962 } 963 case KVM_CPUID_FEATURES: 964 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 965 (1 << KVM_FEATURE_NOP_IO_DELAY) | 966 (1 << KVM_FEATURE_CLOCKSOURCE2) | 967 (1 << KVM_FEATURE_ASYNC_PF) | 968 (1 << KVM_FEATURE_PV_EOI) | 969 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 970 (1 << KVM_FEATURE_PV_UNHALT) | 971 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 972 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 973 (1 << KVM_FEATURE_PV_SEND_IPI) | 974 (1 << KVM_FEATURE_POLL_CONTROL) | 975 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 976 (1 << KVM_FEATURE_ASYNC_PF_INT); 977 978 if (sched_info_on()) 979 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 980 981 entry->ebx = 0; 982 entry->ecx = 0; 983 entry->edx = 0; 984 break; 985 case 0x80000000: 986 entry->eax = min(entry->eax, 0x8000001f); 987 break; 988 case 0x80000001: 989 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 990 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 991 break; 992 case 0x80000006: 993 /* L2 cache and TLB: pass through host info. */ 994 break; 995 case 0x80000007: /* Advanced power management */ 996 /* invariant TSC is CPUID.80000007H:EDX[8] */ 997 entry->edx &= (1 << 8); 998 /* mask against host */ 999 entry->edx &= boot_cpu_data.x86_power; 1000 entry->eax = entry->ebx = entry->ecx = 0; 1001 break; 1002 case 0x80000008: { 1003 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1004 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1005 unsigned phys_as = entry->eax & 0xff; 1006 1007 /* 1008 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1009 * the guest operates in the same PA space as the host, i.e. 1010 * reductions in MAXPHYADDR for memory encryption affect shadow 1011 * paging, too. 1012 * 1013 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1014 * provided, use the raw bare metal MAXPHYADDR as reductions to 1015 * the HPAs do not affect GPAs. 1016 */ 1017 if (!tdp_enabled) 1018 g_phys_as = boot_cpu_data.x86_phys_bits; 1019 else if (!g_phys_as) 1020 g_phys_as = phys_as; 1021 1022 entry->eax = g_phys_as | (virt_as << 8); 1023 entry->edx = 0; 1024 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1025 break; 1026 } 1027 case 0x8000000A: 1028 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1029 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1030 break; 1031 } 1032 entry->eax = 1; /* SVM revision 1 */ 1033 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1034 ASID emulation to nested SVM */ 1035 entry->ecx = 0; /* Reserved */ 1036 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1037 break; 1038 case 0x80000019: 1039 entry->ecx = entry->edx = 0; 1040 break; 1041 case 0x8000001a: 1042 case 0x8000001e: 1043 break; 1044 case 0x8000001F: 1045 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1046 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1047 } else { 1048 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1049 1050 /* 1051 * Enumerate '0' for "PA bits reduction", the adjusted 1052 * MAXPHYADDR is enumerated directly (see 0x80000008). 1053 */ 1054 entry->ebx &= ~GENMASK(11, 6); 1055 } 1056 break; 1057 /*Add support for Centaur's CPUID instruction*/ 1058 case 0xC0000000: 1059 /*Just support up to 0xC0000004 now*/ 1060 entry->eax = min(entry->eax, 0xC0000004); 1061 break; 1062 case 0xC0000001: 1063 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1064 break; 1065 case 3: /* Processor serial number */ 1066 case 5: /* MONITOR/MWAIT */ 1067 case 0xC0000002: 1068 case 0xC0000003: 1069 case 0xC0000004: 1070 default: 1071 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1072 break; 1073 } 1074 1075 r = 0; 1076 1077 out: 1078 put_cpu(); 1079 1080 return r; 1081 } 1082 1083 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1084 unsigned int type) 1085 { 1086 if (type == KVM_GET_EMULATED_CPUID) 1087 return __do_cpuid_func_emulated(array, func); 1088 1089 return __do_cpuid_func(array, func); 1090 } 1091 1092 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1093 1094 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1095 unsigned int type) 1096 { 1097 u32 limit; 1098 int r; 1099 1100 if (func == CENTAUR_CPUID_SIGNATURE && 1101 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1102 return 0; 1103 1104 r = do_cpuid_func(array, func, type); 1105 if (r) 1106 return r; 1107 1108 limit = array->entries[array->nent - 1].eax; 1109 for (func = func + 1; func <= limit; ++func) { 1110 r = do_cpuid_func(array, func, type); 1111 if (r) 1112 break; 1113 } 1114 1115 return r; 1116 } 1117 1118 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1119 __u32 num_entries, unsigned int ioctl_type) 1120 { 1121 int i; 1122 __u32 pad[3]; 1123 1124 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1125 return false; 1126 1127 /* 1128 * We want to make sure that ->padding is being passed clean from 1129 * userspace in case we want to use it for something in the future. 1130 * 1131 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1132 * have to give ourselves satisfied only with the emulated side. /me 1133 * sheds a tear. 1134 */ 1135 for (i = 0; i < num_entries; i++) { 1136 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1137 return true; 1138 1139 if (pad[0] || pad[1] || pad[2]) 1140 return true; 1141 } 1142 return false; 1143 } 1144 1145 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1146 struct kvm_cpuid_entry2 __user *entries, 1147 unsigned int type) 1148 { 1149 static const u32 funcs[] = { 1150 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1151 }; 1152 1153 struct kvm_cpuid_array array = { 1154 .nent = 0, 1155 }; 1156 int r, i; 1157 1158 if (cpuid->nent < 1) 1159 return -E2BIG; 1160 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1161 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1162 1163 if (sanity_check_entries(entries, cpuid->nent, type)) 1164 return -EINVAL; 1165 1166 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 1167 cpuid->nent)); 1168 if (!array.entries) 1169 return -ENOMEM; 1170 1171 array.maxnent = cpuid->nent; 1172 1173 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1174 r = get_cpuid_func(&array, funcs[i], type); 1175 if (r) 1176 goto out_free; 1177 } 1178 cpuid->nent = array.nent; 1179 1180 if (copy_to_user(entries, array.entries, 1181 array.nent * sizeof(struct kvm_cpuid_entry2))) 1182 r = -EFAULT; 1183 1184 out_free: 1185 vfree(array.entries); 1186 return r; 1187 } 1188 1189 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1190 u32 function, u32 index) 1191 { 1192 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1193 function, index); 1194 } 1195 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1196 1197 /* 1198 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1199 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1200 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1201 * range. Centaur/VIA follows Intel semantics. 1202 * 1203 * A leaf is considered out-of-range if its function is higher than the maximum 1204 * supported leaf of its associated class or if its associated class does not 1205 * exist. 1206 * 1207 * There are three primary classes to be considered, with their respective 1208 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1209 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1210 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1211 * 1212 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1213 * - Hypervisor: 0x40000000 - 0x4fffffff 1214 * - Extended: 0x80000000 - 0xbfffffff 1215 * - Centaur: 0xc0000000 - 0xcfffffff 1216 * 1217 * The Hypervisor class is further subdivided into sub-classes that each act as 1218 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1219 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1220 * CPUID sub-classes are: 1221 * 1222 * - HyperV: 0x40000000 - 0x400000ff 1223 * - KVM: 0x40000100 - 0x400001ff 1224 */ 1225 static struct kvm_cpuid_entry2 * 1226 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1227 { 1228 struct kvm_cpuid_entry2 *basic, *class; 1229 u32 function = *fn_ptr; 1230 1231 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1232 if (!basic) 1233 return NULL; 1234 1235 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1236 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1237 return NULL; 1238 1239 if (function >= 0x40000000 && function <= 0x4fffffff) 1240 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1241 else if (function >= 0xc0000000) 1242 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1243 else 1244 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1245 1246 if (class && function <= class->eax) 1247 return NULL; 1248 1249 /* 1250 * Leaf specific adjustments are also applied when redirecting to the 1251 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1252 * entry for CPUID.0xb.index (see below), then the output value for EDX 1253 * needs to be pulled from CPUID.0xb.1. 1254 */ 1255 *fn_ptr = basic->eax; 1256 1257 /* 1258 * The class does not exist or the requested function is out of range; 1259 * the effective CPUID entry is the max basic leaf. Note, the index of 1260 * the original requested leaf is observed! 1261 */ 1262 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1263 } 1264 1265 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1266 u32 *ecx, u32 *edx, bool exact_only) 1267 { 1268 u32 orig_function = *eax, function = *eax, index = *ecx; 1269 struct kvm_cpuid_entry2 *entry; 1270 bool exact, used_max_basic = false; 1271 1272 entry = kvm_find_cpuid_entry(vcpu, function, index); 1273 exact = !!entry; 1274 1275 if (!entry && !exact_only) { 1276 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1277 used_max_basic = !!entry; 1278 } 1279 1280 if (entry) { 1281 *eax = entry->eax; 1282 *ebx = entry->ebx; 1283 *ecx = entry->ecx; 1284 *edx = entry->edx; 1285 if (function == 7 && index == 0) { 1286 u64 data; 1287 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1288 (data & TSX_CTRL_CPUID_CLEAR)) 1289 *ebx &= ~(F(RTM) | F(HLE)); 1290 } 1291 } else { 1292 *eax = *ebx = *ecx = *edx = 0; 1293 /* 1294 * When leaf 0BH or 1FH is defined, CL is pass-through 1295 * and EDX is always the x2APIC ID, even for undefined 1296 * subleaves. Index 1 will exist iff the leaf is 1297 * implemented, so we pass through CL iff leaf 1 1298 * exists. EDX can be copied from any existing index. 1299 */ 1300 if (function == 0xb || function == 0x1f) { 1301 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1302 if (entry) { 1303 *ecx = index & 0xff; 1304 *edx = entry->edx; 1305 } 1306 } 1307 } 1308 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1309 used_max_basic); 1310 return exact; 1311 } 1312 EXPORT_SYMBOL_GPL(kvm_cpuid); 1313 1314 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1315 { 1316 u32 eax, ebx, ecx, edx; 1317 1318 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1319 return 1; 1320 1321 eax = kvm_rax_read(vcpu); 1322 ecx = kvm_rcx_read(vcpu); 1323 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1324 kvm_rax_write(vcpu, eax); 1325 kvm_rbx_write(vcpu, ebx); 1326 kvm_rcx_write(vcpu, ecx); 1327 kvm_rdx_write(vcpu, edx); 1328 return kvm_skip_emulated_instruction(vcpu); 1329 } 1330 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1331