1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include <asm/sgx.h> 22 #include "cpuid.h" 23 #include "lapic.h" 24 #include "mmu.h" 25 #include "trace.h" 26 #include "pmu.h" 27 28 /* 29 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 30 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 31 */ 32 u32 kvm_cpu_caps[NR_KVM_CPU_CAPS] __read_mostly; 33 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 34 35 u32 xstate_required_size(u64 xstate_bv, bool compacted) 36 { 37 int feature_bit = 0; 38 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 39 40 xstate_bv &= XFEATURE_MASK_EXTEND; 41 while (xstate_bv) { 42 if (xstate_bv & 0x1) { 43 u32 eax, ebx, ecx, edx, offset; 44 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 45 /* ECX[1]: 64B alignment in compacted form */ 46 if (compacted) 47 offset = (ecx & 0x2) ? ALIGN(ret, 64) : ret; 48 else 49 offset = ebx; 50 ret = max(ret, offset + eax); 51 } 52 53 xstate_bv >>= 1; 54 feature_bit++; 55 } 56 57 return ret; 58 } 59 60 /* 61 * This one is tied to SSB in the user API, and not 62 * visible in /proc/cpuinfo. 63 */ 64 #define KVM_X86_FEATURE_PSFD (13*32+28) /* Predictive Store Forwarding Disable */ 65 66 #define F feature_bit 67 #define SF(name) (boot_cpu_has(X86_FEATURE_##name) ? F(name) : 0) 68 69 70 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 71 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 72 { 73 struct kvm_cpuid_entry2 *e; 74 int i; 75 76 for (i = 0; i < nent; i++) { 77 e = &entries[i]; 78 79 if (e->function == function && 80 (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index)) 81 return e; 82 } 83 84 return NULL; 85 } 86 87 static int kvm_check_cpuid(struct kvm_vcpu *vcpu, 88 struct kvm_cpuid_entry2 *entries, 89 int nent) 90 { 91 struct kvm_cpuid_entry2 *best; 92 u64 xfeatures; 93 94 /* 95 * The existing code assumes virtual address is 48-bit or 57-bit in the 96 * canonical address checks; exit if it is ever changed. 97 */ 98 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 99 if (best) { 100 int vaddr_bits = (best->eax & 0xff00) >> 8; 101 102 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 103 return -EINVAL; 104 } 105 106 /* 107 * Exposing dynamic xfeatures to the guest requires additional 108 * enabling in the FPU, e.g. to expand the guest XSAVE state size. 109 */ 110 best = cpuid_entry2_find(entries, nent, 0xd, 0); 111 if (!best) 112 return 0; 113 114 xfeatures = best->eax | ((u64)best->edx << 32); 115 xfeatures &= XFEATURE_MASK_USER_DYNAMIC; 116 if (!xfeatures) 117 return 0; 118 119 return fpu_enable_guest_xfd_features(&vcpu->arch.guest_fpu, xfeatures); 120 } 121 122 /* Check whether the supplied CPUID data is equal to what is already set for the vCPU. */ 123 static int kvm_cpuid_check_equal(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 124 int nent) 125 { 126 struct kvm_cpuid_entry2 *orig; 127 int i; 128 129 if (nent != vcpu->arch.cpuid_nent) 130 return -EINVAL; 131 132 for (i = 0; i < nent; i++) { 133 orig = &vcpu->arch.cpuid_entries[i]; 134 if (e2[i].function != orig->function || 135 e2[i].index != orig->index || 136 e2[i].eax != orig->eax || e2[i].ebx != orig->ebx || 137 e2[i].ecx != orig->ecx || e2[i].edx != orig->edx) 138 return -EINVAL; 139 } 140 141 return 0; 142 } 143 144 static void kvm_update_kvm_cpuid_base(struct kvm_vcpu *vcpu) 145 { 146 u32 function; 147 struct kvm_cpuid_entry2 *entry; 148 149 vcpu->arch.kvm_cpuid_base = 0; 150 151 for_each_possible_hypervisor_cpuid_base(function) { 152 entry = kvm_find_cpuid_entry(vcpu, function, 0); 153 154 if (entry) { 155 u32 signature[3]; 156 157 signature[0] = entry->ebx; 158 signature[1] = entry->ecx; 159 signature[2] = entry->edx; 160 161 BUILD_BUG_ON(sizeof(signature) > sizeof(KVM_SIGNATURE)); 162 if (!memcmp(signature, KVM_SIGNATURE, sizeof(signature))) { 163 vcpu->arch.kvm_cpuid_base = function; 164 break; 165 } 166 } 167 } 168 } 169 170 static struct kvm_cpuid_entry2 *__kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu, 171 struct kvm_cpuid_entry2 *entries, int nent) 172 { 173 u32 base = vcpu->arch.kvm_cpuid_base; 174 175 if (!base) 176 return NULL; 177 178 return cpuid_entry2_find(entries, nent, base | KVM_CPUID_FEATURES, 0); 179 } 180 181 static struct kvm_cpuid_entry2 *kvm_find_kvm_cpuid_features(struct kvm_vcpu *vcpu) 182 { 183 return __kvm_find_kvm_cpuid_features(vcpu, vcpu->arch.cpuid_entries, 184 vcpu->arch.cpuid_nent); 185 } 186 187 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 188 { 189 struct kvm_cpuid_entry2 *best = kvm_find_kvm_cpuid_features(vcpu); 190 191 /* 192 * save the feature bitmap to avoid cpuid lookup for every PV 193 * operation 194 */ 195 if (best) 196 vcpu->arch.pv_cpuid.features = best->eax; 197 } 198 199 static void __kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *entries, 200 int nent) 201 { 202 struct kvm_cpuid_entry2 *best; 203 204 best = cpuid_entry2_find(entries, nent, 1, 0); 205 if (best) { 206 /* Update OSXSAVE bit */ 207 if (boot_cpu_has(X86_FEATURE_XSAVE)) 208 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 209 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 210 211 cpuid_entry_change(best, X86_FEATURE_APIC, 212 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 213 } 214 215 best = cpuid_entry2_find(entries, nent, 7, 0); 216 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 217 cpuid_entry_change(best, X86_FEATURE_OSPKE, 218 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 219 220 best = cpuid_entry2_find(entries, nent, 0xD, 0); 221 if (best) 222 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 223 224 best = cpuid_entry2_find(entries, nent, 0xD, 1); 225 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 226 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 227 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 228 229 best = __kvm_find_kvm_cpuid_features(vcpu, entries, nent); 230 if (kvm_hlt_in_guest(vcpu->kvm) && best && 231 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 232 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 233 234 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 235 best = cpuid_entry2_find(entries, nent, 0x1, 0); 236 if (best) 237 cpuid_entry_change(best, X86_FEATURE_MWAIT, 238 vcpu->arch.ia32_misc_enable_msr & 239 MSR_IA32_MISC_ENABLE_MWAIT); 240 } 241 } 242 243 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 244 { 245 __kvm_update_cpuid_runtime(vcpu, vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent); 246 } 247 EXPORT_SYMBOL_GPL(kvm_update_cpuid_runtime); 248 249 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 250 { 251 struct kvm_lapic *apic = vcpu->arch.apic; 252 struct kvm_cpuid_entry2 *best; 253 254 best = kvm_find_cpuid_entry(vcpu, 1, 0); 255 if (best && apic) { 256 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 257 apic->lapic_timer.timer_mode_mask = 3 << 17; 258 else 259 apic->lapic_timer.timer_mode_mask = 1 << 17; 260 261 kvm_apic_set_version(vcpu); 262 } 263 264 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 265 if (!best) 266 vcpu->arch.guest_supported_xcr0 = 0; 267 else 268 vcpu->arch.guest_supported_xcr0 = 269 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 270 271 /* 272 * Bits 127:0 of the allowed SECS.ATTRIBUTES (CPUID.0x12.0x1) enumerate 273 * the supported XSAVE Feature Request Mask (XFRM), i.e. the enclave's 274 * requested XCR0 value. The enclave's XFRM must be a subset of XCRO 275 * at the time of EENTER, thus adjust the allowed XFRM by the guest's 276 * supported XCR0. Similar to XCR0 handling, FP and SSE are forced to 277 * '1' even on CPUs that don't support XSAVE. 278 */ 279 best = kvm_find_cpuid_entry(vcpu, 0x12, 0x1); 280 if (best) { 281 best->ecx &= vcpu->arch.guest_supported_xcr0 & 0xffffffff; 282 best->edx &= vcpu->arch.guest_supported_xcr0 >> 32; 283 best->ecx |= XFEATURE_MASK_FPSSE; 284 } 285 286 kvm_update_pv_runtime(vcpu); 287 288 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 289 vcpu->arch.reserved_gpa_bits = kvm_vcpu_reserved_gpa_bits_raw(vcpu); 290 291 kvm_pmu_refresh(vcpu); 292 vcpu->arch.cr4_guest_rsvd_bits = 293 __cr4_reserved_bits(guest_cpuid_has, vcpu); 294 295 kvm_hv_set_cpuid(vcpu); 296 297 /* Invoke the vendor callback only after the above state is updated. */ 298 static_call(kvm_x86_vcpu_after_set_cpuid)(vcpu); 299 300 /* 301 * Except for the MMU, which needs to do its thing any vendor specific 302 * adjustments to the reserved GPA bits. 303 */ 304 kvm_mmu_after_set_cpuid(vcpu); 305 } 306 307 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 308 { 309 struct kvm_cpuid_entry2 *best; 310 311 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 312 if (!best || best->eax < 0x80000008) 313 goto not_found; 314 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 315 if (best) 316 return best->eax & 0xff; 317 not_found: 318 return 36; 319 } 320 321 /* 322 * This "raw" version returns the reserved GPA bits without any adjustments for 323 * encryption technologies that usurp bits. The raw mask should be used if and 324 * only if hardware does _not_ strip the usurped bits, e.g. in virtual MTRRs. 325 */ 326 u64 kvm_vcpu_reserved_gpa_bits_raw(struct kvm_vcpu *vcpu) 327 { 328 return rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 329 } 330 331 static int kvm_set_cpuid(struct kvm_vcpu *vcpu, struct kvm_cpuid_entry2 *e2, 332 int nent) 333 { 334 int r; 335 336 __kvm_update_cpuid_runtime(vcpu, e2, nent); 337 338 /* 339 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as 340 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't 341 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page 342 * faults due to reusing SPs/SPTEs. In practice no sane VMM mucks with 343 * the core vCPU model on the fly. It would've been better to forbid any 344 * KVM_SET_CPUID{,2} calls after KVM_RUN altogether but unfortunately 345 * some VMMs (e.g. QEMU) reuse vCPU fds for CPU hotplug/unplug and do 346 * KVM_SET_CPUID{,2} again. To support this legacy behavior, check 347 * whether the supplied CPUID data is equal to what's already set. 348 */ 349 if (vcpu->arch.last_vmentry_cpu != -1) 350 return kvm_cpuid_check_equal(vcpu, e2, nent); 351 352 r = kvm_check_cpuid(vcpu, e2, nent); 353 if (r) 354 return r; 355 356 kvfree(vcpu->arch.cpuid_entries); 357 vcpu->arch.cpuid_entries = e2; 358 vcpu->arch.cpuid_nent = nent; 359 360 kvm_update_kvm_cpuid_base(vcpu); 361 kvm_vcpu_after_set_cpuid(vcpu); 362 363 return 0; 364 } 365 366 /* when an old userspace process fills a new kernel module */ 367 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 368 struct kvm_cpuid *cpuid, 369 struct kvm_cpuid_entry __user *entries) 370 { 371 int r, i; 372 struct kvm_cpuid_entry *e = NULL; 373 struct kvm_cpuid_entry2 *e2 = NULL; 374 375 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 376 return -E2BIG; 377 378 if (cpuid->nent) { 379 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 380 if (IS_ERR(e)) 381 return PTR_ERR(e); 382 383 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 384 if (!e2) { 385 r = -ENOMEM; 386 goto out_free_cpuid; 387 } 388 } 389 for (i = 0; i < cpuid->nent; i++) { 390 e2[i].function = e[i].function; 391 e2[i].eax = e[i].eax; 392 e2[i].ebx = e[i].ebx; 393 e2[i].ecx = e[i].ecx; 394 e2[i].edx = e[i].edx; 395 e2[i].index = 0; 396 e2[i].flags = 0; 397 e2[i].padding[0] = 0; 398 e2[i].padding[1] = 0; 399 e2[i].padding[2] = 0; 400 } 401 402 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 403 if (r) 404 kvfree(e2); 405 406 out_free_cpuid: 407 kvfree(e); 408 409 return r; 410 } 411 412 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 413 struct kvm_cpuid2 *cpuid, 414 struct kvm_cpuid_entry2 __user *entries) 415 { 416 struct kvm_cpuid_entry2 *e2 = NULL; 417 int r; 418 419 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 420 return -E2BIG; 421 422 if (cpuid->nent) { 423 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 424 if (IS_ERR(e2)) 425 return PTR_ERR(e2); 426 } 427 428 r = kvm_set_cpuid(vcpu, e2, cpuid->nent); 429 if (r) 430 kvfree(e2); 431 432 return r; 433 } 434 435 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 436 struct kvm_cpuid2 *cpuid, 437 struct kvm_cpuid_entry2 __user *entries) 438 { 439 int r; 440 441 r = -E2BIG; 442 if (cpuid->nent < vcpu->arch.cpuid_nent) 443 goto out; 444 r = -EFAULT; 445 if (copy_to_user(entries, vcpu->arch.cpuid_entries, 446 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 447 goto out; 448 return 0; 449 450 out: 451 cpuid->nent = vcpu->arch.cpuid_nent; 452 return r; 453 } 454 455 /* Mask kvm_cpu_caps for @leaf with the raw CPUID capabilities of this CPU. */ 456 static __always_inline void __kvm_cpu_cap_mask(unsigned int leaf) 457 { 458 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 459 struct kvm_cpuid_entry2 entry; 460 461 reverse_cpuid_check(leaf); 462 463 cpuid_count(cpuid.function, cpuid.index, 464 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 465 466 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 467 } 468 469 static __always_inline 470 void kvm_cpu_cap_init_scattered(enum kvm_only_cpuid_leafs leaf, u32 mask) 471 { 472 /* Use kvm_cpu_cap_mask for non-scattered leafs. */ 473 BUILD_BUG_ON(leaf < NCAPINTS); 474 475 kvm_cpu_caps[leaf] = mask; 476 477 __kvm_cpu_cap_mask(leaf); 478 } 479 480 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 481 { 482 /* Use kvm_cpu_cap_init_scattered for scattered leafs. */ 483 BUILD_BUG_ON(leaf >= NCAPINTS); 484 485 kvm_cpu_caps[leaf] &= mask; 486 487 __kvm_cpu_cap_mask(leaf); 488 } 489 490 void kvm_set_cpu_caps(void) 491 { 492 #ifdef CONFIG_X86_64 493 unsigned int f_gbpages = F(GBPAGES); 494 unsigned int f_lm = F(LM); 495 unsigned int f_xfd = F(XFD); 496 #else 497 unsigned int f_gbpages = 0; 498 unsigned int f_lm = 0; 499 unsigned int f_xfd = 0; 500 #endif 501 memset(kvm_cpu_caps, 0, sizeof(kvm_cpu_caps)); 502 503 BUILD_BUG_ON(sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps)) > 504 sizeof(boot_cpu_data.x86_capability)); 505 506 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 507 sizeof(kvm_cpu_caps) - (NKVMCAPINTS * sizeof(*kvm_cpu_caps))); 508 509 kvm_cpu_cap_mask(CPUID_1_ECX, 510 /* 511 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 512 * advertised to guests via CPUID! 513 */ 514 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 515 0 /* DS-CPL, VMX, SMX, EST */ | 516 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 517 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 518 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 519 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 520 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 521 F(F16C) | F(RDRAND) 522 ); 523 /* KVM emulates x2apic in software irrespective of host support. */ 524 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 525 526 kvm_cpu_cap_mask(CPUID_1_EDX, 527 F(FPU) | F(VME) | F(DE) | F(PSE) | 528 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 529 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 530 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 531 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 532 0 /* Reserved, DS, ACPI */ | F(MMX) | 533 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 534 0 /* HTT, TM, Reserved, PBE */ 535 ); 536 537 kvm_cpu_cap_mask(CPUID_7_0_EBX, 538 F(FSGSBASE) | F(SGX) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 539 F(BMI2) | F(ERMS) | F(INVPCID) | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 540 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 541 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 542 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 543 ); 544 545 kvm_cpu_cap_mask(CPUID_7_ECX, 546 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 547 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 548 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 549 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ | 550 F(SGX_LC) | F(BUS_LOCK_DETECT) 551 ); 552 /* Set LA57 based on hardware capability. */ 553 if (cpuid_ecx(7) & F(LA57)) 554 kvm_cpu_cap_set(X86_FEATURE_LA57); 555 556 /* 557 * PKU not yet implemented for shadow paging and requires OSPKE 558 * to be set on the host. Clear it if that is not the case 559 */ 560 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 561 kvm_cpu_cap_clear(X86_FEATURE_PKU); 562 563 kvm_cpu_cap_mask(CPUID_7_EDX, 564 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 565 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 566 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 567 F(SERIALIZE) | F(TSXLDTRK) | F(AVX512_FP16) | 568 F(AMX_TILE) | F(AMX_INT8) | F(AMX_BF16) 569 ); 570 571 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 572 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 573 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 574 575 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 576 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 577 if (boot_cpu_has(X86_FEATURE_STIBP)) 578 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 579 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 580 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 581 582 kvm_cpu_cap_mask(CPUID_7_1_EAX, 583 F(AVX_VNNI) | F(AVX512_BF16) 584 ); 585 586 kvm_cpu_cap_mask(CPUID_D_1_EAX, 587 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) | f_xfd 588 ); 589 590 kvm_cpu_cap_init_scattered(CPUID_12_EAX, 591 SF(SGX1) | SF(SGX2) 592 ); 593 594 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 595 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 596 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 597 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 598 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 599 F(TOPOEXT) | 0 /* PERFCTR_CORE */ 600 ); 601 602 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 603 F(FPU) | F(VME) | F(DE) | F(PSE) | 604 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 605 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 606 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 607 F(PAT) | F(PSE36) | 0 /* Reserved */ | 608 F(NX) | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 609 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 610 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 611 ); 612 613 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 614 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 615 616 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 617 F(CLZERO) | F(XSAVEERPTR) | 618 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 619 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) | 620 __feature_bit(KVM_X86_FEATURE_PSFD) 621 ); 622 623 /* 624 * AMD has separate bits for each SPEC_CTRL bit. 625 * arch/x86/kernel/cpu/bugs.c is kind enough to 626 * record that in cpufeatures so use them. 627 */ 628 if (boot_cpu_has(X86_FEATURE_IBPB)) 629 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 630 if (boot_cpu_has(X86_FEATURE_IBRS)) 631 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 632 if (boot_cpu_has(X86_FEATURE_STIBP)) 633 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 634 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 635 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 636 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 637 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 638 /* 639 * The preference is to use SPEC CTRL MSR instead of the 640 * VIRT_SPEC MSR. 641 */ 642 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 643 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 644 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 645 646 /* 647 * Hide all SVM features by default, SVM will set the cap bits for 648 * features it emulates and/or exposes for L1. 649 */ 650 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 651 652 kvm_cpu_cap_mask(CPUID_8000_001F_EAX, 653 0 /* SME */ | F(SEV) | 0 /* VM_PAGE_FLUSH */ | F(SEV_ES) | 654 F(SME_COHERENT)); 655 656 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 657 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 658 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 659 F(PMM) | F(PMM_EN) 660 ); 661 662 /* 663 * Hide RDTSCP and RDPID if either feature is reported as supported but 664 * probing MSR_TSC_AUX failed. This is purely a sanity check and 665 * should never happen, but the guest will likely crash if RDTSCP or 666 * RDPID is misreported, and KVM has botched MSR_TSC_AUX emulation in 667 * the past. For example, the sanity check may fire if this instance of 668 * KVM is running as L1 on top of an older, broken KVM. 669 */ 670 if (WARN_ON((kvm_cpu_cap_has(X86_FEATURE_RDTSCP) || 671 kvm_cpu_cap_has(X86_FEATURE_RDPID)) && 672 !kvm_is_supported_user_return_msr(MSR_TSC_AUX))) { 673 kvm_cpu_cap_clear(X86_FEATURE_RDTSCP); 674 kvm_cpu_cap_clear(X86_FEATURE_RDPID); 675 } 676 } 677 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 678 679 struct kvm_cpuid_array { 680 struct kvm_cpuid_entry2 *entries; 681 int maxnent; 682 int nent; 683 }; 684 685 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 686 u32 function, u32 index) 687 { 688 struct kvm_cpuid_entry2 *entry; 689 690 if (array->nent >= array->maxnent) 691 return NULL; 692 693 entry = &array->entries[array->nent++]; 694 695 entry->function = function; 696 entry->index = index; 697 entry->flags = 0; 698 699 cpuid_count(entry->function, entry->index, 700 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 701 702 switch (function) { 703 case 4: 704 case 7: 705 case 0xb: 706 case 0xd: 707 case 0xf: 708 case 0x10: 709 case 0x12: 710 case 0x14: 711 case 0x17: 712 case 0x18: 713 case 0x1d: 714 case 0x1e: 715 case 0x1f: 716 case 0x8000001d: 717 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 718 break; 719 } 720 721 return entry; 722 } 723 724 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 725 { 726 struct kvm_cpuid_entry2 *entry; 727 728 if (array->nent >= array->maxnent) 729 return -E2BIG; 730 731 entry = &array->entries[array->nent]; 732 entry->function = func; 733 entry->index = 0; 734 entry->flags = 0; 735 736 switch (func) { 737 case 0: 738 entry->eax = 7; 739 ++array->nent; 740 break; 741 case 1: 742 entry->ecx = F(MOVBE); 743 ++array->nent; 744 break; 745 case 7: 746 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 747 entry->eax = 0; 748 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) 749 entry->ecx = F(RDPID); 750 ++array->nent; 751 break; 752 default: 753 break; 754 } 755 756 return 0; 757 } 758 759 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 760 { 761 struct kvm_cpuid_entry2 *entry; 762 int r, i, max_idx; 763 764 /* all calls to cpuid_count() should be made on the same cpu */ 765 get_cpu(); 766 767 r = -E2BIG; 768 769 entry = do_host_cpuid(array, function, 0); 770 if (!entry) 771 goto out; 772 773 switch (function) { 774 case 0: 775 /* Limited to the highest leaf implemented in KVM. */ 776 entry->eax = min(entry->eax, 0x1fU); 777 break; 778 case 1: 779 cpuid_entry_override(entry, CPUID_1_EDX); 780 cpuid_entry_override(entry, CPUID_1_ECX); 781 break; 782 case 2: 783 /* 784 * On ancient CPUs, function 2 entries are STATEFUL. That is, 785 * CPUID(function=2, index=0) may return different results each 786 * time, with the least-significant byte in EAX enumerating the 787 * number of times software should do CPUID(2, 0). 788 * 789 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 790 * idiotic. Intel's SDM states that EAX & 0xff "will always 791 * return 01H. Software should ignore this value and not 792 * interpret it as an informational descriptor", while AMD's 793 * APM states that CPUID(2) is reserved. 794 * 795 * WARN if a frankenstein CPU that supports virtualization and 796 * a stateful CPUID.0x2 is encountered. 797 */ 798 WARN_ON_ONCE((entry->eax & 0xff) > 1); 799 break; 800 /* functions 4 and 0x8000001d have additional index. */ 801 case 4: 802 case 0x8000001d: 803 /* 804 * Read entries until the cache type in the previous entry is 805 * zero, i.e. indicates an invalid entry. 806 */ 807 for (i = 1; entry->eax & 0x1f; ++i) { 808 entry = do_host_cpuid(array, function, i); 809 if (!entry) 810 goto out; 811 } 812 break; 813 case 6: /* Thermal management */ 814 entry->eax = 0x4; /* allow ARAT */ 815 entry->ebx = 0; 816 entry->ecx = 0; 817 entry->edx = 0; 818 break; 819 /* function 7 has additional index. */ 820 case 7: 821 entry->eax = min(entry->eax, 1u); 822 cpuid_entry_override(entry, CPUID_7_0_EBX); 823 cpuid_entry_override(entry, CPUID_7_ECX); 824 cpuid_entry_override(entry, CPUID_7_EDX); 825 826 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 827 if (entry->eax == 1) { 828 entry = do_host_cpuid(array, function, 1); 829 if (!entry) 830 goto out; 831 832 cpuid_entry_override(entry, CPUID_7_1_EAX); 833 entry->ebx = 0; 834 entry->ecx = 0; 835 entry->edx = 0; 836 } 837 break; 838 case 9: 839 break; 840 case 0xa: { /* Architectural Performance Monitoring */ 841 struct x86_pmu_capability cap; 842 union cpuid10_eax eax; 843 union cpuid10_edx edx; 844 845 perf_get_x86_pmu_capability(&cap); 846 847 /* 848 * The guest architecture pmu is only supported if the architecture 849 * pmu exists on the host and the module parameters allow it. 850 */ 851 if (!cap.version || !enable_pmu) 852 memset(&cap, 0, sizeof(cap)); 853 854 eax.split.version_id = min(cap.version, 2); 855 eax.split.num_counters = cap.num_counters_gp; 856 eax.split.bit_width = cap.bit_width_gp; 857 eax.split.mask_length = cap.events_mask_len; 858 859 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 860 edx.split.bit_width_fixed = cap.bit_width_fixed; 861 if (cap.version) 862 edx.split.anythread_deprecated = 1; 863 edx.split.reserved1 = 0; 864 edx.split.reserved2 = 0; 865 866 entry->eax = eax.full; 867 entry->ebx = cap.events_mask; 868 entry->ecx = 0; 869 entry->edx = edx.full; 870 break; 871 } 872 /* 873 * Per Intel's SDM, the 0x1f is a superset of 0xb, 874 * thus they can be handled by common code. 875 */ 876 case 0x1f: 877 case 0xb: 878 /* 879 * Populate entries until the level type (ECX[15:8]) of the 880 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 881 * the starting entry, filled by the primary do_host_cpuid(). 882 */ 883 for (i = 1; entry->ecx & 0xff00; ++i) { 884 entry = do_host_cpuid(array, function, i); 885 if (!entry) 886 goto out; 887 } 888 break; 889 case 0xd: { 890 u64 guest_perm = xstate_get_guest_group_perm(); 891 892 entry->eax &= supported_xcr0 & guest_perm; 893 entry->ebx = xstate_required_size(supported_xcr0, false); 894 entry->ecx = entry->ebx; 895 entry->edx &= (supported_xcr0 & guest_perm) >> 32; 896 if (!supported_xcr0) 897 break; 898 899 entry = do_host_cpuid(array, function, 1); 900 if (!entry) 901 goto out; 902 903 cpuid_entry_override(entry, CPUID_D_1_EAX); 904 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 905 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 906 true); 907 else { 908 WARN_ON_ONCE(supported_xss != 0); 909 entry->ebx = 0; 910 } 911 entry->ecx &= supported_xss; 912 entry->edx &= supported_xss >> 32; 913 914 for (i = 2; i < 64; ++i) { 915 bool s_state; 916 if (supported_xcr0 & BIT_ULL(i)) 917 s_state = false; 918 else if (supported_xss & BIT_ULL(i)) 919 s_state = true; 920 else 921 continue; 922 923 entry = do_host_cpuid(array, function, i); 924 if (!entry) 925 goto out; 926 927 /* 928 * The supported check above should have filtered out 929 * invalid sub-leafs. Only valid sub-leafs should 930 * reach this point, and they should have a non-zero 931 * save state size. Furthermore, check whether the 932 * processor agrees with supported_xcr0/supported_xss 933 * on whether this is an XCR0- or IA32_XSS-managed area. 934 */ 935 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 936 --array->nent; 937 continue; 938 } 939 940 if (!kvm_cpu_cap_has(X86_FEATURE_XFD)) 941 entry->ecx &= ~BIT_ULL(2); 942 entry->edx = 0; 943 } 944 break; 945 } 946 case 0x12: 947 /* Intel SGX */ 948 if (!kvm_cpu_cap_has(X86_FEATURE_SGX)) { 949 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 950 break; 951 } 952 953 /* 954 * Index 0: Sub-features, MISCSELECT (a.k.a extended features) 955 * and max enclave sizes. The SGX sub-features and MISCSELECT 956 * are restricted by kernel and KVM capabilities (like most 957 * feature flags), while enclave size is unrestricted. 958 */ 959 cpuid_entry_override(entry, CPUID_12_EAX); 960 entry->ebx &= SGX_MISC_EXINFO; 961 962 entry = do_host_cpuid(array, function, 1); 963 if (!entry) 964 goto out; 965 966 /* 967 * Index 1: SECS.ATTRIBUTES. ATTRIBUTES are restricted a la 968 * feature flags. Advertise all supported flags, including 969 * privileged attributes that require explicit opt-in from 970 * userspace. ATTRIBUTES.XFRM is not adjusted as userspace is 971 * expected to derive it from supported XCR0. 972 */ 973 entry->eax &= SGX_ATTR_DEBUG | SGX_ATTR_MODE64BIT | 974 SGX_ATTR_PROVISIONKEY | SGX_ATTR_EINITTOKENKEY | 975 SGX_ATTR_KSS; 976 entry->ebx &= 0; 977 break; 978 /* Intel PT */ 979 case 0x14: 980 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 981 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 982 break; 983 } 984 985 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 986 if (!do_host_cpuid(array, function, i)) 987 goto out; 988 } 989 break; 990 /* Intel AMX TILE */ 991 case 0x1d: 992 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 993 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 994 break; 995 } 996 997 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 998 if (!do_host_cpuid(array, function, i)) 999 goto out; 1000 } 1001 break; 1002 case 0x1e: /* TMUL information */ 1003 if (!kvm_cpu_cap_has(X86_FEATURE_AMX_TILE)) { 1004 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1005 break; 1006 } 1007 break; 1008 case KVM_CPUID_SIGNATURE: { 1009 const u32 *sigptr = (const u32 *)KVM_SIGNATURE; 1010 entry->eax = KVM_CPUID_FEATURES; 1011 entry->ebx = sigptr[0]; 1012 entry->ecx = sigptr[1]; 1013 entry->edx = sigptr[2]; 1014 break; 1015 } 1016 case KVM_CPUID_FEATURES: 1017 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 1018 (1 << KVM_FEATURE_NOP_IO_DELAY) | 1019 (1 << KVM_FEATURE_CLOCKSOURCE2) | 1020 (1 << KVM_FEATURE_ASYNC_PF) | 1021 (1 << KVM_FEATURE_PV_EOI) | 1022 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 1023 (1 << KVM_FEATURE_PV_UNHALT) | 1024 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 1025 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 1026 (1 << KVM_FEATURE_PV_SEND_IPI) | 1027 (1 << KVM_FEATURE_POLL_CONTROL) | 1028 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 1029 (1 << KVM_FEATURE_ASYNC_PF_INT); 1030 1031 if (sched_info_on()) 1032 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 1033 1034 entry->ebx = 0; 1035 entry->ecx = 0; 1036 entry->edx = 0; 1037 break; 1038 case 0x80000000: 1039 entry->eax = min(entry->eax, 0x8000001f); 1040 break; 1041 case 0x80000001: 1042 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 1043 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 1044 break; 1045 case 0x80000006: 1046 /* L2 cache and TLB: pass through host info. */ 1047 break; 1048 case 0x80000007: /* Advanced power management */ 1049 /* invariant TSC is CPUID.80000007H:EDX[8] */ 1050 entry->edx &= (1 << 8); 1051 /* mask against host */ 1052 entry->edx &= boot_cpu_data.x86_power; 1053 entry->eax = entry->ebx = entry->ecx = 0; 1054 break; 1055 case 0x80000008: { 1056 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 1057 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 1058 unsigned phys_as = entry->eax & 0xff; 1059 1060 /* 1061 * If TDP (NPT) is disabled use the adjusted host MAXPHYADDR as 1062 * the guest operates in the same PA space as the host, i.e. 1063 * reductions in MAXPHYADDR for memory encryption affect shadow 1064 * paging, too. 1065 * 1066 * If TDP is enabled but an explicit guest MAXPHYADDR is not 1067 * provided, use the raw bare metal MAXPHYADDR as reductions to 1068 * the HPAs do not affect GPAs. 1069 */ 1070 if (!tdp_enabled) 1071 g_phys_as = boot_cpu_data.x86_phys_bits; 1072 else if (!g_phys_as) 1073 g_phys_as = phys_as; 1074 1075 entry->eax = g_phys_as | (virt_as << 8); 1076 entry->edx = 0; 1077 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 1078 break; 1079 } 1080 case 0x8000000A: 1081 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 1082 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1083 break; 1084 } 1085 entry->eax = 1; /* SVM revision 1 */ 1086 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 1087 ASID emulation to nested SVM */ 1088 entry->ecx = 0; /* Reserved */ 1089 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 1090 break; 1091 case 0x80000019: 1092 entry->ecx = entry->edx = 0; 1093 break; 1094 case 0x8000001a: 1095 case 0x8000001e: 1096 break; 1097 case 0x8000001F: 1098 if (!kvm_cpu_cap_has(X86_FEATURE_SEV)) { 1099 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1100 } else { 1101 cpuid_entry_override(entry, CPUID_8000_001F_EAX); 1102 1103 /* 1104 * Enumerate '0' for "PA bits reduction", the adjusted 1105 * MAXPHYADDR is enumerated directly (see 0x80000008). 1106 */ 1107 entry->ebx &= ~GENMASK(11, 6); 1108 } 1109 break; 1110 /*Add support for Centaur's CPUID instruction*/ 1111 case 0xC0000000: 1112 /*Just support up to 0xC0000004 now*/ 1113 entry->eax = min(entry->eax, 0xC0000004); 1114 break; 1115 case 0xC0000001: 1116 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 1117 break; 1118 case 3: /* Processor serial number */ 1119 case 5: /* MONITOR/MWAIT */ 1120 case 0xC0000002: 1121 case 0xC0000003: 1122 case 0xC0000004: 1123 default: 1124 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 1125 break; 1126 } 1127 1128 r = 0; 1129 1130 out: 1131 put_cpu(); 1132 1133 return r; 1134 } 1135 1136 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1137 unsigned int type) 1138 { 1139 if (type == KVM_GET_EMULATED_CPUID) 1140 return __do_cpuid_func_emulated(array, func); 1141 1142 return __do_cpuid_func(array, func); 1143 } 1144 1145 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 1146 1147 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 1148 unsigned int type) 1149 { 1150 u32 limit; 1151 int r; 1152 1153 if (func == CENTAUR_CPUID_SIGNATURE && 1154 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 1155 return 0; 1156 1157 r = do_cpuid_func(array, func, type); 1158 if (r) 1159 return r; 1160 1161 limit = array->entries[array->nent - 1].eax; 1162 for (func = func + 1; func <= limit; ++func) { 1163 r = do_cpuid_func(array, func, type); 1164 if (r) 1165 break; 1166 } 1167 1168 return r; 1169 } 1170 1171 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 1172 __u32 num_entries, unsigned int ioctl_type) 1173 { 1174 int i; 1175 __u32 pad[3]; 1176 1177 if (ioctl_type != KVM_GET_EMULATED_CPUID) 1178 return false; 1179 1180 /* 1181 * We want to make sure that ->padding is being passed clean from 1182 * userspace in case we want to use it for something in the future. 1183 * 1184 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 1185 * have to give ourselves satisfied only with the emulated side. /me 1186 * sheds a tear. 1187 */ 1188 for (i = 0; i < num_entries; i++) { 1189 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 1190 return true; 1191 1192 if (pad[0] || pad[1] || pad[2]) 1193 return true; 1194 } 1195 return false; 1196 } 1197 1198 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 1199 struct kvm_cpuid_entry2 __user *entries, 1200 unsigned int type) 1201 { 1202 static const u32 funcs[] = { 1203 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 1204 }; 1205 1206 struct kvm_cpuid_array array = { 1207 .nent = 0, 1208 }; 1209 int r, i; 1210 1211 if (cpuid->nent < 1) 1212 return -E2BIG; 1213 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 1214 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 1215 1216 if (sanity_check_entries(entries, cpuid->nent, type)) 1217 return -EINVAL; 1218 1219 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 1220 cpuid->nent)); 1221 if (!array.entries) 1222 return -ENOMEM; 1223 1224 array.maxnent = cpuid->nent; 1225 1226 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 1227 r = get_cpuid_func(&array, funcs[i], type); 1228 if (r) 1229 goto out_free; 1230 } 1231 cpuid->nent = array.nent; 1232 1233 if (copy_to_user(entries, array.entries, 1234 array.nent * sizeof(struct kvm_cpuid_entry2))) 1235 r = -EFAULT; 1236 1237 out_free: 1238 vfree(array.entries); 1239 return r; 1240 } 1241 1242 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 1243 u32 function, u32 index) 1244 { 1245 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 1246 function, index); 1247 } 1248 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 1249 1250 /* 1251 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1252 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1253 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1254 * range. Centaur/VIA follows Intel semantics. 1255 * 1256 * A leaf is considered out-of-range if its function is higher than the maximum 1257 * supported leaf of its associated class or if its associated class does not 1258 * exist. 1259 * 1260 * There are three primary classes to be considered, with their respective 1261 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1262 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1263 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1264 * 1265 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1266 * - Hypervisor: 0x40000000 - 0x4fffffff 1267 * - Extended: 0x80000000 - 0xbfffffff 1268 * - Centaur: 0xc0000000 - 0xcfffffff 1269 * 1270 * The Hypervisor class is further subdivided into sub-classes that each act as 1271 * their own independent class associated with a 0x100 byte range. E.g. if Qemu 1272 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1273 * CPUID sub-classes are: 1274 * 1275 * - HyperV: 0x40000000 - 0x400000ff 1276 * - KVM: 0x40000100 - 0x400001ff 1277 */ 1278 static struct kvm_cpuid_entry2 * 1279 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1280 { 1281 struct kvm_cpuid_entry2 *basic, *class; 1282 u32 function = *fn_ptr; 1283 1284 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1285 if (!basic) 1286 return NULL; 1287 1288 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1289 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1290 return NULL; 1291 1292 if (function >= 0x40000000 && function <= 0x4fffffff) 1293 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1294 else if (function >= 0xc0000000) 1295 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1296 else 1297 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1298 1299 if (class && function <= class->eax) 1300 return NULL; 1301 1302 /* 1303 * Leaf specific adjustments are also applied when redirecting to the 1304 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1305 * entry for CPUID.0xb.index (see below), then the output value for EDX 1306 * needs to be pulled from CPUID.0xb.1. 1307 */ 1308 *fn_ptr = basic->eax; 1309 1310 /* 1311 * The class does not exist or the requested function is out of range; 1312 * the effective CPUID entry is the max basic leaf. Note, the index of 1313 * the original requested leaf is observed! 1314 */ 1315 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1316 } 1317 1318 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1319 u32 *ecx, u32 *edx, bool exact_only) 1320 { 1321 u32 orig_function = *eax, function = *eax, index = *ecx; 1322 struct kvm_cpuid_entry2 *entry; 1323 bool exact, used_max_basic = false; 1324 1325 entry = kvm_find_cpuid_entry(vcpu, function, index); 1326 exact = !!entry; 1327 1328 if (!entry && !exact_only) { 1329 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1330 used_max_basic = !!entry; 1331 } 1332 1333 if (entry) { 1334 *eax = entry->eax; 1335 *ebx = entry->ebx; 1336 *ecx = entry->ecx; 1337 *edx = entry->edx; 1338 if (function == 7 && index == 0) { 1339 u64 data; 1340 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1341 (data & TSX_CTRL_CPUID_CLEAR)) 1342 *ebx &= ~(F(RTM) | F(HLE)); 1343 } 1344 } else { 1345 *eax = *ebx = *ecx = *edx = 0; 1346 /* 1347 * When leaf 0BH or 1FH is defined, CL is pass-through 1348 * and EDX is always the x2APIC ID, even for undefined 1349 * subleaves. Index 1 will exist iff the leaf is 1350 * implemented, so we pass through CL iff leaf 1 1351 * exists. EDX can be copied from any existing index. 1352 */ 1353 if (function == 0xb || function == 0x1f) { 1354 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1355 if (entry) { 1356 *ecx = index & 0xff; 1357 *edx = entry->edx; 1358 } 1359 } 1360 } 1361 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1362 used_max_basic); 1363 return exact; 1364 } 1365 EXPORT_SYMBOL_GPL(kvm_cpuid); 1366 1367 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1368 { 1369 u32 eax, ebx, ecx, edx; 1370 1371 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1372 return 1; 1373 1374 eax = kvm_rax_read(vcpu); 1375 ecx = kvm_rcx_read(vcpu); 1376 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1377 kvm_rax_write(vcpu, eax); 1378 kvm_rbx_write(vcpu, ebx); 1379 kvm_rcx_write(vcpu, ecx); 1380 kvm_rdx_write(vcpu, edx); 1381 return kvm_skip_emulated_instruction(vcpu); 1382 } 1383 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1384