1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Kernel-based Virtual Machine driver for Linux 4 * cpuid support routines 5 * 6 * derived from arch/x86/kvm/x86.c 7 * 8 * Copyright 2011 Red Hat, Inc. and/or its affiliates. 9 * Copyright IBM Corporation, 2008 10 */ 11 12 #include <linux/kvm_host.h> 13 #include <linux/export.h> 14 #include <linux/vmalloc.h> 15 #include <linux/uaccess.h> 16 #include <linux/sched/stat.h> 17 18 #include <asm/processor.h> 19 #include <asm/user.h> 20 #include <asm/fpu/xstate.h> 21 #include "cpuid.h" 22 #include "lapic.h" 23 #include "mmu.h" 24 #include "trace.h" 25 #include "pmu.h" 26 27 /* 28 * Unlike "struct cpuinfo_x86.x86_capability", kvm_cpu_caps doesn't need to be 29 * aligned to sizeof(unsigned long) because it's not accessed via bitops. 30 */ 31 u32 kvm_cpu_caps[NCAPINTS] __read_mostly; 32 EXPORT_SYMBOL_GPL(kvm_cpu_caps); 33 34 static u32 xstate_required_size(u64 xstate_bv, bool compacted) 35 { 36 int feature_bit = 0; 37 u32 ret = XSAVE_HDR_SIZE + XSAVE_HDR_OFFSET; 38 39 xstate_bv &= XFEATURE_MASK_EXTEND; 40 while (xstate_bv) { 41 if (xstate_bv & 0x1) { 42 u32 eax, ebx, ecx, edx, offset; 43 cpuid_count(0xD, feature_bit, &eax, &ebx, &ecx, &edx); 44 offset = compacted ? ret : ebx; 45 ret = max(ret, offset + eax); 46 } 47 48 xstate_bv >>= 1; 49 feature_bit++; 50 } 51 52 return ret; 53 } 54 55 #define F feature_bit 56 57 static inline struct kvm_cpuid_entry2 *cpuid_entry2_find( 58 struct kvm_cpuid_entry2 *entries, int nent, u32 function, u32 index) 59 { 60 struct kvm_cpuid_entry2 *e; 61 int i; 62 63 for (i = 0; i < nent; i++) { 64 e = &entries[i]; 65 66 if (e->function == function && (e->index == index || 67 !(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX))) 68 return e; 69 } 70 71 return NULL; 72 } 73 74 static int kvm_check_cpuid(struct kvm_cpuid_entry2 *entries, int nent) 75 { 76 struct kvm_cpuid_entry2 *best; 77 78 /* 79 * The existing code assumes virtual address is 48-bit or 57-bit in the 80 * canonical address checks; exit if it is ever changed. 81 */ 82 best = cpuid_entry2_find(entries, nent, 0x80000008, 0); 83 if (best) { 84 int vaddr_bits = (best->eax & 0xff00) >> 8; 85 86 if (vaddr_bits != 48 && vaddr_bits != 57 && vaddr_bits != 0) 87 return -EINVAL; 88 } 89 90 return 0; 91 } 92 93 void kvm_update_pv_runtime(struct kvm_vcpu *vcpu) 94 { 95 struct kvm_cpuid_entry2 *best; 96 97 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 98 99 /* 100 * save the feature bitmap to avoid cpuid lookup for every PV 101 * operation 102 */ 103 if (best) 104 vcpu->arch.pv_cpuid.features = best->eax; 105 } 106 107 void kvm_update_cpuid_runtime(struct kvm_vcpu *vcpu) 108 { 109 struct kvm_cpuid_entry2 *best; 110 111 best = kvm_find_cpuid_entry(vcpu, 1, 0); 112 if (best) { 113 /* Update OSXSAVE bit */ 114 if (boot_cpu_has(X86_FEATURE_XSAVE)) 115 cpuid_entry_change(best, X86_FEATURE_OSXSAVE, 116 kvm_read_cr4_bits(vcpu, X86_CR4_OSXSAVE)); 117 118 cpuid_entry_change(best, X86_FEATURE_APIC, 119 vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE); 120 } 121 122 best = kvm_find_cpuid_entry(vcpu, 7, 0); 123 if (best && boot_cpu_has(X86_FEATURE_PKU) && best->function == 0x7) 124 cpuid_entry_change(best, X86_FEATURE_OSPKE, 125 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)); 126 127 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 128 if (best) 129 best->ebx = xstate_required_size(vcpu->arch.xcr0, false); 130 131 best = kvm_find_cpuid_entry(vcpu, 0xD, 1); 132 if (best && (cpuid_entry_has(best, X86_FEATURE_XSAVES) || 133 cpuid_entry_has(best, X86_FEATURE_XSAVEC))) 134 best->ebx = xstate_required_size(vcpu->arch.xcr0, true); 135 136 best = kvm_find_cpuid_entry(vcpu, KVM_CPUID_FEATURES, 0); 137 if (kvm_hlt_in_guest(vcpu->kvm) && best && 138 (best->eax & (1 << KVM_FEATURE_PV_UNHALT))) 139 best->eax &= ~(1 << KVM_FEATURE_PV_UNHALT); 140 141 if (!kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT)) { 142 best = kvm_find_cpuid_entry(vcpu, 0x1, 0); 143 if (best) 144 cpuid_entry_change(best, X86_FEATURE_MWAIT, 145 vcpu->arch.ia32_misc_enable_msr & 146 MSR_IA32_MISC_ENABLE_MWAIT); 147 } 148 } 149 150 static void kvm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu) 151 { 152 struct kvm_lapic *apic = vcpu->arch.apic; 153 struct kvm_cpuid_entry2 *best; 154 155 best = kvm_find_cpuid_entry(vcpu, 1, 0); 156 if (best && apic) { 157 if (cpuid_entry_has(best, X86_FEATURE_TSC_DEADLINE_TIMER)) 158 apic->lapic_timer.timer_mode_mask = 3 << 17; 159 else 160 apic->lapic_timer.timer_mode_mask = 1 << 17; 161 162 kvm_apic_set_version(vcpu); 163 } 164 165 best = kvm_find_cpuid_entry(vcpu, 0xD, 0); 166 if (!best) 167 vcpu->arch.guest_supported_xcr0 = 0; 168 else 169 vcpu->arch.guest_supported_xcr0 = 170 (best->eax | ((u64)best->edx << 32)) & supported_xcr0; 171 172 kvm_update_pv_runtime(vcpu); 173 174 vcpu->arch.maxphyaddr = cpuid_query_maxphyaddr(vcpu); 175 kvm_mmu_reset_context(vcpu); 176 177 kvm_pmu_refresh(vcpu); 178 vcpu->arch.cr4_guest_rsvd_bits = 179 __cr4_reserved_bits(guest_cpuid_has, vcpu); 180 181 vcpu->arch.cr3_lm_rsvd_bits = rsvd_bits(cpuid_maxphyaddr(vcpu), 63); 182 183 /* Invoke the vendor callback only after the above state is updated. */ 184 kvm_x86_ops.vcpu_after_set_cpuid(vcpu); 185 } 186 187 static int is_efer_nx(void) 188 { 189 return host_efer & EFER_NX; 190 } 191 192 static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu) 193 { 194 int i; 195 struct kvm_cpuid_entry2 *e, *entry; 196 197 entry = NULL; 198 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) { 199 e = &vcpu->arch.cpuid_entries[i]; 200 if (e->function == 0x80000001) { 201 entry = e; 202 break; 203 } 204 } 205 if (entry && cpuid_entry_has(entry, X86_FEATURE_NX) && !is_efer_nx()) { 206 cpuid_entry_clear(entry, X86_FEATURE_NX); 207 printk(KERN_INFO "kvm: guest NX capability removed\n"); 208 } 209 } 210 211 int cpuid_query_maxphyaddr(struct kvm_vcpu *vcpu) 212 { 213 struct kvm_cpuid_entry2 *best; 214 215 best = kvm_find_cpuid_entry(vcpu, 0x80000000, 0); 216 if (!best || best->eax < 0x80000008) 217 goto not_found; 218 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0); 219 if (best) 220 return best->eax & 0xff; 221 not_found: 222 return 36; 223 } 224 225 /* when an old userspace process fills a new kernel module */ 226 int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu, 227 struct kvm_cpuid *cpuid, 228 struct kvm_cpuid_entry __user *entries) 229 { 230 int r, i; 231 struct kvm_cpuid_entry *e = NULL; 232 struct kvm_cpuid_entry2 *e2 = NULL; 233 234 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 235 return -E2BIG; 236 237 if (cpuid->nent) { 238 e = vmemdup_user(entries, array_size(sizeof(*e), cpuid->nent)); 239 if (IS_ERR(e)) 240 return PTR_ERR(e); 241 242 e2 = kvmalloc_array(cpuid->nent, sizeof(*e2), GFP_KERNEL_ACCOUNT); 243 if (!e2) { 244 r = -ENOMEM; 245 goto out_free_cpuid; 246 } 247 } 248 for (i = 0; i < cpuid->nent; i++) { 249 e2[i].function = e[i].function; 250 e2[i].eax = e[i].eax; 251 e2[i].ebx = e[i].ebx; 252 e2[i].ecx = e[i].ecx; 253 e2[i].edx = e[i].edx; 254 e2[i].index = 0; 255 e2[i].flags = 0; 256 e2[i].padding[0] = 0; 257 e2[i].padding[1] = 0; 258 e2[i].padding[2] = 0; 259 } 260 261 r = kvm_check_cpuid(e2, cpuid->nent); 262 if (r) { 263 kvfree(e2); 264 goto out_free_cpuid; 265 } 266 267 kvfree(vcpu->arch.cpuid_entries); 268 vcpu->arch.cpuid_entries = e2; 269 vcpu->arch.cpuid_nent = cpuid->nent; 270 271 cpuid_fix_nx_cap(vcpu); 272 kvm_update_cpuid_runtime(vcpu); 273 kvm_vcpu_after_set_cpuid(vcpu); 274 275 out_free_cpuid: 276 kvfree(e); 277 278 return r; 279 } 280 281 int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu, 282 struct kvm_cpuid2 *cpuid, 283 struct kvm_cpuid_entry2 __user *entries) 284 { 285 struct kvm_cpuid_entry2 *e2 = NULL; 286 int r; 287 288 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 289 return -E2BIG; 290 291 if (cpuid->nent) { 292 e2 = vmemdup_user(entries, array_size(sizeof(*e2), cpuid->nent)); 293 if (IS_ERR(e2)) 294 return PTR_ERR(e2); 295 } 296 297 r = kvm_check_cpuid(e2, cpuid->nent); 298 if (r) { 299 kvfree(e2); 300 return r; 301 } 302 303 kvfree(vcpu->arch.cpuid_entries); 304 vcpu->arch.cpuid_entries = e2; 305 vcpu->arch.cpuid_nent = cpuid->nent; 306 307 kvm_update_cpuid_runtime(vcpu); 308 kvm_vcpu_after_set_cpuid(vcpu); 309 310 return 0; 311 } 312 313 int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu, 314 struct kvm_cpuid2 *cpuid, 315 struct kvm_cpuid_entry2 __user *entries) 316 { 317 int r; 318 319 r = -E2BIG; 320 if (cpuid->nent < vcpu->arch.cpuid_nent) 321 goto out; 322 r = -EFAULT; 323 if (copy_to_user(entries, &vcpu->arch.cpuid_entries, 324 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2))) 325 goto out; 326 return 0; 327 328 out: 329 cpuid->nent = vcpu->arch.cpuid_nent; 330 return r; 331 } 332 333 static __always_inline void kvm_cpu_cap_mask(enum cpuid_leafs leaf, u32 mask) 334 { 335 const struct cpuid_reg cpuid = x86_feature_cpuid(leaf * 32); 336 struct kvm_cpuid_entry2 entry; 337 338 reverse_cpuid_check(leaf); 339 kvm_cpu_caps[leaf] &= mask; 340 341 cpuid_count(cpuid.function, cpuid.index, 342 &entry.eax, &entry.ebx, &entry.ecx, &entry.edx); 343 344 kvm_cpu_caps[leaf] &= *__cpuid_entry_get_reg(&entry, cpuid.reg); 345 } 346 347 void kvm_set_cpu_caps(void) 348 { 349 unsigned int f_nx = is_efer_nx() ? F(NX) : 0; 350 #ifdef CONFIG_X86_64 351 unsigned int f_gbpages = F(GBPAGES); 352 unsigned int f_lm = F(LM); 353 #else 354 unsigned int f_gbpages = 0; 355 unsigned int f_lm = 0; 356 #endif 357 358 BUILD_BUG_ON(sizeof(kvm_cpu_caps) > 359 sizeof(boot_cpu_data.x86_capability)); 360 361 memcpy(&kvm_cpu_caps, &boot_cpu_data.x86_capability, 362 sizeof(kvm_cpu_caps)); 363 364 kvm_cpu_cap_mask(CPUID_1_ECX, 365 /* 366 * NOTE: MONITOR (and MWAIT) are emulated as NOP, but *not* 367 * advertised to guests via CPUID! 368 */ 369 F(XMM3) | F(PCLMULQDQ) | 0 /* DTES64, MONITOR */ | 370 0 /* DS-CPL, VMX, SMX, EST */ | 371 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ | 372 F(FMA) | F(CX16) | 0 /* xTPR Update */ | F(PDCM) | 373 F(PCID) | 0 /* Reserved, DCA */ | F(XMM4_1) | 374 F(XMM4_2) | F(X2APIC) | F(MOVBE) | F(POPCNT) | 375 0 /* Reserved*/ | F(AES) | F(XSAVE) | 0 /* OSXSAVE */ | F(AVX) | 376 F(F16C) | F(RDRAND) 377 ); 378 /* KVM emulates x2apic in software irrespective of host support. */ 379 kvm_cpu_cap_set(X86_FEATURE_X2APIC); 380 381 kvm_cpu_cap_mask(CPUID_1_EDX, 382 F(FPU) | F(VME) | F(DE) | F(PSE) | 383 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 384 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) | 385 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 386 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLUSH) | 387 0 /* Reserved, DS, ACPI */ | F(MMX) | 388 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) | 389 0 /* HTT, TM, Reserved, PBE */ 390 ); 391 392 kvm_cpu_cap_mask(CPUID_7_0_EBX, 393 F(FSGSBASE) | F(BMI1) | F(HLE) | F(AVX2) | F(SMEP) | 394 F(BMI2) | F(ERMS) | 0 /*INVPCID*/ | F(RTM) | 0 /*MPX*/ | F(RDSEED) | 395 F(ADX) | F(SMAP) | F(AVX512IFMA) | F(AVX512F) | F(AVX512PF) | 396 F(AVX512ER) | F(AVX512CD) | F(CLFLUSHOPT) | F(CLWB) | F(AVX512DQ) | 397 F(SHA_NI) | F(AVX512BW) | F(AVX512VL) | 0 /*INTEL_PT*/ 398 ); 399 400 kvm_cpu_cap_mask(CPUID_7_ECX, 401 F(AVX512VBMI) | F(LA57) | F(PKU) | 0 /*OSPKE*/ | F(RDPID) | 402 F(AVX512_VPOPCNTDQ) | F(UMIP) | F(AVX512_VBMI2) | F(GFNI) | 403 F(VAES) | F(VPCLMULQDQ) | F(AVX512_VNNI) | F(AVX512_BITALG) | 404 F(CLDEMOTE) | F(MOVDIRI) | F(MOVDIR64B) | 0 /*WAITPKG*/ 405 ); 406 /* Set LA57 based on hardware capability. */ 407 if (cpuid_ecx(7) & F(LA57)) 408 kvm_cpu_cap_set(X86_FEATURE_LA57); 409 410 /* 411 * PKU not yet implemented for shadow paging and requires OSPKE 412 * to be set on the host. Clear it if that is not the case 413 */ 414 if (!tdp_enabled || !boot_cpu_has(X86_FEATURE_OSPKE)) 415 kvm_cpu_cap_clear(X86_FEATURE_PKU); 416 417 kvm_cpu_cap_mask(CPUID_7_EDX, 418 F(AVX512_4VNNIW) | F(AVX512_4FMAPS) | F(SPEC_CTRL) | 419 F(SPEC_CTRL_SSBD) | F(ARCH_CAPABILITIES) | F(INTEL_STIBP) | 420 F(MD_CLEAR) | F(AVX512_VP2INTERSECT) | F(FSRM) | 421 F(SERIALIZE) | F(TSXLDTRK) 422 ); 423 424 /* TSC_ADJUST and ARCH_CAPABILITIES are emulated in software. */ 425 kvm_cpu_cap_set(X86_FEATURE_TSC_ADJUST); 426 kvm_cpu_cap_set(X86_FEATURE_ARCH_CAPABILITIES); 427 428 if (boot_cpu_has(X86_FEATURE_IBPB) && boot_cpu_has(X86_FEATURE_IBRS)) 429 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL); 430 if (boot_cpu_has(X86_FEATURE_STIBP)) 431 kvm_cpu_cap_set(X86_FEATURE_INTEL_STIBP); 432 if (boot_cpu_has(X86_FEATURE_AMD_SSBD)) 433 kvm_cpu_cap_set(X86_FEATURE_SPEC_CTRL_SSBD); 434 435 kvm_cpu_cap_mask(CPUID_7_1_EAX, 436 F(AVX512_BF16) 437 ); 438 439 kvm_cpu_cap_mask(CPUID_D_1_EAX, 440 F(XSAVEOPT) | F(XSAVEC) | F(XGETBV1) | F(XSAVES) 441 ); 442 443 kvm_cpu_cap_mask(CPUID_8000_0001_ECX, 444 F(LAHF_LM) | F(CMP_LEGACY) | 0 /*SVM*/ | 0 /* ExtApicSpace */ | 445 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) | 446 F(3DNOWPREFETCH) | F(OSVW) | 0 /* IBS */ | F(XOP) | 447 0 /* SKINIT, WDT, LWP */ | F(FMA4) | F(TBM) | 448 F(TOPOEXT) | F(PERFCTR_CORE) 449 ); 450 451 kvm_cpu_cap_mask(CPUID_8000_0001_EDX, 452 F(FPU) | F(VME) | F(DE) | F(PSE) | 453 F(TSC) | F(MSR) | F(PAE) | F(MCE) | 454 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) | 455 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) | 456 F(PAT) | F(PSE36) | 0 /* Reserved */ | 457 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) | 458 F(FXSR) | F(FXSR_OPT) | f_gbpages | F(RDTSCP) | 459 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW) 460 ); 461 462 if (!tdp_enabled && IS_ENABLED(CONFIG_X86_64)) 463 kvm_cpu_cap_set(X86_FEATURE_GBPAGES); 464 465 kvm_cpu_cap_mask(CPUID_8000_0008_EBX, 466 F(CLZERO) | F(XSAVEERPTR) | 467 F(WBNOINVD) | F(AMD_IBPB) | F(AMD_IBRS) | F(AMD_SSBD) | F(VIRT_SSBD) | 468 F(AMD_SSB_NO) | F(AMD_STIBP) | F(AMD_STIBP_ALWAYS_ON) 469 ); 470 471 /* 472 * AMD has separate bits for each SPEC_CTRL bit. 473 * arch/x86/kernel/cpu/bugs.c is kind enough to 474 * record that in cpufeatures so use them. 475 */ 476 if (boot_cpu_has(X86_FEATURE_IBPB)) 477 kvm_cpu_cap_set(X86_FEATURE_AMD_IBPB); 478 if (boot_cpu_has(X86_FEATURE_IBRS)) 479 kvm_cpu_cap_set(X86_FEATURE_AMD_IBRS); 480 if (boot_cpu_has(X86_FEATURE_STIBP)) 481 kvm_cpu_cap_set(X86_FEATURE_AMD_STIBP); 482 if (boot_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD)) 483 kvm_cpu_cap_set(X86_FEATURE_AMD_SSBD); 484 if (!boot_cpu_has_bug(X86_BUG_SPEC_STORE_BYPASS)) 485 kvm_cpu_cap_set(X86_FEATURE_AMD_SSB_NO); 486 /* 487 * The preference is to use SPEC CTRL MSR instead of the 488 * VIRT_SPEC MSR. 489 */ 490 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) && 491 !boot_cpu_has(X86_FEATURE_AMD_SSBD)) 492 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD); 493 494 /* 495 * Hide all SVM features by default, SVM will set the cap bits for 496 * features it emulates and/or exposes for L1. 497 */ 498 kvm_cpu_cap_mask(CPUID_8000_000A_EDX, 0); 499 500 kvm_cpu_cap_mask(CPUID_C000_0001_EDX, 501 F(XSTORE) | F(XSTORE_EN) | F(XCRYPT) | F(XCRYPT_EN) | 502 F(ACE2) | F(ACE2_EN) | F(PHE) | F(PHE_EN) | 503 F(PMM) | F(PMM_EN) 504 ); 505 } 506 EXPORT_SYMBOL_GPL(kvm_set_cpu_caps); 507 508 struct kvm_cpuid_array { 509 struct kvm_cpuid_entry2 *entries; 510 int maxnent; 511 int nent; 512 }; 513 514 static struct kvm_cpuid_entry2 *do_host_cpuid(struct kvm_cpuid_array *array, 515 u32 function, u32 index) 516 { 517 struct kvm_cpuid_entry2 *entry; 518 519 if (array->nent >= array->maxnent) 520 return NULL; 521 522 entry = &array->entries[array->nent++]; 523 524 entry->function = function; 525 entry->index = index; 526 entry->flags = 0; 527 528 cpuid_count(entry->function, entry->index, 529 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx); 530 531 switch (function) { 532 case 4: 533 case 7: 534 case 0xb: 535 case 0xd: 536 case 0xf: 537 case 0x10: 538 case 0x12: 539 case 0x14: 540 case 0x17: 541 case 0x18: 542 case 0x1f: 543 case 0x8000001d: 544 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 545 break; 546 } 547 548 return entry; 549 } 550 551 static int __do_cpuid_func_emulated(struct kvm_cpuid_array *array, u32 func) 552 { 553 struct kvm_cpuid_entry2 *entry; 554 555 if (array->nent >= array->maxnent) 556 return -E2BIG; 557 558 entry = &array->entries[array->nent]; 559 entry->function = func; 560 entry->index = 0; 561 entry->flags = 0; 562 563 switch (func) { 564 case 0: 565 entry->eax = 7; 566 ++array->nent; 567 break; 568 case 1: 569 entry->ecx = F(MOVBE); 570 ++array->nent; 571 break; 572 case 7: 573 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX; 574 entry->eax = 0; 575 entry->ecx = F(RDPID); 576 ++array->nent; 577 default: 578 break; 579 } 580 581 return 0; 582 } 583 584 static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function) 585 { 586 struct kvm_cpuid_entry2 *entry; 587 int r, i, max_idx; 588 589 /* all calls to cpuid_count() should be made on the same cpu */ 590 get_cpu(); 591 592 r = -E2BIG; 593 594 entry = do_host_cpuid(array, function, 0); 595 if (!entry) 596 goto out; 597 598 switch (function) { 599 case 0: 600 /* Limited to the highest leaf implemented in KVM. */ 601 entry->eax = min(entry->eax, 0x1fU); 602 break; 603 case 1: 604 cpuid_entry_override(entry, CPUID_1_EDX); 605 cpuid_entry_override(entry, CPUID_1_ECX); 606 break; 607 case 2: 608 /* 609 * On ancient CPUs, function 2 entries are STATEFUL. That is, 610 * CPUID(function=2, index=0) may return different results each 611 * time, with the least-significant byte in EAX enumerating the 612 * number of times software should do CPUID(2, 0). 613 * 614 * Modern CPUs, i.e. every CPU KVM has *ever* run on are less 615 * idiotic. Intel's SDM states that EAX & 0xff "will always 616 * return 01H. Software should ignore this value and not 617 * interpret it as an informational descriptor", while AMD's 618 * APM states that CPUID(2) is reserved. 619 * 620 * WARN if a frankenstein CPU that supports virtualization and 621 * a stateful CPUID.0x2 is encountered. 622 */ 623 WARN_ON_ONCE((entry->eax & 0xff) > 1); 624 break; 625 /* functions 4 and 0x8000001d have additional index. */ 626 case 4: 627 case 0x8000001d: 628 /* 629 * Read entries until the cache type in the previous entry is 630 * zero, i.e. indicates an invalid entry. 631 */ 632 for (i = 1; entry->eax & 0x1f; ++i) { 633 entry = do_host_cpuid(array, function, i); 634 if (!entry) 635 goto out; 636 } 637 break; 638 case 6: /* Thermal management */ 639 entry->eax = 0x4; /* allow ARAT */ 640 entry->ebx = 0; 641 entry->ecx = 0; 642 entry->edx = 0; 643 break; 644 /* function 7 has additional index. */ 645 case 7: 646 entry->eax = min(entry->eax, 1u); 647 cpuid_entry_override(entry, CPUID_7_0_EBX); 648 cpuid_entry_override(entry, CPUID_7_ECX); 649 cpuid_entry_override(entry, CPUID_7_EDX); 650 651 /* KVM only supports 0x7.0 and 0x7.1, capped above via min(). */ 652 if (entry->eax == 1) { 653 entry = do_host_cpuid(array, function, 1); 654 if (!entry) 655 goto out; 656 657 cpuid_entry_override(entry, CPUID_7_1_EAX); 658 entry->ebx = 0; 659 entry->ecx = 0; 660 entry->edx = 0; 661 } 662 break; 663 case 9: 664 break; 665 case 0xa: { /* Architectural Performance Monitoring */ 666 struct x86_pmu_capability cap; 667 union cpuid10_eax eax; 668 union cpuid10_edx edx; 669 670 perf_get_x86_pmu_capability(&cap); 671 672 /* 673 * Only support guest architectural pmu on a host 674 * with architectural pmu. 675 */ 676 if (!cap.version) 677 memset(&cap, 0, sizeof(cap)); 678 679 eax.split.version_id = min(cap.version, 2); 680 eax.split.num_counters = cap.num_counters_gp; 681 eax.split.bit_width = cap.bit_width_gp; 682 eax.split.mask_length = cap.events_mask_len; 683 684 edx.split.num_counters_fixed = min(cap.num_counters_fixed, MAX_FIXED_COUNTERS); 685 edx.split.bit_width_fixed = cap.bit_width_fixed; 686 edx.split.anythread_deprecated = 1; 687 edx.split.reserved1 = 0; 688 edx.split.reserved2 = 0; 689 690 entry->eax = eax.full; 691 entry->ebx = cap.events_mask; 692 entry->ecx = 0; 693 entry->edx = edx.full; 694 break; 695 } 696 /* 697 * Per Intel's SDM, the 0x1f is a superset of 0xb, 698 * thus they can be handled by common code. 699 */ 700 case 0x1f: 701 case 0xb: 702 /* 703 * Populate entries until the level type (ECX[15:8]) of the 704 * previous entry is zero. Note, CPUID EAX.{0x1f,0xb}.0 is 705 * the starting entry, filled by the primary do_host_cpuid(). 706 */ 707 for (i = 1; entry->ecx & 0xff00; ++i) { 708 entry = do_host_cpuid(array, function, i); 709 if (!entry) 710 goto out; 711 } 712 break; 713 case 0xd: 714 entry->eax &= supported_xcr0; 715 entry->ebx = xstate_required_size(supported_xcr0, false); 716 entry->ecx = entry->ebx; 717 entry->edx &= supported_xcr0 >> 32; 718 if (!supported_xcr0) 719 break; 720 721 entry = do_host_cpuid(array, function, 1); 722 if (!entry) 723 goto out; 724 725 cpuid_entry_override(entry, CPUID_D_1_EAX); 726 if (entry->eax & (F(XSAVES)|F(XSAVEC))) 727 entry->ebx = xstate_required_size(supported_xcr0 | supported_xss, 728 true); 729 else { 730 WARN_ON_ONCE(supported_xss != 0); 731 entry->ebx = 0; 732 } 733 entry->ecx &= supported_xss; 734 entry->edx &= supported_xss >> 32; 735 736 for (i = 2; i < 64; ++i) { 737 bool s_state; 738 if (supported_xcr0 & BIT_ULL(i)) 739 s_state = false; 740 else if (supported_xss & BIT_ULL(i)) 741 s_state = true; 742 else 743 continue; 744 745 entry = do_host_cpuid(array, function, i); 746 if (!entry) 747 goto out; 748 749 /* 750 * The supported check above should have filtered out 751 * invalid sub-leafs. Only valid sub-leafs should 752 * reach this point, and they should have a non-zero 753 * save state size. Furthermore, check whether the 754 * processor agrees with supported_xcr0/supported_xss 755 * on whether this is an XCR0- or IA32_XSS-managed area. 756 */ 757 if (WARN_ON_ONCE(!entry->eax || (entry->ecx & 0x1) != s_state)) { 758 --array->nent; 759 continue; 760 } 761 entry->edx = 0; 762 } 763 break; 764 /* Intel PT */ 765 case 0x14: 766 if (!kvm_cpu_cap_has(X86_FEATURE_INTEL_PT)) { 767 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 768 break; 769 } 770 771 for (i = 1, max_idx = entry->eax; i <= max_idx; ++i) { 772 if (!do_host_cpuid(array, function, i)) 773 goto out; 774 } 775 break; 776 case KVM_CPUID_SIGNATURE: { 777 static const char signature[12] = "KVMKVMKVM\0\0"; 778 const u32 *sigptr = (const u32 *)signature; 779 entry->eax = KVM_CPUID_FEATURES; 780 entry->ebx = sigptr[0]; 781 entry->ecx = sigptr[1]; 782 entry->edx = sigptr[2]; 783 break; 784 } 785 case KVM_CPUID_FEATURES: 786 entry->eax = (1 << KVM_FEATURE_CLOCKSOURCE) | 787 (1 << KVM_FEATURE_NOP_IO_DELAY) | 788 (1 << KVM_FEATURE_CLOCKSOURCE2) | 789 (1 << KVM_FEATURE_ASYNC_PF) | 790 (1 << KVM_FEATURE_PV_EOI) | 791 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT) | 792 (1 << KVM_FEATURE_PV_UNHALT) | 793 (1 << KVM_FEATURE_PV_TLB_FLUSH) | 794 (1 << KVM_FEATURE_ASYNC_PF_VMEXIT) | 795 (1 << KVM_FEATURE_PV_SEND_IPI) | 796 (1 << KVM_FEATURE_POLL_CONTROL) | 797 (1 << KVM_FEATURE_PV_SCHED_YIELD) | 798 (1 << KVM_FEATURE_ASYNC_PF_INT); 799 800 if (sched_info_on()) 801 entry->eax |= (1 << KVM_FEATURE_STEAL_TIME); 802 803 entry->ebx = 0; 804 entry->ecx = 0; 805 entry->edx = 0; 806 break; 807 case 0x80000000: 808 entry->eax = min(entry->eax, 0x8000001f); 809 break; 810 case 0x80000001: 811 cpuid_entry_override(entry, CPUID_8000_0001_EDX); 812 cpuid_entry_override(entry, CPUID_8000_0001_ECX); 813 break; 814 case 0x80000006: 815 /* L2 cache and TLB: pass through host info. */ 816 break; 817 case 0x80000007: /* Advanced power management */ 818 /* invariant TSC is CPUID.80000007H:EDX[8] */ 819 entry->edx &= (1 << 8); 820 /* mask against host */ 821 entry->edx &= boot_cpu_data.x86_power; 822 entry->eax = entry->ebx = entry->ecx = 0; 823 break; 824 case 0x80000008: { 825 unsigned g_phys_as = (entry->eax >> 16) & 0xff; 826 unsigned virt_as = max((entry->eax >> 8) & 0xff, 48U); 827 unsigned phys_as = entry->eax & 0xff; 828 829 if (!g_phys_as) 830 g_phys_as = phys_as; 831 entry->eax = g_phys_as | (virt_as << 8); 832 entry->edx = 0; 833 cpuid_entry_override(entry, CPUID_8000_0008_EBX); 834 break; 835 } 836 case 0x8000000A: 837 if (!kvm_cpu_cap_has(X86_FEATURE_SVM)) { 838 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 839 break; 840 } 841 entry->eax = 1; /* SVM revision 1 */ 842 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper 843 ASID emulation to nested SVM */ 844 entry->ecx = 0; /* Reserved */ 845 cpuid_entry_override(entry, CPUID_8000_000A_EDX); 846 break; 847 case 0x80000019: 848 entry->ecx = entry->edx = 0; 849 break; 850 case 0x8000001a: 851 case 0x8000001e: 852 break; 853 /* Support memory encryption cpuid if host supports it */ 854 case 0x8000001F: 855 if (!boot_cpu_has(X86_FEATURE_SEV)) 856 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 857 break; 858 /*Add support for Centaur's CPUID instruction*/ 859 case 0xC0000000: 860 /*Just support up to 0xC0000004 now*/ 861 entry->eax = min(entry->eax, 0xC0000004); 862 break; 863 case 0xC0000001: 864 cpuid_entry_override(entry, CPUID_C000_0001_EDX); 865 break; 866 case 3: /* Processor serial number */ 867 case 5: /* MONITOR/MWAIT */ 868 case 0xC0000002: 869 case 0xC0000003: 870 case 0xC0000004: 871 default: 872 entry->eax = entry->ebx = entry->ecx = entry->edx = 0; 873 break; 874 } 875 876 r = 0; 877 878 out: 879 put_cpu(); 880 881 return r; 882 } 883 884 static int do_cpuid_func(struct kvm_cpuid_array *array, u32 func, 885 unsigned int type) 886 { 887 if (type == KVM_GET_EMULATED_CPUID) 888 return __do_cpuid_func_emulated(array, func); 889 890 return __do_cpuid_func(array, func); 891 } 892 893 #define CENTAUR_CPUID_SIGNATURE 0xC0000000 894 895 static int get_cpuid_func(struct kvm_cpuid_array *array, u32 func, 896 unsigned int type) 897 { 898 u32 limit; 899 int r; 900 901 if (func == CENTAUR_CPUID_SIGNATURE && 902 boot_cpu_data.x86_vendor != X86_VENDOR_CENTAUR) 903 return 0; 904 905 r = do_cpuid_func(array, func, type); 906 if (r) 907 return r; 908 909 limit = array->entries[array->nent - 1].eax; 910 for (func = func + 1; func <= limit; ++func) { 911 r = do_cpuid_func(array, func, type); 912 if (r) 913 break; 914 } 915 916 return r; 917 } 918 919 static bool sanity_check_entries(struct kvm_cpuid_entry2 __user *entries, 920 __u32 num_entries, unsigned int ioctl_type) 921 { 922 int i; 923 __u32 pad[3]; 924 925 if (ioctl_type != KVM_GET_EMULATED_CPUID) 926 return false; 927 928 /* 929 * We want to make sure that ->padding is being passed clean from 930 * userspace in case we want to use it for something in the future. 931 * 932 * Sadly, this wasn't enforced for KVM_GET_SUPPORTED_CPUID and so we 933 * have to give ourselves satisfied only with the emulated side. /me 934 * sheds a tear. 935 */ 936 for (i = 0; i < num_entries; i++) { 937 if (copy_from_user(pad, entries[i].padding, sizeof(pad))) 938 return true; 939 940 if (pad[0] || pad[1] || pad[2]) 941 return true; 942 } 943 return false; 944 } 945 946 int kvm_dev_ioctl_get_cpuid(struct kvm_cpuid2 *cpuid, 947 struct kvm_cpuid_entry2 __user *entries, 948 unsigned int type) 949 { 950 static const u32 funcs[] = { 951 0, 0x80000000, CENTAUR_CPUID_SIGNATURE, KVM_CPUID_SIGNATURE, 952 }; 953 954 struct kvm_cpuid_array array = { 955 .nent = 0, 956 }; 957 int r, i; 958 959 if (cpuid->nent < 1) 960 return -E2BIG; 961 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES) 962 cpuid->nent = KVM_MAX_CPUID_ENTRIES; 963 964 if (sanity_check_entries(entries, cpuid->nent, type)) 965 return -EINVAL; 966 967 array.entries = vzalloc(array_size(sizeof(struct kvm_cpuid_entry2), 968 cpuid->nent)); 969 if (!array.entries) 970 return -ENOMEM; 971 972 array.maxnent = cpuid->nent; 973 974 for (i = 0; i < ARRAY_SIZE(funcs); i++) { 975 r = get_cpuid_func(&array, funcs[i], type); 976 if (r) 977 goto out_free; 978 } 979 cpuid->nent = array.nent; 980 981 if (copy_to_user(entries, array.entries, 982 array.nent * sizeof(struct kvm_cpuid_entry2))) 983 r = -EFAULT; 984 985 out_free: 986 vfree(array.entries); 987 return r; 988 } 989 990 struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu, 991 u32 function, u32 index) 992 { 993 return cpuid_entry2_find(vcpu->arch.cpuid_entries, vcpu->arch.cpuid_nent, 994 function, index); 995 } 996 EXPORT_SYMBOL_GPL(kvm_find_cpuid_entry); 997 998 /* 999 * Intel CPUID semantics treats any query for an out-of-range leaf as if the 1000 * highest basic leaf (i.e. CPUID.0H:EAX) were requested. AMD CPUID semantics 1001 * returns all zeroes for any undefined leaf, whether or not the leaf is in 1002 * range. Centaur/VIA follows Intel semantics. 1003 * 1004 * A leaf is considered out-of-range if its function is higher than the maximum 1005 * supported leaf of its associated class or if its associated class does not 1006 * exist. 1007 * 1008 * There are three primary classes to be considered, with their respective 1009 * ranges described as "<base> - <top>[,<base2> - <top2>] inclusive. A primary 1010 * class exists if a guest CPUID entry for its <base> leaf exists. For a given 1011 * class, CPUID.<base>.EAX contains the max supported leaf for the class. 1012 * 1013 * - Basic: 0x00000000 - 0x3fffffff, 0x50000000 - 0x7fffffff 1014 * - Hypervisor: 0x40000000 - 0x4fffffff 1015 * - Extended: 0x80000000 - 0xbfffffff 1016 * - Centaur: 0xc0000000 - 0xcfffffff 1017 * 1018 * The Hypervisor class is further subdivided into sub-classes that each act as 1019 * their own indepdent class associated with a 0x100 byte range. E.g. if Qemu 1020 * is advertising support for both HyperV and KVM, the resulting Hypervisor 1021 * CPUID sub-classes are: 1022 * 1023 * - HyperV: 0x40000000 - 0x400000ff 1024 * - KVM: 0x40000100 - 0x400001ff 1025 */ 1026 static struct kvm_cpuid_entry2 * 1027 get_out_of_range_cpuid_entry(struct kvm_vcpu *vcpu, u32 *fn_ptr, u32 index) 1028 { 1029 struct kvm_cpuid_entry2 *basic, *class; 1030 u32 function = *fn_ptr; 1031 1032 basic = kvm_find_cpuid_entry(vcpu, 0, 0); 1033 if (!basic) 1034 return NULL; 1035 1036 if (is_guest_vendor_amd(basic->ebx, basic->ecx, basic->edx) || 1037 is_guest_vendor_hygon(basic->ebx, basic->ecx, basic->edx)) 1038 return NULL; 1039 1040 if (function >= 0x40000000 && function <= 0x4fffffff) 1041 class = kvm_find_cpuid_entry(vcpu, function & 0xffffff00, 0); 1042 else if (function >= 0xc0000000) 1043 class = kvm_find_cpuid_entry(vcpu, 0xc0000000, 0); 1044 else 1045 class = kvm_find_cpuid_entry(vcpu, function & 0x80000000, 0); 1046 1047 if (class && function <= class->eax) 1048 return NULL; 1049 1050 /* 1051 * Leaf specific adjustments are also applied when redirecting to the 1052 * max basic entry, e.g. if the max basic leaf is 0xb but there is no 1053 * entry for CPUID.0xb.index (see below), then the output value for EDX 1054 * needs to be pulled from CPUID.0xb.1. 1055 */ 1056 *fn_ptr = basic->eax; 1057 1058 /* 1059 * The class does not exist or the requested function is out of range; 1060 * the effective CPUID entry is the max basic leaf. Note, the index of 1061 * the original requested leaf is observed! 1062 */ 1063 return kvm_find_cpuid_entry(vcpu, basic->eax, index); 1064 } 1065 1066 bool kvm_cpuid(struct kvm_vcpu *vcpu, u32 *eax, u32 *ebx, 1067 u32 *ecx, u32 *edx, bool exact_only) 1068 { 1069 u32 orig_function = *eax, function = *eax, index = *ecx; 1070 struct kvm_cpuid_entry2 *entry; 1071 bool exact, used_max_basic = false; 1072 1073 entry = kvm_find_cpuid_entry(vcpu, function, index); 1074 exact = !!entry; 1075 1076 if (!entry && !exact_only) { 1077 entry = get_out_of_range_cpuid_entry(vcpu, &function, index); 1078 used_max_basic = !!entry; 1079 } 1080 1081 if (entry) { 1082 *eax = entry->eax; 1083 *ebx = entry->ebx; 1084 *ecx = entry->ecx; 1085 *edx = entry->edx; 1086 if (function == 7 && index == 0) { 1087 u64 data; 1088 if (!__kvm_get_msr(vcpu, MSR_IA32_TSX_CTRL, &data, true) && 1089 (data & TSX_CTRL_CPUID_CLEAR)) 1090 *ebx &= ~(F(RTM) | F(HLE)); 1091 } 1092 } else { 1093 *eax = *ebx = *ecx = *edx = 0; 1094 /* 1095 * When leaf 0BH or 1FH is defined, CL is pass-through 1096 * and EDX is always the x2APIC ID, even for undefined 1097 * subleaves. Index 1 will exist iff the leaf is 1098 * implemented, so we pass through CL iff leaf 1 1099 * exists. EDX can be copied from any existing index. 1100 */ 1101 if (function == 0xb || function == 0x1f) { 1102 entry = kvm_find_cpuid_entry(vcpu, function, 1); 1103 if (entry) { 1104 *ecx = index & 0xff; 1105 *edx = entry->edx; 1106 } 1107 } 1108 } 1109 trace_kvm_cpuid(orig_function, index, *eax, *ebx, *ecx, *edx, exact, 1110 used_max_basic); 1111 return exact; 1112 } 1113 EXPORT_SYMBOL_GPL(kvm_cpuid); 1114 1115 int kvm_emulate_cpuid(struct kvm_vcpu *vcpu) 1116 { 1117 u32 eax, ebx, ecx, edx; 1118 1119 if (cpuid_fault_enabled(vcpu) && !kvm_require_cpl(vcpu, 0)) 1120 return 1; 1121 1122 eax = kvm_rax_read(vcpu); 1123 ecx = kvm_rcx_read(vcpu); 1124 kvm_cpuid(vcpu, &eax, &ebx, &ecx, &edx, false); 1125 kvm_rax_write(vcpu, eax); 1126 kvm_rbx_write(vcpu, ebx); 1127 kvm_rcx_write(vcpu, ecx); 1128 kvm_rdx_write(vcpu, edx); 1129 return kvm_skip_emulated_instruction(vcpu); 1130 } 1131 EXPORT_SYMBOL_GPL(kvm_emulate_cpuid); 1132