xref: /openbmc/linux/arch/x86/kernel/x86_init.c (revision bb0eb050) 
1 /*
2  * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de>
3  *
4  *  For licencing details see kernel-base/COPYING
5  */
6 #include <linux/init.h>
7 #include <linux/ioport.h>
8 #include <linux/export.h>
9 #include <linux/pci.h>
10 
11 #include <asm/bios_ebda.h>
12 #include <asm/paravirt.h>
13 #include <asm/pci_x86.h>
14 #include <asm/mpspec.h>
15 #include <asm/setup.h>
16 #include <asm/apic.h>
17 #include <asm/e820/api.h>
18 #include <asm/time.h>
19 #include <asm/irq.h>
20 #include <asm/io_apic.h>
21 #include <asm/hpet.h>
22 #include <asm/pat.h>
23 #include <asm/tsc.h>
24 #include <asm/iommu.h>
25 #include <asm/mach_traps.h>
26 
27 void x86_init_noop(void) { }
28 void __init x86_init_uint_noop(unsigned int unused) { }
29 int __init iommu_init_noop(void) { return 0; }
30 void iommu_shutdown_noop(void) { }
31 
32 /*
33  * The platform setup functions are preset with the default functions
34  * for standard PC hardware.
35  */
36 struct x86_init_ops x86_init __initdata = {
37 
38 	.resources = {
39 		.probe_roms		= probe_roms,
40 		.reserve_resources	= reserve_standard_io_resources,
41 		.memory_setup		= e820__memory_setup_default,
42 	},
43 
44 	.mpparse = {
45 		.mpc_record		= x86_init_uint_noop,
46 		.setup_ioapic_ids	= x86_init_noop,
47 		.mpc_apic_id		= default_mpc_apic_id,
48 		.smp_read_mpc_oem	= default_smp_read_mpc_oem,
49 		.mpc_oem_bus_info	= default_mpc_oem_bus_info,
50 		.find_smp_config	= default_find_smp_config,
51 		.get_smp_config		= default_get_smp_config,
52 	},
53 
54 	.irqs = {
55 		.pre_vector_init	= init_ISA_irqs,
56 		.intr_init		= native_init_IRQ,
57 		.trap_init		= x86_init_noop,
58 	},
59 
60 	.oem = {
61 		.arch_setup		= x86_init_noop,
62 		.banner			= default_banner,
63 	},
64 
65 	.paging = {
66 		.pagetable_init		= native_pagetable_init,
67 	},
68 
69 	.timers = {
70 		.setup_percpu_clockev	= setup_boot_APIC_clock,
71 		.timer_init		= hpet_time_init,
72 		.wallclock_init		= x86_init_noop,
73 	},
74 
75 	.iommu = {
76 		.iommu_init		= iommu_init_noop,
77 	},
78 
79 	.pci = {
80 		.init			= x86_default_pci_init,
81 		.init_irq		= x86_default_pci_init_irq,
82 		.fixup_irqs		= x86_default_pci_fixup_irqs,
83 	},
84 };
85 
86 struct x86_cpuinit_ops x86_cpuinit = {
87 	.early_percpu_clock_init	= x86_init_noop,
88 	.setup_percpu_clockev		= setup_secondary_APIC_clock,
89 };
90 
91 static void default_nmi_init(void) { };
92 
93 struct x86_platform_ops x86_platform __ro_after_init = {
94 	.calibrate_cpu			= native_calibrate_cpu,
95 	.calibrate_tsc			= native_calibrate_tsc,
96 	.get_wallclock			= mach_get_cmos_time,
97 	.set_wallclock			= mach_set_rtc_mmss,
98 	.iommu_shutdown			= iommu_shutdown_noop,
99 	.is_untracked_pat_range		= is_ISA_range,
100 	.nmi_init			= default_nmi_init,
101 	.get_nmi_reason			= default_get_nmi_reason,
102 	.save_sched_clock_state 	= tsc_save_sched_clock_state,
103 	.restore_sched_clock_state 	= tsc_restore_sched_clock_state,
104 };
105 
106 EXPORT_SYMBOL_GPL(x86_platform);
107 
108 #if defined(CONFIG_PCI_MSI)
109 struct x86_msi_ops x86_msi __ro_after_init = {
110 	.setup_msi_irqs		= native_setup_msi_irqs,
111 	.teardown_msi_irq	= native_teardown_msi_irq,
112 	.teardown_msi_irqs	= default_teardown_msi_irqs,
113 	.restore_msi_irqs	= default_restore_msi_irqs,
114 };
115 
116 /* MSI arch specific hooks */
117 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
118 {
119 	return x86_msi.setup_msi_irqs(dev, nvec, type);
120 }
121 
122 void arch_teardown_msi_irqs(struct pci_dev *dev)
123 {
124 	x86_msi.teardown_msi_irqs(dev);
125 }
126 
127 void arch_teardown_msi_irq(unsigned int irq)
128 {
129 	x86_msi.teardown_msi_irq(irq);
130 }
131 
132 void arch_restore_msi_irqs(struct pci_dev *dev)
133 {
134 	x86_msi.restore_msi_irqs(dev);
135 }
136 #endif
137 
138 struct x86_io_apic_ops x86_io_apic_ops __ro_after_init = {
139 	.read			= native_io_apic_read,
140 	.disable		= native_disable_io_apic,
141 };
142