1 /* 2 * Copyright (C) 2009 Thomas Gleixner <tglx@linutronix.de> 3 * 4 * For licencing details see kernel-base/COPYING 5 */ 6 #include <linux/init.h> 7 #include <linux/ioport.h> 8 #include <linux/export.h> 9 #include <linux/pci.h> 10 11 #include <asm/acpi.h> 12 #include <asm/bios_ebda.h> 13 #include <asm/paravirt.h> 14 #include <asm/pci_x86.h> 15 #include <asm/mpspec.h> 16 #include <asm/setup.h> 17 #include <asm/apic.h> 18 #include <asm/e820/api.h> 19 #include <asm/time.h> 20 #include <asm/irq.h> 21 #include <asm/io_apic.h> 22 #include <asm/hpet.h> 23 #include <asm/memtype.h> 24 #include <asm/tsc.h> 25 #include <asm/iommu.h> 26 #include <asm/mach_traps.h> 27 28 void x86_init_noop(void) { } 29 void __init x86_init_uint_noop(unsigned int unused) { } 30 static int __init iommu_init_noop(void) { return 0; } 31 static void iommu_shutdown_noop(void) { } 32 bool __init bool_x86_init_noop(void) { return false; } 33 void x86_op_int_noop(int cpu) { } 34 static __init int set_rtc_noop(const struct timespec64 *now) { return -EINVAL; } 35 static __init void get_rtc_noop(struct timespec64 *now) { } 36 37 static __initconst const struct of_device_id of_cmos_match[] = { 38 { .compatible = "motorola,mc146818" }, 39 {} 40 }; 41 42 /* 43 * Allow devicetree configured systems to disable the RTC by setting the 44 * corresponding DT node's status property to disabled. Code is optimized 45 * out for CONFIG_OF=n builds. 46 */ 47 static __init void x86_wallclock_init(void) 48 { 49 struct device_node *node = of_find_matching_node(NULL, of_cmos_match); 50 51 if (node && !of_device_is_available(node)) { 52 x86_platform.get_wallclock = get_rtc_noop; 53 x86_platform.set_wallclock = set_rtc_noop; 54 } 55 } 56 57 /* 58 * The platform setup functions are preset with the default functions 59 * for standard PC hardware. 60 */ 61 struct x86_init_ops x86_init __initdata = { 62 63 .resources = { 64 .probe_roms = probe_roms, 65 .reserve_resources = reserve_standard_io_resources, 66 .memory_setup = e820__memory_setup_default, 67 }, 68 69 .mpparse = { 70 .mpc_record = x86_init_uint_noop, 71 .setup_ioapic_ids = x86_init_noop, 72 .mpc_apic_id = default_mpc_apic_id, 73 .smp_read_mpc_oem = default_smp_read_mpc_oem, 74 .mpc_oem_bus_info = default_mpc_oem_bus_info, 75 .find_smp_config = default_find_smp_config, 76 .get_smp_config = default_get_smp_config, 77 }, 78 79 .irqs = { 80 .pre_vector_init = init_ISA_irqs, 81 .intr_init = native_init_IRQ, 82 .trap_init = x86_init_noop, 83 .intr_mode_select = apic_intr_mode_select, 84 .intr_mode_init = apic_intr_mode_init 85 }, 86 87 .oem = { 88 .arch_setup = x86_init_noop, 89 .banner = default_banner, 90 }, 91 92 .paging = { 93 .pagetable_init = native_pagetable_init, 94 }, 95 96 .timers = { 97 .setup_percpu_clockev = setup_boot_APIC_clock, 98 .timer_init = hpet_time_init, 99 .wallclock_init = x86_wallclock_init, 100 }, 101 102 .iommu = { 103 .iommu_init = iommu_init_noop, 104 }, 105 106 .pci = { 107 .init = x86_default_pci_init, 108 .init_irq = x86_default_pci_init_irq, 109 .fixup_irqs = x86_default_pci_fixup_irqs, 110 }, 111 112 .hyper = { 113 .init_platform = x86_init_noop, 114 .guest_late_init = x86_init_noop, 115 .x2apic_available = bool_x86_init_noop, 116 .init_mem_mapping = x86_init_noop, 117 .init_after_bootmem = x86_init_noop, 118 }, 119 120 .acpi = { 121 .set_root_pointer = x86_default_set_root_pointer, 122 .get_root_pointer = x86_default_get_root_pointer, 123 .reduced_hw_early_init = acpi_generic_reduced_hw_init, 124 }, 125 }; 126 127 struct x86_cpuinit_ops x86_cpuinit = { 128 .early_percpu_clock_init = x86_init_noop, 129 .setup_percpu_clockev = setup_secondary_APIC_clock, 130 }; 131 132 static void default_nmi_init(void) { }; 133 134 struct x86_platform_ops x86_platform __ro_after_init = { 135 .calibrate_cpu = native_calibrate_cpu_early, 136 .calibrate_tsc = native_calibrate_tsc, 137 .get_wallclock = mach_get_cmos_time, 138 .set_wallclock = mach_set_rtc_mmss, 139 .iommu_shutdown = iommu_shutdown_noop, 140 .is_untracked_pat_range = is_ISA_range, 141 .nmi_init = default_nmi_init, 142 .get_nmi_reason = default_get_nmi_reason, 143 .save_sched_clock_state = tsc_save_sched_clock_state, 144 .restore_sched_clock_state = tsc_restore_sched_clock_state, 145 .hyper.pin_vcpu = x86_op_int_noop, 146 }; 147 148 EXPORT_SYMBOL_GPL(x86_platform); 149 150 #if defined(CONFIG_PCI_MSI) 151 struct x86_msi_ops x86_msi __ro_after_init = { 152 .setup_msi_irqs = native_setup_msi_irqs, 153 .teardown_msi_irq = native_teardown_msi_irq, 154 .teardown_msi_irqs = default_teardown_msi_irqs, 155 .restore_msi_irqs = default_restore_msi_irqs, 156 }; 157 158 /* MSI arch specific hooks */ 159 int arch_setup_msi_irqs(struct pci_dev *dev, int nvec, int type) 160 { 161 return x86_msi.setup_msi_irqs(dev, nvec, type); 162 } 163 164 void arch_teardown_msi_irqs(struct pci_dev *dev) 165 { 166 x86_msi.teardown_msi_irqs(dev); 167 } 168 169 void arch_teardown_msi_irq(unsigned int irq) 170 { 171 x86_msi.teardown_msi_irq(irq); 172 } 173 174 void arch_restore_msi_irqs(struct pci_dev *dev) 175 { 176 x86_msi.restore_msi_irqs(dev); 177 } 178 #endif 179 180 struct x86_apic_ops x86_apic_ops __ro_after_init = { 181 .io_apic_read = native_io_apic_read, 182 .restore = native_restore_boot_irq_mode, 183 }; 184