1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * ld script for the x86 kernel 4 * 5 * Historic 32-bit version written by Martin Mares <mj@atrey.karlin.mff.cuni.cz> 6 * 7 * Modernisation, unification and other changes and fixes: 8 * Copyright (C) 2007-2009 Sam Ravnborg <sam@ravnborg.org> 9 * 10 * 11 * Don't define absolute symbols until and unless you know that symbol 12 * value is should remain constant even if kernel image is relocated 13 * at run time. Absolute symbols are not relocated. If symbol value should 14 * change if kernel is relocated, make the symbol section relative and 15 * put it inside the section definition. 16 */ 17 18#ifdef CONFIG_X86_32 19#define LOAD_OFFSET __PAGE_OFFSET 20#else 21#define LOAD_OFFSET __START_KERNEL_map 22#endif 23 24#define RUNTIME_DISCARD_EXIT 25#define EMITS_PT_NOTE 26#define RO_EXCEPTION_TABLE_ALIGN 16 27 28#include <asm-generic/vmlinux.lds.h> 29#include <asm/asm-offsets.h> 30#include <asm/thread_info.h> 31#include <asm/page_types.h> 32#include <asm/orc_lookup.h> 33#include <asm/cache.h> 34#include <asm/boot.h> 35 36#undef i386 /* in case the preprocessor is a 32bit one */ 37 38OUTPUT_FORMAT(CONFIG_OUTPUT_FORMAT) 39 40#ifdef CONFIG_X86_32 41OUTPUT_ARCH(i386) 42ENTRY(phys_startup_32) 43#else 44OUTPUT_ARCH(i386:x86-64) 45ENTRY(phys_startup_64) 46#endif 47 48jiffies = jiffies_64; 49 50#if defined(CONFIG_X86_64) 51/* 52 * On 64-bit, align RODATA to 2MB so we retain large page mappings for 53 * boundaries spanning kernel text, rodata and data sections. 54 * 55 * However, kernel identity mappings will have different RWX permissions 56 * to the pages mapping to text and to the pages padding (which are freed) the 57 * text section. Hence kernel identity mappings will be broken to smaller 58 * pages. For 64-bit, kernel text and kernel identity mappings are different, 59 * so we can enable protection checks as well as retain 2MB large page 60 * mappings for kernel text. 61 */ 62#define X86_ALIGN_RODATA_BEGIN . = ALIGN(HPAGE_SIZE); 63 64#define X86_ALIGN_RODATA_END \ 65 . = ALIGN(HPAGE_SIZE); \ 66 __end_rodata_hpage_align = .; \ 67 __end_rodata_aligned = .; 68 69#define ALIGN_ENTRY_TEXT_BEGIN . = ALIGN(PMD_SIZE); 70#define ALIGN_ENTRY_TEXT_END . = ALIGN(PMD_SIZE); 71 72/* 73 * This section contains data which will be mapped as decrypted. Memory 74 * encryption operates on a page basis. Make this section PMD-aligned 75 * to avoid splitting the pages while mapping the section early. 76 * 77 * Note: We use a separate section so that only this section gets 78 * decrypted to avoid exposing more than we wish. 79 */ 80#define BSS_DECRYPTED \ 81 . = ALIGN(PMD_SIZE); \ 82 __start_bss_decrypted = .; \ 83 *(.bss..decrypted); \ 84 . = ALIGN(PAGE_SIZE); \ 85 __start_bss_decrypted_unused = .; \ 86 . = ALIGN(PMD_SIZE); \ 87 __end_bss_decrypted = .; \ 88 89#else 90 91#define X86_ALIGN_RODATA_BEGIN 92#define X86_ALIGN_RODATA_END \ 93 . = ALIGN(PAGE_SIZE); \ 94 __end_rodata_aligned = .; 95 96#define ALIGN_ENTRY_TEXT_BEGIN 97#define ALIGN_ENTRY_TEXT_END 98#define BSS_DECRYPTED 99 100#endif 101 102PHDRS { 103 text PT_LOAD FLAGS(5); /* R_E */ 104 data PT_LOAD FLAGS(6); /* RW_ */ 105#ifdef CONFIG_X86_64 106#ifdef CONFIG_SMP 107 percpu PT_LOAD FLAGS(6); /* RW_ */ 108#endif 109 init PT_LOAD FLAGS(7); /* RWE */ 110#endif 111 note PT_NOTE FLAGS(0); /* ___ */ 112} 113 114SECTIONS 115{ 116#ifdef CONFIG_X86_32 117 . = LOAD_OFFSET + LOAD_PHYSICAL_ADDR; 118 phys_startup_32 = ABSOLUTE(startup_32 - LOAD_OFFSET); 119#else 120 . = __START_KERNEL; 121 phys_startup_64 = ABSOLUTE(startup_64 - LOAD_OFFSET); 122#endif 123 124 /* Text and read-only data */ 125 .text : AT(ADDR(.text) - LOAD_OFFSET) { 126 _text = .; 127 _stext = .; 128 /* bootstrapping code */ 129 HEAD_TEXT 130 TEXT_TEXT 131 SCHED_TEXT 132 LOCK_TEXT 133 KPROBES_TEXT 134 SOFTIRQENTRY_TEXT 135#ifdef CONFIG_RETPOLINE 136 __indirect_thunk_start = .; 137 *(.text.__x86.indirect_thunk) 138 *(.text.__x86.return_thunk) 139 __indirect_thunk_end = .; 140#endif 141 STATIC_CALL_TEXT 142 143 ALIGN_ENTRY_TEXT_BEGIN 144#ifdef CONFIG_CPU_SRSO 145 *(.text.__x86.rethunk_untrain) 146#endif 147 148 ENTRY_TEXT 149 150#ifdef CONFIG_CPU_SRSO 151 /* 152 * See the comment above srso_untrain_ret_alias()'s 153 * definition. 154 */ 155 . = srso_untrain_ret_alias | (1 << 2) | (1 << 8) | (1 << 14) | (1 << 20); 156 *(.text.__x86.rethunk_safe) 157#endif 158 ALIGN_ENTRY_TEXT_END 159 *(.gnu.warning) 160 161 } :text =0xcccc 162 163 /* End of text section, which should occupy whole number of pages */ 164 _etext = .; 165 . = ALIGN(PAGE_SIZE); 166 167 X86_ALIGN_RODATA_BEGIN 168 RO_DATA(PAGE_SIZE) 169 X86_ALIGN_RODATA_END 170 171 /* Data */ 172 .data : AT(ADDR(.data) - LOAD_OFFSET) { 173 /* Start of data section */ 174 _sdata = .; 175 176 /* init_task */ 177 INIT_TASK_DATA(THREAD_SIZE) 178 179#ifdef CONFIG_X86_32 180 /* 32 bit has nosave before _edata */ 181 NOSAVE_DATA 182#endif 183 184 PAGE_ALIGNED_DATA(PAGE_SIZE) 185 186 CACHELINE_ALIGNED_DATA(L1_CACHE_BYTES) 187 188 DATA_DATA 189 CONSTRUCTORS 190 191 /* rarely changed data like cpu maps */ 192 READ_MOSTLY_DATA(INTERNODE_CACHE_BYTES) 193 194 /* End of data section */ 195 _edata = .; 196 } :data 197 198 BUG_TABLE 199 200 ORC_UNWIND_TABLE 201 202 . = ALIGN(PAGE_SIZE); 203 __vvar_page = .; 204 205 .vvar : AT(ADDR(.vvar) - LOAD_OFFSET) { 206 /* work around gold bug 13023 */ 207 __vvar_beginning_hack = .; 208 209 /* Place all vvars at the offsets in asm/vvar.h. */ 210#define EMIT_VVAR(name, offset) \ 211 . = __vvar_beginning_hack + offset; \ 212 *(.vvar_ ## name) 213#include <asm/vvar.h> 214#undef EMIT_VVAR 215 216 /* 217 * Pad the rest of the page with zeros. Otherwise the loader 218 * can leave garbage here. 219 */ 220 . = __vvar_beginning_hack + PAGE_SIZE; 221 } :data 222 223 . = ALIGN(__vvar_page + PAGE_SIZE, PAGE_SIZE); 224 225 /* Init code and data - will be freed after init */ 226 . = ALIGN(PAGE_SIZE); 227 .init.begin : AT(ADDR(.init.begin) - LOAD_OFFSET) { 228 __init_begin = .; /* paired with __init_end */ 229 } 230 231#if defined(CONFIG_X86_64) && defined(CONFIG_SMP) 232 /* 233 * percpu offsets are zero-based on SMP. PERCPU_VADDR() changes the 234 * output PHDR, so the next output section - .init.text - should 235 * start another segment - init. 236 */ 237 PERCPU_VADDR(INTERNODE_CACHE_BYTES, 0, :percpu) 238 ASSERT(SIZEOF(.data..percpu) < CONFIG_PHYSICAL_START, 239 "per-CPU data too large - increase CONFIG_PHYSICAL_START") 240#endif 241 242 INIT_TEXT_SECTION(PAGE_SIZE) 243#ifdef CONFIG_X86_64 244 :init 245#endif 246 247 /* 248 * Section for code used exclusively before alternatives are run. All 249 * references to such code must be patched out by alternatives, normally 250 * by using X86_FEATURE_ALWAYS CPU feature bit. 251 * 252 * See static_cpu_has() for an example. 253 */ 254 .altinstr_aux : AT(ADDR(.altinstr_aux) - LOAD_OFFSET) { 255 *(.altinstr_aux) 256 } 257 258 INIT_DATA_SECTION(16) 259 260 .x86_cpu_dev.init : AT(ADDR(.x86_cpu_dev.init) - LOAD_OFFSET) { 261 __x86_cpu_dev_start = .; 262 *(.x86_cpu_dev.init) 263 __x86_cpu_dev_end = .; 264 } 265 266#ifdef CONFIG_X86_INTEL_MID 267 .x86_intel_mid_dev.init : AT(ADDR(.x86_intel_mid_dev.init) - \ 268 LOAD_OFFSET) { 269 __x86_intel_mid_dev_start = .; 270 *(.x86_intel_mid_dev.init) 271 __x86_intel_mid_dev_end = .; 272 } 273#endif 274 275 /* 276 * start address and size of operations which during runtime 277 * can be patched with virtualization friendly instructions or 278 * baremetal native ones. Think page table operations. 279 * Details in paravirt_types.h 280 */ 281 . = ALIGN(8); 282 .parainstructions : AT(ADDR(.parainstructions) - LOAD_OFFSET) { 283 __parainstructions = .; 284 *(.parainstructions) 285 __parainstructions_end = .; 286 } 287 288#ifdef CONFIG_RETPOLINE 289 /* 290 * List of instructions that call/jmp/jcc to retpoline thunks 291 * __x86_indirect_thunk_*(). These instructions can be patched along 292 * with alternatives, after which the section can be freed. 293 */ 294 . = ALIGN(8); 295 .retpoline_sites : AT(ADDR(.retpoline_sites) - LOAD_OFFSET) { 296 __retpoline_sites = .; 297 *(.retpoline_sites) 298 __retpoline_sites_end = .; 299 } 300 301 . = ALIGN(8); 302 .return_sites : AT(ADDR(.return_sites) - LOAD_OFFSET) { 303 __return_sites = .; 304 *(.return_sites) 305 __return_sites_end = .; 306 } 307 308 . = ALIGN(8); 309 .call_sites : AT(ADDR(.call_sites) - LOAD_OFFSET) { 310 __call_sites = .; 311 *(.call_sites) 312 __call_sites_end = .; 313 } 314#endif 315 316#ifdef CONFIG_X86_KERNEL_IBT 317 . = ALIGN(8); 318 .ibt_endbr_seal : AT(ADDR(.ibt_endbr_seal) - LOAD_OFFSET) { 319 __ibt_endbr_seal = .; 320 *(.ibt_endbr_seal) 321 __ibt_endbr_seal_end = .; 322 } 323#endif 324 325#ifdef CONFIG_FINEIBT 326 . = ALIGN(8); 327 .cfi_sites : AT(ADDR(.cfi_sites) - LOAD_OFFSET) { 328 __cfi_sites = .; 329 *(.cfi_sites) 330 __cfi_sites_end = .; 331 } 332#endif 333 334 /* 335 * struct alt_inst entries. From the header (alternative.h): 336 * "Alternative instructions for different CPU types or capabilities" 337 * Think locking instructions on spinlocks. 338 */ 339 . = ALIGN(8); 340 .altinstructions : AT(ADDR(.altinstructions) - LOAD_OFFSET) { 341 __alt_instructions = .; 342 *(.altinstructions) 343 __alt_instructions_end = .; 344 } 345 346 /* 347 * And here are the replacement instructions. The linker sticks 348 * them as binary blobs. The .altinstructions has enough data to 349 * get the address and the length of them to patch the kernel safely. 350 */ 351 .altinstr_replacement : AT(ADDR(.altinstr_replacement) - LOAD_OFFSET) { 352 *(.altinstr_replacement) 353 } 354 355 . = ALIGN(8); 356 .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) { 357 __apicdrivers = .; 358 *(.apicdrivers); 359 __apicdrivers_end = .; 360 } 361 362 . = ALIGN(8); 363 /* 364 * .exit.text is discarded at runtime, not link time, to deal with 365 * references from .altinstructions 366 */ 367 .exit.text : AT(ADDR(.exit.text) - LOAD_OFFSET) { 368 EXIT_TEXT 369 } 370 371 .exit.data : AT(ADDR(.exit.data) - LOAD_OFFSET) { 372 EXIT_DATA 373 } 374 375#if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP) 376 PERCPU_SECTION(INTERNODE_CACHE_BYTES) 377#endif 378 379 . = ALIGN(PAGE_SIZE); 380 381 /* freed after init ends here */ 382 .init.end : AT(ADDR(.init.end) - LOAD_OFFSET) { 383 __init_end = .; 384 } 385 386 /* 387 * smp_locks might be freed after init 388 * start/end must be page aligned 389 */ 390 . = ALIGN(PAGE_SIZE); 391 .smp_locks : AT(ADDR(.smp_locks) - LOAD_OFFSET) { 392 __smp_locks = .; 393 *(.smp_locks) 394 . = ALIGN(PAGE_SIZE); 395 __smp_locks_end = .; 396 } 397 398#ifdef CONFIG_X86_64 399 .data_nosave : AT(ADDR(.data_nosave) - LOAD_OFFSET) { 400 NOSAVE_DATA 401 } 402#endif 403 404 /* BSS */ 405 . = ALIGN(PAGE_SIZE); 406 .bss : AT(ADDR(.bss) - LOAD_OFFSET) { 407 __bss_start = .; 408 *(.bss..page_aligned) 409 . = ALIGN(PAGE_SIZE); 410 *(BSS_MAIN) 411 BSS_DECRYPTED 412 . = ALIGN(PAGE_SIZE); 413 __bss_stop = .; 414 } 415 416 /* 417 * The memory occupied from _text to here, __end_of_kernel_reserve, is 418 * automatically reserved in setup_arch(). Anything after here must be 419 * explicitly reserved using memblock_reserve() or it will be discarded 420 * and treated as available memory. 421 */ 422 __end_of_kernel_reserve = .; 423 424 . = ALIGN(PAGE_SIZE); 425 .brk : AT(ADDR(.brk) - LOAD_OFFSET) { 426 __brk_base = .; 427 . += 64 * 1024; /* 64k alignment slop space */ 428 *(.bss..brk) /* areas brk users have reserved */ 429 __brk_limit = .; 430 } 431 432 . = ALIGN(PAGE_SIZE); /* keep VO_INIT_SIZE page aligned */ 433 _end = .; 434 435#ifdef CONFIG_AMD_MEM_ENCRYPT 436 /* 437 * Early scratch/workarea section: Lives outside of the kernel proper 438 * (_text - _end). 439 * 440 * Resides after _end because even though the .brk section is after 441 * __end_of_kernel_reserve, the .brk section is later reserved as a 442 * part of the kernel. Since it is located after __end_of_kernel_reserve 443 * it will be discarded and become part of the available memory. As 444 * such, it can only be used by very early boot code and must not be 445 * needed afterwards. 446 * 447 * Currently used by SME for performing in-place encryption of the 448 * kernel during boot. Resides on a 2MB boundary to simplify the 449 * pagetable setup used for SME in-place encryption. 450 */ 451 . = ALIGN(HPAGE_SIZE); 452 .init.scratch : AT(ADDR(.init.scratch) - LOAD_OFFSET) { 453 __init_scratch_begin = .; 454 *(.init.scratch) 455 . = ALIGN(HPAGE_SIZE); 456 __init_scratch_end = .; 457 } 458#endif 459 460 STABS_DEBUG 461 DWARF_DEBUG 462 ELF_DETAILS 463 464 DISCARDS 465 466 /* 467 * Make sure that the .got.plt is either completely empty or it 468 * contains only the lazy dispatch entries. 469 */ 470 .got.plt (INFO) : { *(.got.plt) } 471 ASSERT(SIZEOF(.got.plt) == 0 || 472#ifdef CONFIG_X86_64 473 SIZEOF(.got.plt) == 0x18, 474#else 475 SIZEOF(.got.plt) == 0xc, 476#endif 477 "Unexpected GOT/PLT entries detected!") 478 479 /* 480 * Sections that should stay zero sized, which is safer to 481 * explicitly check instead of blindly discarding. 482 */ 483 .got : { 484 *(.got) *(.igot.*) 485 } 486 ASSERT(SIZEOF(.got) == 0, "Unexpected GOT entries detected!") 487 488 .plt : { 489 *(.plt) *(.plt.*) *(.iplt) 490 } 491 ASSERT(SIZEOF(.plt) == 0, "Unexpected run-time procedure linkages detected!") 492 493 .rel.dyn : { 494 *(.rel.*) *(.rel_*) 495 } 496 ASSERT(SIZEOF(.rel.dyn) == 0, "Unexpected run-time relocations (.rel) detected!") 497 498 .rela.dyn : { 499 *(.rela.*) *(.rela_*) 500 } 501 ASSERT(SIZEOF(.rela.dyn) == 0, "Unexpected run-time relocations (.rela) detected!") 502} 503 504/* 505 * The ASSERT() sink to . is intentional, for binutils 2.14 compatibility: 506 */ 507. = ASSERT((_end - LOAD_OFFSET <= KERNEL_IMAGE_SIZE), 508 "kernel image bigger than KERNEL_IMAGE_SIZE"); 509 510#ifdef CONFIG_X86_64 511/* 512 * Per-cpu symbols which need to be offset from __per_cpu_load 513 * for the boot processor. 514 */ 515#define INIT_PER_CPU(x) init_per_cpu__##x = ABSOLUTE(x) + __per_cpu_load 516INIT_PER_CPU(gdt_page); 517INIT_PER_CPU(fixed_percpu_data); 518INIT_PER_CPU(irq_stack_backing_store); 519 520#ifdef CONFIG_SMP 521. = ASSERT((fixed_percpu_data == 0), 522 "fixed_percpu_data is not at start of per-cpu area"); 523#endif 524 525#ifdef CONFIG_RETHUNK 526. = ASSERT((__ret & 0x3f) == 0, "__ret not cacheline-aligned"); 527. = ASSERT((srso_safe_ret & 0x3f) == 0, "srso_safe_ret not cacheline-aligned"); 528#endif 529 530#ifdef CONFIG_CPU_SRSO 531/* 532 * GNU ld cannot do XOR until 2.41. 533 * https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=f6f78318fca803c4907fb8d7f6ded8295f1947b1 534 * 535 * LLVM lld cannot do XOR until lld-17. 536 * https://github.com/llvm/llvm-project/commit/fae96104d4378166cbe5c875ef8ed808a356f3fb 537 * 538 * Instead do: (A | B) - (A & B) in order to compute the XOR 539 * of the two function addresses: 540 */ 541. = ASSERT(((ABSOLUTE(srso_untrain_ret_alias) | srso_safe_ret_alias) - 542 (ABSOLUTE(srso_untrain_ret_alias) & srso_safe_ret_alias)) == ((1 << 2) | (1 << 8) | (1 << 14) | (1 << 20)), 543 "SRSO function pair won't alias"); 544#endif 545 546#endif /* CONFIG_X86_64 */ 547