1 /* 2 * check TSC synchronization. 3 * 4 * Copyright (C) 2006, Red Hat, Inc., Ingo Molnar 5 * 6 * We check whether all boot CPUs have their TSC's synchronized, 7 * print a warning if not and turn off the TSC clock-source. 8 * 9 * The warp-check is point-to-point between two CPUs, the CPU 10 * initiating the bootup is the 'source CPU', the freshly booting 11 * CPU is the 'target CPU'. 12 * 13 * Only two CPUs may participate - they can enter in any order. 14 * ( The serial nature of the boot logic and the CPU hotplug lock 15 * protects against more than 2 CPUs entering this code. ) 16 */ 17 #include <linux/topology.h> 18 #include <linux/spinlock.h> 19 #include <linux/kernel.h> 20 #include <linux/smp.h> 21 #include <linux/nmi.h> 22 #include <asm/tsc.h> 23 24 struct tsc_adjust { 25 s64 bootval; 26 s64 adjusted; 27 unsigned long nextcheck; 28 bool warned; 29 }; 30 31 static DEFINE_PER_CPU(struct tsc_adjust, tsc_adjust); 32 33 /* 34 * TSC's on different sockets may be reset asynchronously. 35 * This may cause the TSC ADJUST value on socket 0 to be NOT 0. 36 */ 37 bool __read_mostly tsc_async_resets; 38 39 void mark_tsc_async_resets(char *reason) 40 { 41 if (tsc_async_resets) 42 return; 43 tsc_async_resets = true; 44 pr_info("tsc: Marking TSC async resets true due to %s\n", reason); 45 } 46 47 void tsc_verify_tsc_adjust(bool resume) 48 { 49 struct tsc_adjust *adj = this_cpu_ptr(&tsc_adjust); 50 s64 curval; 51 52 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST)) 53 return; 54 55 /* Skip unnecessary error messages if TSC already unstable */ 56 if (check_tsc_unstable()) 57 return; 58 59 /* Rate limit the MSR check */ 60 if (!resume && time_before(jiffies, adj->nextcheck)) 61 return; 62 63 adj->nextcheck = jiffies + HZ; 64 65 rdmsrl(MSR_IA32_TSC_ADJUST, curval); 66 if (adj->adjusted == curval) 67 return; 68 69 /* Restore the original value */ 70 wrmsrl(MSR_IA32_TSC_ADJUST, adj->adjusted); 71 72 if (!adj->warned || resume) { 73 pr_warn(FW_BUG "TSC ADJUST differs: CPU%u %lld --> %lld. Restoring\n", 74 smp_processor_id(), adj->adjusted, curval); 75 adj->warned = true; 76 } 77 } 78 79 static void tsc_sanitize_first_cpu(struct tsc_adjust *cur, s64 bootval, 80 unsigned int cpu, bool bootcpu) 81 { 82 /* 83 * First online CPU in a package stores the boot value in the 84 * adjustment value. This value might change later via the sync 85 * mechanism. If that fails we still can yell about boot values not 86 * being consistent. 87 * 88 * On the boot cpu we just force set the ADJUST value to 0 if it's 89 * non zero. We don't do that on non boot cpus because physical 90 * hotplug should have set the ADJUST register to a value > 0 so 91 * the TSC is in sync with the already running cpus. 92 * 93 * Also don't force the ADJUST value to zero if that is a valid value 94 * for socket 0 as determined by the system arch. This is required 95 * when multiple sockets are reset asynchronously with each other 96 * and socket 0 may not have an TSC ADJUST value of 0. 97 */ 98 if (bootcpu && bootval != 0) { 99 if (likely(!tsc_async_resets)) { 100 pr_warn(FW_BUG "TSC ADJUST: CPU%u: %lld force to 0\n", 101 cpu, bootval); 102 wrmsrl(MSR_IA32_TSC_ADJUST, 0); 103 bootval = 0; 104 } else { 105 pr_info("TSC ADJUST: CPU%u: %lld NOT forced to 0\n", 106 cpu, bootval); 107 } 108 } 109 cur->adjusted = bootval; 110 } 111 112 #ifndef CONFIG_SMP 113 bool __init tsc_store_and_check_tsc_adjust(bool bootcpu) 114 { 115 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust); 116 s64 bootval; 117 118 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST)) 119 return false; 120 121 /* Skip unnecessary error messages if TSC already unstable */ 122 if (check_tsc_unstable()) 123 return false; 124 125 rdmsrl(MSR_IA32_TSC_ADJUST, bootval); 126 cur->bootval = bootval; 127 cur->nextcheck = jiffies + HZ; 128 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), bootcpu); 129 return false; 130 } 131 132 #else /* !CONFIG_SMP */ 133 134 /* 135 * Store and check the TSC ADJUST MSR if available 136 */ 137 bool tsc_store_and_check_tsc_adjust(bool bootcpu) 138 { 139 struct tsc_adjust *ref, *cur = this_cpu_ptr(&tsc_adjust); 140 unsigned int refcpu, cpu = smp_processor_id(); 141 struct cpumask *mask; 142 s64 bootval; 143 144 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST)) 145 return false; 146 147 rdmsrl(MSR_IA32_TSC_ADJUST, bootval); 148 cur->bootval = bootval; 149 cur->nextcheck = jiffies + HZ; 150 cur->warned = false; 151 152 /* 153 * If a non-zero TSC value for socket 0 may be valid then the default 154 * adjusted value cannot assumed to be zero either. 155 */ 156 if (tsc_async_resets) 157 cur->adjusted = bootval; 158 159 /* 160 * Check whether this CPU is the first in a package to come up. In 161 * this case do not check the boot value against another package 162 * because the new package might have been physically hotplugged, 163 * where TSC_ADJUST is expected to be different. When called on the 164 * boot CPU topology_core_cpumask() might not be available yet. 165 */ 166 mask = topology_core_cpumask(cpu); 167 refcpu = mask ? cpumask_any_but(mask, cpu) : nr_cpu_ids; 168 169 if (refcpu >= nr_cpu_ids) { 170 tsc_sanitize_first_cpu(cur, bootval, smp_processor_id(), 171 bootcpu); 172 return false; 173 } 174 175 ref = per_cpu_ptr(&tsc_adjust, refcpu); 176 /* 177 * Compare the boot value and complain if it differs in the 178 * package. 179 */ 180 if (bootval != ref->bootval) 181 printk_once(FW_BUG "TSC ADJUST differs within socket(s), fixing all errors\n"); 182 183 /* 184 * The TSC_ADJUST values in a package must be the same. If the boot 185 * value on this newly upcoming CPU differs from the adjustment 186 * value of the already online CPU in this package, set it to that 187 * adjusted value. 188 */ 189 if (bootval != ref->adjusted) { 190 cur->adjusted = ref->adjusted; 191 wrmsrl(MSR_IA32_TSC_ADJUST, ref->adjusted); 192 } 193 /* 194 * We have the TSCs forced to be in sync on this package. Skip sync 195 * test: 196 */ 197 return true; 198 } 199 200 /* 201 * Entry/exit counters that make sure that both CPUs 202 * run the measurement code at once: 203 */ 204 static atomic_t start_count; 205 static atomic_t stop_count; 206 static atomic_t skip_test; 207 static atomic_t test_runs; 208 209 /* 210 * We use a raw spinlock in this exceptional case, because 211 * we want to have the fastest, inlined, non-debug version 212 * of a critical section, to be able to prove TSC time-warps: 213 */ 214 static arch_spinlock_t sync_lock = __ARCH_SPIN_LOCK_UNLOCKED; 215 216 static cycles_t last_tsc; 217 static cycles_t max_warp; 218 static int nr_warps; 219 static int random_warps; 220 221 /* 222 * TSC-warp measurement loop running on both CPUs. This is not called 223 * if there is no TSC. 224 */ 225 static cycles_t check_tsc_warp(unsigned int timeout) 226 { 227 cycles_t start, now, prev, end, cur_max_warp = 0; 228 int i, cur_warps = 0; 229 230 start = rdtsc_ordered(); 231 /* 232 * The measurement runs for 'timeout' msecs: 233 */ 234 end = start + (cycles_t) tsc_khz * timeout; 235 now = start; 236 237 for (i = 0; ; i++) { 238 /* 239 * We take the global lock, measure TSC, save the 240 * previous TSC that was measured (possibly on 241 * another CPU) and update the previous TSC timestamp. 242 */ 243 arch_spin_lock(&sync_lock); 244 prev = last_tsc; 245 now = rdtsc_ordered(); 246 last_tsc = now; 247 arch_spin_unlock(&sync_lock); 248 249 /* 250 * Be nice every now and then (and also check whether 251 * measurement is done [we also insert a 10 million 252 * loops safety exit, so we dont lock up in case the 253 * TSC readout is totally broken]): 254 */ 255 if (unlikely(!(i & 7))) { 256 if (now > end || i > 10000000) 257 break; 258 cpu_relax(); 259 touch_nmi_watchdog(); 260 } 261 /* 262 * Outside the critical section we can now see whether 263 * we saw a time-warp of the TSC going backwards: 264 */ 265 if (unlikely(prev > now)) { 266 arch_spin_lock(&sync_lock); 267 max_warp = max(max_warp, prev - now); 268 cur_max_warp = max_warp; 269 /* 270 * Check whether this bounces back and forth. Only 271 * one CPU should observe time going backwards. 272 */ 273 if (cur_warps != nr_warps) 274 random_warps++; 275 nr_warps++; 276 cur_warps = nr_warps; 277 arch_spin_unlock(&sync_lock); 278 } 279 } 280 WARN(!(now-start), 281 "Warning: zero tsc calibration delta: %Ld [max: %Ld]\n", 282 now-start, end-start); 283 return cur_max_warp; 284 } 285 286 /* 287 * If the target CPU coming online doesn't have any of its core-siblings 288 * online, a timeout of 20msec will be used for the TSC-warp measurement 289 * loop. Otherwise a smaller timeout of 2msec will be used, as we have some 290 * information about this socket already (and this information grows as we 291 * have more and more logical-siblings in that socket). 292 * 293 * Ideally we should be able to skip the TSC sync check on the other 294 * core-siblings, if the first logical CPU in a socket passed the sync test. 295 * But as the TSC is per-logical CPU and can potentially be modified wrongly 296 * by the bios, TSC sync test for smaller duration should be able 297 * to catch such errors. Also this will catch the condition where all the 298 * cores in the socket doesn't get reset at the same time. 299 */ 300 static inline unsigned int loop_timeout(int cpu) 301 { 302 return (cpumask_weight(topology_core_cpumask(cpu)) > 1) ? 2 : 20; 303 } 304 305 /* 306 * Source CPU calls into this - it waits for the freshly booted 307 * target CPU to arrive and then starts the measurement: 308 */ 309 void check_tsc_sync_source(int cpu) 310 { 311 int cpus = 2; 312 313 /* 314 * No need to check if we already know that the TSC is not 315 * synchronized or if we have no TSC. 316 */ 317 if (unsynchronized_tsc()) 318 return; 319 320 /* 321 * Set the maximum number of test runs to 322 * 1 if the CPU does not provide the TSC_ADJUST MSR 323 * 3 if the MSR is available, so the target can try to adjust 324 */ 325 if (!boot_cpu_has(X86_FEATURE_TSC_ADJUST)) 326 atomic_set(&test_runs, 1); 327 else 328 atomic_set(&test_runs, 3); 329 retry: 330 /* 331 * Wait for the target to start or to skip the test: 332 */ 333 while (atomic_read(&start_count) != cpus - 1) { 334 if (atomic_read(&skip_test) > 0) { 335 atomic_set(&skip_test, 0); 336 return; 337 } 338 cpu_relax(); 339 } 340 341 /* 342 * Trigger the target to continue into the measurement too: 343 */ 344 atomic_inc(&start_count); 345 346 check_tsc_warp(loop_timeout(cpu)); 347 348 while (atomic_read(&stop_count) != cpus-1) 349 cpu_relax(); 350 351 /* 352 * If the test was successful set the number of runs to zero and 353 * stop. If not, decrement the number of runs an check if we can 354 * retry. In case of random warps no retry is attempted. 355 */ 356 if (!nr_warps) { 357 atomic_set(&test_runs, 0); 358 359 pr_debug("TSC synchronization [CPU#%d -> CPU#%d]: passed\n", 360 smp_processor_id(), cpu); 361 362 } else if (atomic_dec_and_test(&test_runs) || random_warps) { 363 /* Force it to 0 if random warps brought us here */ 364 atomic_set(&test_runs, 0); 365 366 pr_warning("TSC synchronization [CPU#%d -> CPU#%d]:\n", 367 smp_processor_id(), cpu); 368 pr_warning("Measured %Ld cycles TSC warp between CPUs, " 369 "turning off TSC clock.\n", max_warp); 370 if (random_warps) 371 pr_warning("TSC warped randomly between CPUs\n"); 372 mark_tsc_unstable("check_tsc_sync_source failed"); 373 } 374 375 /* 376 * Reset it - just in case we boot another CPU later: 377 */ 378 atomic_set(&start_count, 0); 379 random_warps = 0; 380 nr_warps = 0; 381 max_warp = 0; 382 last_tsc = 0; 383 384 /* 385 * Let the target continue with the bootup: 386 */ 387 atomic_inc(&stop_count); 388 389 /* 390 * Retry, if there is a chance to do so. 391 */ 392 if (atomic_read(&test_runs) > 0) 393 goto retry; 394 } 395 396 /* 397 * Freshly booted CPUs call into this: 398 */ 399 void check_tsc_sync_target(void) 400 { 401 struct tsc_adjust *cur = this_cpu_ptr(&tsc_adjust); 402 unsigned int cpu = smp_processor_id(); 403 cycles_t cur_max_warp, gbl_max_warp; 404 int cpus = 2; 405 406 /* Also aborts if there is no TSC. */ 407 if (unsynchronized_tsc()) 408 return; 409 410 /* 411 * Store, verify and sanitize the TSC adjust register. If 412 * successful skip the test. 413 * 414 * The test is also skipped when the TSC is marked reliable. This 415 * is true for SoCs which have no fallback clocksource. On these 416 * SoCs the TSC is frequency synchronized, but still the TSC ADJUST 417 * register might have been wreckaged by the BIOS.. 418 */ 419 if (tsc_store_and_check_tsc_adjust(false) || tsc_clocksource_reliable) { 420 atomic_inc(&skip_test); 421 return; 422 } 423 424 retry: 425 /* 426 * Register this CPU's participation and wait for the 427 * source CPU to start the measurement: 428 */ 429 atomic_inc(&start_count); 430 while (atomic_read(&start_count) != cpus) 431 cpu_relax(); 432 433 cur_max_warp = check_tsc_warp(loop_timeout(cpu)); 434 435 /* 436 * Store the maximum observed warp value for a potential retry: 437 */ 438 gbl_max_warp = max_warp; 439 440 /* 441 * Ok, we are done: 442 */ 443 atomic_inc(&stop_count); 444 445 /* 446 * Wait for the source CPU to print stuff: 447 */ 448 while (atomic_read(&stop_count) != cpus) 449 cpu_relax(); 450 451 /* 452 * Reset it for the next sync test: 453 */ 454 atomic_set(&stop_count, 0); 455 456 /* 457 * Check the number of remaining test runs. If not zero, the test 458 * failed and a retry with adjusted TSC is possible. If zero the 459 * test was either successful or failed terminally. 460 */ 461 if (!atomic_read(&test_runs)) 462 return; 463 464 /* 465 * If the warp value of this CPU is 0, then the other CPU 466 * observed time going backwards so this TSC was ahead and 467 * needs to move backwards. 468 */ 469 if (!cur_max_warp) 470 cur_max_warp = -gbl_max_warp; 471 472 /* 473 * Add the result to the previous adjustment value. 474 * 475 * The adjustement value is slightly off by the overhead of the 476 * sync mechanism (observed values are ~200 TSC cycles), but this 477 * really depends on CPU, node distance and frequency. So 478 * compensating for this is hard to get right. Experiments show 479 * that the warp is not longer detectable when the observed warp 480 * value is used. In the worst case the adjustment needs to go 481 * through a 3rd run for fine tuning. 482 */ 483 cur->adjusted += cur_max_warp; 484 485 pr_warn("TSC ADJUST compensate: CPU%u observed %lld warp. Adjust: %lld\n", 486 cpu, cur_max_warp, cur->adjusted); 487 488 wrmsrl(MSR_IA32_TSC_ADJUST, cur->adjusted); 489 goto retry; 490 491 } 492 493 #endif /* CONFIG_SMP */ 494