1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TSC frequency enumeration via MSR 4 * 5 * Copyright (C) 2013, 2018 Intel Corporation 6 * Author: Bin Gao <bin.gao@intel.com> 7 */ 8 9 #include <linux/kernel.h> 10 11 #include <asm/apic.h> 12 #include <asm/cpu_device_id.h> 13 #include <asm/intel-family.h> 14 #include <asm/msr.h> 15 #include <asm/param.h> 16 #include <asm/tsc.h> 17 18 #define MAX_NUM_FREQS 16 /* 4 bits to select the frequency */ 19 20 /* 21 * The frequency numbers in the SDM are e.g. 83.3 MHz, which does not contain a 22 * lot of accuracy which leads to clock drift. As far as we know Bay Trail SoCs 23 * use a 25 MHz crystal and Cherry Trail uses a 19.2 MHz crystal, the crystal 24 * is the source clk for a root PLL which outputs 1600 and 100 MHz. It is 25 * unclear if the root PLL outputs are used directly by the CPU clock PLL or 26 * if there is another PLL in between. 27 * This does not matter though, we can model the chain of PLLs as a single PLL 28 * with a quotient equal to the quotients of all PLLs in the chain multiplied. 29 * So we can create a simplified model of the CPU clock setup using a reference 30 * clock of 100 MHz plus a quotient which gets us as close to the frequency 31 * from the SDM as possible. 32 * For the 83.3 MHz example from above this would give us 100 MHz * 5 / 6 = 33 * 83 and 1/3 MHz, which matches exactly what has been measured on actual hw. 34 */ 35 #define TSC_REFERENCE_KHZ 100000 36 37 struct muldiv { 38 u32 multiplier; 39 u32 divider; 40 }; 41 42 /* 43 * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be 44 * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. 45 * Unfortunately some Intel Atom SoCs aren't quite compliant to this, 46 * so we need manually differentiate SoC families. This is what the 47 * field use_msr_plat does. 48 */ 49 struct freq_desc { 50 bool use_msr_plat; 51 struct muldiv muldiv[MAX_NUM_FREQS]; 52 /* 53 * Some CPU frequencies in the SDM do not map to known PLL freqs, in 54 * that case the muldiv array is empty and the freqs array is used. 55 */ 56 u32 freqs[MAX_NUM_FREQS]; 57 u32 mask; 58 }; 59 60 /* 61 * Penwell and Clovertrail use spread spectrum clock, 62 * so the freq number is not exactly the same as reported 63 * by MSR based on SDM. 64 */ 65 static const struct freq_desc freq_desc_pnw = { 66 .use_msr_plat = false, 67 .freqs = { 0, 0, 0, 0, 0, 99840, 0, 83200 }, 68 .mask = 0x07, 69 }; 70 71 static const struct freq_desc freq_desc_clv = { 72 .use_msr_plat = false, 73 .freqs = { 0, 133200, 0, 0, 0, 99840, 0, 83200 }, 74 .mask = 0x07, 75 }; 76 77 /* 78 * Bay Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: 79 * 000: 100 * 5 / 6 = 83.3333 MHz 80 * 001: 100 * 1 / 1 = 100.0000 MHz 81 * 010: 100 * 4 / 3 = 133.3333 MHz 82 * 011: 100 * 7 / 6 = 116.6667 MHz 83 * 100: 100 * 4 / 5 = 80.0000 MHz 84 */ 85 static const struct freq_desc freq_desc_byt = { 86 .use_msr_plat = true, 87 .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 }, 88 { 4, 5 } }, 89 .mask = 0x07, 90 }; 91 92 /* 93 * Cherry Trail SDM MSR_FSB_FREQ frequencies simplified PLL model: 94 * 0000: 100 * 5 / 6 = 83.3333 MHz 95 * 0001: 100 * 1 / 1 = 100.0000 MHz 96 * 0010: 100 * 4 / 3 = 133.3333 MHz 97 * 0011: 100 * 7 / 6 = 116.6667 MHz 98 * 0100: 100 * 4 / 5 = 80.0000 MHz 99 * 0101: 100 * 14 / 15 = 93.3333 MHz 100 * 0110: 100 * 9 / 10 = 90.0000 MHz 101 * 0111: 100 * 8 / 9 = 88.8889 MHz 102 * 1000: 100 * 7 / 8 = 87.5000 MHz 103 */ 104 static const struct freq_desc freq_desc_cht = { 105 .use_msr_plat = true, 106 .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 7, 6 }, 107 { 4, 5 }, { 14, 15 }, { 9, 10 }, { 8, 9 }, 108 { 7, 8 } }, 109 .mask = 0x0f, 110 }; 111 112 /* 113 * Merriefield SDM MSR_FSB_FREQ frequencies simplified PLL model: 114 * 0001: 100 * 1 / 1 = 100.0000 MHz 115 * 0010: 100 * 4 / 3 = 133.3333 MHz 116 */ 117 static const struct freq_desc freq_desc_tng = { 118 .use_msr_plat = true, 119 .muldiv = { { 0, 0 }, { 1, 1 }, { 4, 3 } }, 120 .mask = 0x07, 121 }; 122 123 /* 124 * Moorefield SDM MSR_FSB_FREQ frequencies simplified PLL model: 125 * 0000: 100 * 5 / 6 = 83.3333 MHz 126 * 0001: 100 * 1 / 1 = 100.0000 MHz 127 * 0010: 100 * 4 / 3 = 133.3333 MHz 128 * 0011: 100 * 1 / 1 = 100.0000 MHz 129 */ 130 static const struct freq_desc freq_desc_ann = { 131 .use_msr_plat = true, 132 .muldiv = { { 5, 6 }, { 1, 1 }, { 4, 3 }, { 1, 1 } }, 133 .mask = 0x0f, 134 }; 135 136 /* 24 MHz crystal? : 24 * 13 / 4 = 78 MHz */ 137 static const struct freq_desc freq_desc_lgm = { 138 .use_msr_plat = true, 139 .freqs = { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }, 140 .mask = 0x0f, 141 }; 142 143 static const struct x86_cpu_id tsc_msr_cpu_ids[] = { 144 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_MID, &freq_desc_pnw), 145 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL_TABLET,&freq_desc_clv), 146 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &freq_desc_byt), 147 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &freq_desc_tng), 148 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &freq_desc_cht), 149 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_MID, &freq_desc_ann), 150 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT_NP, &freq_desc_lgm), 151 {} 152 }; 153 154 /* 155 * MSR-based CPU/TSC frequency discovery for certain CPUs. 156 * 157 * Set global "lapic_timer_period" to bus_clock_cycles/jiffy 158 * Return processor base frequency in KHz, or 0 on failure. 159 */ 160 unsigned long cpu_khz_from_msr(void) 161 { 162 u32 lo, hi, ratio, freq, tscref; 163 const struct freq_desc *freq_desc; 164 const struct x86_cpu_id *id; 165 const struct muldiv *md; 166 unsigned long res; 167 int index; 168 169 id = x86_match_cpu(tsc_msr_cpu_ids); 170 if (!id) 171 return 0; 172 173 freq_desc = (struct freq_desc *)id->driver_data; 174 if (freq_desc->use_msr_plat) { 175 rdmsr(MSR_PLATFORM_INFO, lo, hi); 176 ratio = (lo >> 8) & 0xff; 177 } else { 178 rdmsr(MSR_IA32_PERF_STATUS, lo, hi); 179 ratio = (hi >> 8) & 0x1f; 180 } 181 182 /* Get FSB FREQ ID */ 183 rdmsr(MSR_FSB_FREQ, lo, hi); 184 index = lo & freq_desc->mask; 185 md = &freq_desc->muldiv[index]; 186 187 /* 188 * Note this also catches cases where the index points to an unpopulated 189 * part of muldiv, in that case the else will set freq and res to 0. 190 */ 191 if (md->divider) { 192 tscref = TSC_REFERENCE_KHZ * md->multiplier; 193 freq = DIV_ROUND_CLOSEST(tscref, md->divider); 194 /* 195 * Multiplying by ratio before the division has better 196 * accuracy than just calculating freq * ratio. 197 */ 198 res = DIV_ROUND_CLOSEST(tscref * ratio, md->divider); 199 } else { 200 freq = freq_desc->freqs[index]; 201 res = freq * ratio; 202 } 203 204 if (freq == 0) 205 pr_err("Error MSR_FSB_FREQ index %d is unknown\n", index); 206 207 #ifdef CONFIG_X86_LOCAL_APIC 208 lapic_timer_period = (freq * 1000) / HZ; 209 #endif 210 211 /* 212 * TSC frequency determined by MSR is always considered "known" 213 * because it is reported by HW. 214 * Another fact is that on MSR capable platforms, PIT/HPET is 215 * generally not available so calibration won't work at all. 216 */ 217 setup_force_cpu_cap(X86_FEATURE_TSC_KNOWN_FREQ); 218 219 /* 220 * Unfortunately there is no way for hardware to tell whether the 221 * TSC is reliable. We were told by silicon design team that TSC 222 * on Atom SoCs are always "reliable". TSC is also the only 223 * reliable clocksource on these SoCs (HPET is either not present 224 * or not functional) so mark TSC reliable which removes the 225 * requirement for a watchdog clocksource. 226 */ 227 setup_force_cpu_cap(X86_FEATURE_TSC_RELIABLE); 228 229 return res; 230 } 231