1 #include <linux/kernel.h> 2 #include <linux/sched.h> 3 #include <linux/init.h> 4 #include <linux/module.h> 5 #include <linux/timer.h> 6 #include <linux/acpi_pmtmr.h> 7 #include <linux/cpufreq.h> 8 #include <linux/dmi.h> 9 #include <linux/delay.h> 10 #include <linux/clocksource.h> 11 #include <linux/percpu.h> 12 13 #include <asm/hpet.h> 14 #include <asm/timer.h> 15 #include <asm/vgtod.h> 16 #include <asm/time.h> 17 #include <asm/delay.h> 18 19 unsigned int cpu_khz; /* TSC clocks / usec, not used here */ 20 EXPORT_SYMBOL(cpu_khz); 21 unsigned int tsc_khz; 22 EXPORT_SYMBOL(tsc_khz); 23 24 /* 25 * TSC can be unstable due to cpufreq or due to unsynced TSCs 26 */ 27 static int tsc_unstable; 28 29 /* native_sched_clock() is called before tsc_init(), so 30 we must start with the TSC soft disabled to prevent 31 erroneous rdtsc usage on !cpu_has_tsc processors */ 32 static int tsc_disabled = -1; 33 34 /* 35 * Scheduler clock - returns current time in nanosec units. 36 */ 37 u64 native_sched_clock(void) 38 { 39 u64 this_offset; 40 41 /* 42 * Fall back to jiffies if there's no TSC available: 43 * ( But note that we still use it if the TSC is marked 44 * unstable. We do this because unlike Time Of Day, 45 * the scheduler clock tolerates small errors and it's 46 * very important for it to be as fast as the platform 47 * can achive it. ) 48 */ 49 if (unlikely(tsc_disabled)) { 50 /* No locking but a rare wrong value is not a big deal: */ 51 return (jiffies_64 - INITIAL_JIFFIES) * (1000000000 / HZ); 52 } 53 54 /* read the Time Stamp Counter: */ 55 rdtscll(this_offset); 56 57 /* return the value in ns */ 58 return cycles_2_ns(this_offset); 59 } 60 61 /* We need to define a real function for sched_clock, to override the 62 weak default version */ 63 #ifdef CONFIG_PARAVIRT 64 unsigned long long sched_clock(void) 65 { 66 return paravirt_sched_clock(); 67 } 68 #else 69 unsigned long long 70 sched_clock(void) __attribute__((alias("native_sched_clock"))); 71 #endif 72 73 int check_tsc_unstable(void) 74 { 75 return tsc_unstable; 76 } 77 EXPORT_SYMBOL_GPL(check_tsc_unstable); 78 79 #ifdef CONFIG_X86_TSC 80 int __init notsc_setup(char *str) 81 { 82 printk(KERN_WARNING "notsc: Kernel compiled with CONFIG_X86_TSC, " 83 "cannot disable TSC completely.\n"); 84 tsc_disabled = 1; 85 return 1; 86 } 87 #else 88 /* 89 * disable flag for tsc. Takes effect by clearing the TSC cpu flag 90 * in cpu/common.c 91 */ 92 int __init notsc_setup(char *str) 93 { 94 setup_clear_cpu_cap(X86_FEATURE_TSC); 95 return 1; 96 } 97 #endif 98 99 __setup("notsc", notsc_setup); 100 101 #define MAX_RETRIES 5 102 #define SMI_TRESHOLD 50000 103 104 /* 105 * Read TSC and the reference counters. Take care of SMI disturbance 106 */ 107 static u64 tsc_read_refs(u64 *p, int hpet) 108 { 109 u64 t1, t2; 110 int i; 111 112 for (i = 0; i < MAX_RETRIES; i++) { 113 t1 = get_cycles(); 114 if (hpet) 115 *p = hpet_readl(HPET_COUNTER) & 0xFFFFFFFF; 116 else 117 *p = acpi_pm_read_early(); 118 t2 = get_cycles(); 119 if ((t2 - t1) < SMI_TRESHOLD) 120 return t2; 121 } 122 return ULLONG_MAX; 123 } 124 125 /* 126 * Calculate the TSC frequency from HPET reference 127 */ 128 static unsigned long calc_hpet_ref(u64 deltatsc, u64 hpet1, u64 hpet2) 129 { 130 u64 tmp; 131 132 if (hpet2 < hpet1) 133 hpet2 += 0x100000000ULL; 134 hpet2 -= hpet1; 135 tmp = ((u64)hpet2 * hpet_readl(HPET_PERIOD)); 136 do_div(tmp, 1000000); 137 do_div(deltatsc, tmp); 138 139 return (unsigned long) deltatsc; 140 } 141 142 /* 143 * Calculate the TSC frequency from PMTimer reference 144 */ 145 static unsigned long calc_pmtimer_ref(u64 deltatsc, u64 pm1, u64 pm2) 146 { 147 u64 tmp; 148 149 if (!pm1 && !pm2) 150 return ULONG_MAX; 151 152 if (pm2 < pm1) 153 pm2 += (u64)ACPI_PM_OVRRUN; 154 pm2 -= pm1; 155 tmp = pm2 * 1000000000LL; 156 do_div(tmp, PMTMR_TICKS_PER_SEC); 157 do_div(deltatsc, tmp); 158 159 return (unsigned long) deltatsc; 160 } 161 162 #define CAL_MS 10 163 #define CAL_LATCH (CLOCK_TICK_RATE / (1000 / CAL_MS)) 164 #define CAL_PIT_LOOPS 1000 165 166 #define CAL2_MS 50 167 #define CAL2_LATCH (CLOCK_TICK_RATE / (1000 / CAL2_MS)) 168 #define CAL2_PIT_LOOPS 5000 169 170 171 /* 172 * Try to calibrate the TSC against the Programmable 173 * Interrupt Timer and return the frequency of the TSC 174 * in kHz. 175 * 176 * Return ULONG_MAX on failure to calibrate. 177 */ 178 static unsigned long pit_calibrate_tsc(u32 latch, unsigned long ms, int loopmin) 179 { 180 u64 tsc, t1, t2, delta; 181 unsigned long tscmin, tscmax; 182 int pitcnt; 183 184 /* Set the Gate high, disable speaker */ 185 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 186 187 /* 188 * Setup CTC channel 2* for mode 0, (interrupt on terminal 189 * count mode), binary count. Set the latch register to 50ms 190 * (LSB then MSB) to begin countdown. 191 */ 192 outb(0xb0, 0x43); 193 outb(latch & 0xff, 0x42); 194 outb(latch >> 8, 0x42); 195 196 tsc = t1 = t2 = get_cycles(); 197 198 pitcnt = 0; 199 tscmax = 0; 200 tscmin = ULONG_MAX; 201 while ((inb(0x61) & 0x20) == 0) { 202 t2 = get_cycles(); 203 delta = t2 - tsc; 204 tsc = t2; 205 if ((unsigned long) delta < tscmin) 206 tscmin = (unsigned int) delta; 207 if ((unsigned long) delta > tscmax) 208 tscmax = (unsigned int) delta; 209 pitcnt++; 210 } 211 212 /* 213 * Sanity checks: 214 * 215 * If we were not able to read the PIT more than loopmin 216 * times, then we have been hit by a massive SMI 217 * 218 * If the maximum is 10 times larger than the minimum, 219 * then we got hit by an SMI as well. 220 */ 221 if (pitcnt < loopmin || tscmax > 10 * tscmin) 222 return ULONG_MAX; 223 224 /* Calculate the PIT value */ 225 delta = t2 - t1; 226 do_div(delta, ms); 227 return delta; 228 } 229 230 /* 231 * This reads the current MSB of the PIT counter, and 232 * checks if we are running on sufficiently fast and 233 * non-virtualized hardware. 234 * 235 * Our expectations are: 236 * 237 * - the PIT is running at roughly 1.19MHz 238 * 239 * - each IO is going to take about 1us on real hardware, 240 * but we allow it to be much faster (by a factor of 10) or 241 * _slightly_ slower (ie we allow up to a 2us read+counter 242 * update - anything else implies a unacceptably slow CPU 243 * or PIT for the fast calibration to work. 244 * 245 * - with 256 PIT ticks to read the value, we have 214us to 246 * see the same MSB (and overhead like doing a single TSC 247 * read per MSB value etc). 248 * 249 * - We're doing 2 reads per loop (LSB, MSB), and we expect 250 * them each to take about a microsecond on real hardware. 251 * So we expect a count value of around 100. But we'll be 252 * generous, and accept anything over 50. 253 * 254 * - if the PIT is stuck, and we see *many* more reads, we 255 * return early (and the next caller of pit_expect_msb() 256 * then consider it a failure when they don't see the 257 * next expected value). 258 * 259 * These expectations mean that we know that we have seen the 260 * transition from one expected value to another with a fairly 261 * high accuracy, and we didn't miss any events. We can thus 262 * use the TSC value at the transitions to calculate a pretty 263 * good value for the TSC frequencty. 264 */ 265 static inline int pit_expect_msb(unsigned char val) 266 { 267 int count = 0; 268 269 for (count = 0; count < 50000; count++) { 270 /* Ignore LSB */ 271 inb(0x42); 272 if (inb(0x42) != val) 273 break; 274 } 275 return count > 50; 276 } 277 278 /* 279 * How many MSB values do we want to see? We aim for a 280 * 15ms calibration, which assuming a 2us counter read 281 * error should give us roughly 150 ppm precision for 282 * the calibration. 283 */ 284 #define QUICK_PIT_MS 15 285 #define QUICK_PIT_ITERATIONS (QUICK_PIT_MS * PIT_TICK_RATE / 1000 / 256) 286 287 static unsigned long quick_pit_calibrate(void) 288 { 289 /* Set the Gate high, disable speaker */ 290 outb((inb(0x61) & ~0x02) | 0x01, 0x61); 291 292 /* 293 * Counter 2, mode 0 (one-shot), binary count 294 * 295 * NOTE! Mode 2 decrements by two (and then the 296 * output is flipped each time, giving the same 297 * final output frequency as a decrement-by-one), 298 * so mode 0 is much better when looking at the 299 * individual counts. 300 */ 301 outb(0xb0, 0x43); 302 303 /* Start at 0xffff */ 304 outb(0xff, 0x42); 305 outb(0xff, 0x42); 306 307 if (pit_expect_msb(0xff)) { 308 int i; 309 u64 t1, t2, delta; 310 unsigned char expect = 0xfe; 311 312 t1 = get_cycles(); 313 for (i = 0; i < QUICK_PIT_ITERATIONS; i++, expect--) { 314 if (!pit_expect_msb(expect)) 315 goto failed; 316 } 317 t2 = get_cycles(); 318 319 /* 320 * Make sure we can rely on the second TSC timestamp: 321 */ 322 if (!pit_expect_msb(expect)) 323 goto failed; 324 325 /* 326 * Ok, if we get here, then we've seen the 327 * MSB of the PIT decrement QUICK_PIT_ITERATIONS 328 * times, and each MSB had many hits, so we never 329 * had any sudden jumps. 330 * 331 * As a result, we can depend on there not being 332 * any odd delays anywhere, and the TSC reads are 333 * reliable. 334 * 335 * kHz = ticks / time-in-seconds / 1000; 336 * kHz = (t2 - t1) / (QPI * 256 / PIT_TICK_RATE) / 1000 337 * kHz = ((t2 - t1) * PIT_TICK_RATE) / (QPI * 256 * 1000) 338 */ 339 delta = (t2 - t1)*PIT_TICK_RATE; 340 do_div(delta, QUICK_PIT_ITERATIONS*256*1000); 341 printk("Fast TSC calibration using PIT\n"); 342 return delta; 343 } 344 failed: 345 return 0; 346 } 347 348 /** 349 * native_calibrate_tsc - calibrate the tsc on boot 350 */ 351 unsigned long native_calibrate_tsc(void) 352 { 353 u64 tsc1, tsc2, delta, ref1, ref2; 354 unsigned long tsc_pit_min = ULONG_MAX, tsc_ref_min = ULONG_MAX; 355 unsigned long flags, latch, ms, fast_calibrate; 356 int hpet = is_hpet_enabled(), i, loopmin; 357 358 local_irq_save(flags); 359 fast_calibrate = quick_pit_calibrate(); 360 local_irq_restore(flags); 361 if (fast_calibrate) 362 return fast_calibrate; 363 364 /* 365 * Run 5 calibration loops to get the lowest frequency value 366 * (the best estimate). We use two different calibration modes 367 * here: 368 * 369 * 1) PIT loop. We set the PIT Channel 2 to oneshot mode and 370 * load a timeout of 50ms. We read the time right after we 371 * started the timer and wait until the PIT count down reaches 372 * zero. In each wait loop iteration we read the TSC and check 373 * the delta to the previous read. We keep track of the min 374 * and max values of that delta. The delta is mostly defined 375 * by the IO time of the PIT access, so we can detect when a 376 * SMI/SMM disturbance happend between the two reads. If the 377 * maximum time is significantly larger than the minimum time, 378 * then we discard the result and have another try. 379 * 380 * 2) Reference counter. If available we use the HPET or the 381 * PMTIMER as a reference to check the sanity of that value. 382 * We use separate TSC readouts and check inside of the 383 * reference read for a SMI/SMM disturbance. We dicard 384 * disturbed values here as well. We do that around the PIT 385 * calibration delay loop as we have to wait for a certain 386 * amount of time anyway. 387 */ 388 389 /* Preset PIT loop values */ 390 latch = CAL_LATCH; 391 ms = CAL_MS; 392 loopmin = CAL_PIT_LOOPS; 393 394 for (i = 0; i < 3; i++) { 395 unsigned long tsc_pit_khz; 396 397 /* 398 * Read the start value and the reference count of 399 * hpet/pmtimer when available. Then do the PIT 400 * calibration, which will take at least 50ms, and 401 * read the end value. 402 */ 403 local_irq_save(flags); 404 tsc1 = tsc_read_refs(&ref1, hpet); 405 tsc_pit_khz = pit_calibrate_tsc(latch, ms, loopmin); 406 tsc2 = tsc_read_refs(&ref2, hpet); 407 local_irq_restore(flags); 408 409 /* Pick the lowest PIT TSC calibration so far */ 410 tsc_pit_min = min(tsc_pit_min, tsc_pit_khz); 411 412 /* hpet or pmtimer available ? */ 413 if (!hpet && !ref1 && !ref2) 414 continue; 415 416 /* Check, whether the sampling was disturbed by an SMI */ 417 if (tsc1 == ULLONG_MAX || tsc2 == ULLONG_MAX) 418 continue; 419 420 tsc2 = (tsc2 - tsc1) * 1000000LL; 421 if (hpet) 422 tsc2 = calc_hpet_ref(tsc2, ref1, ref2); 423 else 424 tsc2 = calc_pmtimer_ref(tsc2, ref1, ref2); 425 426 tsc_ref_min = min(tsc_ref_min, (unsigned long) tsc2); 427 428 /* Check the reference deviation */ 429 delta = ((u64) tsc_pit_min) * 100; 430 do_div(delta, tsc_ref_min); 431 432 /* 433 * If both calibration results are inside a 10% window 434 * then we can be sure, that the calibration 435 * succeeded. We break out of the loop right away. We 436 * use the reference value, as it is more precise. 437 */ 438 if (delta >= 90 && delta <= 110) { 439 printk(KERN_INFO 440 "TSC: PIT calibration matches %s. %d loops\n", 441 hpet ? "HPET" : "PMTIMER", i + 1); 442 return tsc_ref_min; 443 } 444 445 /* 446 * Check whether PIT failed more than once. This 447 * happens in virtualized environments. We need to 448 * give the virtual PC a slightly longer timeframe for 449 * the HPET/PMTIMER to make the result precise. 450 */ 451 if (i == 1 && tsc_pit_min == ULONG_MAX) { 452 latch = CAL2_LATCH; 453 ms = CAL2_MS; 454 loopmin = CAL2_PIT_LOOPS; 455 } 456 } 457 458 /* 459 * Now check the results. 460 */ 461 if (tsc_pit_min == ULONG_MAX) { 462 /* PIT gave no useful value */ 463 printk(KERN_WARNING "TSC: Unable to calibrate against PIT\n"); 464 465 /* We don't have an alternative source, disable TSC */ 466 if (!hpet && !ref1 && !ref2) { 467 printk("TSC: No reference (HPET/PMTIMER) available\n"); 468 return 0; 469 } 470 471 /* The alternative source failed as well, disable TSC */ 472 if (tsc_ref_min == ULONG_MAX) { 473 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration " 474 "failed.\n"); 475 return 0; 476 } 477 478 /* Use the alternative source */ 479 printk(KERN_INFO "TSC: using %s reference calibration\n", 480 hpet ? "HPET" : "PMTIMER"); 481 482 return tsc_ref_min; 483 } 484 485 /* We don't have an alternative source, use the PIT calibration value */ 486 if (!hpet && !ref1 && !ref2) { 487 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 488 return tsc_pit_min; 489 } 490 491 /* The alternative source failed, use the PIT calibration value */ 492 if (tsc_ref_min == ULONG_MAX) { 493 printk(KERN_WARNING "TSC: HPET/PMTIMER calibration failed. " 494 "Using PIT calibration\n"); 495 return tsc_pit_min; 496 } 497 498 /* 499 * The calibration values differ too much. In doubt, we use 500 * the PIT value as we know that there are PMTIMERs around 501 * running at double speed. At least we let the user know: 502 */ 503 printk(KERN_WARNING "TSC: PIT calibration deviates from %s: %lu %lu.\n", 504 hpet ? "HPET" : "PMTIMER", tsc_pit_min, tsc_ref_min); 505 printk(KERN_INFO "TSC: Using PIT calibration value\n"); 506 return tsc_pit_min; 507 } 508 509 #ifdef CONFIG_X86_32 510 /* Only called from the Powernow K7 cpu freq driver */ 511 int recalibrate_cpu_khz(void) 512 { 513 #ifndef CONFIG_SMP 514 unsigned long cpu_khz_old = cpu_khz; 515 516 if (cpu_has_tsc) { 517 tsc_khz = calibrate_tsc(); 518 cpu_khz = tsc_khz; 519 cpu_data(0).loops_per_jiffy = 520 cpufreq_scale(cpu_data(0).loops_per_jiffy, 521 cpu_khz_old, cpu_khz); 522 return 0; 523 } else 524 return -ENODEV; 525 #else 526 return -ENODEV; 527 #endif 528 } 529 530 EXPORT_SYMBOL(recalibrate_cpu_khz); 531 532 #endif /* CONFIG_X86_32 */ 533 534 /* Accelerators for sched_clock() 535 * convert from cycles(64bits) => nanoseconds (64bits) 536 * basic equation: 537 * ns = cycles / (freq / ns_per_sec) 538 * ns = cycles * (ns_per_sec / freq) 539 * ns = cycles * (10^9 / (cpu_khz * 10^3)) 540 * ns = cycles * (10^6 / cpu_khz) 541 * 542 * Then we use scaling math (suggested by george@mvista.com) to get: 543 * ns = cycles * (10^6 * SC / cpu_khz) / SC 544 * ns = cycles * cyc2ns_scale / SC 545 * 546 * And since SC is a constant power of two, we can convert the div 547 * into a shift. 548 * 549 * We can use khz divisor instead of mhz to keep a better precision, since 550 * cyc2ns_scale is limited to 10^6 * 2^10, which fits in 32 bits. 551 * (mathieu.desnoyers@polymtl.ca) 552 * 553 * -johnstul@us.ibm.com "math is hard, lets go shopping!" 554 */ 555 556 DEFINE_PER_CPU(unsigned long, cyc2ns); 557 558 static void set_cyc2ns_scale(unsigned long cpu_khz, int cpu) 559 { 560 unsigned long long tsc_now, ns_now; 561 unsigned long flags, *scale; 562 563 local_irq_save(flags); 564 sched_clock_idle_sleep_event(); 565 566 scale = &per_cpu(cyc2ns, cpu); 567 568 rdtscll(tsc_now); 569 ns_now = __cycles_2_ns(tsc_now); 570 571 if (cpu_khz) 572 *scale = (NSEC_PER_MSEC << CYC2NS_SCALE_FACTOR)/cpu_khz; 573 574 sched_clock_idle_wakeup_event(0); 575 local_irq_restore(flags); 576 } 577 578 #ifdef CONFIG_CPU_FREQ 579 580 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency 581 * changes. 582 * 583 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's 584 * not that important because current Opteron setups do not support 585 * scaling on SMP anyroads. 586 * 587 * Should fix up last_tsc too. Currently gettimeofday in the 588 * first tick after the change will be slightly wrong. 589 */ 590 591 static unsigned int ref_freq; 592 static unsigned long loops_per_jiffy_ref; 593 static unsigned long tsc_khz_ref; 594 595 static int time_cpufreq_notifier(struct notifier_block *nb, unsigned long val, 596 void *data) 597 { 598 struct cpufreq_freqs *freq = data; 599 unsigned long *lpj, dummy; 600 601 if (cpu_has(&cpu_data(freq->cpu), X86_FEATURE_CONSTANT_TSC)) 602 return 0; 603 604 lpj = &dummy; 605 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 606 #ifdef CONFIG_SMP 607 lpj = &cpu_data(freq->cpu).loops_per_jiffy; 608 #else 609 lpj = &boot_cpu_data.loops_per_jiffy; 610 #endif 611 612 if (!ref_freq) { 613 ref_freq = freq->old; 614 loops_per_jiffy_ref = *lpj; 615 tsc_khz_ref = tsc_khz; 616 } 617 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) || 618 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) || 619 (val == CPUFREQ_RESUMECHANGE)) { 620 *lpj = cpufreq_scale(loops_per_jiffy_ref, ref_freq, freq->new); 621 622 tsc_khz = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new); 623 if (!(freq->flags & CPUFREQ_CONST_LOOPS)) 624 mark_tsc_unstable("cpufreq changes"); 625 } 626 627 set_cyc2ns_scale(tsc_khz, freq->cpu); 628 629 return 0; 630 } 631 632 static struct notifier_block time_cpufreq_notifier_block = { 633 .notifier_call = time_cpufreq_notifier 634 }; 635 636 static int __init cpufreq_tsc(void) 637 { 638 if (!cpu_has_tsc) 639 return 0; 640 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 641 return 0; 642 cpufreq_register_notifier(&time_cpufreq_notifier_block, 643 CPUFREQ_TRANSITION_NOTIFIER); 644 return 0; 645 } 646 647 core_initcall(cpufreq_tsc); 648 649 #endif /* CONFIG_CPU_FREQ */ 650 651 /* clocksource code */ 652 653 static struct clocksource clocksource_tsc; 654 655 /* 656 * We compare the TSC to the cycle_last value in the clocksource 657 * structure to avoid a nasty time-warp. This can be observed in a 658 * very small window right after one CPU updated cycle_last under 659 * xtime/vsyscall_gtod lock and the other CPU reads a TSC value which 660 * is smaller than the cycle_last reference value due to a TSC which 661 * is slighty behind. This delta is nowhere else observable, but in 662 * that case it results in a forward time jump in the range of hours 663 * due to the unsigned delta calculation of the time keeping core 664 * code, which is necessary to support wrapping clocksources like pm 665 * timer. 666 */ 667 static cycle_t read_tsc(void) 668 { 669 cycle_t ret = (cycle_t)get_cycles(); 670 671 return ret >= clocksource_tsc.cycle_last ? 672 ret : clocksource_tsc.cycle_last; 673 } 674 675 #ifdef CONFIG_X86_64 676 static cycle_t __vsyscall_fn vread_tsc(void) 677 { 678 cycle_t ret = (cycle_t)vget_cycles(); 679 680 return ret >= __vsyscall_gtod_data.clock.cycle_last ? 681 ret : __vsyscall_gtod_data.clock.cycle_last; 682 } 683 #endif 684 685 static struct clocksource clocksource_tsc = { 686 .name = "tsc", 687 .rating = 300, 688 .read = read_tsc, 689 .mask = CLOCKSOURCE_MASK(64), 690 .shift = 22, 691 .flags = CLOCK_SOURCE_IS_CONTINUOUS | 692 CLOCK_SOURCE_MUST_VERIFY, 693 #ifdef CONFIG_X86_64 694 .vread = vread_tsc, 695 #endif 696 }; 697 698 void mark_tsc_unstable(char *reason) 699 { 700 if (!tsc_unstable) { 701 tsc_unstable = 1; 702 printk("Marking TSC unstable due to %s\n", reason); 703 /* Change only the rating, when not registered */ 704 if (clocksource_tsc.mult) 705 clocksource_change_rating(&clocksource_tsc, 0); 706 else 707 clocksource_tsc.rating = 0; 708 } 709 } 710 711 EXPORT_SYMBOL_GPL(mark_tsc_unstable); 712 713 static int __init dmi_mark_tsc_unstable(const struct dmi_system_id *d) 714 { 715 printk(KERN_NOTICE "%s detected: marking TSC unstable.\n", 716 d->ident); 717 tsc_unstable = 1; 718 return 0; 719 } 720 721 /* List of systems that have known TSC problems */ 722 static struct dmi_system_id __initdata bad_tsc_dmi_table[] = { 723 { 724 .callback = dmi_mark_tsc_unstable, 725 .ident = "IBM Thinkpad 380XD", 726 .matches = { 727 DMI_MATCH(DMI_BOARD_VENDOR, "IBM"), 728 DMI_MATCH(DMI_BOARD_NAME, "2635FA0"), 729 }, 730 }, 731 {} 732 }; 733 734 /* 735 * Geode_LX - the OLPC CPU has a possibly a very reliable TSC 736 */ 737 #ifdef CONFIG_MGEODE_LX 738 /* RTSC counts during suspend */ 739 #define RTSC_SUSP 0x100 740 741 static void __init check_geode_tsc_reliable(void) 742 { 743 unsigned long res_low, res_high; 744 745 rdmsr_safe(MSR_GEODE_BUSCONT_CONF0, &res_low, &res_high); 746 if (res_low & RTSC_SUSP) 747 clocksource_tsc.flags &= ~CLOCK_SOURCE_MUST_VERIFY; 748 } 749 #else 750 static inline void check_geode_tsc_reliable(void) { } 751 #endif 752 753 /* 754 * Make an educated guess if the TSC is trustworthy and synchronized 755 * over all CPUs. 756 */ 757 __cpuinit int unsynchronized_tsc(void) 758 { 759 if (!cpu_has_tsc || tsc_unstable) 760 return 1; 761 762 #ifdef CONFIG_SMP 763 if (apic_is_clustered_box()) 764 return 1; 765 #endif 766 767 if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) 768 return 0; 769 /* 770 * Intel systems are normally all synchronized. 771 * Exceptions must mark TSC as unstable: 772 */ 773 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) { 774 /* assume multi socket systems are not synchronized: */ 775 if (num_possible_cpus() > 1) 776 tsc_unstable = 1; 777 } 778 779 return tsc_unstable; 780 } 781 782 static void __init init_tsc_clocksource(void) 783 { 784 clocksource_tsc.mult = clocksource_khz2mult(tsc_khz, 785 clocksource_tsc.shift); 786 /* lower the rating if we already know its unstable: */ 787 if (check_tsc_unstable()) { 788 clocksource_tsc.rating = 0; 789 clocksource_tsc.flags &= ~CLOCK_SOURCE_IS_CONTINUOUS; 790 } 791 clocksource_register(&clocksource_tsc); 792 } 793 794 void __init tsc_init(void) 795 { 796 u64 lpj; 797 int cpu; 798 799 if (!cpu_has_tsc) 800 return; 801 802 tsc_khz = calibrate_tsc(); 803 cpu_khz = tsc_khz; 804 805 if (!tsc_khz) { 806 mark_tsc_unstable("could not calculate TSC khz"); 807 return; 808 } 809 810 #ifdef CONFIG_X86_64 811 if (cpu_has(&boot_cpu_data, X86_FEATURE_CONSTANT_TSC) && 812 (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)) 813 cpu_khz = calibrate_cpu(); 814 #endif 815 816 lpj = ((u64)tsc_khz * 1000); 817 do_div(lpj, HZ); 818 lpj_fine = lpj; 819 820 printk("Detected %lu.%03lu MHz processor.\n", 821 (unsigned long)cpu_khz / 1000, 822 (unsigned long)cpu_khz % 1000); 823 824 /* 825 * Secondary CPUs do not run through tsc_init(), so set up 826 * all the scale factors for all CPUs, assuming the same 827 * speed as the bootup CPU. (cpufreq notifiers will fix this 828 * up if their speed diverges) 829 */ 830 for_each_possible_cpu(cpu) 831 set_cyc2ns_scale(cpu_khz, cpu); 832 833 if (tsc_disabled > 0) 834 return; 835 836 /* now allow native_sched_clock() to use rdtsc */ 837 tsc_disabled = 0; 838 839 use_tsc_delay(); 840 /* Check and install the TSC clocksource */ 841 dmi_check_system(bad_tsc_dmi_table); 842 843 if (unsynchronized_tsc()) 844 mark_tsc_unstable("TSCs unsynchronized"); 845 846 check_geode_tsc_reliable(); 847 init_tsc_clocksource(); 848 } 849 850