1 /* 2 * Copyright (C) 1991, 1992 Linus Torvalds 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs 4 * 5 * Pentium III FXSR, SSE support 6 * Gareth Hughes <gareth@valinux.com>, May 2000 7 */ 8 9 /* 10 * Handle hardware traps and faults. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/context_tracking.h> 16 #include <linux/interrupt.h> 17 #include <linux/kallsyms.h> 18 #include <linux/spinlock.h> 19 #include <linux/kprobes.h> 20 #include <linux/uaccess.h> 21 #include <linux/kdebug.h> 22 #include <linux/kgdb.h> 23 #include <linux/kernel.h> 24 #include <linux/export.h> 25 #include <linux/ptrace.h> 26 #include <linux/uprobes.h> 27 #include <linux/string.h> 28 #include <linux/delay.h> 29 #include <linux/errno.h> 30 #include <linux/kexec.h> 31 #include <linux/sched.h> 32 #include <linux/sched/task_stack.h> 33 #include <linux/timer.h> 34 #include <linux/init.h> 35 #include <linux/bug.h> 36 #include <linux/nmi.h> 37 #include <linux/mm.h> 38 #include <linux/smp.h> 39 #include <linux/io.h> 40 #include <linux/hardirq.h> 41 #include <linux/atomic.h> 42 #include <linux/ioasid.h> 43 44 #include <asm/stacktrace.h> 45 #include <asm/processor.h> 46 #include <asm/debugreg.h> 47 #include <asm/realmode.h> 48 #include <asm/text-patching.h> 49 #include <asm/ftrace.h> 50 #include <asm/traps.h> 51 #include <asm/desc.h> 52 #include <asm/fpu/api.h> 53 #include <asm/cpu.h> 54 #include <asm/cpu_entry_area.h> 55 #include <asm/mce.h> 56 #include <asm/fixmap.h> 57 #include <asm/mach_traps.h> 58 #include <asm/alternative.h> 59 #include <asm/fpu/xstate.h> 60 #include <asm/vm86.h> 61 #include <asm/umip.h> 62 #include <asm/insn.h> 63 #include <asm/insn-eval.h> 64 #include <asm/vdso.h> 65 #include <asm/tdx.h> 66 #include <asm/cfi.h> 67 68 #ifdef CONFIG_X86_64 69 #include <asm/x86_init.h> 70 #include <asm/proto.h> 71 #else 72 #include <asm/processor-flags.h> 73 #include <asm/setup.h> 74 #include <asm/proto.h> 75 #endif 76 77 DECLARE_BITMAP(system_vectors, NR_VECTORS); 78 79 static inline void cond_local_irq_enable(struct pt_regs *regs) 80 { 81 if (regs->flags & X86_EFLAGS_IF) 82 local_irq_enable(); 83 } 84 85 static inline void cond_local_irq_disable(struct pt_regs *regs) 86 { 87 if (regs->flags & X86_EFLAGS_IF) 88 local_irq_disable(); 89 } 90 91 __always_inline int is_valid_bugaddr(unsigned long addr) 92 { 93 if (addr < TASK_SIZE_MAX) 94 return 0; 95 96 /* 97 * We got #UD, if the text isn't readable we'd have gotten 98 * a different exception. 99 */ 100 return *(unsigned short *)addr == INSN_UD2; 101 } 102 103 static nokprobe_inline int 104 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, 105 struct pt_regs *regs, long error_code) 106 { 107 if (v8086_mode(regs)) { 108 /* 109 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. 110 * On nmi (interrupt 2), do_trap should not be called. 111 */ 112 if (trapnr < X86_TRAP_UD) { 113 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, 114 error_code, trapnr)) 115 return 0; 116 } 117 } else if (!user_mode(regs)) { 118 if (fixup_exception(regs, trapnr, error_code, 0)) 119 return 0; 120 121 tsk->thread.error_code = error_code; 122 tsk->thread.trap_nr = trapnr; 123 die(str, regs, error_code); 124 } else { 125 if (fixup_vdso_exception(regs, trapnr, error_code, 0)) 126 return 0; 127 } 128 129 /* 130 * We want error_code and trap_nr set for userspace faults and 131 * kernelspace faults which result in die(), but not 132 * kernelspace faults which are fixed up. die() gives the 133 * process no chance to handle the signal and notice the 134 * kernel fault information, so that won't result in polluting 135 * the information about previously queued, but not yet 136 * delivered, faults. See also exc_general_protection below. 137 */ 138 tsk->thread.error_code = error_code; 139 tsk->thread.trap_nr = trapnr; 140 141 return -1; 142 } 143 144 static void show_signal(struct task_struct *tsk, int signr, 145 const char *type, const char *desc, 146 struct pt_regs *regs, long error_code) 147 { 148 if (show_unhandled_signals && unhandled_signal(tsk, signr) && 149 printk_ratelimit()) { 150 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx", 151 tsk->comm, task_pid_nr(tsk), type, desc, 152 regs->ip, regs->sp, error_code); 153 print_vma_addr(KERN_CONT " in ", regs->ip); 154 pr_cont("\n"); 155 } 156 } 157 158 static void 159 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, 160 long error_code, int sicode, void __user *addr) 161 { 162 struct task_struct *tsk = current; 163 164 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) 165 return; 166 167 show_signal(tsk, signr, "trap ", str, regs, error_code); 168 169 if (!sicode) 170 force_sig(signr); 171 else 172 force_sig_fault(signr, sicode, addr); 173 } 174 NOKPROBE_SYMBOL(do_trap); 175 176 static void do_error_trap(struct pt_regs *regs, long error_code, char *str, 177 unsigned long trapnr, int signr, int sicode, void __user *addr) 178 { 179 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 180 181 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != 182 NOTIFY_STOP) { 183 cond_local_irq_enable(regs); 184 do_trap(trapnr, signr, str, regs, error_code, sicode, addr); 185 cond_local_irq_disable(regs); 186 } 187 } 188 189 /* 190 * Posix requires to provide the address of the faulting instruction for 191 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t. 192 * 193 * This address is usually regs->ip, but when an uprobe moved the code out 194 * of line then regs->ip points to the XOL code which would confuse 195 * anything which analyzes the fault address vs. the unmodified binary. If 196 * a trap happened in XOL code then uprobe maps regs->ip back to the 197 * original instruction address. 198 */ 199 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs) 200 { 201 return (void __user *)uprobe_get_trap_addr(regs); 202 } 203 204 DEFINE_IDTENTRY(exc_divide_error) 205 { 206 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE, 207 FPE_INTDIV, error_get_trap_addr(regs)); 208 } 209 210 DEFINE_IDTENTRY(exc_overflow) 211 { 212 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); 213 } 214 215 #ifdef CONFIG_X86_KERNEL_IBT 216 217 static __ro_after_init bool ibt_fatal = true; 218 219 extern void ibt_selftest_ip(void); /* code label defined in asm below */ 220 221 enum cp_error_code { 222 CP_EC = (1 << 15) - 1, 223 224 CP_RET = 1, 225 CP_IRET = 2, 226 CP_ENDBR = 3, 227 CP_RSTRORSSP = 4, 228 CP_SETSSBSY = 5, 229 230 CP_ENCL = 1 << 15, 231 }; 232 233 DEFINE_IDTENTRY_ERRORCODE(exc_control_protection) 234 { 235 if (!cpu_feature_enabled(X86_FEATURE_IBT)) { 236 pr_err("Unexpected #CP\n"); 237 BUG(); 238 } 239 240 if (WARN_ON_ONCE(user_mode(regs) || (error_code & CP_EC) != CP_ENDBR)) 241 return; 242 243 if (unlikely(regs->ip == (unsigned long)&ibt_selftest_ip)) { 244 regs->ax = 0; 245 return; 246 } 247 248 pr_err("Missing ENDBR: %pS\n", (void *)instruction_pointer(regs)); 249 if (!ibt_fatal) { 250 printk(KERN_DEFAULT CUT_HERE); 251 __warn(__FILE__, __LINE__, (void *)regs->ip, TAINT_WARN, regs, NULL); 252 return; 253 } 254 BUG(); 255 } 256 257 /* Must be noinline to ensure uniqueness of ibt_selftest_ip. */ 258 noinline bool ibt_selftest(void) 259 { 260 unsigned long ret; 261 262 asm (" lea ibt_selftest_ip(%%rip), %%rax\n\t" 263 ANNOTATE_RETPOLINE_SAFE 264 " jmp *%%rax\n\t" 265 "ibt_selftest_ip:\n\t" 266 UNWIND_HINT_FUNC 267 ANNOTATE_NOENDBR 268 " nop\n\t" 269 270 : "=a" (ret) : : "memory"); 271 272 return !ret; 273 } 274 275 static int __init ibt_setup(char *str) 276 { 277 if (!strcmp(str, "off")) 278 setup_clear_cpu_cap(X86_FEATURE_IBT); 279 280 if (!strcmp(str, "warn")) 281 ibt_fatal = false; 282 283 return 1; 284 } 285 286 __setup("ibt=", ibt_setup); 287 288 #endif /* CONFIG_X86_KERNEL_IBT */ 289 290 #ifdef CONFIG_X86_F00F_BUG 291 void handle_invalid_op(struct pt_regs *regs) 292 #else 293 static inline void handle_invalid_op(struct pt_regs *regs) 294 #endif 295 { 296 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL, 297 ILL_ILLOPN, error_get_trap_addr(regs)); 298 } 299 300 static noinstr bool handle_bug(struct pt_regs *regs) 301 { 302 bool handled = false; 303 304 if (!is_valid_bugaddr(regs->ip)) 305 return handled; 306 307 /* 308 * All lies, just get the WARN/BUG out. 309 */ 310 instrumentation_begin(); 311 /* 312 * Since we're emulating a CALL with exceptions, restore the interrupt 313 * state to what it was at the exception site. 314 */ 315 if (regs->flags & X86_EFLAGS_IF) 316 raw_local_irq_enable(); 317 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN || 318 handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) { 319 regs->ip += LEN_UD2; 320 handled = true; 321 } 322 if (regs->flags & X86_EFLAGS_IF) 323 raw_local_irq_disable(); 324 instrumentation_end(); 325 326 return handled; 327 } 328 329 DEFINE_IDTENTRY_RAW(exc_invalid_op) 330 { 331 irqentry_state_t state; 332 333 /* 334 * We use UD2 as a short encoding for 'CALL __WARN', as such 335 * handle it before exception entry to avoid recursive WARN 336 * in case exception entry is the one triggering WARNs. 337 */ 338 if (!user_mode(regs) && handle_bug(regs)) 339 return; 340 341 state = irqentry_enter(regs); 342 instrumentation_begin(); 343 handle_invalid_op(regs); 344 instrumentation_end(); 345 irqentry_exit(regs, state); 346 } 347 348 DEFINE_IDTENTRY(exc_coproc_segment_overrun) 349 { 350 do_error_trap(regs, 0, "coprocessor segment overrun", 351 X86_TRAP_OLD_MF, SIGFPE, 0, NULL); 352 } 353 354 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss) 355 { 356 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV, 357 0, NULL); 358 } 359 360 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present) 361 { 362 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP, 363 SIGBUS, 0, NULL); 364 } 365 366 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment) 367 { 368 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS, 369 0, NULL); 370 } 371 372 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check) 373 { 374 char *str = "alignment check"; 375 376 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP) 377 return; 378 379 if (!user_mode(regs)) 380 die("Split lock detected\n", regs, error_code); 381 382 local_irq_enable(); 383 384 if (handle_user_split_lock(regs, error_code)) 385 goto out; 386 387 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, 388 error_code, BUS_ADRALN, NULL); 389 390 out: 391 local_irq_disable(); 392 } 393 394 #ifdef CONFIG_VMAP_STACK 395 __visible void __noreturn handle_stack_overflow(struct pt_regs *regs, 396 unsigned long fault_address, 397 struct stack_info *info) 398 { 399 const char *name = stack_type_name(info->type); 400 401 printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n", 402 name, (void *)fault_address, info->begin, info->end); 403 404 die("stack guard page", regs, 0); 405 406 /* Be absolutely certain we don't return. */ 407 panic("%s stack guard hit", name); 408 } 409 #endif 410 411 /* 412 * Runs on an IST stack for x86_64 and on a special task stack for x86_32. 413 * 414 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the 415 * SDM's warnings about double faults being unrecoverable, returning works as 416 * expected. Presumably what the SDM actually means is that the CPU may get 417 * the register state wrong on entry, so returning could be a bad idea. 418 * 419 * Various CPU engineers have promised that double faults due to an IRET fault 420 * while the stack is read-only are, in fact, recoverable. 421 * 422 * On x86_32, this is entered through a task gate, and regs are synthesized 423 * from the TSS. Returning is, in principle, okay, but changes to regs will 424 * be lost. If, for some reason, we need to return to a context with modified 425 * regs, the shim code could be adjusted to synchronize the registers. 426 * 427 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs 428 * to be read before doing anything else. 429 */ 430 DEFINE_IDTENTRY_DF(exc_double_fault) 431 { 432 static const char str[] = "double fault"; 433 struct task_struct *tsk = current; 434 435 #ifdef CONFIG_VMAP_STACK 436 unsigned long address = read_cr2(); 437 struct stack_info info; 438 #endif 439 440 #ifdef CONFIG_X86_ESPFIX64 441 extern unsigned char native_irq_return_iret[]; 442 443 /* 444 * If IRET takes a non-IST fault on the espfix64 stack, then we 445 * end up promoting it to a doublefault. In that case, take 446 * advantage of the fact that we're not using the normal (TSS.sp0) 447 * stack right now. We can write a fake #GP(0) frame at TSS.sp0 448 * and then modify our own IRET frame so that, when we return, 449 * we land directly at the #GP(0) vector with the stack already 450 * set up according to its expectations. 451 * 452 * The net result is that our #GP handler will think that we 453 * entered from usermode with the bad user context. 454 * 455 * No need for nmi_enter() here because we don't use RCU. 456 */ 457 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && 458 regs->cs == __KERNEL_CS && 459 regs->ip == (unsigned long)native_irq_return_iret) 460 { 461 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 462 unsigned long *p = (unsigned long *)regs->sp; 463 464 /* 465 * regs->sp points to the failing IRET frame on the 466 * ESPFIX64 stack. Copy it to the entry stack. This fills 467 * in gpregs->ss through gpregs->ip. 468 * 469 */ 470 gpregs->ip = p[0]; 471 gpregs->cs = p[1]; 472 gpregs->flags = p[2]; 473 gpregs->sp = p[3]; 474 gpregs->ss = p[4]; 475 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ 476 477 /* 478 * Adjust our frame so that we return straight to the #GP 479 * vector with the expected RSP value. This is safe because 480 * we won't enable interrupts or schedule before we invoke 481 * general_protection, so nothing will clobber the stack 482 * frame we just set up. 483 * 484 * We will enter general_protection with kernel GSBASE, 485 * which is what the stub expects, given that the faulting 486 * RIP will be the IRET instruction. 487 */ 488 regs->ip = (unsigned long)asm_exc_general_protection; 489 regs->sp = (unsigned long)&gpregs->orig_ax; 490 491 return; 492 } 493 #endif 494 495 irqentry_nmi_enter(regs); 496 instrumentation_begin(); 497 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); 498 499 tsk->thread.error_code = error_code; 500 tsk->thread.trap_nr = X86_TRAP_DF; 501 502 #ifdef CONFIG_VMAP_STACK 503 /* 504 * If we overflow the stack into a guard page, the CPU will fail 505 * to deliver #PF and will send #DF instead. Similarly, if we 506 * take any non-IST exception while too close to the bottom of 507 * the stack, the processor will get a page fault while 508 * delivering the exception and will generate a double fault. 509 * 510 * According to the SDM (footnote in 6.15 under "Interrupt 14 - 511 * Page-Fault Exception (#PF): 512 * 513 * Processors update CR2 whenever a page fault is detected. If a 514 * second page fault occurs while an earlier page fault is being 515 * delivered, the faulting linear address of the second fault will 516 * overwrite the contents of CR2 (replacing the previous 517 * address). These updates to CR2 occur even if the page fault 518 * results in a double fault or occurs during the delivery of a 519 * double fault. 520 * 521 * The logic below has a small possibility of incorrectly diagnosing 522 * some errors as stack overflows. For example, if the IDT or GDT 523 * gets corrupted such that #GP delivery fails due to a bad descriptor 524 * causing #GP and we hit this condition while CR2 coincidentally 525 * points to the stack guard page, we'll think we overflowed the 526 * stack. Given that we're going to panic one way or another 527 * if this happens, this isn't necessarily worth fixing. 528 * 529 * If necessary, we could improve the test by only diagnosing 530 * a stack overflow if the saved RSP points within 47 bytes of 531 * the bottom of the stack: if RSP == tsk_stack + 48 and we 532 * take an exception, the stack is already aligned and there 533 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a 534 * possible error code, so a stack overflow would *not* double 535 * fault. With any less space left, exception delivery could 536 * fail, and, as a practical matter, we've overflowed the 537 * stack even if the actual trigger for the double fault was 538 * something else. 539 */ 540 if (get_stack_guard_info((void *)address, &info)) 541 handle_stack_overflow(regs, address, &info); 542 #endif 543 544 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code); 545 die("double fault", regs, error_code); 546 panic("Machine halted."); 547 instrumentation_end(); 548 } 549 550 DEFINE_IDTENTRY(exc_bounds) 551 { 552 if (notify_die(DIE_TRAP, "bounds", regs, 0, 553 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) 554 return; 555 cond_local_irq_enable(regs); 556 557 if (!user_mode(regs)) 558 die("bounds", regs, 0); 559 560 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL); 561 562 cond_local_irq_disable(regs); 563 } 564 565 enum kernel_gp_hint { 566 GP_NO_HINT, 567 GP_NON_CANONICAL, 568 GP_CANONICAL 569 }; 570 571 /* 572 * When an uncaught #GP occurs, try to determine the memory address accessed by 573 * the instruction and return that address to the caller. Also, try to figure 574 * out whether any part of the access to that address was non-canonical. 575 */ 576 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, 577 unsigned long *addr) 578 { 579 u8 insn_buf[MAX_INSN_SIZE]; 580 struct insn insn; 581 int ret; 582 583 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, 584 MAX_INSN_SIZE)) 585 return GP_NO_HINT; 586 587 ret = insn_decode_kernel(&insn, insn_buf); 588 if (ret < 0) 589 return GP_NO_HINT; 590 591 *addr = (unsigned long)insn_get_addr_ref(&insn, regs); 592 if (*addr == -1UL) 593 return GP_NO_HINT; 594 595 #ifdef CONFIG_X86_64 596 /* 597 * Check that: 598 * - the operand is not in the kernel half 599 * - the last byte of the operand is not in the user canonical half 600 */ 601 if (*addr < ~__VIRTUAL_MASK && 602 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) 603 return GP_NON_CANONICAL; 604 #endif 605 606 return GP_CANONICAL; 607 } 608 609 #define GPFSTR "general protection fault" 610 611 static bool fixup_iopl_exception(struct pt_regs *regs) 612 { 613 struct thread_struct *t = ¤t->thread; 614 unsigned char byte; 615 unsigned long ip; 616 617 if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3) 618 return false; 619 620 if (insn_get_effective_ip(regs, &ip)) 621 return false; 622 623 if (get_user(byte, (const char __user *)ip)) 624 return false; 625 626 if (byte != 0xfa && byte != 0xfb) 627 return false; 628 629 if (!t->iopl_warn && printk_ratelimit()) { 630 pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx", 631 current->comm, task_pid_nr(current), ip); 632 print_vma_addr(KERN_CONT " in ", ip); 633 pr_cont("\n"); 634 t->iopl_warn = 1; 635 } 636 637 regs->ip += 1; 638 return true; 639 } 640 641 /* 642 * The unprivileged ENQCMD instruction generates #GPs if the 643 * IA32_PASID MSR has not been populated. If possible, populate 644 * the MSR from a PASID previously allocated to the mm. 645 */ 646 static bool try_fixup_enqcmd_gp(void) 647 { 648 #ifdef CONFIG_IOMMU_SVA 649 u32 pasid; 650 651 /* 652 * MSR_IA32_PASID is managed using XSAVE. Directly 653 * writing to the MSR is only possible when fpregs 654 * are valid and the fpstate is not. This is 655 * guaranteed when handling a userspace exception 656 * in *before* interrupts are re-enabled. 657 */ 658 lockdep_assert_irqs_disabled(); 659 660 /* 661 * Hardware without ENQCMD will not generate 662 * #GPs that can be fixed up here. 663 */ 664 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 665 return false; 666 667 pasid = current->mm->pasid; 668 669 /* 670 * If the mm has not been allocated a 671 * PASID, the #GP can not be fixed up. 672 */ 673 if (!pasid_valid(pasid)) 674 return false; 675 676 /* 677 * Did this thread already have its PASID activated? 678 * If so, the #GP must be from something else. 679 */ 680 if (current->pasid_activated) 681 return false; 682 683 wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); 684 current->pasid_activated = 1; 685 686 return true; 687 #else 688 return false; 689 #endif 690 } 691 692 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr, 693 unsigned long error_code, const char *str) 694 { 695 if (fixup_exception(regs, trapnr, error_code, 0)) 696 return true; 697 698 current->thread.error_code = error_code; 699 current->thread.trap_nr = trapnr; 700 701 /* 702 * To be potentially processing a kprobe fault and to trust the result 703 * from kprobe_running(), we have to be non-preemptible. 704 */ 705 if (!preemptible() && kprobe_running() && 706 kprobe_fault_handler(regs, trapnr)) 707 return true; 708 709 return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP; 710 } 711 712 static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr, 713 unsigned long error_code, const char *str) 714 { 715 current->thread.error_code = error_code; 716 current->thread.trap_nr = trapnr; 717 show_signal(current, SIGSEGV, "", str, regs, error_code); 718 force_sig(SIGSEGV); 719 } 720 721 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) 722 { 723 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; 724 enum kernel_gp_hint hint = GP_NO_HINT; 725 unsigned long gp_addr; 726 727 if (user_mode(regs) && try_fixup_enqcmd_gp()) 728 return; 729 730 cond_local_irq_enable(regs); 731 732 if (static_cpu_has(X86_FEATURE_UMIP)) { 733 if (user_mode(regs) && fixup_umip_exception(regs)) 734 goto exit; 735 } 736 737 if (v8086_mode(regs)) { 738 local_irq_enable(); 739 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); 740 local_irq_disable(); 741 return; 742 } 743 744 if (user_mode(regs)) { 745 if (fixup_iopl_exception(regs)) 746 goto exit; 747 748 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0)) 749 goto exit; 750 751 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc); 752 goto exit; 753 } 754 755 if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc)) 756 goto exit; 757 758 if (error_code) 759 snprintf(desc, sizeof(desc), "segment-related " GPFSTR); 760 else 761 hint = get_kernel_gp_address(regs, &gp_addr); 762 763 if (hint != GP_NO_HINT) 764 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", 765 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address" 766 : "maybe for address", 767 gp_addr); 768 769 /* 770 * KASAN is interested only in the non-canonical case, clear it 771 * otherwise. 772 */ 773 if (hint != GP_NON_CANONICAL) 774 gp_addr = 0; 775 776 die_addr(desc, regs, error_code, gp_addr); 777 778 exit: 779 cond_local_irq_disable(regs); 780 } 781 782 static bool do_int3(struct pt_regs *regs) 783 { 784 int res; 785 786 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 787 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, 788 SIGTRAP) == NOTIFY_STOP) 789 return true; 790 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 791 792 #ifdef CONFIG_KPROBES 793 if (kprobe_int3_handler(regs)) 794 return true; 795 #endif 796 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP); 797 798 return res == NOTIFY_STOP; 799 } 800 NOKPROBE_SYMBOL(do_int3); 801 802 static void do_int3_user(struct pt_regs *regs) 803 { 804 if (do_int3(regs)) 805 return; 806 807 cond_local_irq_enable(regs); 808 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL); 809 cond_local_irq_disable(regs); 810 } 811 812 DEFINE_IDTENTRY_RAW(exc_int3) 813 { 814 /* 815 * poke_int3_handler() is completely self contained code; it does (and 816 * must) *NOT* call out to anything, lest it hits upon yet another 817 * INT3. 818 */ 819 if (poke_int3_handler(regs)) 820 return; 821 822 /* 823 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely() 824 * and therefore can trigger INT3, hence poke_int3_handler() must 825 * be done before. If the entry came from kernel mode, then use 826 * nmi_enter() because the INT3 could have been hit in any context 827 * including NMI. 828 */ 829 if (user_mode(regs)) { 830 irqentry_enter_from_user_mode(regs); 831 instrumentation_begin(); 832 do_int3_user(regs); 833 instrumentation_end(); 834 irqentry_exit_to_user_mode(regs); 835 } else { 836 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 837 838 instrumentation_begin(); 839 if (!do_int3(regs)) 840 die("int3", regs, 0); 841 instrumentation_end(); 842 irqentry_nmi_exit(regs, irq_state); 843 } 844 } 845 846 #ifdef CONFIG_X86_64 847 /* 848 * Help handler running on a per-cpu (IST or entry trampoline) stack 849 * to switch to the normal thread stack if the interrupted code was in 850 * user mode. The actual stack switch is done in entry_64.S 851 */ 852 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) 853 { 854 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(cpu_current_top_of_stack) - 1; 855 if (regs != eregs) 856 *regs = *eregs; 857 return regs; 858 } 859 860 #ifdef CONFIG_AMD_MEM_ENCRYPT 861 asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs) 862 { 863 unsigned long sp, *stack; 864 struct stack_info info; 865 struct pt_regs *regs_ret; 866 867 /* 868 * In the SYSCALL entry path the RSP value comes from user-space - don't 869 * trust it and switch to the current kernel stack 870 */ 871 if (ip_within_syscall_gap(regs)) { 872 sp = this_cpu_read(cpu_current_top_of_stack); 873 goto sync; 874 } 875 876 /* 877 * From here on the RSP value is trusted. Now check whether entry 878 * happened from a safe stack. Not safe are the entry or unknown stacks, 879 * use the fall-back stack instead in this case. 880 */ 881 sp = regs->sp; 882 stack = (unsigned long *)sp; 883 884 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY || 885 info.type > STACK_TYPE_EXCEPTION_LAST) 886 sp = __this_cpu_ist_top_va(VC2); 887 888 sync: 889 /* 890 * Found a safe stack - switch to it as if the entry didn't happen via 891 * IST stack. The code below only copies pt_regs, the real switch happens 892 * in assembly code. 893 */ 894 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret); 895 896 regs_ret = (struct pt_regs *)sp; 897 *regs_ret = *regs; 898 899 return regs_ret; 900 } 901 #endif 902 903 asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs) 904 { 905 struct pt_regs tmp, *new_stack; 906 907 /* 908 * This is called from entry_64.S early in handling a fault 909 * caused by a bad iret to user mode. To handle the fault 910 * correctly, we want to move our stack frame to where it would 911 * be had we entered directly on the entry stack (rather than 912 * just below the IRET frame) and we want to pretend that the 913 * exception came from the IRET target. 914 */ 915 new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 916 917 /* Copy the IRET target to the temporary storage. */ 918 __memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8); 919 920 /* Copy the remainder of the stack from the current stack. */ 921 __memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip)); 922 923 /* Update the entry stack */ 924 __memcpy(new_stack, &tmp, sizeof(tmp)); 925 926 BUG_ON(!user_mode(new_stack)); 927 return new_stack; 928 } 929 #endif 930 931 static bool is_sysenter_singlestep(struct pt_regs *regs) 932 { 933 /* 934 * We don't try for precision here. If we're anywhere in the region of 935 * code that can be single-stepped in the SYSENTER entry path, then 936 * assume that this is a useless single-step trap due to SYSENTER 937 * being invoked with TF set. (We don't know in advance exactly 938 * which instructions will be hit because BTF could plausibly 939 * be set.) 940 */ 941 #ifdef CONFIG_X86_32 942 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < 943 (unsigned long)__end_SYSENTER_singlestep_region - 944 (unsigned long)__begin_SYSENTER_singlestep_region; 945 #elif defined(CONFIG_IA32_EMULATION) 946 return (regs->ip - (unsigned long)entry_SYSENTER_compat) < 947 (unsigned long)__end_entry_SYSENTER_compat - 948 (unsigned long)entry_SYSENTER_compat; 949 #else 950 return false; 951 #endif 952 } 953 954 static __always_inline unsigned long debug_read_clear_dr6(void) 955 { 956 unsigned long dr6; 957 958 /* 959 * The Intel SDM says: 960 * 961 * Certain debug exceptions may clear bits 0-3. The remaining 962 * contents of the DR6 register are never cleared by the 963 * processor. To avoid confusion in identifying debug 964 * exceptions, debug handlers should clear the register before 965 * returning to the interrupted task. 966 * 967 * Keep it simple: clear DR6 immediately. 968 */ 969 get_debugreg(dr6, 6); 970 set_debugreg(DR6_RESERVED, 6); 971 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */ 972 973 return dr6; 974 } 975 976 /* 977 * Our handling of the processor debug registers is non-trivial. 978 * We do not clear them on entry and exit from the kernel. Therefore 979 * it is possible to get a watchpoint trap here from inside the kernel. 980 * However, the code in ./ptrace.c has ensured that the user can 981 * only set watchpoints on userspace addresses. Therefore the in-kernel 982 * watchpoint trap can only occur in code which is reading/writing 983 * from user space. Such code must not hold kernel locks (since it 984 * can equally take a page fault), therefore it is safe to call 985 * force_sig_info even though that claims and releases locks. 986 * 987 * Code in ./signal.c ensures that the debug control register 988 * is restored before we deliver any signal, and therefore that 989 * user code runs with the correct debug control register even though 990 * we clear it here. 991 * 992 * Being careful here means that we don't have to be as careful in a 993 * lot of more complicated places (task switching can be a bit lazy 994 * about restoring all the debug state, and ptrace doesn't have to 995 * find every occurrence of the TF bit that could be saved away even 996 * by user code) 997 * 998 * May run on IST stack. 999 */ 1000 1001 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) 1002 { 1003 /* 1004 * Notifiers will clear bits in @dr6 to indicate the event has been 1005 * consumed - hw_breakpoint_handler(), single_stop_cont(). 1006 * 1007 * Notifiers will set bits in @virtual_dr6 to indicate the desire 1008 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler(). 1009 */ 1010 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP) 1011 return true; 1012 1013 return false; 1014 } 1015 1016 static __always_inline void exc_debug_kernel(struct pt_regs *regs, 1017 unsigned long dr6) 1018 { 1019 /* 1020 * Disable breakpoints during exception handling; recursive exceptions 1021 * are exceedingly 'fun'. 1022 * 1023 * Since this function is NOKPROBE, and that also applies to 1024 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a 1025 * HW_BREAKPOINT_W on our stack) 1026 * 1027 * Entry text is excluded for HW_BP_X and cpu_entry_area, which 1028 * includes the entry stack is excluded for everything. 1029 */ 1030 unsigned long dr7 = local_db_save(); 1031 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 1032 instrumentation_begin(); 1033 1034 /* 1035 * If something gets miswired and we end up here for a user mode 1036 * #DB, we will malfunction. 1037 */ 1038 WARN_ON_ONCE(user_mode(regs)); 1039 1040 if (test_thread_flag(TIF_BLOCKSTEP)) { 1041 /* 1042 * The SDM says "The processor clears the BTF flag when it 1043 * generates a debug exception." but PTRACE_BLOCKSTEP requested 1044 * it for userspace, but we just took a kernel #DB, so re-set 1045 * BTF. 1046 */ 1047 unsigned long debugctl; 1048 1049 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1050 debugctl |= DEBUGCTLMSR_BTF; 1051 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1052 } 1053 1054 /* 1055 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a 1056 * watchpoint at the same time then that will still be handled. 1057 */ 1058 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) 1059 dr6 &= ~DR_STEP; 1060 1061 /* 1062 * The kernel doesn't use INT1 1063 */ 1064 if (!dr6) 1065 goto out; 1066 1067 if (notify_debug(regs, &dr6)) 1068 goto out; 1069 1070 /* 1071 * The kernel doesn't use TF single-step outside of: 1072 * 1073 * - Kprobes, consumed through kprobe_debug_handler() 1074 * - KGDB, consumed through notify_debug() 1075 * 1076 * So if we get here with DR_STEP set, something is wonky. 1077 * 1078 * A known way to trigger this is through QEMU's GDB stub, 1079 * which leaks #DB into the guest and causes IST recursion. 1080 */ 1081 if (WARN_ON_ONCE(dr6 & DR_STEP)) 1082 regs->flags &= ~X86_EFLAGS_TF; 1083 out: 1084 instrumentation_end(); 1085 irqentry_nmi_exit(regs, irq_state); 1086 1087 local_db_restore(dr7); 1088 } 1089 1090 static __always_inline void exc_debug_user(struct pt_regs *regs, 1091 unsigned long dr6) 1092 { 1093 bool icebp; 1094 1095 /* 1096 * If something gets miswired and we end up here for a kernel mode 1097 * #DB, we will malfunction. 1098 */ 1099 WARN_ON_ONCE(!user_mode(regs)); 1100 1101 /* 1102 * NB: We can't easily clear DR7 here because 1103 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access 1104 * user memory, etc. This means that a recursive #DB is possible. If 1105 * this happens, that #DB will hit exc_debug_kernel() and clear DR7. 1106 * Since we're not on the IST stack right now, everything will be 1107 * fine. 1108 */ 1109 1110 irqentry_enter_from_user_mode(regs); 1111 instrumentation_begin(); 1112 1113 /* 1114 * Start the virtual/ptrace DR6 value with just the DR_STEP mask 1115 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits. 1116 * 1117 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6) 1118 * even if it is not the result of PTRACE_SINGLESTEP. 1119 */ 1120 current->thread.virtual_dr6 = (dr6 & DR_STEP); 1121 1122 /* 1123 * The SDM says "The processor clears the BTF flag when it 1124 * generates a debug exception." Clear TIF_BLOCKSTEP to keep 1125 * TIF_BLOCKSTEP in sync with the hardware BTF flag. 1126 */ 1127 clear_thread_flag(TIF_BLOCKSTEP); 1128 1129 /* 1130 * If dr6 has no reason to give us about the origin of this trap, 1131 * then it's very likely the result of an icebp/int01 trap. 1132 * User wants a sigtrap for that. 1133 */ 1134 icebp = !dr6; 1135 1136 if (notify_debug(regs, &dr6)) 1137 goto out; 1138 1139 /* It's safe to allow irq's after DR6 has been saved */ 1140 local_irq_enable(); 1141 1142 if (v8086_mode(regs)) { 1143 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB); 1144 goto out_irq; 1145 } 1146 1147 /* #DB for bus lock can only be triggered from userspace. */ 1148 if (dr6 & DR_BUS_LOCK) 1149 handle_bus_lock(regs); 1150 1151 /* Add the virtual_dr6 bits for signals. */ 1152 dr6 |= current->thread.virtual_dr6; 1153 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp) 1154 send_sigtrap(regs, 0, get_si_code(dr6)); 1155 1156 out_irq: 1157 local_irq_disable(); 1158 out: 1159 instrumentation_end(); 1160 irqentry_exit_to_user_mode(regs); 1161 } 1162 1163 #ifdef CONFIG_X86_64 1164 /* IST stack entry */ 1165 DEFINE_IDTENTRY_DEBUG(exc_debug) 1166 { 1167 exc_debug_kernel(regs, debug_read_clear_dr6()); 1168 } 1169 1170 /* User entry, runs on regular task stack */ 1171 DEFINE_IDTENTRY_DEBUG_USER(exc_debug) 1172 { 1173 exc_debug_user(regs, debug_read_clear_dr6()); 1174 } 1175 #else 1176 /* 32 bit does not have separate entry points. */ 1177 DEFINE_IDTENTRY_RAW(exc_debug) 1178 { 1179 unsigned long dr6 = debug_read_clear_dr6(); 1180 1181 if (user_mode(regs)) 1182 exc_debug_user(regs, dr6); 1183 else 1184 exc_debug_kernel(regs, dr6); 1185 } 1186 #endif 1187 1188 /* 1189 * Note that we play around with the 'TS' bit in an attempt to get 1190 * the correct behaviour even in the presence of the asynchronous 1191 * IRQ13 behaviour 1192 */ 1193 static void math_error(struct pt_regs *regs, int trapnr) 1194 { 1195 struct task_struct *task = current; 1196 struct fpu *fpu = &task->thread.fpu; 1197 int si_code; 1198 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : 1199 "simd exception"; 1200 1201 cond_local_irq_enable(regs); 1202 1203 if (!user_mode(regs)) { 1204 if (fixup_exception(regs, trapnr, 0, 0)) 1205 goto exit; 1206 1207 task->thread.error_code = 0; 1208 task->thread.trap_nr = trapnr; 1209 1210 if (notify_die(DIE_TRAP, str, regs, 0, trapnr, 1211 SIGFPE) != NOTIFY_STOP) 1212 die(str, regs, 0); 1213 goto exit; 1214 } 1215 1216 /* 1217 * Synchronize the FPU register state to the memory register state 1218 * if necessary. This allows the exception handler to inspect it. 1219 */ 1220 fpu_sync_fpstate(fpu); 1221 1222 task->thread.trap_nr = trapnr; 1223 task->thread.error_code = 0; 1224 1225 si_code = fpu__exception_code(fpu, trapnr); 1226 /* Retry when we get spurious exceptions: */ 1227 if (!si_code) 1228 goto exit; 1229 1230 if (fixup_vdso_exception(regs, trapnr, 0, 0)) 1231 goto exit; 1232 1233 force_sig_fault(SIGFPE, si_code, 1234 (void __user *)uprobe_get_trap_addr(regs)); 1235 exit: 1236 cond_local_irq_disable(regs); 1237 } 1238 1239 DEFINE_IDTENTRY(exc_coprocessor_error) 1240 { 1241 math_error(regs, X86_TRAP_MF); 1242 } 1243 1244 DEFINE_IDTENTRY(exc_simd_coprocessor_error) 1245 { 1246 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) { 1247 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */ 1248 if (!static_cpu_has(X86_FEATURE_XMM)) { 1249 __exc_general_protection(regs, 0); 1250 return; 1251 } 1252 } 1253 math_error(regs, X86_TRAP_XF); 1254 } 1255 1256 DEFINE_IDTENTRY(exc_spurious_interrupt_bug) 1257 { 1258 /* 1259 * This addresses a Pentium Pro Erratum: 1260 * 1261 * PROBLEM: If the APIC subsystem is configured in mixed mode with 1262 * Virtual Wire mode implemented through the local APIC, an 1263 * interrupt vector of 0Fh (Intel reserved encoding) may be 1264 * generated by the local APIC (Int 15). This vector may be 1265 * generated upon receipt of a spurious interrupt (an interrupt 1266 * which is removed before the system receives the INTA sequence) 1267 * instead of the programmed 8259 spurious interrupt vector. 1268 * 1269 * IMPLICATION: The spurious interrupt vector programmed in the 1270 * 8259 is normally handled by an operating system's spurious 1271 * interrupt handler. However, a vector of 0Fh is unknown to some 1272 * operating systems, which would crash if this erratum occurred. 1273 * 1274 * In theory this could be limited to 32bit, but the handler is not 1275 * hurting and who knows which other CPUs suffer from this. 1276 */ 1277 } 1278 1279 static bool handle_xfd_event(struct pt_regs *regs) 1280 { 1281 u64 xfd_err; 1282 int err; 1283 1284 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD)) 1285 return false; 1286 1287 rdmsrl(MSR_IA32_XFD_ERR, xfd_err); 1288 if (!xfd_err) 1289 return false; 1290 1291 wrmsrl(MSR_IA32_XFD_ERR, 0); 1292 1293 /* Die if that happens in kernel space */ 1294 if (WARN_ON(!user_mode(regs))) 1295 return false; 1296 1297 local_irq_enable(); 1298 1299 err = xfd_enable_feature(xfd_err); 1300 1301 switch (err) { 1302 case -EPERM: 1303 force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs)); 1304 break; 1305 case -EFAULT: 1306 force_sig(SIGSEGV); 1307 break; 1308 } 1309 1310 local_irq_disable(); 1311 return true; 1312 } 1313 1314 DEFINE_IDTENTRY(exc_device_not_available) 1315 { 1316 unsigned long cr0 = read_cr0(); 1317 1318 if (handle_xfd_event(regs)) 1319 return; 1320 1321 #ifdef CONFIG_MATH_EMULATION 1322 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) { 1323 struct math_emu_info info = { }; 1324 1325 cond_local_irq_enable(regs); 1326 1327 info.regs = regs; 1328 math_emulate(&info); 1329 1330 cond_local_irq_disable(regs); 1331 return; 1332 } 1333 #endif 1334 1335 /* This should not happen. */ 1336 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { 1337 /* Try to fix it up and carry on. */ 1338 write_cr0(cr0 & ~X86_CR0_TS); 1339 } else { 1340 /* 1341 * Something terrible happened, and we're better off trying 1342 * to kill the task than getting stuck in a never-ending 1343 * loop of #NM faults. 1344 */ 1345 die("unexpected #NM exception", regs, 0); 1346 } 1347 } 1348 1349 #ifdef CONFIG_INTEL_TDX_GUEST 1350 1351 #define VE_FAULT_STR "VE fault" 1352 1353 static void ve_raise_fault(struct pt_regs *regs, long error_code) 1354 { 1355 if (user_mode(regs)) { 1356 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR); 1357 return; 1358 } 1359 1360 if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, VE_FAULT_STR)) 1361 return; 1362 1363 die_addr(VE_FAULT_STR, regs, error_code, 0); 1364 } 1365 1366 /* 1367 * Virtualization Exceptions (#VE) are delivered to TDX guests due to 1368 * specific guest actions which may happen in either user space or the 1369 * kernel: 1370 * 1371 * * Specific instructions (WBINVD, for example) 1372 * * Specific MSR accesses 1373 * * Specific CPUID leaf accesses 1374 * * Access to specific guest physical addresses 1375 * 1376 * In the settings that Linux will run in, virtualization exceptions are 1377 * never generated on accesses to normal, TD-private memory that has been 1378 * accepted (by BIOS or with tdx_enc_status_changed()). 1379 * 1380 * Syscall entry code has a critical window where the kernel stack is not 1381 * yet set up. Any exception in this window leads to hard to debug issues 1382 * and can be exploited for privilege escalation. Exceptions in the NMI 1383 * entry code also cause issues. Returning from the exception handler with 1384 * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack. 1385 * 1386 * For these reasons, the kernel avoids #VEs during the syscall gap and 1387 * the NMI entry code. Entry code paths do not access TD-shared memory, 1388 * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves 1389 * that might generate #VE. VMM can remove memory from TD at any point, 1390 * but access to unaccepted (or missing) private memory leads to VM 1391 * termination, not to #VE. 1392 * 1393 * Similarly to page faults and breakpoints, #VEs are allowed in NMI 1394 * handlers once the kernel is ready to deal with nested NMIs. 1395 * 1396 * During #VE delivery, all interrupts, including NMIs, are blocked until 1397 * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads 1398 * the VE info. 1399 * 1400 * If a guest kernel action which would normally cause a #VE occurs in 1401 * the interrupt-disabled region before TDGETVEINFO, a #DF (fault 1402 * exception) is delivered to the guest which will result in an oops. 1403 * 1404 * The entry code has been audited carefully for following these expectations. 1405 * Changes in the entry code have to be audited for correctness vs. this 1406 * aspect. Similarly to #PF, #VE in these places will expose kernel to 1407 * privilege escalation or may lead to random crashes. 1408 */ 1409 DEFINE_IDTENTRY(exc_virtualization_exception) 1410 { 1411 struct ve_info ve; 1412 1413 /* 1414 * NMIs/Machine-checks/Interrupts will be in a disabled state 1415 * till TDGETVEINFO TDCALL is executed. This ensures that VE 1416 * info cannot be overwritten by a nested #VE. 1417 */ 1418 tdx_get_ve_info(&ve); 1419 1420 cond_local_irq_enable(regs); 1421 1422 /* 1423 * If tdx_handle_virt_exception() could not process 1424 * it successfully, treat it as #GP(0) and handle it. 1425 */ 1426 if (!tdx_handle_virt_exception(regs, &ve)) 1427 ve_raise_fault(regs, 0); 1428 1429 cond_local_irq_disable(regs); 1430 } 1431 1432 #endif 1433 1434 #ifdef CONFIG_X86_32 1435 DEFINE_IDTENTRY_SW(iret_error) 1436 { 1437 local_irq_enable(); 1438 if (notify_die(DIE_TRAP, "iret exception", regs, 0, 1439 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { 1440 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0, 1441 ILL_BADSTK, (void __user *)NULL); 1442 } 1443 local_irq_disable(); 1444 } 1445 #endif 1446 1447 void __init trap_init(void) 1448 { 1449 /* Init cpu_entry_area before IST entries are set up */ 1450 setup_cpu_entry_areas(); 1451 1452 /* Init GHCB memory pages when running as an SEV-ES guest */ 1453 sev_es_init_vc_handling(); 1454 1455 /* Initialize TSS before setting up traps so ISTs work */ 1456 cpu_init_exception_handling(); 1457 /* Setup traps as cpu_init() might #GP */ 1458 idt_setup_traps(); 1459 cpu_init(); 1460 } 1461