1 /* 2 * Copyright (C) 1991, 1992 Linus Torvalds 3 * Copyright (C) 2000, 2001, 2002 Andi Kleen, SuSE Labs 4 * 5 * Pentium III FXSR, SSE support 6 * Gareth Hughes <gareth@valinux.com>, May 2000 7 */ 8 9 /* 10 * Handle hardware traps and faults. 11 */ 12 13 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 14 15 #include <linux/context_tracking.h> 16 #include <linux/interrupt.h> 17 #include <linux/kallsyms.h> 18 #include <linux/kmsan.h> 19 #include <linux/spinlock.h> 20 #include <linux/kprobes.h> 21 #include <linux/uaccess.h> 22 #include <linux/kdebug.h> 23 #include <linux/kgdb.h> 24 #include <linux/kernel.h> 25 #include <linux/export.h> 26 #include <linux/ptrace.h> 27 #include <linux/uprobes.h> 28 #include <linux/string.h> 29 #include <linux/delay.h> 30 #include <linux/errno.h> 31 #include <linux/kexec.h> 32 #include <linux/sched.h> 33 #include <linux/sched/task_stack.h> 34 #include <linux/timer.h> 35 #include <linux/init.h> 36 #include <linux/bug.h> 37 #include <linux/nmi.h> 38 #include <linux/mm.h> 39 #include <linux/smp.h> 40 #include <linux/io.h> 41 #include <linux/hardirq.h> 42 #include <linux/atomic.h> 43 #include <linux/iommu.h> 44 45 #include <asm/stacktrace.h> 46 #include <asm/processor.h> 47 #include <asm/debugreg.h> 48 #include <asm/realmode.h> 49 #include <asm/text-patching.h> 50 #include <asm/ftrace.h> 51 #include <asm/traps.h> 52 #include <asm/desc.h> 53 #include <asm/fpu/api.h> 54 #include <asm/cpu.h> 55 #include <asm/cpu_entry_area.h> 56 #include <asm/mce.h> 57 #include <asm/fixmap.h> 58 #include <asm/mach_traps.h> 59 #include <asm/alternative.h> 60 #include <asm/fpu/xstate.h> 61 #include <asm/vm86.h> 62 #include <asm/umip.h> 63 #include <asm/insn.h> 64 #include <asm/insn-eval.h> 65 #include <asm/vdso.h> 66 #include <asm/tdx.h> 67 #include <asm/cfi.h> 68 69 #ifdef CONFIG_X86_64 70 #include <asm/x86_init.h> 71 #else 72 #include <asm/processor-flags.h> 73 #include <asm/setup.h> 74 #endif 75 76 #include <asm/proto.h> 77 78 DECLARE_BITMAP(system_vectors, NR_VECTORS); 79 80 static inline void cond_local_irq_enable(struct pt_regs *regs) 81 { 82 if (regs->flags & X86_EFLAGS_IF) 83 local_irq_enable(); 84 } 85 86 static inline void cond_local_irq_disable(struct pt_regs *regs) 87 { 88 if (regs->flags & X86_EFLAGS_IF) 89 local_irq_disable(); 90 } 91 92 __always_inline int is_valid_bugaddr(unsigned long addr) 93 { 94 if (addr < TASK_SIZE_MAX) 95 return 0; 96 97 /* 98 * We got #UD, if the text isn't readable we'd have gotten 99 * a different exception. 100 */ 101 return *(unsigned short *)addr == INSN_UD2; 102 } 103 104 static nokprobe_inline int 105 do_trap_no_signal(struct task_struct *tsk, int trapnr, const char *str, 106 struct pt_regs *regs, long error_code) 107 { 108 if (v8086_mode(regs)) { 109 /* 110 * Traps 0, 1, 3, 4, and 5 should be forwarded to vm86. 111 * On nmi (interrupt 2), do_trap should not be called. 112 */ 113 if (trapnr < X86_TRAP_UD) { 114 if (!handle_vm86_trap((struct kernel_vm86_regs *) regs, 115 error_code, trapnr)) 116 return 0; 117 } 118 } else if (!user_mode(regs)) { 119 if (fixup_exception(regs, trapnr, error_code, 0)) 120 return 0; 121 122 tsk->thread.error_code = error_code; 123 tsk->thread.trap_nr = trapnr; 124 die(str, regs, error_code); 125 } else { 126 if (fixup_vdso_exception(regs, trapnr, error_code, 0)) 127 return 0; 128 } 129 130 /* 131 * We want error_code and trap_nr set for userspace faults and 132 * kernelspace faults which result in die(), but not 133 * kernelspace faults which are fixed up. die() gives the 134 * process no chance to handle the signal and notice the 135 * kernel fault information, so that won't result in polluting 136 * the information about previously queued, but not yet 137 * delivered, faults. See also exc_general_protection below. 138 */ 139 tsk->thread.error_code = error_code; 140 tsk->thread.trap_nr = trapnr; 141 142 return -1; 143 } 144 145 static void show_signal(struct task_struct *tsk, int signr, 146 const char *type, const char *desc, 147 struct pt_regs *regs, long error_code) 148 { 149 if (show_unhandled_signals && unhandled_signal(tsk, signr) && 150 printk_ratelimit()) { 151 pr_info("%s[%d] %s%s ip:%lx sp:%lx error:%lx", 152 tsk->comm, task_pid_nr(tsk), type, desc, 153 regs->ip, regs->sp, error_code); 154 print_vma_addr(KERN_CONT " in ", regs->ip); 155 pr_cont("\n"); 156 } 157 } 158 159 static void 160 do_trap(int trapnr, int signr, char *str, struct pt_regs *regs, 161 long error_code, int sicode, void __user *addr) 162 { 163 struct task_struct *tsk = current; 164 165 if (!do_trap_no_signal(tsk, trapnr, str, regs, error_code)) 166 return; 167 168 show_signal(tsk, signr, "trap ", str, regs, error_code); 169 170 if (!sicode) 171 force_sig(signr); 172 else 173 force_sig_fault(signr, sicode, addr); 174 } 175 NOKPROBE_SYMBOL(do_trap); 176 177 static void do_error_trap(struct pt_regs *regs, long error_code, char *str, 178 unsigned long trapnr, int signr, int sicode, void __user *addr) 179 { 180 RCU_LOCKDEP_WARN(!rcu_is_watching(), "entry code didn't wake RCU"); 181 182 if (notify_die(DIE_TRAP, str, regs, error_code, trapnr, signr) != 183 NOTIFY_STOP) { 184 cond_local_irq_enable(regs); 185 do_trap(trapnr, signr, str, regs, error_code, sicode, addr); 186 cond_local_irq_disable(regs); 187 } 188 } 189 190 /* 191 * Posix requires to provide the address of the faulting instruction for 192 * SIGILL (#UD) and SIGFPE (#DE) in the si_addr member of siginfo_t. 193 * 194 * This address is usually regs->ip, but when an uprobe moved the code out 195 * of line then regs->ip points to the XOL code which would confuse 196 * anything which analyzes the fault address vs. the unmodified binary. If 197 * a trap happened in XOL code then uprobe maps regs->ip back to the 198 * original instruction address. 199 */ 200 static __always_inline void __user *error_get_trap_addr(struct pt_regs *regs) 201 { 202 return (void __user *)uprobe_get_trap_addr(regs); 203 } 204 205 DEFINE_IDTENTRY(exc_divide_error) 206 { 207 do_error_trap(regs, 0, "divide error", X86_TRAP_DE, SIGFPE, 208 FPE_INTDIV, error_get_trap_addr(regs)); 209 210 amd_clear_divider(); 211 } 212 213 DEFINE_IDTENTRY(exc_overflow) 214 { 215 do_error_trap(regs, 0, "overflow", X86_TRAP_OF, SIGSEGV, 0, NULL); 216 } 217 218 #ifdef CONFIG_X86_KERNEL_IBT 219 220 static __ro_after_init bool ibt_fatal = true; 221 222 extern void ibt_selftest_ip(void); /* code label defined in asm below */ 223 224 enum cp_error_code { 225 CP_EC = (1 << 15) - 1, 226 227 CP_RET = 1, 228 CP_IRET = 2, 229 CP_ENDBR = 3, 230 CP_RSTRORSSP = 4, 231 CP_SETSSBSY = 5, 232 233 CP_ENCL = 1 << 15, 234 }; 235 236 DEFINE_IDTENTRY_ERRORCODE(exc_control_protection) 237 { 238 if (!cpu_feature_enabled(X86_FEATURE_IBT)) { 239 pr_err("Unexpected #CP\n"); 240 BUG(); 241 } 242 243 if (WARN_ON_ONCE(user_mode(regs) || (error_code & CP_EC) != CP_ENDBR)) 244 return; 245 246 if (unlikely(regs->ip == (unsigned long)&ibt_selftest_ip)) { 247 regs->ax = 0; 248 return; 249 } 250 251 pr_err("Missing ENDBR: %pS\n", (void *)instruction_pointer(regs)); 252 if (!ibt_fatal) { 253 printk(KERN_DEFAULT CUT_HERE); 254 __warn(__FILE__, __LINE__, (void *)regs->ip, TAINT_WARN, regs, NULL); 255 return; 256 } 257 BUG(); 258 } 259 260 /* Must be noinline to ensure uniqueness of ibt_selftest_ip. */ 261 noinline bool ibt_selftest(void) 262 { 263 unsigned long ret; 264 265 asm (" lea ibt_selftest_ip(%%rip), %%rax\n\t" 266 ANNOTATE_RETPOLINE_SAFE 267 " jmp *%%rax\n\t" 268 "ibt_selftest_ip:\n\t" 269 UNWIND_HINT_FUNC 270 ANNOTATE_NOENDBR 271 " nop\n\t" 272 273 : "=a" (ret) : : "memory"); 274 275 return !ret; 276 } 277 278 static int __init ibt_setup(char *str) 279 { 280 if (!strcmp(str, "off")) 281 setup_clear_cpu_cap(X86_FEATURE_IBT); 282 283 if (!strcmp(str, "warn")) 284 ibt_fatal = false; 285 286 return 1; 287 } 288 289 __setup("ibt=", ibt_setup); 290 291 #endif /* CONFIG_X86_KERNEL_IBT */ 292 293 #ifdef CONFIG_X86_F00F_BUG 294 void handle_invalid_op(struct pt_regs *regs) 295 #else 296 static inline void handle_invalid_op(struct pt_regs *regs) 297 #endif 298 { 299 do_error_trap(regs, 0, "invalid opcode", X86_TRAP_UD, SIGILL, 300 ILL_ILLOPN, error_get_trap_addr(regs)); 301 } 302 303 static noinstr bool handle_bug(struct pt_regs *regs) 304 { 305 bool handled = false; 306 307 /* 308 * Normally @regs are unpoisoned by irqentry_enter(), but handle_bug() 309 * is a rare case that uses @regs without passing them to 310 * irqentry_enter(). 311 */ 312 kmsan_unpoison_entry_regs(regs); 313 if (!is_valid_bugaddr(regs->ip)) 314 return handled; 315 316 /* 317 * All lies, just get the WARN/BUG out. 318 */ 319 instrumentation_begin(); 320 /* 321 * Since we're emulating a CALL with exceptions, restore the interrupt 322 * state to what it was at the exception site. 323 */ 324 if (regs->flags & X86_EFLAGS_IF) 325 raw_local_irq_enable(); 326 if (report_bug(regs->ip, regs) == BUG_TRAP_TYPE_WARN || 327 handle_cfi_failure(regs) == BUG_TRAP_TYPE_WARN) { 328 regs->ip += LEN_UD2; 329 handled = true; 330 } 331 if (regs->flags & X86_EFLAGS_IF) 332 raw_local_irq_disable(); 333 instrumentation_end(); 334 335 return handled; 336 } 337 338 DEFINE_IDTENTRY_RAW(exc_invalid_op) 339 { 340 irqentry_state_t state; 341 342 /* 343 * We use UD2 as a short encoding for 'CALL __WARN', as such 344 * handle it before exception entry to avoid recursive WARN 345 * in case exception entry is the one triggering WARNs. 346 */ 347 if (!user_mode(regs) && handle_bug(regs)) 348 return; 349 350 state = irqentry_enter(regs); 351 instrumentation_begin(); 352 handle_invalid_op(regs); 353 instrumentation_end(); 354 irqentry_exit(regs, state); 355 } 356 357 DEFINE_IDTENTRY(exc_coproc_segment_overrun) 358 { 359 do_error_trap(regs, 0, "coprocessor segment overrun", 360 X86_TRAP_OLD_MF, SIGFPE, 0, NULL); 361 } 362 363 DEFINE_IDTENTRY_ERRORCODE(exc_invalid_tss) 364 { 365 do_error_trap(regs, error_code, "invalid TSS", X86_TRAP_TS, SIGSEGV, 366 0, NULL); 367 } 368 369 DEFINE_IDTENTRY_ERRORCODE(exc_segment_not_present) 370 { 371 do_error_trap(regs, error_code, "segment not present", X86_TRAP_NP, 372 SIGBUS, 0, NULL); 373 } 374 375 DEFINE_IDTENTRY_ERRORCODE(exc_stack_segment) 376 { 377 do_error_trap(regs, error_code, "stack segment", X86_TRAP_SS, SIGBUS, 378 0, NULL); 379 } 380 381 DEFINE_IDTENTRY_ERRORCODE(exc_alignment_check) 382 { 383 char *str = "alignment check"; 384 385 if (notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_AC, SIGBUS) == NOTIFY_STOP) 386 return; 387 388 if (!user_mode(regs)) 389 die("Split lock detected\n", regs, error_code); 390 391 local_irq_enable(); 392 393 if (handle_user_split_lock(regs, error_code)) 394 goto out; 395 396 do_trap(X86_TRAP_AC, SIGBUS, "alignment check", regs, 397 error_code, BUS_ADRALN, NULL); 398 399 out: 400 local_irq_disable(); 401 } 402 403 #ifdef CONFIG_VMAP_STACK 404 __visible void __noreturn handle_stack_overflow(struct pt_regs *regs, 405 unsigned long fault_address, 406 struct stack_info *info) 407 { 408 const char *name = stack_type_name(info->type); 409 410 printk(KERN_EMERG "BUG: %s stack guard page was hit at %p (stack is %p..%p)\n", 411 name, (void *)fault_address, info->begin, info->end); 412 413 die("stack guard page", regs, 0); 414 415 /* Be absolutely certain we don't return. */ 416 panic("%s stack guard hit", name); 417 } 418 #endif 419 420 /* 421 * Runs on an IST stack for x86_64 and on a special task stack for x86_32. 422 * 423 * On x86_64, this is more or less a normal kernel entry. Notwithstanding the 424 * SDM's warnings about double faults being unrecoverable, returning works as 425 * expected. Presumably what the SDM actually means is that the CPU may get 426 * the register state wrong on entry, so returning could be a bad idea. 427 * 428 * Various CPU engineers have promised that double faults due to an IRET fault 429 * while the stack is read-only are, in fact, recoverable. 430 * 431 * On x86_32, this is entered through a task gate, and regs are synthesized 432 * from the TSS. Returning is, in principle, okay, but changes to regs will 433 * be lost. If, for some reason, we need to return to a context with modified 434 * regs, the shim code could be adjusted to synchronize the registers. 435 * 436 * The 32bit #DF shim provides CR2 already as an argument. On 64bit it needs 437 * to be read before doing anything else. 438 */ 439 DEFINE_IDTENTRY_DF(exc_double_fault) 440 { 441 static const char str[] = "double fault"; 442 struct task_struct *tsk = current; 443 444 #ifdef CONFIG_VMAP_STACK 445 unsigned long address = read_cr2(); 446 struct stack_info info; 447 #endif 448 449 #ifdef CONFIG_X86_ESPFIX64 450 extern unsigned char native_irq_return_iret[]; 451 452 /* 453 * If IRET takes a non-IST fault on the espfix64 stack, then we 454 * end up promoting it to a doublefault. In that case, take 455 * advantage of the fact that we're not using the normal (TSS.sp0) 456 * stack right now. We can write a fake #GP(0) frame at TSS.sp0 457 * and then modify our own IRET frame so that, when we return, 458 * we land directly at the #GP(0) vector with the stack already 459 * set up according to its expectations. 460 * 461 * The net result is that our #GP handler will think that we 462 * entered from usermode with the bad user context. 463 * 464 * No need for nmi_enter() here because we don't use RCU. 465 */ 466 if (((long)regs->sp >> P4D_SHIFT) == ESPFIX_PGD_ENTRY && 467 regs->cs == __KERNEL_CS && 468 regs->ip == (unsigned long)native_irq_return_iret) 469 { 470 struct pt_regs *gpregs = (struct pt_regs *)this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 471 unsigned long *p = (unsigned long *)regs->sp; 472 473 /* 474 * regs->sp points to the failing IRET frame on the 475 * ESPFIX64 stack. Copy it to the entry stack. This fills 476 * in gpregs->ss through gpregs->ip. 477 * 478 */ 479 gpregs->ip = p[0]; 480 gpregs->cs = p[1]; 481 gpregs->flags = p[2]; 482 gpregs->sp = p[3]; 483 gpregs->ss = p[4]; 484 gpregs->orig_ax = 0; /* Missing (lost) #GP error code */ 485 486 /* 487 * Adjust our frame so that we return straight to the #GP 488 * vector with the expected RSP value. This is safe because 489 * we won't enable interrupts or schedule before we invoke 490 * general_protection, so nothing will clobber the stack 491 * frame we just set up. 492 * 493 * We will enter general_protection with kernel GSBASE, 494 * which is what the stub expects, given that the faulting 495 * RIP will be the IRET instruction. 496 */ 497 regs->ip = (unsigned long)asm_exc_general_protection; 498 regs->sp = (unsigned long)&gpregs->orig_ax; 499 500 return; 501 } 502 #endif 503 504 irqentry_nmi_enter(regs); 505 instrumentation_begin(); 506 notify_die(DIE_TRAP, str, regs, error_code, X86_TRAP_DF, SIGSEGV); 507 508 tsk->thread.error_code = error_code; 509 tsk->thread.trap_nr = X86_TRAP_DF; 510 511 #ifdef CONFIG_VMAP_STACK 512 /* 513 * If we overflow the stack into a guard page, the CPU will fail 514 * to deliver #PF and will send #DF instead. Similarly, if we 515 * take any non-IST exception while too close to the bottom of 516 * the stack, the processor will get a page fault while 517 * delivering the exception and will generate a double fault. 518 * 519 * According to the SDM (footnote in 6.15 under "Interrupt 14 - 520 * Page-Fault Exception (#PF): 521 * 522 * Processors update CR2 whenever a page fault is detected. If a 523 * second page fault occurs while an earlier page fault is being 524 * delivered, the faulting linear address of the second fault will 525 * overwrite the contents of CR2 (replacing the previous 526 * address). These updates to CR2 occur even if the page fault 527 * results in a double fault or occurs during the delivery of a 528 * double fault. 529 * 530 * The logic below has a small possibility of incorrectly diagnosing 531 * some errors as stack overflows. For example, if the IDT or GDT 532 * gets corrupted such that #GP delivery fails due to a bad descriptor 533 * causing #GP and we hit this condition while CR2 coincidentally 534 * points to the stack guard page, we'll think we overflowed the 535 * stack. Given that we're going to panic one way or another 536 * if this happens, this isn't necessarily worth fixing. 537 * 538 * If necessary, we could improve the test by only diagnosing 539 * a stack overflow if the saved RSP points within 47 bytes of 540 * the bottom of the stack: if RSP == tsk_stack + 48 and we 541 * take an exception, the stack is already aligned and there 542 * will be enough room SS, RSP, RFLAGS, CS, RIP, and a 543 * possible error code, so a stack overflow would *not* double 544 * fault. With any less space left, exception delivery could 545 * fail, and, as a practical matter, we've overflowed the 546 * stack even if the actual trigger for the double fault was 547 * something else. 548 */ 549 if (get_stack_guard_info((void *)address, &info)) 550 handle_stack_overflow(regs, address, &info); 551 #endif 552 553 pr_emerg("PANIC: double fault, error_code: 0x%lx\n", error_code); 554 die("double fault", regs, error_code); 555 panic("Machine halted."); 556 instrumentation_end(); 557 } 558 559 DEFINE_IDTENTRY(exc_bounds) 560 { 561 if (notify_die(DIE_TRAP, "bounds", regs, 0, 562 X86_TRAP_BR, SIGSEGV) == NOTIFY_STOP) 563 return; 564 cond_local_irq_enable(regs); 565 566 if (!user_mode(regs)) 567 die("bounds", regs, 0); 568 569 do_trap(X86_TRAP_BR, SIGSEGV, "bounds", regs, 0, 0, NULL); 570 571 cond_local_irq_disable(regs); 572 } 573 574 enum kernel_gp_hint { 575 GP_NO_HINT, 576 GP_NON_CANONICAL, 577 GP_CANONICAL 578 }; 579 580 /* 581 * When an uncaught #GP occurs, try to determine the memory address accessed by 582 * the instruction and return that address to the caller. Also, try to figure 583 * out whether any part of the access to that address was non-canonical. 584 */ 585 static enum kernel_gp_hint get_kernel_gp_address(struct pt_regs *regs, 586 unsigned long *addr) 587 { 588 u8 insn_buf[MAX_INSN_SIZE]; 589 struct insn insn; 590 int ret; 591 592 if (copy_from_kernel_nofault(insn_buf, (void *)regs->ip, 593 MAX_INSN_SIZE)) 594 return GP_NO_HINT; 595 596 ret = insn_decode_kernel(&insn, insn_buf); 597 if (ret < 0) 598 return GP_NO_HINT; 599 600 *addr = (unsigned long)insn_get_addr_ref(&insn, regs); 601 if (*addr == -1UL) 602 return GP_NO_HINT; 603 604 #ifdef CONFIG_X86_64 605 /* 606 * Check that: 607 * - the operand is not in the kernel half 608 * - the last byte of the operand is not in the user canonical half 609 */ 610 if (*addr < ~__VIRTUAL_MASK && 611 *addr + insn.opnd_bytes - 1 > __VIRTUAL_MASK) 612 return GP_NON_CANONICAL; 613 #endif 614 615 return GP_CANONICAL; 616 } 617 618 #define GPFSTR "general protection fault" 619 620 static bool fixup_iopl_exception(struct pt_regs *regs) 621 { 622 struct thread_struct *t = ¤t->thread; 623 unsigned char byte; 624 unsigned long ip; 625 626 if (!IS_ENABLED(CONFIG_X86_IOPL_IOPERM) || t->iopl_emul != 3) 627 return false; 628 629 if (insn_get_effective_ip(regs, &ip)) 630 return false; 631 632 if (get_user(byte, (const char __user *)ip)) 633 return false; 634 635 if (byte != 0xfa && byte != 0xfb) 636 return false; 637 638 if (!t->iopl_warn && printk_ratelimit()) { 639 pr_err("%s[%d] attempts to use CLI/STI, pretending it's a NOP, ip:%lx", 640 current->comm, task_pid_nr(current), ip); 641 print_vma_addr(KERN_CONT " in ", ip); 642 pr_cont("\n"); 643 t->iopl_warn = 1; 644 } 645 646 regs->ip += 1; 647 return true; 648 } 649 650 /* 651 * The unprivileged ENQCMD instruction generates #GPs if the 652 * IA32_PASID MSR has not been populated. If possible, populate 653 * the MSR from a PASID previously allocated to the mm. 654 */ 655 static bool try_fixup_enqcmd_gp(void) 656 { 657 #ifdef CONFIG_IOMMU_SVA 658 u32 pasid; 659 660 /* 661 * MSR_IA32_PASID is managed using XSAVE. Directly 662 * writing to the MSR is only possible when fpregs 663 * are valid and the fpstate is not. This is 664 * guaranteed when handling a userspace exception 665 * in *before* interrupts are re-enabled. 666 */ 667 lockdep_assert_irqs_disabled(); 668 669 /* 670 * Hardware without ENQCMD will not generate 671 * #GPs that can be fixed up here. 672 */ 673 if (!cpu_feature_enabled(X86_FEATURE_ENQCMD)) 674 return false; 675 676 /* 677 * If the mm has not been allocated a 678 * PASID, the #GP can not be fixed up. 679 */ 680 if (!mm_valid_pasid(current->mm)) 681 return false; 682 683 pasid = current->mm->pasid; 684 685 /* 686 * Did this thread already have its PASID activated? 687 * If so, the #GP must be from something else. 688 */ 689 if (current->pasid_activated) 690 return false; 691 692 wrmsrl(MSR_IA32_PASID, pasid | MSR_IA32_PASID_VALID); 693 current->pasid_activated = 1; 694 695 return true; 696 #else 697 return false; 698 #endif 699 } 700 701 static bool gp_try_fixup_and_notify(struct pt_regs *regs, int trapnr, 702 unsigned long error_code, const char *str, 703 unsigned long address) 704 { 705 if (fixup_exception(regs, trapnr, error_code, address)) 706 return true; 707 708 current->thread.error_code = error_code; 709 current->thread.trap_nr = trapnr; 710 711 /* 712 * To be potentially processing a kprobe fault and to trust the result 713 * from kprobe_running(), we have to be non-preemptible. 714 */ 715 if (!preemptible() && kprobe_running() && 716 kprobe_fault_handler(regs, trapnr)) 717 return true; 718 719 return notify_die(DIE_GPF, str, regs, error_code, trapnr, SIGSEGV) == NOTIFY_STOP; 720 } 721 722 static void gp_user_force_sig_segv(struct pt_regs *regs, int trapnr, 723 unsigned long error_code, const char *str) 724 { 725 current->thread.error_code = error_code; 726 current->thread.trap_nr = trapnr; 727 show_signal(current, SIGSEGV, "", str, regs, error_code); 728 force_sig(SIGSEGV); 729 } 730 731 DEFINE_IDTENTRY_ERRORCODE(exc_general_protection) 732 { 733 char desc[sizeof(GPFSTR) + 50 + 2*sizeof(unsigned long) + 1] = GPFSTR; 734 enum kernel_gp_hint hint = GP_NO_HINT; 735 unsigned long gp_addr; 736 737 if (user_mode(regs) && try_fixup_enqcmd_gp()) 738 return; 739 740 cond_local_irq_enable(regs); 741 742 if (static_cpu_has(X86_FEATURE_UMIP)) { 743 if (user_mode(regs) && fixup_umip_exception(regs)) 744 goto exit; 745 } 746 747 if (v8086_mode(regs)) { 748 local_irq_enable(); 749 handle_vm86_fault((struct kernel_vm86_regs *) regs, error_code); 750 local_irq_disable(); 751 return; 752 } 753 754 if (user_mode(regs)) { 755 if (fixup_iopl_exception(regs)) 756 goto exit; 757 758 if (fixup_vdso_exception(regs, X86_TRAP_GP, error_code, 0)) 759 goto exit; 760 761 gp_user_force_sig_segv(regs, X86_TRAP_GP, error_code, desc); 762 goto exit; 763 } 764 765 if (gp_try_fixup_and_notify(regs, X86_TRAP_GP, error_code, desc, 0)) 766 goto exit; 767 768 if (error_code) 769 snprintf(desc, sizeof(desc), "segment-related " GPFSTR); 770 else 771 hint = get_kernel_gp_address(regs, &gp_addr); 772 773 if (hint != GP_NO_HINT) 774 snprintf(desc, sizeof(desc), GPFSTR ", %s 0x%lx", 775 (hint == GP_NON_CANONICAL) ? "probably for non-canonical address" 776 : "maybe for address", 777 gp_addr); 778 779 /* 780 * KASAN is interested only in the non-canonical case, clear it 781 * otherwise. 782 */ 783 if (hint != GP_NON_CANONICAL) 784 gp_addr = 0; 785 786 die_addr(desc, regs, error_code, gp_addr); 787 788 exit: 789 cond_local_irq_disable(regs); 790 } 791 792 static bool do_int3(struct pt_regs *regs) 793 { 794 int res; 795 796 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP 797 if (kgdb_ll_trap(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, 798 SIGTRAP) == NOTIFY_STOP) 799 return true; 800 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */ 801 802 #ifdef CONFIG_KPROBES 803 if (kprobe_int3_handler(regs)) 804 return true; 805 #endif 806 res = notify_die(DIE_INT3, "int3", regs, 0, X86_TRAP_BP, SIGTRAP); 807 808 return res == NOTIFY_STOP; 809 } 810 NOKPROBE_SYMBOL(do_int3); 811 812 static void do_int3_user(struct pt_regs *regs) 813 { 814 if (do_int3(regs)) 815 return; 816 817 cond_local_irq_enable(regs); 818 do_trap(X86_TRAP_BP, SIGTRAP, "int3", regs, 0, 0, NULL); 819 cond_local_irq_disable(regs); 820 } 821 822 DEFINE_IDTENTRY_RAW(exc_int3) 823 { 824 /* 825 * poke_int3_handler() is completely self contained code; it does (and 826 * must) *NOT* call out to anything, lest it hits upon yet another 827 * INT3. 828 */ 829 if (poke_int3_handler(regs)) 830 return; 831 832 /* 833 * irqentry_enter_from_user_mode() uses static_branch_{,un}likely() 834 * and therefore can trigger INT3, hence poke_int3_handler() must 835 * be done before. If the entry came from kernel mode, then use 836 * nmi_enter() because the INT3 could have been hit in any context 837 * including NMI. 838 */ 839 if (user_mode(regs)) { 840 irqentry_enter_from_user_mode(regs); 841 instrumentation_begin(); 842 do_int3_user(regs); 843 instrumentation_end(); 844 irqentry_exit_to_user_mode(regs); 845 } else { 846 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 847 848 instrumentation_begin(); 849 if (!do_int3(regs)) 850 die("int3", regs, 0); 851 instrumentation_end(); 852 irqentry_nmi_exit(regs, irq_state); 853 } 854 } 855 856 #ifdef CONFIG_X86_64 857 /* 858 * Help handler running on a per-cpu (IST or entry trampoline) stack 859 * to switch to the normal thread stack if the interrupted code was in 860 * user mode. The actual stack switch is done in entry_64.S 861 */ 862 asmlinkage __visible noinstr struct pt_regs *sync_regs(struct pt_regs *eregs) 863 { 864 struct pt_regs *regs = (struct pt_regs *)this_cpu_read(pcpu_hot.top_of_stack) - 1; 865 if (regs != eregs) 866 *regs = *eregs; 867 return regs; 868 } 869 870 #ifdef CONFIG_AMD_MEM_ENCRYPT 871 asmlinkage __visible noinstr struct pt_regs *vc_switch_off_ist(struct pt_regs *regs) 872 { 873 unsigned long sp, *stack; 874 struct stack_info info; 875 struct pt_regs *regs_ret; 876 877 /* 878 * In the SYSCALL entry path the RSP value comes from user-space - don't 879 * trust it and switch to the current kernel stack 880 */ 881 if (ip_within_syscall_gap(regs)) { 882 sp = this_cpu_read(pcpu_hot.top_of_stack); 883 goto sync; 884 } 885 886 /* 887 * From here on the RSP value is trusted. Now check whether entry 888 * happened from a safe stack. Not safe are the entry or unknown stacks, 889 * use the fall-back stack instead in this case. 890 */ 891 sp = regs->sp; 892 stack = (unsigned long *)sp; 893 894 if (!get_stack_info_noinstr(stack, current, &info) || info.type == STACK_TYPE_ENTRY || 895 info.type > STACK_TYPE_EXCEPTION_LAST) 896 sp = __this_cpu_ist_top_va(VC2); 897 898 sync: 899 /* 900 * Found a safe stack - switch to it as if the entry didn't happen via 901 * IST stack. The code below only copies pt_regs, the real switch happens 902 * in assembly code. 903 */ 904 sp = ALIGN_DOWN(sp, 8) - sizeof(*regs_ret); 905 906 regs_ret = (struct pt_regs *)sp; 907 *regs_ret = *regs; 908 909 return regs_ret; 910 } 911 #endif 912 913 asmlinkage __visible noinstr struct pt_regs *fixup_bad_iret(struct pt_regs *bad_regs) 914 { 915 struct pt_regs tmp, *new_stack; 916 917 /* 918 * This is called from entry_64.S early in handling a fault 919 * caused by a bad iret to user mode. To handle the fault 920 * correctly, we want to move our stack frame to where it would 921 * be had we entered directly on the entry stack (rather than 922 * just below the IRET frame) and we want to pretend that the 923 * exception came from the IRET target. 924 */ 925 new_stack = (struct pt_regs *)__this_cpu_read(cpu_tss_rw.x86_tss.sp0) - 1; 926 927 /* Copy the IRET target to the temporary storage. */ 928 __memcpy(&tmp.ip, (void *)bad_regs->sp, 5*8); 929 930 /* Copy the remainder of the stack from the current stack. */ 931 __memcpy(&tmp, bad_regs, offsetof(struct pt_regs, ip)); 932 933 /* Update the entry stack */ 934 __memcpy(new_stack, &tmp, sizeof(tmp)); 935 936 BUG_ON(!user_mode(new_stack)); 937 return new_stack; 938 } 939 #endif 940 941 static bool is_sysenter_singlestep(struct pt_regs *regs) 942 { 943 /* 944 * We don't try for precision here. If we're anywhere in the region of 945 * code that can be single-stepped in the SYSENTER entry path, then 946 * assume that this is a useless single-step trap due to SYSENTER 947 * being invoked with TF set. (We don't know in advance exactly 948 * which instructions will be hit because BTF could plausibly 949 * be set.) 950 */ 951 #ifdef CONFIG_X86_32 952 return (regs->ip - (unsigned long)__begin_SYSENTER_singlestep_region) < 953 (unsigned long)__end_SYSENTER_singlestep_region - 954 (unsigned long)__begin_SYSENTER_singlestep_region; 955 #elif defined(CONFIG_IA32_EMULATION) 956 return (regs->ip - (unsigned long)entry_SYSENTER_compat) < 957 (unsigned long)__end_entry_SYSENTER_compat - 958 (unsigned long)entry_SYSENTER_compat; 959 #else 960 return false; 961 #endif 962 } 963 964 static __always_inline unsigned long debug_read_clear_dr6(void) 965 { 966 unsigned long dr6; 967 968 /* 969 * The Intel SDM says: 970 * 971 * Certain debug exceptions may clear bits 0-3. The remaining 972 * contents of the DR6 register are never cleared by the 973 * processor. To avoid confusion in identifying debug 974 * exceptions, debug handlers should clear the register before 975 * returning to the interrupted task. 976 * 977 * Keep it simple: clear DR6 immediately. 978 */ 979 get_debugreg(dr6, 6); 980 set_debugreg(DR6_RESERVED, 6); 981 dr6 ^= DR6_RESERVED; /* Flip to positive polarity */ 982 983 return dr6; 984 } 985 986 /* 987 * Our handling of the processor debug registers is non-trivial. 988 * We do not clear them on entry and exit from the kernel. Therefore 989 * it is possible to get a watchpoint trap here from inside the kernel. 990 * However, the code in ./ptrace.c has ensured that the user can 991 * only set watchpoints on userspace addresses. Therefore the in-kernel 992 * watchpoint trap can only occur in code which is reading/writing 993 * from user space. Such code must not hold kernel locks (since it 994 * can equally take a page fault), therefore it is safe to call 995 * force_sig_info even though that claims and releases locks. 996 * 997 * Code in ./signal.c ensures that the debug control register 998 * is restored before we deliver any signal, and therefore that 999 * user code runs with the correct debug control register even though 1000 * we clear it here. 1001 * 1002 * Being careful here means that we don't have to be as careful in a 1003 * lot of more complicated places (task switching can be a bit lazy 1004 * about restoring all the debug state, and ptrace doesn't have to 1005 * find every occurrence of the TF bit that could be saved away even 1006 * by user code) 1007 * 1008 * May run on IST stack. 1009 */ 1010 1011 static bool notify_debug(struct pt_regs *regs, unsigned long *dr6) 1012 { 1013 /* 1014 * Notifiers will clear bits in @dr6 to indicate the event has been 1015 * consumed - hw_breakpoint_handler(), single_stop_cont(). 1016 * 1017 * Notifiers will set bits in @virtual_dr6 to indicate the desire 1018 * for signals - ptrace_triggered(), kgdb_hw_overflow_handler(). 1019 */ 1020 if (notify_die(DIE_DEBUG, "debug", regs, (long)dr6, 0, SIGTRAP) == NOTIFY_STOP) 1021 return true; 1022 1023 return false; 1024 } 1025 1026 static __always_inline void exc_debug_kernel(struct pt_regs *regs, 1027 unsigned long dr6) 1028 { 1029 /* 1030 * Disable breakpoints during exception handling; recursive exceptions 1031 * are exceedingly 'fun'. 1032 * 1033 * Since this function is NOKPROBE, and that also applies to 1034 * HW_BREAKPOINT_X, we can't hit a breakpoint before this (XXX except a 1035 * HW_BREAKPOINT_W on our stack) 1036 * 1037 * Entry text is excluded for HW_BP_X and cpu_entry_area, which 1038 * includes the entry stack is excluded for everything. 1039 */ 1040 unsigned long dr7 = local_db_save(); 1041 irqentry_state_t irq_state = irqentry_nmi_enter(regs); 1042 instrumentation_begin(); 1043 1044 /* 1045 * If something gets miswired and we end up here for a user mode 1046 * #DB, we will malfunction. 1047 */ 1048 WARN_ON_ONCE(user_mode(regs)); 1049 1050 if (test_thread_flag(TIF_BLOCKSTEP)) { 1051 /* 1052 * The SDM says "The processor clears the BTF flag when it 1053 * generates a debug exception." but PTRACE_BLOCKSTEP requested 1054 * it for userspace, but we just took a kernel #DB, so re-set 1055 * BTF. 1056 */ 1057 unsigned long debugctl; 1058 1059 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1060 debugctl |= DEBUGCTLMSR_BTF; 1061 wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl); 1062 } 1063 1064 /* 1065 * Catch SYSENTER with TF set and clear DR_STEP. If this hit a 1066 * watchpoint at the same time then that will still be handled. 1067 */ 1068 if ((dr6 & DR_STEP) && is_sysenter_singlestep(regs)) 1069 dr6 &= ~DR_STEP; 1070 1071 /* 1072 * The kernel doesn't use INT1 1073 */ 1074 if (!dr6) 1075 goto out; 1076 1077 if (notify_debug(regs, &dr6)) 1078 goto out; 1079 1080 /* 1081 * The kernel doesn't use TF single-step outside of: 1082 * 1083 * - Kprobes, consumed through kprobe_debug_handler() 1084 * - KGDB, consumed through notify_debug() 1085 * 1086 * So if we get here with DR_STEP set, something is wonky. 1087 * 1088 * A known way to trigger this is through QEMU's GDB stub, 1089 * which leaks #DB into the guest and causes IST recursion. 1090 */ 1091 if (WARN_ON_ONCE(dr6 & DR_STEP)) 1092 regs->flags &= ~X86_EFLAGS_TF; 1093 out: 1094 instrumentation_end(); 1095 irqentry_nmi_exit(regs, irq_state); 1096 1097 local_db_restore(dr7); 1098 } 1099 1100 static __always_inline void exc_debug_user(struct pt_regs *regs, 1101 unsigned long dr6) 1102 { 1103 bool icebp; 1104 1105 /* 1106 * If something gets miswired and we end up here for a kernel mode 1107 * #DB, we will malfunction. 1108 */ 1109 WARN_ON_ONCE(!user_mode(regs)); 1110 1111 /* 1112 * NB: We can't easily clear DR7 here because 1113 * irqentry_exit_to_usermode() can invoke ptrace, schedule, access 1114 * user memory, etc. This means that a recursive #DB is possible. If 1115 * this happens, that #DB will hit exc_debug_kernel() and clear DR7. 1116 * Since we're not on the IST stack right now, everything will be 1117 * fine. 1118 */ 1119 1120 irqentry_enter_from_user_mode(regs); 1121 instrumentation_begin(); 1122 1123 /* 1124 * Start the virtual/ptrace DR6 value with just the DR_STEP mask 1125 * of the real DR6. ptrace_triggered() will set the DR_TRAPn bits. 1126 * 1127 * Userspace expects DR_STEP to be visible in ptrace_get_debugreg(6) 1128 * even if it is not the result of PTRACE_SINGLESTEP. 1129 */ 1130 current->thread.virtual_dr6 = (dr6 & DR_STEP); 1131 1132 /* 1133 * The SDM says "The processor clears the BTF flag when it 1134 * generates a debug exception." Clear TIF_BLOCKSTEP to keep 1135 * TIF_BLOCKSTEP in sync with the hardware BTF flag. 1136 */ 1137 clear_thread_flag(TIF_BLOCKSTEP); 1138 1139 /* 1140 * If dr6 has no reason to give us about the origin of this trap, 1141 * then it's very likely the result of an icebp/int01 trap. 1142 * User wants a sigtrap for that. 1143 */ 1144 icebp = !dr6; 1145 1146 if (notify_debug(regs, &dr6)) 1147 goto out; 1148 1149 /* It's safe to allow irq's after DR6 has been saved */ 1150 local_irq_enable(); 1151 1152 if (v8086_mode(regs)) { 1153 handle_vm86_trap((struct kernel_vm86_regs *)regs, 0, X86_TRAP_DB); 1154 goto out_irq; 1155 } 1156 1157 /* #DB for bus lock can only be triggered from userspace. */ 1158 if (dr6 & DR_BUS_LOCK) 1159 handle_bus_lock(regs); 1160 1161 /* Add the virtual_dr6 bits for signals. */ 1162 dr6 |= current->thread.virtual_dr6; 1163 if (dr6 & (DR_STEP | DR_TRAP_BITS) || icebp) 1164 send_sigtrap(regs, 0, get_si_code(dr6)); 1165 1166 out_irq: 1167 local_irq_disable(); 1168 out: 1169 instrumentation_end(); 1170 irqentry_exit_to_user_mode(regs); 1171 } 1172 1173 #ifdef CONFIG_X86_64 1174 /* IST stack entry */ 1175 DEFINE_IDTENTRY_DEBUG(exc_debug) 1176 { 1177 exc_debug_kernel(regs, debug_read_clear_dr6()); 1178 } 1179 1180 /* User entry, runs on regular task stack */ 1181 DEFINE_IDTENTRY_DEBUG_USER(exc_debug) 1182 { 1183 exc_debug_user(regs, debug_read_clear_dr6()); 1184 } 1185 #else 1186 /* 32 bit does not have separate entry points. */ 1187 DEFINE_IDTENTRY_RAW(exc_debug) 1188 { 1189 unsigned long dr6 = debug_read_clear_dr6(); 1190 1191 if (user_mode(regs)) 1192 exc_debug_user(regs, dr6); 1193 else 1194 exc_debug_kernel(regs, dr6); 1195 } 1196 #endif 1197 1198 /* 1199 * Note that we play around with the 'TS' bit in an attempt to get 1200 * the correct behaviour even in the presence of the asynchronous 1201 * IRQ13 behaviour 1202 */ 1203 static void math_error(struct pt_regs *regs, int trapnr) 1204 { 1205 struct task_struct *task = current; 1206 struct fpu *fpu = &task->thread.fpu; 1207 int si_code; 1208 char *str = (trapnr == X86_TRAP_MF) ? "fpu exception" : 1209 "simd exception"; 1210 1211 cond_local_irq_enable(regs); 1212 1213 if (!user_mode(regs)) { 1214 if (fixup_exception(regs, trapnr, 0, 0)) 1215 goto exit; 1216 1217 task->thread.error_code = 0; 1218 task->thread.trap_nr = trapnr; 1219 1220 if (notify_die(DIE_TRAP, str, regs, 0, trapnr, 1221 SIGFPE) != NOTIFY_STOP) 1222 die(str, regs, 0); 1223 goto exit; 1224 } 1225 1226 /* 1227 * Synchronize the FPU register state to the memory register state 1228 * if necessary. This allows the exception handler to inspect it. 1229 */ 1230 fpu_sync_fpstate(fpu); 1231 1232 task->thread.trap_nr = trapnr; 1233 task->thread.error_code = 0; 1234 1235 si_code = fpu__exception_code(fpu, trapnr); 1236 /* Retry when we get spurious exceptions: */ 1237 if (!si_code) 1238 goto exit; 1239 1240 if (fixup_vdso_exception(regs, trapnr, 0, 0)) 1241 goto exit; 1242 1243 force_sig_fault(SIGFPE, si_code, 1244 (void __user *)uprobe_get_trap_addr(regs)); 1245 exit: 1246 cond_local_irq_disable(regs); 1247 } 1248 1249 DEFINE_IDTENTRY(exc_coprocessor_error) 1250 { 1251 math_error(regs, X86_TRAP_MF); 1252 } 1253 1254 DEFINE_IDTENTRY(exc_simd_coprocessor_error) 1255 { 1256 if (IS_ENABLED(CONFIG_X86_INVD_BUG)) { 1257 /* AMD 486 bug: INVD in CPL 0 raises #XF instead of #GP */ 1258 if (!static_cpu_has(X86_FEATURE_XMM)) { 1259 __exc_general_protection(regs, 0); 1260 return; 1261 } 1262 } 1263 math_error(regs, X86_TRAP_XF); 1264 } 1265 1266 DEFINE_IDTENTRY(exc_spurious_interrupt_bug) 1267 { 1268 /* 1269 * This addresses a Pentium Pro Erratum: 1270 * 1271 * PROBLEM: If the APIC subsystem is configured in mixed mode with 1272 * Virtual Wire mode implemented through the local APIC, an 1273 * interrupt vector of 0Fh (Intel reserved encoding) may be 1274 * generated by the local APIC (Int 15). This vector may be 1275 * generated upon receipt of a spurious interrupt (an interrupt 1276 * which is removed before the system receives the INTA sequence) 1277 * instead of the programmed 8259 spurious interrupt vector. 1278 * 1279 * IMPLICATION: The spurious interrupt vector programmed in the 1280 * 8259 is normally handled by an operating system's spurious 1281 * interrupt handler. However, a vector of 0Fh is unknown to some 1282 * operating systems, which would crash if this erratum occurred. 1283 * 1284 * In theory this could be limited to 32bit, but the handler is not 1285 * hurting and who knows which other CPUs suffer from this. 1286 */ 1287 } 1288 1289 static bool handle_xfd_event(struct pt_regs *regs) 1290 { 1291 u64 xfd_err; 1292 int err; 1293 1294 if (!IS_ENABLED(CONFIG_X86_64) || !cpu_feature_enabled(X86_FEATURE_XFD)) 1295 return false; 1296 1297 rdmsrl(MSR_IA32_XFD_ERR, xfd_err); 1298 if (!xfd_err) 1299 return false; 1300 1301 wrmsrl(MSR_IA32_XFD_ERR, 0); 1302 1303 /* Die if that happens in kernel space */ 1304 if (WARN_ON(!user_mode(regs))) 1305 return false; 1306 1307 local_irq_enable(); 1308 1309 err = xfd_enable_feature(xfd_err); 1310 1311 switch (err) { 1312 case -EPERM: 1313 force_sig_fault(SIGILL, ILL_ILLOPC, error_get_trap_addr(regs)); 1314 break; 1315 case -EFAULT: 1316 force_sig(SIGSEGV); 1317 break; 1318 } 1319 1320 local_irq_disable(); 1321 return true; 1322 } 1323 1324 DEFINE_IDTENTRY(exc_device_not_available) 1325 { 1326 unsigned long cr0 = read_cr0(); 1327 1328 if (handle_xfd_event(regs)) 1329 return; 1330 1331 #ifdef CONFIG_MATH_EMULATION 1332 if (!boot_cpu_has(X86_FEATURE_FPU) && (cr0 & X86_CR0_EM)) { 1333 struct math_emu_info info = { }; 1334 1335 cond_local_irq_enable(regs); 1336 1337 info.regs = regs; 1338 math_emulate(&info); 1339 1340 cond_local_irq_disable(regs); 1341 return; 1342 } 1343 #endif 1344 1345 /* This should not happen. */ 1346 if (WARN(cr0 & X86_CR0_TS, "CR0.TS was set")) { 1347 /* Try to fix it up and carry on. */ 1348 write_cr0(cr0 & ~X86_CR0_TS); 1349 } else { 1350 /* 1351 * Something terrible happened, and we're better off trying 1352 * to kill the task than getting stuck in a never-ending 1353 * loop of #NM faults. 1354 */ 1355 die("unexpected #NM exception", regs, 0); 1356 } 1357 } 1358 1359 #ifdef CONFIG_INTEL_TDX_GUEST 1360 1361 #define VE_FAULT_STR "VE fault" 1362 1363 static void ve_raise_fault(struct pt_regs *regs, long error_code, 1364 unsigned long address) 1365 { 1366 if (user_mode(regs)) { 1367 gp_user_force_sig_segv(regs, X86_TRAP_VE, error_code, VE_FAULT_STR); 1368 return; 1369 } 1370 1371 if (gp_try_fixup_and_notify(regs, X86_TRAP_VE, error_code, 1372 VE_FAULT_STR, address)) { 1373 return; 1374 } 1375 1376 die_addr(VE_FAULT_STR, regs, error_code, address); 1377 } 1378 1379 /* 1380 * Virtualization Exceptions (#VE) are delivered to TDX guests due to 1381 * specific guest actions which may happen in either user space or the 1382 * kernel: 1383 * 1384 * * Specific instructions (WBINVD, for example) 1385 * * Specific MSR accesses 1386 * * Specific CPUID leaf accesses 1387 * * Access to specific guest physical addresses 1388 * 1389 * In the settings that Linux will run in, virtualization exceptions are 1390 * never generated on accesses to normal, TD-private memory that has been 1391 * accepted (by BIOS or with tdx_enc_status_changed()). 1392 * 1393 * Syscall entry code has a critical window where the kernel stack is not 1394 * yet set up. Any exception in this window leads to hard to debug issues 1395 * and can be exploited for privilege escalation. Exceptions in the NMI 1396 * entry code also cause issues. Returning from the exception handler with 1397 * IRET will re-enable NMIs and nested NMI will corrupt the NMI stack. 1398 * 1399 * For these reasons, the kernel avoids #VEs during the syscall gap and 1400 * the NMI entry code. Entry code paths do not access TD-shared memory, 1401 * MMIO regions, use #VE triggering MSRs, instructions, or CPUID leaves 1402 * that might generate #VE. VMM can remove memory from TD at any point, 1403 * but access to unaccepted (or missing) private memory leads to VM 1404 * termination, not to #VE. 1405 * 1406 * Similarly to page faults and breakpoints, #VEs are allowed in NMI 1407 * handlers once the kernel is ready to deal with nested NMIs. 1408 * 1409 * During #VE delivery, all interrupts, including NMIs, are blocked until 1410 * TDGETVEINFO is called. It prevents #VE nesting until the kernel reads 1411 * the VE info. 1412 * 1413 * If a guest kernel action which would normally cause a #VE occurs in 1414 * the interrupt-disabled region before TDGETVEINFO, a #DF (fault 1415 * exception) is delivered to the guest which will result in an oops. 1416 * 1417 * The entry code has been audited carefully for following these expectations. 1418 * Changes in the entry code have to be audited for correctness vs. this 1419 * aspect. Similarly to #PF, #VE in these places will expose kernel to 1420 * privilege escalation or may lead to random crashes. 1421 */ 1422 DEFINE_IDTENTRY(exc_virtualization_exception) 1423 { 1424 struct ve_info ve; 1425 1426 /* 1427 * NMIs/Machine-checks/Interrupts will be in a disabled state 1428 * till TDGETVEINFO TDCALL is executed. This ensures that VE 1429 * info cannot be overwritten by a nested #VE. 1430 */ 1431 tdx_get_ve_info(&ve); 1432 1433 cond_local_irq_enable(regs); 1434 1435 /* 1436 * If tdx_handle_virt_exception() could not process 1437 * it successfully, treat it as #GP(0) and handle it. 1438 */ 1439 if (!tdx_handle_virt_exception(regs, &ve)) 1440 ve_raise_fault(regs, 0, ve.gla); 1441 1442 cond_local_irq_disable(regs); 1443 } 1444 1445 #endif 1446 1447 #ifdef CONFIG_X86_32 1448 DEFINE_IDTENTRY_SW(iret_error) 1449 { 1450 local_irq_enable(); 1451 if (notify_die(DIE_TRAP, "iret exception", regs, 0, 1452 X86_TRAP_IRET, SIGILL) != NOTIFY_STOP) { 1453 do_trap(X86_TRAP_IRET, SIGILL, "iret exception", regs, 0, 1454 ILL_BADSTK, (void __user *)NULL); 1455 } 1456 local_irq_disable(); 1457 } 1458 #endif 1459 1460 void __init trap_init(void) 1461 { 1462 /* Init cpu_entry_area before IST entries are set up */ 1463 setup_cpu_entry_areas(); 1464 1465 /* Init GHCB memory pages when running as an SEV-ES guest */ 1466 sev_es_init_vc_handling(); 1467 1468 /* Initialize TSS before setting up traps so ISTs work */ 1469 cpu_init_exception_handling(); 1470 /* Setup traps as cpu_init() might #GP */ 1471 idt_setup_traps(); 1472 cpu_init(); 1473 } 1474