1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/memblock.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/misc.h> 79 #include <asm/qspinlock.h> 80 #include <asm/intel-family.h> 81 #include <asm/cpu_device_id.h> 82 #include <asm/spec-ctrl.h> 83 #include <asm/hw_irq.h> 84 85 /* representing HT siblings of each logical CPU */ 86 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 87 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 88 89 /* representing HT and core siblings of each logical CPU */ 90 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 91 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 92 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 94 95 /* Per CPU bogomips and other parameters */ 96 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 97 EXPORT_PER_CPU_SYMBOL(cpu_info); 98 99 /* Logical package management. We might want to allocate that dynamically */ 100 unsigned int __max_logical_packages __read_mostly; 101 EXPORT_SYMBOL(__max_logical_packages); 102 static unsigned int logical_packages __read_mostly; 103 104 /* Maximum number of SMT threads on any online core */ 105 int __read_mostly __max_smt_threads = 1; 106 107 /* Flag to indicate if a complete sched domain rebuild is required */ 108 bool x86_topology_update; 109 110 int arch_update_cpu_topology(void) 111 { 112 int retval = x86_topology_update; 113 114 x86_topology_update = false; 115 return retval; 116 } 117 118 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 119 { 120 unsigned long flags; 121 122 spin_lock_irqsave(&rtc_lock, flags); 123 CMOS_WRITE(0xa, 0xf); 124 spin_unlock_irqrestore(&rtc_lock, flags); 125 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 126 start_eip >> 4; 127 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 128 start_eip & 0xf; 129 } 130 131 static inline void smpboot_restore_warm_reset_vector(void) 132 { 133 unsigned long flags; 134 135 /* 136 * Paranoid: Set warm reset code and vector here back 137 * to default values. 138 */ 139 spin_lock_irqsave(&rtc_lock, flags); 140 CMOS_WRITE(0, 0xf); 141 spin_unlock_irqrestore(&rtc_lock, flags); 142 143 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 144 } 145 146 /* 147 * Report back to the Boot Processor during boot time or to the caller processor 148 * during CPU online. 149 */ 150 static void smp_callin(void) 151 { 152 int cpuid, phys_id; 153 154 /* 155 * If waken up by an INIT in an 82489DX configuration 156 * cpu_callout_mask guarantees we don't get here before 157 * an INIT_deassert IPI reaches our local APIC, so it is 158 * now safe to touch our local APIC. 159 */ 160 cpuid = smp_processor_id(); 161 162 /* 163 * (This works even if the APIC is not enabled.) 164 */ 165 phys_id = read_apic_id(); 166 167 /* 168 * the boot CPU has finished the init stage and is spinning 169 * on callin_map until we finish. We are free to set up this 170 * CPU, first the APIC. (this is probably redundant on most 171 * boards) 172 */ 173 apic_ap_setup(); 174 175 /* 176 * Save our processor parameters. Note: this information 177 * is needed for clock calibration. 178 */ 179 smp_store_cpu_info(cpuid); 180 181 /* 182 * The topology information must be up to date before 183 * calibrate_delay() and notify_cpu_starting(). 184 */ 185 set_cpu_sibling_map(raw_smp_processor_id()); 186 187 /* 188 * Get our bogomips. 189 * Update loops_per_jiffy in cpu_data. Previous call to 190 * smp_store_cpu_info() stored a value that is close but not as 191 * accurate as the value just calculated. 192 */ 193 calibrate_delay(); 194 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 195 pr_debug("Stack at about %p\n", &cpuid); 196 197 wmb(); 198 199 notify_cpu_starting(cpuid); 200 201 /* 202 * Allow the master to continue. 203 */ 204 cpumask_set_cpu(cpuid, cpu_callin_mask); 205 } 206 207 static int cpu0_logical_apicid; 208 static int enable_start_cpu0; 209 /* 210 * Activate a secondary processor. 211 */ 212 static void notrace start_secondary(void *unused) 213 { 214 /* 215 * Don't put *anything* except direct CPU state initialization 216 * before cpu_init(), SMP booting is too fragile that we want to 217 * limit the things done here to the most necessary things. 218 */ 219 if (boot_cpu_has(X86_FEATURE_PCID)) 220 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 221 222 #ifdef CONFIG_X86_32 223 /* switch away from the initial page table */ 224 load_cr3(swapper_pg_dir); 225 /* 226 * Initialize the CR4 shadow before doing anything that could 227 * try to read it. 228 */ 229 cr4_init_shadow(); 230 __flush_tlb_all(); 231 #endif 232 load_current_idt(); 233 cpu_init(); 234 x86_cpuinit.early_percpu_clock_init(); 235 preempt_disable(); 236 smp_callin(); 237 238 enable_start_cpu0 = 0; 239 240 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 241 barrier(); 242 /* 243 * Check TSC synchronization with the boot CPU: 244 */ 245 check_tsc_sync_target(); 246 247 speculative_store_bypass_ht_init(); 248 249 /* 250 * Lock vector_lock, set CPU online and bring the vector 251 * allocator online. Online must be set with vector_lock held 252 * to prevent a concurrent irq setup/teardown from seeing a 253 * half valid vector space. 254 */ 255 lock_vector_lock(); 256 set_cpu_online(smp_processor_id(), true); 257 lapic_online(); 258 unlock_vector_lock(); 259 cpu_set_state_online(smp_processor_id()); 260 x86_platform.nmi_init(); 261 262 /* enable local interrupts */ 263 local_irq_enable(); 264 265 /* to prevent fake stack check failure in clock setup */ 266 boot_init_stack_canary(); 267 268 x86_cpuinit.setup_percpu_clockev(); 269 270 wmb(); 271 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 272 } 273 274 /** 275 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 276 * @cpu: CPU to check 277 */ 278 bool topology_is_primary_thread(unsigned int cpu) 279 { 280 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 281 } 282 283 /** 284 * topology_smt_supported - Check whether SMT is supported by the CPUs 285 */ 286 bool topology_smt_supported(void) 287 { 288 return smp_num_siblings > 1; 289 } 290 291 /** 292 * topology_phys_to_logical_pkg - Map a physical package id to a logical 293 * 294 * Returns logical package id or -1 if not found 295 */ 296 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 297 { 298 int cpu; 299 300 for_each_possible_cpu(cpu) { 301 struct cpuinfo_x86 *c = &cpu_data(cpu); 302 303 if (c->initialized && c->phys_proc_id == phys_pkg) 304 return c->logical_proc_id; 305 } 306 return -1; 307 } 308 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 309 310 /** 311 * topology_update_package_map - Update the physical to logical package map 312 * @pkg: The physical package id as retrieved via CPUID 313 * @cpu: The cpu for which this is updated 314 */ 315 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 316 { 317 int new; 318 319 /* Already available somewhere? */ 320 new = topology_phys_to_logical_pkg(pkg); 321 if (new >= 0) 322 goto found; 323 324 new = logical_packages++; 325 if (new != pkg) { 326 pr_info("CPU %u Converting physical %u to logical package %u\n", 327 cpu, pkg, new); 328 } 329 found: 330 cpu_data(cpu).logical_proc_id = new; 331 return 0; 332 } 333 334 void __init smp_store_boot_cpu_info(void) 335 { 336 int id = 0; /* CPU 0 */ 337 struct cpuinfo_x86 *c = &cpu_data(id); 338 339 *c = boot_cpu_data; 340 c->cpu_index = id; 341 topology_update_package_map(c->phys_proc_id, id); 342 c->initialized = true; 343 } 344 345 /* 346 * The bootstrap kernel entry code has set these up. Save them for 347 * a given CPU 348 */ 349 void smp_store_cpu_info(int id) 350 { 351 struct cpuinfo_x86 *c = &cpu_data(id); 352 353 /* Copy boot_cpu_data only on the first bringup */ 354 if (!c->initialized) 355 *c = boot_cpu_data; 356 c->cpu_index = id; 357 /* 358 * During boot time, CPU0 has this setup already. Save the info when 359 * bringing up AP or offlined CPU0. 360 */ 361 identify_secondary_cpu(c); 362 c->initialized = true; 363 } 364 365 static bool 366 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 367 { 368 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 369 370 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 371 } 372 373 static bool 374 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 375 { 376 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 377 378 return !WARN_ONCE(!topology_same_node(c, o), 379 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 380 "[node: %d != %d]. Ignoring dependency.\n", 381 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 382 } 383 384 #define link_mask(mfunc, c1, c2) \ 385 do { \ 386 cpumask_set_cpu((c1), mfunc(c2)); \ 387 cpumask_set_cpu((c2), mfunc(c1)); \ 388 } while (0) 389 390 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 391 { 392 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 393 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 394 395 if (c->phys_proc_id == o->phys_proc_id && 396 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 397 if (c->cpu_core_id == o->cpu_core_id) 398 return topology_sane(c, o, "smt"); 399 400 if ((c->cu_id != 0xff) && 401 (o->cu_id != 0xff) && 402 (c->cu_id == o->cu_id)) 403 return topology_sane(c, o, "smt"); 404 } 405 406 } else if (c->phys_proc_id == o->phys_proc_id && 407 c->cpu_core_id == o->cpu_core_id) { 408 return topology_sane(c, o, "smt"); 409 } 410 411 return false; 412 } 413 414 /* 415 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 416 * 417 * These are Intel CPUs that enumerate an LLC that is shared by 418 * multiple NUMA nodes. The LLC on these systems is shared for 419 * off-package data access but private to the NUMA node (half 420 * of the package) for on-package access. 421 * 422 * CPUID (the source of the information about the LLC) can only 423 * enumerate the cache as being shared *or* unshared, but not 424 * this particular configuration. The CPU in this case enumerates 425 * the cache to be shared across the entire package (spanning both 426 * NUMA nodes). 427 */ 428 429 static const struct x86_cpu_id snc_cpu[] = { 430 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X }, 431 {} 432 }; 433 434 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 435 { 436 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 437 438 /* Do not match if we do not have a valid APICID for cpu: */ 439 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 440 return false; 441 442 /* Do not match if LLC id does not match: */ 443 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 444 return false; 445 446 /* 447 * Allow the SNC topology without warning. Return of false 448 * means 'c' does not share the LLC of 'o'. This will be 449 * reflected to userspace. 450 */ 451 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 452 return false; 453 454 return topology_sane(c, o, "llc"); 455 } 456 457 /* 458 * Unlike the other levels, we do not enforce keeping a 459 * multicore group inside a NUMA node. If this happens, we will 460 * discard the MC level of the topology later. 461 */ 462 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 463 { 464 if (c->phys_proc_id == o->phys_proc_id) 465 return true; 466 return false; 467 } 468 469 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 470 static inline int x86_sched_itmt_flags(void) 471 { 472 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 473 } 474 475 #ifdef CONFIG_SCHED_MC 476 static int x86_core_flags(void) 477 { 478 return cpu_core_flags() | x86_sched_itmt_flags(); 479 } 480 #endif 481 #ifdef CONFIG_SCHED_SMT 482 static int x86_smt_flags(void) 483 { 484 return cpu_smt_flags() | x86_sched_itmt_flags(); 485 } 486 #endif 487 #endif 488 489 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 490 #ifdef CONFIG_SCHED_SMT 491 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 492 #endif 493 #ifdef CONFIG_SCHED_MC 494 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 495 #endif 496 { NULL, }, 497 }; 498 499 static struct sched_domain_topology_level x86_topology[] = { 500 #ifdef CONFIG_SCHED_SMT 501 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 502 #endif 503 #ifdef CONFIG_SCHED_MC 504 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 505 #endif 506 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 507 { NULL, }, 508 }; 509 510 /* 511 * Set if a package/die has multiple NUMA nodes inside. 512 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 513 * Sub-NUMA Clustering have this. 514 */ 515 static bool x86_has_numa_in_package; 516 517 void set_cpu_sibling_map(int cpu) 518 { 519 bool has_smt = smp_num_siblings > 1; 520 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 521 struct cpuinfo_x86 *c = &cpu_data(cpu); 522 struct cpuinfo_x86 *o; 523 int i, threads; 524 525 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 526 527 if (!has_mp) { 528 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 529 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 530 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 531 c->booted_cores = 1; 532 return; 533 } 534 535 for_each_cpu(i, cpu_sibling_setup_mask) { 536 o = &cpu_data(i); 537 538 if ((i == cpu) || (has_smt && match_smt(c, o))) 539 link_mask(topology_sibling_cpumask, cpu, i); 540 541 if ((i == cpu) || (has_mp && match_llc(c, o))) 542 link_mask(cpu_llc_shared_mask, cpu, i); 543 544 } 545 546 /* 547 * This needs a separate iteration over the cpus because we rely on all 548 * topology_sibling_cpumask links to be set-up. 549 */ 550 for_each_cpu(i, cpu_sibling_setup_mask) { 551 o = &cpu_data(i); 552 553 if ((i == cpu) || (has_mp && match_die(c, o))) { 554 link_mask(topology_core_cpumask, cpu, i); 555 556 /* 557 * Does this new cpu bringup a new core? 558 */ 559 if (cpumask_weight( 560 topology_sibling_cpumask(cpu)) == 1) { 561 /* 562 * for each core in package, increment 563 * the booted_cores for this new cpu 564 */ 565 if (cpumask_first( 566 topology_sibling_cpumask(i)) == i) 567 c->booted_cores++; 568 /* 569 * increment the core count for all 570 * the other cpus in this package 571 */ 572 if (i != cpu) 573 cpu_data(i).booted_cores++; 574 } else if (i != cpu && !c->booted_cores) 575 c->booted_cores = cpu_data(i).booted_cores; 576 } 577 if (match_die(c, o) && !topology_same_node(c, o)) 578 x86_has_numa_in_package = true; 579 } 580 581 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 582 if (threads > __max_smt_threads) 583 __max_smt_threads = threads; 584 } 585 586 /* maps the cpu to the sched domain representing multi-core */ 587 const struct cpumask *cpu_coregroup_mask(int cpu) 588 { 589 return cpu_llc_shared_mask(cpu); 590 } 591 592 static void impress_friends(void) 593 { 594 int cpu; 595 unsigned long bogosum = 0; 596 /* 597 * Allow the user to impress friends. 598 */ 599 pr_debug("Before bogomips\n"); 600 for_each_possible_cpu(cpu) 601 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 602 bogosum += cpu_data(cpu).loops_per_jiffy; 603 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 604 num_online_cpus(), 605 bogosum/(500000/HZ), 606 (bogosum/(5000/HZ))%100); 607 608 pr_debug("Before bogocount - setting activated=1\n"); 609 } 610 611 void __inquire_remote_apic(int apicid) 612 { 613 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 614 const char * const names[] = { "ID", "VERSION", "SPIV" }; 615 int timeout; 616 u32 status; 617 618 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 619 620 for (i = 0; i < ARRAY_SIZE(regs); i++) { 621 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 622 623 /* 624 * Wait for idle. 625 */ 626 status = safe_apic_wait_icr_idle(); 627 if (status) 628 pr_cont("a previous APIC delivery may have failed\n"); 629 630 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 631 632 timeout = 0; 633 do { 634 udelay(100); 635 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 636 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 637 638 switch (status) { 639 case APIC_ICR_RR_VALID: 640 status = apic_read(APIC_RRR); 641 pr_cont("%08x\n", status); 642 break; 643 default: 644 pr_cont("failed\n"); 645 } 646 } 647 } 648 649 /* 650 * The Multiprocessor Specification 1.4 (1997) example code suggests 651 * that there should be a 10ms delay between the BSP asserting INIT 652 * and de-asserting INIT, when starting a remote processor. 653 * But that slows boot and resume on modern processors, which include 654 * many cores and don't require that delay. 655 * 656 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 657 * Modern processor families are quirked to remove the delay entirely. 658 */ 659 #define UDELAY_10MS_DEFAULT 10000 660 661 static unsigned int init_udelay = UINT_MAX; 662 663 static int __init cpu_init_udelay(char *str) 664 { 665 get_option(&str, &init_udelay); 666 667 return 0; 668 } 669 early_param("cpu_init_udelay", cpu_init_udelay); 670 671 static void __init smp_quirk_init_udelay(void) 672 { 673 /* if cmdline changed it from default, leave it alone */ 674 if (init_udelay != UINT_MAX) 675 return; 676 677 /* if modern processor, use no delay */ 678 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 679 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 680 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 681 init_udelay = 0; 682 return; 683 } 684 /* else, use legacy delay */ 685 init_udelay = UDELAY_10MS_DEFAULT; 686 } 687 688 /* 689 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 690 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 691 * won't ... remember to clear down the APIC, etc later. 692 */ 693 int 694 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 695 { 696 unsigned long send_status, accept_status = 0; 697 int maxlvt; 698 699 /* Target chip */ 700 /* Boot on the stack */ 701 /* Kick the second */ 702 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 703 704 pr_debug("Waiting for send to finish...\n"); 705 send_status = safe_apic_wait_icr_idle(); 706 707 /* 708 * Give the other CPU some time to accept the IPI. 709 */ 710 udelay(200); 711 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 712 maxlvt = lapic_get_maxlvt(); 713 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 714 apic_write(APIC_ESR, 0); 715 accept_status = (apic_read(APIC_ESR) & 0xEF); 716 } 717 pr_debug("NMI sent\n"); 718 719 if (send_status) 720 pr_err("APIC never delivered???\n"); 721 if (accept_status) 722 pr_err("APIC delivery error (%lx)\n", accept_status); 723 724 return (send_status | accept_status); 725 } 726 727 static int 728 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 729 { 730 unsigned long send_status = 0, accept_status = 0; 731 int maxlvt, num_starts, j; 732 733 maxlvt = lapic_get_maxlvt(); 734 735 /* 736 * Be paranoid about clearing APIC errors. 737 */ 738 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 739 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 740 apic_write(APIC_ESR, 0); 741 apic_read(APIC_ESR); 742 } 743 744 pr_debug("Asserting INIT\n"); 745 746 /* 747 * Turn INIT on target chip 748 */ 749 /* 750 * Send IPI 751 */ 752 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 753 phys_apicid); 754 755 pr_debug("Waiting for send to finish...\n"); 756 send_status = safe_apic_wait_icr_idle(); 757 758 udelay(init_udelay); 759 760 pr_debug("Deasserting INIT\n"); 761 762 /* Target chip */ 763 /* Send IPI */ 764 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 765 766 pr_debug("Waiting for send to finish...\n"); 767 send_status = safe_apic_wait_icr_idle(); 768 769 mb(); 770 771 /* 772 * Should we send STARTUP IPIs ? 773 * 774 * Determine this based on the APIC version. 775 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 776 */ 777 if (APIC_INTEGRATED(boot_cpu_apic_version)) 778 num_starts = 2; 779 else 780 num_starts = 0; 781 782 /* 783 * Run STARTUP IPI loop. 784 */ 785 pr_debug("#startup loops: %d\n", num_starts); 786 787 for (j = 1; j <= num_starts; j++) { 788 pr_debug("Sending STARTUP #%d\n", j); 789 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 790 apic_write(APIC_ESR, 0); 791 apic_read(APIC_ESR); 792 pr_debug("After apic_write\n"); 793 794 /* 795 * STARTUP IPI 796 */ 797 798 /* Target chip */ 799 /* Boot on the stack */ 800 /* Kick the second */ 801 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 802 phys_apicid); 803 804 /* 805 * Give the other CPU some time to accept the IPI. 806 */ 807 if (init_udelay == 0) 808 udelay(10); 809 else 810 udelay(300); 811 812 pr_debug("Startup point 1\n"); 813 814 pr_debug("Waiting for send to finish...\n"); 815 send_status = safe_apic_wait_icr_idle(); 816 817 /* 818 * Give the other CPU some time to accept the IPI. 819 */ 820 if (init_udelay == 0) 821 udelay(10); 822 else 823 udelay(200); 824 825 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 826 apic_write(APIC_ESR, 0); 827 accept_status = (apic_read(APIC_ESR) & 0xEF); 828 if (send_status || accept_status) 829 break; 830 } 831 pr_debug("After Startup\n"); 832 833 if (send_status) 834 pr_err("APIC never delivered???\n"); 835 if (accept_status) 836 pr_err("APIC delivery error (%lx)\n", accept_status); 837 838 return (send_status | accept_status); 839 } 840 841 /* reduce the number of lines printed when booting a large cpu count system */ 842 static void announce_cpu(int cpu, int apicid) 843 { 844 static int current_node = -1; 845 int node = early_cpu_to_node(cpu); 846 static int width, node_width; 847 848 if (!width) 849 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 850 851 if (!node_width) 852 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 853 854 if (cpu == 1) 855 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 856 857 if (system_state < SYSTEM_RUNNING) { 858 if (node != current_node) { 859 if (current_node > (-1)) 860 pr_cont("\n"); 861 current_node = node; 862 863 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 864 node_width - num_digits(node), " ", node); 865 } 866 867 /* Add padding for the BSP */ 868 if (cpu == 1) 869 pr_cont("%*s", width + 1, " "); 870 871 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 872 873 } else 874 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 875 node, cpu, apicid); 876 } 877 878 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 879 { 880 int cpu; 881 882 cpu = smp_processor_id(); 883 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 884 return NMI_HANDLED; 885 886 return NMI_DONE; 887 } 888 889 /* 890 * Wake up AP by INIT, INIT, STARTUP sequence. 891 * 892 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 893 * boot-strap code which is not a desired behavior for waking up BSP. To 894 * void the boot-strap code, wake up CPU0 by NMI instead. 895 * 896 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 897 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 898 * We'll change this code in the future to wake up hard offlined CPU0 if 899 * real platform and request are available. 900 */ 901 static int 902 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 903 int *cpu0_nmi_registered) 904 { 905 int id; 906 int boot_error; 907 908 preempt_disable(); 909 910 /* 911 * Wake up AP by INIT, INIT, STARTUP sequence. 912 */ 913 if (cpu) { 914 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 915 goto out; 916 } 917 918 /* 919 * Wake up BSP by nmi. 920 * 921 * Register a NMI handler to help wake up CPU0. 922 */ 923 boot_error = register_nmi_handler(NMI_LOCAL, 924 wakeup_cpu0_nmi, 0, "wake_cpu0"); 925 926 if (!boot_error) { 927 enable_start_cpu0 = 1; 928 *cpu0_nmi_registered = 1; 929 if (apic->dest_logical == APIC_DEST_LOGICAL) 930 id = cpu0_logical_apicid; 931 else 932 id = apicid; 933 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 934 } 935 936 out: 937 preempt_enable(); 938 939 return boot_error; 940 } 941 942 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 943 { 944 /* Just in case we booted with a single CPU. */ 945 alternatives_enable_smp(); 946 947 per_cpu(current_task, cpu) = idle; 948 949 #ifdef CONFIG_X86_32 950 /* Stack for startup_32 can be just as for start_secondary onwards */ 951 irq_ctx_init(cpu); 952 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 953 #else 954 initial_gs = per_cpu_offset(cpu); 955 #endif 956 } 957 958 /* 959 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 960 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 961 * Returns zero if CPU booted OK, else error code from 962 * ->wakeup_secondary_cpu. 963 */ 964 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 965 int *cpu0_nmi_registered) 966 { 967 volatile u32 *trampoline_status = 968 (volatile u32 *) __va(real_mode_header->trampoline_status); 969 /* start_ip had better be page-aligned! */ 970 unsigned long start_ip = real_mode_header->trampoline_start; 971 972 unsigned long boot_error = 0; 973 unsigned long timeout; 974 975 idle->thread.sp = (unsigned long)task_pt_regs(idle); 976 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 977 initial_code = (unsigned long)start_secondary; 978 initial_stack = idle->thread.sp; 979 980 /* Enable the espfix hack for this CPU */ 981 init_espfix_ap(cpu); 982 983 /* So we see what's up */ 984 announce_cpu(cpu, apicid); 985 986 /* 987 * This grunge runs the startup process for 988 * the targeted processor. 989 */ 990 991 if (x86_platform.legacy.warm_reset) { 992 993 pr_debug("Setting warm reset code and vector.\n"); 994 995 smpboot_setup_warm_reset_vector(start_ip); 996 /* 997 * Be paranoid about clearing APIC errors. 998 */ 999 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1000 apic_write(APIC_ESR, 0); 1001 apic_read(APIC_ESR); 1002 } 1003 } 1004 1005 /* 1006 * AP might wait on cpu_callout_mask in cpu_init() with 1007 * cpu_initialized_mask set if previous attempt to online 1008 * it timed-out. Clear cpu_initialized_mask so that after 1009 * INIT/SIPI it could start with a clean state. 1010 */ 1011 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1012 smp_mb(); 1013 1014 /* 1015 * Wake up a CPU in difference cases: 1016 * - Use the method in the APIC driver if it's defined 1017 * Otherwise, 1018 * - Use an INIT boot APIC message for APs or NMI for BSP. 1019 */ 1020 if (apic->wakeup_secondary_cpu) 1021 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1022 else 1023 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1024 cpu0_nmi_registered); 1025 1026 if (!boot_error) { 1027 /* 1028 * Wait 10s total for first sign of life from AP 1029 */ 1030 boot_error = -1; 1031 timeout = jiffies + 10*HZ; 1032 while (time_before(jiffies, timeout)) { 1033 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1034 /* 1035 * Tell AP to proceed with initialization 1036 */ 1037 cpumask_set_cpu(cpu, cpu_callout_mask); 1038 boot_error = 0; 1039 break; 1040 } 1041 schedule(); 1042 } 1043 } 1044 1045 if (!boot_error) { 1046 /* 1047 * Wait till AP completes initial initialization 1048 */ 1049 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1050 /* 1051 * Allow other tasks to run while we wait for the 1052 * AP to come online. This also gives a chance 1053 * for the MTRR work(triggered by the AP coming online) 1054 * to be completed in the stop machine context. 1055 */ 1056 schedule(); 1057 } 1058 } 1059 1060 /* mark "stuck" area as not stuck */ 1061 *trampoline_status = 0; 1062 1063 if (x86_platform.legacy.warm_reset) { 1064 /* 1065 * Cleanup possible dangling ends... 1066 */ 1067 smpboot_restore_warm_reset_vector(); 1068 } 1069 1070 return boot_error; 1071 } 1072 1073 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1074 { 1075 int apicid = apic->cpu_present_to_apicid(cpu); 1076 int cpu0_nmi_registered = 0; 1077 unsigned long flags; 1078 int err, ret = 0; 1079 1080 lockdep_assert_irqs_enabled(); 1081 1082 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1083 1084 if (apicid == BAD_APICID || 1085 !physid_isset(apicid, phys_cpu_present_map) || 1086 !apic->apic_id_valid(apicid)) { 1087 pr_err("%s: bad cpu %d\n", __func__, cpu); 1088 return -EINVAL; 1089 } 1090 1091 /* 1092 * Already booted CPU? 1093 */ 1094 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1095 pr_debug("do_boot_cpu %d Already started\n", cpu); 1096 return -ENOSYS; 1097 } 1098 1099 /* 1100 * Save current MTRR state in case it was changed since early boot 1101 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1102 */ 1103 mtrr_save_state(); 1104 1105 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1106 err = cpu_check_up_prepare(cpu); 1107 if (err && err != -EBUSY) 1108 return err; 1109 1110 /* the FPU context is blank, nobody can own it */ 1111 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1112 1113 common_cpu_up(cpu, tidle); 1114 1115 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1116 if (err) { 1117 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1118 ret = -EIO; 1119 goto unreg_nmi; 1120 } 1121 1122 /* 1123 * Check TSC synchronization with the AP (keep irqs disabled 1124 * while doing so): 1125 */ 1126 local_irq_save(flags); 1127 check_tsc_sync_source(cpu); 1128 local_irq_restore(flags); 1129 1130 while (!cpu_online(cpu)) { 1131 cpu_relax(); 1132 touch_nmi_watchdog(); 1133 } 1134 1135 unreg_nmi: 1136 /* 1137 * Clean up the nmi handler. Do this after the callin and callout sync 1138 * to avoid impact of possible long unregister time. 1139 */ 1140 if (cpu0_nmi_registered) 1141 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1142 1143 return ret; 1144 } 1145 1146 /** 1147 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1148 */ 1149 void arch_disable_smp_support(void) 1150 { 1151 disable_ioapic_support(); 1152 } 1153 1154 /* 1155 * Fall back to non SMP mode after errors. 1156 * 1157 * RED-PEN audit/test this more. I bet there is more state messed up here. 1158 */ 1159 static __init void disable_smp(void) 1160 { 1161 pr_info("SMP disabled\n"); 1162 1163 disable_ioapic_support(); 1164 1165 init_cpu_present(cpumask_of(0)); 1166 init_cpu_possible(cpumask_of(0)); 1167 1168 if (smp_found_config) 1169 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1170 else 1171 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1172 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1173 cpumask_set_cpu(0, topology_core_cpumask(0)); 1174 } 1175 1176 /* 1177 * Various sanity checks. 1178 */ 1179 static void __init smp_sanity_check(void) 1180 { 1181 preempt_disable(); 1182 1183 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1184 if (def_to_bigsmp && nr_cpu_ids > 8) { 1185 unsigned int cpu; 1186 unsigned nr; 1187 1188 pr_warn("More than 8 CPUs detected - skipping them\n" 1189 "Use CONFIG_X86_BIGSMP\n"); 1190 1191 nr = 0; 1192 for_each_present_cpu(cpu) { 1193 if (nr >= 8) 1194 set_cpu_present(cpu, false); 1195 nr++; 1196 } 1197 1198 nr = 0; 1199 for_each_possible_cpu(cpu) { 1200 if (nr >= 8) 1201 set_cpu_possible(cpu, false); 1202 nr++; 1203 } 1204 1205 nr_cpu_ids = 8; 1206 } 1207 #endif 1208 1209 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1210 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1211 hard_smp_processor_id()); 1212 1213 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1214 } 1215 1216 /* 1217 * Should not be necessary because the MP table should list the boot 1218 * CPU too, but we do it for the sake of robustness anyway. 1219 */ 1220 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1221 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1222 boot_cpu_physical_apicid); 1223 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1224 } 1225 preempt_enable(); 1226 } 1227 1228 static void __init smp_cpu_index_default(void) 1229 { 1230 int i; 1231 struct cpuinfo_x86 *c; 1232 1233 for_each_possible_cpu(i) { 1234 c = &cpu_data(i); 1235 /* mark all to hotplug */ 1236 c->cpu_index = nr_cpu_ids; 1237 } 1238 } 1239 1240 static void __init smp_get_logical_apicid(void) 1241 { 1242 if (x2apic_mode) 1243 cpu0_logical_apicid = apic_read(APIC_LDR); 1244 else 1245 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1246 } 1247 1248 /* 1249 * Prepare for SMP bootup. 1250 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1251 * for common interface support. 1252 */ 1253 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1254 { 1255 unsigned int i; 1256 1257 smp_cpu_index_default(); 1258 1259 /* 1260 * Setup boot CPU information 1261 */ 1262 smp_store_boot_cpu_info(); /* Final full version of the data */ 1263 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1264 mb(); 1265 1266 for_each_possible_cpu(i) { 1267 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1268 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1269 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1270 } 1271 1272 /* 1273 * Set 'default' x86 topology, this matches default_topology() in that 1274 * it has NUMA nodes as a topology level. See also 1275 * native_smp_cpus_done(). 1276 * 1277 * Must be done before set_cpus_sibling_map() is ran. 1278 */ 1279 set_sched_topology(x86_topology); 1280 1281 set_cpu_sibling_map(0); 1282 1283 smp_sanity_check(); 1284 1285 switch (apic_intr_mode) { 1286 case APIC_PIC: 1287 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1288 disable_smp(); 1289 return; 1290 case APIC_SYMMETRIC_IO_NO_ROUTING: 1291 disable_smp(); 1292 /* Setup local timer */ 1293 x86_init.timers.setup_percpu_clockev(); 1294 return; 1295 case APIC_VIRTUAL_WIRE: 1296 case APIC_SYMMETRIC_IO: 1297 break; 1298 } 1299 1300 /* Setup local timer */ 1301 x86_init.timers.setup_percpu_clockev(); 1302 1303 smp_get_logical_apicid(); 1304 1305 pr_info("CPU0: "); 1306 print_cpu_info(&cpu_data(0)); 1307 1308 native_pv_lock_init(); 1309 1310 uv_system_init(); 1311 1312 set_mtrr_aps_delayed_init(); 1313 1314 smp_quirk_init_udelay(); 1315 1316 speculative_store_bypass_ht_init(); 1317 } 1318 1319 void arch_enable_nonboot_cpus_begin(void) 1320 { 1321 set_mtrr_aps_delayed_init(); 1322 } 1323 1324 void arch_enable_nonboot_cpus_end(void) 1325 { 1326 mtrr_aps_init(); 1327 } 1328 1329 /* 1330 * Early setup to make printk work. 1331 */ 1332 void __init native_smp_prepare_boot_cpu(void) 1333 { 1334 int me = smp_processor_id(); 1335 switch_to_new_gdt(me); 1336 /* already set me in cpu_online_mask in boot_cpu_init() */ 1337 cpumask_set_cpu(me, cpu_callout_mask); 1338 cpu_set_state_online(me); 1339 } 1340 1341 void __init calculate_max_logical_packages(void) 1342 { 1343 int ncpus; 1344 1345 /* 1346 * Today neither Intel nor AMD support heterogenous systems so 1347 * extrapolate the boot cpu's data to all packages. 1348 */ 1349 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1350 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); 1351 pr_info("Max logical packages: %u\n", __max_logical_packages); 1352 } 1353 1354 void __init native_smp_cpus_done(unsigned int max_cpus) 1355 { 1356 pr_debug("Boot done\n"); 1357 1358 calculate_max_logical_packages(); 1359 1360 if (x86_has_numa_in_package) 1361 set_sched_topology(x86_numa_in_package_topology); 1362 1363 nmi_selftest(); 1364 impress_friends(); 1365 mtrr_aps_init(); 1366 } 1367 1368 static int __initdata setup_possible_cpus = -1; 1369 static int __init _setup_possible_cpus(char *str) 1370 { 1371 get_option(&str, &setup_possible_cpus); 1372 return 0; 1373 } 1374 early_param("possible_cpus", _setup_possible_cpus); 1375 1376 1377 /* 1378 * cpu_possible_mask should be static, it cannot change as cpu's 1379 * are onlined, or offlined. The reason is per-cpu data-structures 1380 * are allocated by some modules at init time, and dont expect to 1381 * do this dynamically on cpu arrival/departure. 1382 * cpu_present_mask on the other hand can change dynamically. 1383 * In case when cpu_hotplug is not compiled, then we resort to current 1384 * behaviour, which is cpu_possible == cpu_present. 1385 * - Ashok Raj 1386 * 1387 * Three ways to find out the number of additional hotplug CPUs: 1388 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1389 * - The user can overwrite it with possible_cpus=NUM 1390 * - Otherwise don't reserve additional CPUs. 1391 * We do this because additional CPUs waste a lot of memory. 1392 * -AK 1393 */ 1394 __init void prefill_possible_map(void) 1395 { 1396 int i, possible; 1397 1398 /* No boot processor was found in mptable or ACPI MADT */ 1399 if (!num_processors) { 1400 if (boot_cpu_has(X86_FEATURE_APIC)) { 1401 int apicid = boot_cpu_physical_apicid; 1402 int cpu = hard_smp_processor_id(); 1403 1404 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1405 1406 /* Make sure boot cpu is enumerated */ 1407 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1408 apic->apic_id_valid(apicid)) 1409 generic_processor_info(apicid, boot_cpu_apic_version); 1410 } 1411 1412 if (!num_processors) 1413 num_processors = 1; 1414 } 1415 1416 i = setup_max_cpus ?: 1; 1417 if (setup_possible_cpus == -1) { 1418 possible = num_processors; 1419 #ifdef CONFIG_HOTPLUG_CPU 1420 if (setup_max_cpus) 1421 possible += disabled_cpus; 1422 #else 1423 if (possible > i) 1424 possible = i; 1425 #endif 1426 } else 1427 possible = setup_possible_cpus; 1428 1429 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1430 1431 /* nr_cpu_ids could be reduced via nr_cpus= */ 1432 if (possible > nr_cpu_ids) { 1433 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1434 possible, nr_cpu_ids); 1435 possible = nr_cpu_ids; 1436 } 1437 1438 #ifdef CONFIG_HOTPLUG_CPU 1439 if (!setup_max_cpus) 1440 #endif 1441 if (possible > i) { 1442 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1443 possible, setup_max_cpus); 1444 possible = i; 1445 } 1446 1447 nr_cpu_ids = possible; 1448 1449 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1450 possible, max_t(int, possible - num_processors, 0)); 1451 1452 reset_cpu_possible_mask(); 1453 1454 for (i = 0; i < possible; i++) 1455 set_cpu_possible(i, true); 1456 } 1457 1458 #ifdef CONFIG_HOTPLUG_CPU 1459 1460 /* Recompute SMT state for all CPUs on offline */ 1461 static void recompute_smt_state(void) 1462 { 1463 int max_threads, cpu; 1464 1465 max_threads = 0; 1466 for_each_online_cpu (cpu) { 1467 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1468 1469 if (threads > max_threads) 1470 max_threads = threads; 1471 } 1472 __max_smt_threads = max_threads; 1473 } 1474 1475 static void remove_siblinginfo(int cpu) 1476 { 1477 int sibling; 1478 struct cpuinfo_x86 *c = &cpu_data(cpu); 1479 1480 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1481 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1482 /*/ 1483 * last thread sibling in this cpu core going down 1484 */ 1485 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1486 cpu_data(sibling).booted_cores--; 1487 } 1488 1489 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1490 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1491 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1492 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1493 cpumask_clear(cpu_llc_shared_mask(cpu)); 1494 cpumask_clear(topology_sibling_cpumask(cpu)); 1495 cpumask_clear(topology_core_cpumask(cpu)); 1496 c->cpu_core_id = 0; 1497 c->booted_cores = 0; 1498 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1499 recompute_smt_state(); 1500 } 1501 1502 static void remove_cpu_from_maps(int cpu) 1503 { 1504 set_cpu_online(cpu, false); 1505 cpumask_clear_cpu(cpu, cpu_callout_mask); 1506 cpumask_clear_cpu(cpu, cpu_callin_mask); 1507 /* was set by cpu_init() */ 1508 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1509 numa_remove_cpu(cpu); 1510 } 1511 1512 void cpu_disable_common(void) 1513 { 1514 int cpu = smp_processor_id(); 1515 1516 remove_siblinginfo(cpu); 1517 1518 /* It's now safe to remove this processor from the online map */ 1519 lock_vector_lock(); 1520 remove_cpu_from_maps(cpu); 1521 unlock_vector_lock(); 1522 fixup_irqs(); 1523 lapic_offline(); 1524 } 1525 1526 int native_cpu_disable(void) 1527 { 1528 int ret; 1529 1530 ret = lapic_can_unplug_cpu(); 1531 if (ret) 1532 return ret; 1533 1534 clear_local_APIC(); 1535 cpu_disable_common(); 1536 1537 return 0; 1538 } 1539 1540 int common_cpu_die(unsigned int cpu) 1541 { 1542 int ret = 0; 1543 1544 /* We don't do anything here: idle task is faking death itself. */ 1545 1546 /* They ack this in play_dead() by setting CPU_DEAD */ 1547 if (cpu_wait_death(cpu, 5)) { 1548 if (system_state == SYSTEM_RUNNING) 1549 pr_info("CPU %u is now offline\n", cpu); 1550 } else { 1551 pr_err("CPU %u didn't die...\n", cpu); 1552 ret = -1; 1553 } 1554 1555 return ret; 1556 } 1557 1558 void native_cpu_die(unsigned int cpu) 1559 { 1560 common_cpu_die(cpu); 1561 } 1562 1563 void play_dead_common(void) 1564 { 1565 idle_task_exit(); 1566 1567 /* Ack it */ 1568 (void)cpu_report_death(); 1569 1570 /* 1571 * With physical CPU hotplug, we should halt the cpu 1572 */ 1573 local_irq_disable(); 1574 } 1575 1576 static bool wakeup_cpu0(void) 1577 { 1578 if (smp_processor_id() == 0 && enable_start_cpu0) 1579 return true; 1580 1581 return false; 1582 } 1583 1584 /* 1585 * We need to flush the caches before going to sleep, lest we have 1586 * dirty data in our caches when we come back up. 1587 */ 1588 static inline void mwait_play_dead(void) 1589 { 1590 unsigned int eax, ebx, ecx, edx; 1591 unsigned int highest_cstate = 0; 1592 unsigned int highest_subcstate = 0; 1593 void *mwait_ptr; 1594 int i; 1595 1596 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1597 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1598 return; 1599 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1600 return; 1601 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1602 return; 1603 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1604 return; 1605 1606 eax = CPUID_MWAIT_LEAF; 1607 ecx = 0; 1608 native_cpuid(&eax, &ebx, &ecx, &edx); 1609 1610 /* 1611 * eax will be 0 if EDX enumeration is not valid. 1612 * Initialized below to cstate, sub_cstate value when EDX is valid. 1613 */ 1614 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1615 eax = 0; 1616 } else { 1617 edx >>= MWAIT_SUBSTATE_SIZE; 1618 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1619 if (edx & MWAIT_SUBSTATE_MASK) { 1620 highest_cstate = i; 1621 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1622 } 1623 } 1624 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1625 (highest_subcstate - 1); 1626 } 1627 1628 /* 1629 * This should be a memory location in a cache line which is 1630 * unlikely to be touched by other processors. The actual 1631 * content is immaterial as it is not actually modified in any way. 1632 */ 1633 mwait_ptr = ¤t_thread_info()->flags; 1634 1635 wbinvd(); 1636 1637 while (1) { 1638 /* 1639 * The CLFLUSH is a workaround for erratum AAI65 for 1640 * the Xeon 7400 series. It's not clear it is actually 1641 * needed, but it should be harmless in either case. 1642 * The WBINVD is insufficient due to the spurious-wakeup 1643 * case where we return around the loop. 1644 */ 1645 mb(); 1646 clflush(mwait_ptr); 1647 mb(); 1648 __monitor(mwait_ptr, 0, 0); 1649 mb(); 1650 __mwait(eax, 0); 1651 /* 1652 * If NMI wants to wake up CPU0, start CPU0. 1653 */ 1654 if (wakeup_cpu0()) 1655 start_cpu0(); 1656 } 1657 } 1658 1659 void hlt_play_dead(void) 1660 { 1661 if (__this_cpu_read(cpu_info.x86) >= 4) 1662 wbinvd(); 1663 1664 while (1) { 1665 native_halt(); 1666 /* 1667 * If NMI wants to wake up CPU0, start CPU0. 1668 */ 1669 if (wakeup_cpu0()) 1670 start_cpu0(); 1671 } 1672 } 1673 1674 void native_play_dead(void) 1675 { 1676 play_dead_common(); 1677 tboot_shutdown(TB_SHUTDOWN_WFS); 1678 1679 mwait_play_dead(); /* Only returns on failure */ 1680 if (cpuidle_play_dead()) 1681 hlt_play_dead(); 1682 } 1683 1684 #else /* ... !CONFIG_HOTPLUG_CPU */ 1685 int native_cpu_disable(void) 1686 { 1687 return -ENOSYS; 1688 } 1689 1690 void native_cpu_die(unsigned int cpu) 1691 { 1692 /* We said "no" in __cpu_disable */ 1693 BUG(); 1694 } 1695 1696 void native_play_dead(void) 1697 { 1698 BUG(); 1699 } 1700 1701 #endif 1702