1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/bootmem.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/misc.h> 79 #include <asm/qspinlock.h> 80 #include <asm/intel-family.h> 81 #include <asm/cpu_device_id.h> 82 83 /* Number of siblings per CPU package */ 84 int smp_num_siblings = 1; 85 EXPORT_SYMBOL(smp_num_siblings); 86 87 /* Last level cache ID of each logical CPU */ 88 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 89 90 /* representing HT siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 93 94 /* representing HT and core siblings of each logical CPU */ 95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 96 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 97 98 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 99 100 /* Per CPU bogomips and other parameters */ 101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 102 EXPORT_PER_CPU_SYMBOL(cpu_info); 103 104 /* Logical package management. We might want to allocate that dynamically */ 105 unsigned int __max_logical_packages __read_mostly; 106 EXPORT_SYMBOL(__max_logical_packages); 107 static unsigned int logical_packages __read_mostly; 108 109 /* Maximum number of SMT threads on any online core */ 110 int __read_mostly __max_smt_threads = 1; 111 112 /* Flag to indicate if a complete sched domain rebuild is required */ 113 bool x86_topology_update; 114 115 int arch_update_cpu_topology(void) 116 { 117 int retval = x86_topology_update; 118 119 x86_topology_update = false; 120 return retval; 121 } 122 123 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 124 { 125 unsigned long flags; 126 127 spin_lock_irqsave(&rtc_lock, flags); 128 CMOS_WRITE(0xa, 0xf); 129 spin_unlock_irqrestore(&rtc_lock, flags); 130 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 131 start_eip >> 4; 132 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 133 start_eip & 0xf; 134 } 135 136 static inline void smpboot_restore_warm_reset_vector(void) 137 { 138 unsigned long flags; 139 140 /* 141 * Paranoid: Set warm reset code and vector here back 142 * to default values. 143 */ 144 spin_lock_irqsave(&rtc_lock, flags); 145 CMOS_WRITE(0, 0xf); 146 spin_unlock_irqrestore(&rtc_lock, flags); 147 148 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 149 } 150 151 /* 152 * Report back to the Boot Processor during boot time or to the caller processor 153 * during CPU online. 154 */ 155 static void smp_callin(void) 156 { 157 int cpuid, phys_id; 158 159 /* 160 * If waken up by an INIT in an 82489DX configuration 161 * cpu_callout_mask guarantees we don't get here before 162 * an INIT_deassert IPI reaches our local APIC, so it is 163 * now safe to touch our local APIC. 164 */ 165 cpuid = smp_processor_id(); 166 167 /* 168 * (This works even if the APIC is not enabled.) 169 */ 170 phys_id = read_apic_id(); 171 172 /* 173 * the boot CPU has finished the init stage and is spinning 174 * on callin_map until we finish. We are free to set up this 175 * CPU, first the APIC. (this is probably redundant on most 176 * boards) 177 */ 178 apic_ap_setup(); 179 180 /* 181 * Save our processor parameters. Note: this information 182 * is needed for clock calibration. 183 */ 184 smp_store_cpu_info(cpuid); 185 186 /* 187 * The topology information must be up to date before 188 * calibrate_delay() and notify_cpu_starting(). 189 */ 190 set_cpu_sibling_map(raw_smp_processor_id()); 191 192 /* 193 * Get our bogomips. 194 * Update loops_per_jiffy in cpu_data. Previous call to 195 * smp_store_cpu_info() stored a value that is close but not as 196 * accurate as the value just calculated. 197 */ 198 calibrate_delay(); 199 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 200 pr_debug("Stack at about %p\n", &cpuid); 201 202 wmb(); 203 204 notify_cpu_starting(cpuid); 205 206 /* 207 * Allow the master to continue. 208 */ 209 cpumask_set_cpu(cpuid, cpu_callin_mask); 210 } 211 212 static int cpu0_logical_apicid; 213 static int enable_start_cpu0; 214 /* 215 * Activate a secondary processor. 216 */ 217 static void notrace start_secondary(void *unused) 218 { 219 /* 220 * Don't put *anything* except direct CPU state initialization 221 * before cpu_init(), SMP booting is too fragile that we want to 222 * limit the things done here to the most necessary things. 223 */ 224 if (boot_cpu_has(X86_FEATURE_PCID)) 225 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 226 227 #ifdef CONFIG_X86_32 228 /* switch away from the initial page table */ 229 load_cr3(swapper_pg_dir); 230 __flush_tlb_all(); 231 #endif 232 load_current_idt(); 233 cpu_init(); 234 x86_cpuinit.early_percpu_clock_init(); 235 preempt_disable(); 236 smp_callin(); 237 238 enable_start_cpu0 = 0; 239 240 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 241 barrier(); 242 /* 243 * Check TSC synchronization with the boot CPU: 244 */ 245 check_tsc_sync_target(); 246 247 /* 248 * Lock vector_lock, set CPU online and bring the vector 249 * allocator online. Online must be set with vector_lock held 250 * to prevent a concurrent irq setup/teardown from seeing a 251 * half valid vector space. 252 */ 253 lock_vector_lock(); 254 set_cpu_online(smp_processor_id(), true); 255 lapic_online(); 256 unlock_vector_lock(); 257 cpu_set_state_online(smp_processor_id()); 258 x86_platform.nmi_init(); 259 260 /* enable local interrupts */ 261 local_irq_enable(); 262 263 /* to prevent fake stack check failure in clock setup */ 264 boot_init_stack_canary(); 265 266 x86_cpuinit.setup_percpu_clockev(); 267 268 wmb(); 269 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 270 } 271 272 /** 273 * topology_phys_to_logical_pkg - Map a physical package id to a logical 274 * 275 * Returns logical package id or -1 if not found 276 */ 277 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 278 { 279 int cpu; 280 281 for_each_possible_cpu(cpu) { 282 struct cpuinfo_x86 *c = &cpu_data(cpu); 283 284 if (c->initialized && c->phys_proc_id == phys_pkg) 285 return c->logical_proc_id; 286 } 287 return -1; 288 } 289 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 290 291 /** 292 * topology_update_package_map - Update the physical to logical package map 293 * @pkg: The physical package id as retrieved via CPUID 294 * @cpu: The cpu for which this is updated 295 */ 296 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 297 { 298 int new; 299 300 /* Already available somewhere? */ 301 new = topology_phys_to_logical_pkg(pkg); 302 if (new >= 0) 303 goto found; 304 305 new = logical_packages++; 306 if (new != pkg) { 307 pr_info("CPU %u Converting physical %u to logical package %u\n", 308 cpu, pkg, new); 309 } 310 found: 311 cpu_data(cpu).logical_proc_id = new; 312 return 0; 313 } 314 315 void __init smp_store_boot_cpu_info(void) 316 { 317 int id = 0; /* CPU 0 */ 318 struct cpuinfo_x86 *c = &cpu_data(id); 319 320 *c = boot_cpu_data; 321 c->cpu_index = id; 322 topology_update_package_map(c->phys_proc_id, id); 323 c->initialized = true; 324 } 325 326 /* 327 * The bootstrap kernel entry code has set these up. Save them for 328 * a given CPU 329 */ 330 void smp_store_cpu_info(int id) 331 { 332 struct cpuinfo_x86 *c = &cpu_data(id); 333 334 /* Copy boot_cpu_data only on the first bringup */ 335 if (!c->initialized) 336 *c = boot_cpu_data; 337 c->cpu_index = id; 338 /* 339 * During boot time, CPU0 has this setup already. Save the info when 340 * bringing up AP or offlined CPU0. 341 */ 342 identify_secondary_cpu(c); 343 c->initialized = true; 344 } 345 346 static bool 347 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 348 { 349 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 350 351 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 352 } 353 354 static bool 355 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 356 { 357 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 358 359 return !WARN_ONCE(!topology_same_node(c, o), 360 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 361 "[node: %d != %d]. Ignoring dependency.\n", 362 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 363 } 364 365 #define link_mask(mfunc, c1, c2) \ 366 do { \ 367 cpumask_set_cpu((c1), mfunc(c2)); \ 368 cpumask_set_cpu((c2), mfunc(c1)); \ 369 } while (0) 370 371 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 372 { 373 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 374 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 375 376 if (c->phys_proc_id == o->phys_proc_id && 377 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 378 if (c->cpu_core_id == o->cpu_core_id) 379 return topology_sane(c, o, "smt"); 380 381 if ((c->cu_id != 0xff) && 382 (o->cu_id != 0xff) && 383 (c->cu_id == o->cu_id)) 384 return topology_sane(c, o, "smt"); 385 } 386 387 } else if (c->phys_proc_id == o->phys_proc_id && 388 c->cpu_core_id == o->cpu_core_id) { 389 return topology_sane(c, o, "smt"); 390 } 391 392 return false; 393 } 394 395 /* 396 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 397 * 398 * These are Intel CPUs that enumerate an LLC that is shared by 399 * multiple NUMA nodes. The LLC on these systems is shared for 400 * off-package data access but private to the NUMA node (half 401 * of the package) for on-package access. 402 * 403 * CPUID (the source of the information about the LLC) can only 404 * enumerate the cache as being shared *or* unshared, but not 405 * this particular configuration. The CPU in this case enumerates 406 * the cache to be shared across the entire package (spanning both 407 * NUMA nodes). 408 */ 409 410 static const struct x86_cpu_id snc_cpu[] = { 411 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X }, 412 {} 413 }; 414 415 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 416 { 417 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 418 419 /* Do not match if we do not have a valid APICID for cpu: */ 420 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 421 return false; 422 423 /* Do not match if LLC id does not match: */ 424 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 425 return false; 426 427 /* 428 * Allow the SNC topology without warning. Return of false 429 * means 'c' does not share the LLC of 'o'. This will be 430 * reflected to userspace. 431 */ 432 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 433 return false; 434 435 return topology_sane(c, o, "llc"); 436 } 437 438 /* 439 * Unlike the other levels, we do not enforce keeping a 440 * multicore group inside a NUMA node. If this happens, we will 441 * discard the MC level of the topology later. 442 */ 443 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 444 { 445 if (c->phys_proc_id == o->phys_proc_id) 446 return true; 447 return false; 448 } 449 450 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 451 static inline int x86_sched_itmt_flags(void) 452 { 453 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 454 } 455 456 #ifdef CONFIG_SCHED_MC 457 static int x86_core_flags(void) 458 { 459 return cpu_core_flags() | x86_sched_itmt_flags(); 460 } 461 #endif 462 #ifdef CONFIG_SCHED_SMT 463 static int x86_smt_flags(void) 464 { 465 return cpu_smt_flags() | x86_sched_itmt_flags(); 466 } 467 #endif 468 #endif 469 470 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 471 #ifdef CONFIG_SCHED_SMT 472 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 473 #endif 474 #ifdef CONFIG_SCHED_MC 475 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 476 #endif 477 { NULL, }, 478 }; 479 480 static struct sched_domain_topology_level x86_topology[] = { 481 #ifdef CONFIG_SCHED_SMT 482 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 483 #endif 484 #ifdef CONFIG_SCHED_MC 485 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 486 #endif 487 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 488 { NULL, }, 489 }; 490 491 /* 492 * Set if a package/die has multiple NUMA nodes inside. 493 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 494 * Sub-NUMA Clustering have this. 495 */ 496 static bool x86_has_numa_in_package; 497 498 void set_cpu_sibling_map(int cpu) 499 { 500 bool has_smt = smp_num_siblings > 1; 501 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 502 struct cpuinfo_x86 *c = &cpu_data(cpu); 503 struct cpuinfo_x86 *o; 504 int i, threads; 505 506 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 507 508 if (!has_mp) { 509 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 510 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 511 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 512 c->booted_cores = 1; 513 return; 514 } 515 516 for_each_cpu(i, cpu_sibling_setup_mask) { 517 o = &cpu_data(i); 518 519 if ((i == cpu) || (has_smt && match_smt(c, o))) 520 link_mask(topology_sibling_cpumask, cpu, i); 521 522 if ((i == cpu) || (has_mp && match_llc(c, o))) 523 link_mask(cpu_llc_shared_mask, cpu, i); 524 525 } 526 527 /* 528 * This needs a separate iteration over the cpus because we rely on all 529 * topology_sibling_cpumask links to be set-up. 530 */ 531 for_each_cpu(i, cpu_sibling_setup_mask) { 532 o = &cpu_data(i); 533 534 if ((i == cpu) || (has_mp && match_die(c, o))) { 535 link_mask(topology_core_cpumask, cpu, i); 536 537 /* 538 * Does this new cpu bringup a new core? 539 */ 540 if (cpumask_weight( 541 topology_sibling_cpumask(cpu)) == 1) { 542 /* 543 * for each core in package, increment 544 * the booted_cores for this new cpu 545 */ 546 if (cpumask_first( 547 topology_sibling_cpumask(i)) == i) 548 c->booted_cores++; 549 /* 550 * increment the core count for all 551 * the other cpus in this package 552 */ 553 if (i != cpu) 554 cpu_data(i).booted_cores++; 555 } else if (i != cpu && !c->booted_cores) 556 c->booted_cores = cpu_data(i).booted_cores; 557 } 558 if (match_die(c, o) && !topology_same_node(c, o)) 559 x86_has_numa_in_package = true; 560 } 561 562 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 563 if (threads > __max_smt_threads) 564 __max_smt_threads = threads; 565 } 566 567 /* maps the cpu to the sched domain representing multi-core */ 568 const struct cpumask *cpu_coregroup_mask(int cpu) 569 { 570 return cpu_llc_shared_mask(cpu); 571 } 572 573 static void impress_friends(void) 574 { 575 int cpu; 576 unsigned long bogosum = 0; 577 /* 578 * Allow the user to impress friends. 579 */ 580 pr_debug("Before bogomips\n"); 581 for_each_possible_cpu(cpu) 582 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 583 bogosum += cpu_data(cpu).loops_per_jiffy; 584 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 585 num_online_cpus(), 586 bogosum/(500000/HZ), 587 (bogosum/(5000/HZ))%100); 588 589 pr_debug("Before bogocount - setting activated=1\n"); 590 } 591 592 void __inquire_remote_apic(int apicid) 593 { 594 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 595 const char * const names[] = { "ID", "VERSION", "SPIV" }; 596 int timeout; 597 u32 status; 598 599 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 600 601 for (i = 0; i < ARRAY_SIZE(regs); i++) { 602 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 603 604 /* 605 * Wait for idle. 606 */ 607 status = safe_apic_wait_icr_idle(); 608 if (status) 609 pr_cont("a previous APIC delivery may have failed\n"); 610 611 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 612 613 timeout = 0; 614 do { 615 udelay(100); 616 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 617 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 618 619 switch (status) { 620 case APIC_ICR_RR_VALID: 621 status = apic_read(APIC_RRR); 622 pr_cont("%08x\n", status); 623 break; 624 default: 625 pr_cont("failed\n"); 626 } 627 } 628 } 629 630 /* 631 * The Multiprocessor Specification 1.4 (1997) example code suggests 632 * that there should be a 10ms delay between the BSP asserting INIT 633 * and de-asserting INIT, when starting a remote processor. 634 * But that slows boot and resume on modern processors, which include 635 * many cores and don't require that delay. 636 * 637 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 638 * Modern processor families are quirked to remove the delay entirely. 639 */ 640 #define UDELAY_10MS_DEFAULT 10000 641 642 static unsigned int init_udelay = UINT_MAX; 643 644 static int __init cpu_init_udelay(char *str) 645 { 646 get_option(&str, &init_udelay); 647 648 return 0; 649 } 650 early_param("cpu_init_udelay", cpu_init_udelay); 651 652 static void __init smp_quirk_init_udelay(void) 653 { 654 /* if cmdline changed it from default, leave it alone */ 655 if (init_udelay != UINT_MAX) 656 return; 657 658 /* if modern processor, use no delay */ 659 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 660 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 661 init_udelay = 0; 662 return; 663 } 664 /* else, use legacy delay */ 665 init_udelay = UDELAY_10MS_DEFAULT; 666 } 667 668 /* 669 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 670 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 671 * won't ... remember to clear down the APIC, etc later. 672 */ 673 int 674 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 675 { 676 unsigned long send_status, accept_status = 0; 677 int maxlvt; 678 679 /* Target chip */ 680 /* Boot on the stack */ 681 /* Kick the second */ 682 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 683 684 pr_debug("Waiting for send to finish...\n"); 685 send_status = safe_apic_wait_icr_idle(); 686 687 /* 688 * Give the other CPU some time to accept the IPI. 689 */ 690 udelay(200); 691 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 692 maxlvt = lapic_get_maxlvt(); 693 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 694 apic_write(APIC_ESR, 0); 695 accept_status = (apic_read(APIC_ESR) & 0xEF); 696 } 697 pr_debug("NMI sent\n"); 698 699 if (send_status) 700 pr_err("APIC never delivered???\n"); 701 if (accept_status) 702 pr_err("APIC delivery error (%lx)\n", accept_status); 703 704 return (send_status | accept_status); 705 } 706 707 static int 708 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 709 { 710 unsigned long send_status = 0, accept_status = 0; 711 int maxlvt, num_starts, j; 712 713 maxlvt = lapic_get_maxlvt(); 714 715 /* 716 * Be paranoid about clearing APIC errors. 717 */ 718 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 719 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 720 apic_write(APIC_ESR, 0); 721 apic_read(APIC_ESR); 722 } 723 724 pr_debug("Asserting INIT\n"); 725 726 /* 727 * Turn INIT on target chip 728 */ 729 /* 730 * Send IPI 731 */ 732 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 733 phys_apicid); 734 735 pr_debug("Waiting for send to finish...\n"); 736 send_status = safe_apic_wait_icr_idle(); 737 738 udelay(init_udelay); 739 740 pr_debug("Deasserting INIT\n"); 741 742 /* Target chip */ 743 /* Send IPI */ 744 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 745 746 pr_debug("Waiting for send to finish...\n"); 747 send_status = safe_apic_wait_icr_idle(); 748 749 mb(); 750 751 /* 752 * Should we send STARTUP IPIs ? 753 * 754 * Determine this based on the APIC version. 755 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 756 */ 757 if (APIC_INTEGRATED(boot_cpu_apic_version)) 758 num_starts = 2; 759 else 760 num_starts = 0; 761 762 /* 763 * Run STARTUP IPI loop. 764 */ 765 pr_debug("#startup loops: %d\n", num_starts); 766 767 for (j = 1; j <= num_starts; j++) { 768 pr_debug("Sending STARTUP #%d\n", j); 769 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 770 apic_write(APIC_ESR, 0); 771 apic_read(APIC_ESR); 772 pr_debug("After apic_write\n"); 773 774 /* 775 * STARTUP IPI 776 */ 777 778 /* Target chip */ 779 /* Boot on the stack */ 780 /* Kick the second */ 781 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 782 phys_apicid); 783 784 /* 785 * Give the other CPU some time to accept the IPI. 786 */ 787 if (init_udelay == 0) 788 udelay(10); 789 else 790 udelay(300); 791 792 pr_debug("Startup point 1\n"); 793 794 pr_debug("Waiting for send to finish...\n"); 795 send_status = safe_apic_wait_icr_idle(); 796 797 /* 798 * Give the other CPU some time to accept the IPI. 799 */ 800 if (init_udelay == 0) 801 udelay(10); 802 else 803 udelay(200); 804 805 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 806 apic_write(APIC_ESR, 0); 807 accept_status = (apic_read(APIC_ESR) & 0xEF); 808 if (send_status || accept_status) 809 break; 810 } 811 pr_debug("After Startup\n"); 812 813 if (send_status) 814 pr_err("APIC never delivered???\n"); 815 if (accept_status) 816 pr_err("APIC delivery error (%lx)\n", accept_status); 817 818 return (send_status | accept_status); 819 } 820 821 /* reduce the number of lines printed when booting a large cpu count system */ 822 static void announce_cpu(int cpu, int apicid) 823 { 824 static int current_node = -1; 825 int node = early_cpu_to_node(cpu); 826 static int width, node_width; 827 828 if (!width) 829 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 830 831 if (!node_width) 832 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 833 834 if (cpu == 1) 835 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 836 837 if (system_state < SYSTEM_RUNNING) { 838 if (node != current_node) { 839 if (current_node > (-1)) 840 pr_cont("\n"); 841 current_node = node; 842 843 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 844 node_width - num_digits(node), " ", node); 845 } 846 847 /* Add padding for the BSP */ 848 if (cpu == 1) 849 pr_cont("%*s", width + 1, " "); 850 851 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 852 853 } else 854 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 855 node, cpu, apicid); 856 } 857 858 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 859 { 860 int cpu; 861 862 cpu = smp_processor_id(); 863 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 864 return NMI_HANDLED; 865 866 return NMI_DONE; 867 } 868 869 /* 870 * Wake up AP by INIT, INIT, STARTUP sequence. 871 * 872 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 873 * boot-strap code which is not a desired behavior for waking up BSP. To 874 * void the boot-strap code, wake up CPU0 by NMI instead. 875 * 876 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 877 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 878 * We'll change this code in the future to wake up hard offlined CPU0 if 879 * real platform and request are available. 880 */ 881 static int 882 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 883 int *cpu0_nmi_registered) 884 { 885 int id; 886 int boot_error; 887 888 preempt_disable(); 889 890 /* 891 * Wake up AP by INIT, INIT, STARTUP sequence. 892 */ 893 if (cpu) { 894 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 895 goto out; 896 } 897 898 /* 899 * Wake up BSP by nmi. 900 * 901 * Register a NMI handler to help wake up CPU0. 902 */ 903 boot_error = register_nmi_handler(NMI_LOCAL, 904 wakeup_cpu0_nmi, 0, "wake_cpu0"); 905 906 if (!boot_error) { 907 enable_start_cpu0 = 1; 908 *cpu0_nmi_registered = 1; 909 if (apic->dest_logical == APIC_DEST_LOGICAL) 910 id = cpu0_logical_apicid; 911 else 912 id = apicid; 913 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 914 } 915 916 out: 917 preempt_enable(); 918 919 return boot_error; 920 } 921 922 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 923 { 924 /* Just in case we booted with a single CPU. */ 925 alternatives_enable_smp(); 926 927 per_cpu(current_task, cpu) = idle; 928 929 #ifdef CONFIG_X86_32 930 /* Stack for startup_32 can be just as for start_secondary onwards */ 931 irq_ctx_init(cpu); 932 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 933 #else 934 initial_gs = per_cpu_offset(cpu); 935 #endif 936 } 937 938 /* 939 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 940 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 941 * Returns zero if CPU booted OK, else error code from 942 * ->wakeup_secondary_cpu. 943 */ 944 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 945 int *cpu0_nmi_registered) 946 { 947 volatile u32 *trampoline_status = 948 (volatile u32 *) __va(real_mode_header->trampoline_status); 949 /* start_ip had better be page-aligned! */ 950 unsigned long start_ip = real_mode_header->trampoline_start; 951 952 unsigned long boot_error = 0; 953 unsigned long timeout; 954 955 idle->thread.sp = (unsigned long)task_pt_regs(idle); 956 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 957 initial_code = (unsigned long)start_secondary; 958 initial_stack = idle->thread.sp; 959 960 /* Enable the espfix hack for this CPU */ 961 init_espfix_ap(cpu); 962 963 /* So we see what's up */ 964 announce_cpu(cpu, apicid); 965 966 /* 967 * This grunge runs the startup process for 968 * the targeted processor. 969 */ 970 971 if (x86_platform.legacy.warm_reset) { 972 973 pr_debug("Setting warm reset code and vector.\n"); 974 975 smpboot_setup_warm_reset_vector(start_ip); 976 /* 977 * Be paranoid about clearing APIC errors. 978 */ 979 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 980 apic_write(APIC_ESR, 0); 981 apic_read(APIC_ESR); 982 } 983 } 984 985 /* 986 * AP might wait on cpu_callout_mask in cpu_init() with 987 * cpu_initialized_mask set if previous attempt to online 988 * it timed-out. Clear cpu_initialized_mask so that after 989 * INIT/SIPI it could start with a clean state. 990 */ 991 cpumask_clear_cpu(cpu, cpu_initialized_mask); 992 smp_mb(); 993 994 /* 995 * Wake up a CPU in difference cases: 996 * - Use the method in the APIC driver if it's defined 997 * Otherwise, 998 * - Use an INIT boot APIC message for APs or NMI for BSP. 999 */ 1000 if (apic->wakeup_secondary_cpu) 1001 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1002 else 1003 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1004 cpu0_nmi_registered); 1005 1006 if (!boot_error) { 1007 /* 1008 * Wait 10s total for first sign of life from AP 1009 */ 1010 boot_error = -1; 1011 timeout = jiffies + 10*HZ; 1012 while (time_before(jiffies, timeout)) { 1013 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1014 /* 1015 * Tell AP to proceed with initialization 1016 */ 1017 cpumask_set_cpu(cpu, cpu_callout_mask); 1018 boot_error = 0; 1019 break; 1020 } 1021 schedule(); 1022 } 1023 } 1024 1025 if (!boot_error) { 1026 /* 1027 * Wait till AP completes initial initialization 1028 */ 1029 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1030 /* 1031 * Allow other tasks to run while we wait for the 1032 * AP to come online. This also gives a chance 1033 * for the MTRR work(triggered by the AP coming online) 1034 * to be completed in the stop machine context. 1035 */ 1036 schedule(); 1037 } 1038 } 1039 1040 /* mark "stuck" area as not stuck */ 1041 *trampoline_status = 0; 1042 1043 if (x86_platform.legacy.warm_reset) { 1044 /* 1045 * Cleanup possible dangling ends... 1046 */ 1047 smpboot_restore_warm_reset_vector(); 1048 } 1049 1050 return boot_error; 1051 } 1052 1053 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1054 { 1055 int apicid = apic->cpu_present_to_apicid(cpu); 1056 int cpu0_nmi_registered = 0; 1057 unsigned long flags; 1058 int err, ret = 0; 1059 1060 lockdep_assert_irqs_enabled(); 1061 1062 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1063 1064 if (apicid == BAD_APICID || 1065 !physid_isset(apicid, phys_cpu_present_map) || 1066 !apic->apic_id_valid(apicid)) { 1067 pr_err("%s: bad cpu %d\n", __func__, cpu); 1068 return -EINVAL; 1069 } 1070 1071 /* 1072 * Already booted CPU? 1073 */ 1074 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1075 pr_debug("do_boot_cpu %d Already started\n", cpu); 1076 return -ENOSYS; 1077 } 1078 1079 /* 1080 * Save current MTRR state in case it was changed since early boot 1081 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1082 */ 1083 mtrr_save_state(); 1084 1085 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1086 err = cpu_check_up_prepare(cpu); 1087 if (err && err != -EBUSY) 1088 return err; 1089 1090 /* the FPU context is blank, nobody can own it */ 1091 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1092 1093 common_cpu_up(cpu, tidle); 1094 1095 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1096 if (err) { 1097 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1098 ret = -EIO; 1099 goto unreg_nmi; 1100 } 1101 1102 /* 1103 * Check TSC synchronization with the AP (keep irqs disabled 1104 * while doing so): 1105 */ 1106 local_irq_save(flags); 1107 check_tsc_sync_source(cpu); 1108 local_irq_restore(flags); 1109 1110 while (!cpu_online(cpu)) { 1111 cpu_relax(); 1112 touch_nmi_watchdog(); 1113 } 1114 1115 unreg_nmi: 1116 /* 1117 * Clean up the nmi handler. Do this after the callin and callout sync 1118 * to avoid impact of possible long unregister time. 1119 */ 1120 if (cpu0_nmi_registered) 1121 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1122 1123 return ret; 1124 } 1125 1126 /** 1127 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1128 */ 1129 void arch_disable_smp_support(void) 1130 { 1131 disable_ioapic_support(); 1132 } 1133 1134 /* 1135 * Fall back to non SMP mode after errors. 1136 * 1137 * RED-PEN audit/test this more. I bet there is more state messed up here. 1138 */ 1139 static __init void disable_smp(void) 1140 { 1141 pr_info("SMP disabled\n"); 1142 1143 disable_ioapic_support(); 1144 1145 init_cpu_present(cpumask_of(0)); 1146 init_cpu_possible(cpumask_of(0)); 1147 1148 if (smp_found_config) 1149 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1150 else 1151 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1152 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1153 cpumask_set_cpu(0, topology_core_cpumask(0)); 1154 } 1155 1156 /* 1157 * Various sanity checks. 1158 */ 1159 static void __init smp_sanity_check(void) 1160 { 1161 preempt_disable(); 1162 1163 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1164 if (def_to_bigsmp && nr_cpu_ids > 8) { 1165 unsigned int cpu; 1166 unsigned nr; 1167 1168 pr_warn("More than 8 CPUs detected - skipping them\n" 1169 "Use CONFIG_X86_BIGSMP\n"); 1170 1171 nr = 0; 1172 for_each_present_cpu(cpu) { 1173 if (nr >= 8) 1174 set_cpu_present(cpu, false); 1175 nr++; 1176 } 1177 1178 nr = 0; 1179 for_each_possible_cpu(cpu) { 1180 if (nr >= 8) 1181 set_cpu_possible(cpu, false); 1182 nr++; 1183 } 1184 1185 nr_cpu_ids = 8; 1186 } 1187 #endif 1188 1189 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1190 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1191 hard_smp_processor_id()); 1192 1193 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1194 } 1195 1196 /* 1197 * Should not be necessary because the MP table should list the boot 1198 * CPU too, but we do it for the sake of robustness anyway. 1199 */ 1200 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1201 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1202 boot_cpu_physical_apicid); 1203 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1204 } 1205 preempt_enable(); 1206 } 1207 1208 static void __init smp_cpu_index_default(void) 1209 { 1210 int i; 1211 struct cpuinfo_x86 *c; 1212 1213 for_each_possible_cpu(i) { 1214 c = &cpu_data(i); 1215 /* mark all to hotplug */ 1216 c->cpu_index = nr_cpu_ids; 1217 } 1218 } 1219 1220 static void __init smp_get_logical_apicid(void) 1221 { 1222 if (x2apic_mode) 1223 cpu0_logical_apicid = apic_read(APIC_LDR); 1224 else 1225 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1226 } 1227 1228 /* 1229 * Prepare for SMP bootup. 1230 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1231 * for common interface support. 1232 */ 1233 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1234 { 1235 unsigned int i; 1236 1237 smp_cpu_index_default(); 1238 1239 /* 1240 * Setup boot CPU information 1241 */ 1242 smp_store_boot_cpu_info(); /* Final full version of the data */ 1243 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1244 mb(); 1245 1246 for_each_possible_cpu(i) { 1247 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1248 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1249 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1250 } 1251 1252 /* 1253 * Set 'default' x86 topology, this matches default_topology() in that 1254 * it has NUMA nodes as a topology level. See also 1255 * native_smp_cpus_done(). 1256 * 1257 * Must be done before set_cpus_sibling_map() is ran. 1258 */ 1259 set_sched_topology(x86_topology); 1260 1261 set_cpu_sibling_map(0); 1262 1263 smp_sanity_check(); 1264 1265 switch (apic_intr_mode) { 1266 case APIC_PIC: 1267 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1268 disable_smp(); 1269 return; 1270 case APIC_SYMMETRIC_IO_NO_ROUTING: 1271 disable_smp(); 1272 /* Setup local timer */ 1273 x86_init.timers.setup_percpu_clockev(); 1274 return; 1275 case APIC_VIRTUAL_WIRE: 1276 case APIC_SYMMETRIC_IO: 1277 break; 1278 } 1279 1280 /* Setup local timer */ 1281 x86_init.timers.setup_percpu_clockev(); 1282 1283 smp_get_logical_apicid(); 1284 1285 pr_info("CPU0: "); 1286 print_cpu_info(&cpu_data(0)); 1287 1288 native_pv_lock_init(); 1289 1290 uv_system_init(); 1291 1292 set_mtrr_aps_delayed_init(); 1293 1294 smp_quirk_init_udelay(); 1295 } 1296 1297 void arch_enable_nonboot_cpus_begin(void) 1298 { 1299 set_mtrr_aps_delayed_init(); 1300 } 1301 1302 void arch_enable_nonboot_cpus_end(void) 1303 { 1304 mtrr_aps_init(); 1305 } 1306 1307 /* 1308 * Early setup to make printk work. 1309 */ 1310 void __init native_smp_prepare_boot_cpu(void) 1311 { 1312 int me = smp_processor_id(); 1313 switch_to_new_gdt(me); 1314 /* already set me in cpu_online_mask in boot_cpu_init() */ 1315 cpumask_set_cpu(me, cpu_callout_mask); 1316 cpu_set_state_online(me); 1317 } 1318 1319 void __init calculate_max_logical_packages(void) 1320 { 1321 int ncpus; 1322 1323 /* 1324 * Today neither Intel nor AMD support heterogenous systems so 1325 * extrapolate the boot cpu's data to all packages. 1326 */ 1327 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1328 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); 1329 pr_info("Max logical packages: %u\n", __max_logical_packages); 1330 } 1331 1332 void __init native_smp_cpus_done(unsigned int max_cpus) 1333 { 1334 pr_debug("Boot done\n"); 1335 1336 calculate_max_logical_packages(); 1337 1338 if (x86_has_numa_in_package) 1339 set_sched_topology(x86_numa_in_package_topology); 1340 1341 nmi_selftest(); 1342 impress_friends(); 1343 mtrr_aps_init(); 1344 } 1345 1346 static int __initdata setup_possible_cpus = -1; 1347 static int __init _setup_possible_cpus(char *str) 1348 { 1349 get_option(&str, &setup_possible_cpus); 1350 return 0; 1351 } 1352 early_param("possible_cpus", _setup_possible_cpus); 1353 1354 1355 /* 1356 * cpu_possible_mask should be static, it cannot change as cpu's 1357 * are onlined, or offlined. The reason is per-cpu data-structures 1358 * are allocated by some modules at init time, and dont expect to 1359 * do this dynamically on cpu arrival/departure. 1360 * cpu_present_mask on the other hand can change dynamically. 1361 * In case when cpu_hotplug is not compiled, then we resort to current 1362 * behaviour, which is cpu_possible == cpu_present. 1363 * - Ashok Raj 1364 * 1365 * Three ways to find out the number of additional hotplug CPUs: 1366 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1367 * - The user can overwrite it with possible_cpus=NUM 1368 * - Otherwise don't reserve additional CPUs. 1369 * We do this because additional CPUs waste a lot of memory. 1370 * -AK 1371 */ 1372 __init void prefill_possible_map(void) 1373 { 1374 int i, possible; 1375 1376 /* No boot processor was found in mptable or ACPI MADT */ 1377 if (!num_processors) { 1378 if (boot_cpu_has(X86_FEATURE_APIC)) { 1379 int apicid = boot_cpu_physical_apicid; 1380 int cpu = hard_smp_processor_id(); 1381 1382 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1383 1384 /* Make sure boot cpu is enumerated */ 1385 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1386 apic->apic_id_valid(apicid)) 1387 generic_processor_info(apicid, boot_cpu_apic_version); 1388 } 1389 1390 if (!num_processors) 1391 num_processors = 1; 1392 } 1393 1394 i = setup_max_cpus ?: 1; 1395 if (setup_possible_cpus == -1) { 1396 possible = num_processors; 1397 #ifdef CONFIG_HOTPLUG_CPU 1398 if (setup_max_cpus) 1399 possible += disabled_cpus; 1400 #else 1401 if (possible > i) 1402 possible = i; 1403 #endif 1404 } else 1405 possible = setup_possible_cpus; 1406 1407 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1408 1409 /* nr_cpu_ids could be reduced via nr_cpus= */ 1410 if (possible > nr_cpu_ids) { 1411 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1412 possible, nr_cpu_ids); 1413 possible = nr_cpu_ids; 1414 } 1415 1416 #ifdef CONFIG_HOTPLUG_CPU 1417 if (!setup_max_cpus) 1418 #endif 1419 if (possible > i) { 1420 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1421 possible, setup_max_cpus); 1422 possible = i; 1423 } 1424 1425 nr_cpu_ids = possible; 1426 1427 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1428 possible, max_t(int, possible - num_processors, 0)); 1429 1430 reset_cpu_possible_mask(); 1431 1432 for (i = 0; i < possible; i++) 1433 set_cpu_possible(i, true); 1434 } 1435 1436 #ifdef CONFIG_HOTPLUG_CPU 1437 1438 /* Recompute SMT state for all CPUs on offline */ 1439 static void recompute_smt_state(void) 1440 { 1441 int max_threads, cpu; 1442 1443 max_threads = 0; 1444 for_each_online_cpu (cpu) { 1445 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1446 1447 if (threads > max_threads) 1448 max_threads = threads; 1449 } 1450 __max_smt_threads = max_threads; 1451 } 1452 1453 static void remove_siblinginfo(int cpu) 1454 { 1455 int sibling; 1456 struct cpuinfo_x86 *c = &cpu_data(cpu); 1457 1458 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1459 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1460 /*/ 1461 * last thread sibling in this cpu core going down 1462 */ 1463 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1464 cpu_data(sibling).booted_cores--; 1465 } 1466 1467 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1468 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1469 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1470 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1471 cpumask_clear(cpu_llc_shared_mask(cpu)); 1472 cpumask_clear(topology_sibling_cpumask(cpu)); 1473 cpumask_clear(topology_core_cpumask(cpu)); 1474 c->cpu_core_id = 0; 1475 c->booted_cores = 0; 1476 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1477 recompute_smt_state(); 1478 } 1479 1480 static void remove_cpu_from_maps(int cpu) 1481 { 1482 set_cpu_online(cpu, false); 1483 cpumask_clear_cpu(cpu, cpu_callout_mask); 1484 cpumask_clear_cpu(cpu, cpu_callin_mask); 1485 /* was set by cpu_init() */ 1486 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1487 numa_remove_cpu(cpu); 1488 } 1489 1490 void cpu_disable_common(void) 1491 { 1492 int cpu = smp_processor_id(); 1493 1494 remove_siblinginfo(cpu); 1495 1496 /* It's now safe to remove this processor from the online map */ 1497 lock_vector_lock(); 1498 remove_cpu_from_maps(cpu); 1499 unlock_vector_lock(); 1500 fixup_irqs(); 1501 lapic_offline(); 1502 } 1503 1504 int native_cpu_disable(void) 1505 { 1506 int ret; 1507 1508 ret = lapic_can_unplug_cpu(); 1509 if (ret) 1510 return ret; 1511 1512 clear_local_APIC(); 1513 cpu_disable_common(); 1514 1515 return 0; 1516 } 1517 1518 int common_cpu_die(unsigned int cpu) 1519 { 1520 int ret = 0; 1521 1522 /* We don't do anything here: idle task is faking death itself. */ 1523 1524 /* They ack this in play_dead() by setting CPU_DEAD */ 1525 if (cpu_wait_death(cpu, 5)) { 1526 if (system_state == SYSTEM_RUNNING) 1527 pr_info("CPU %u is now offline\n", cpu); 1528 } else { 1529 pr_err("CPU %u didn't die...\n", cpu); 1530 ret = -1; 1531 } 1532 1533 return ret; 1534 } 1535 1536 void native_cpu_die(unsigned int cpu) 1537 { 1538 common_cpu_die(cpu); 1539 } 1540 1541 void play_dead_common(void) 1542 { 1543 idle_task_exit(); 1544 1545 /* Ack it */ 1546 (void)cpu_report_death(); 1547 1548 /* 1549 * With physical CPU hotplug, we should halt the cpu 1550 */ 1551 local_irq_disable(); 1552 } 1553 1554 static bool wakeup_cpu0(void) 1555 { 1556 if (smp_processor_id() == 0 && enable_start_cpu0) 1557 return true; 1558 1559 return false; 1560 } 1561 1562 /* 1563 * We need to flush the caches before going to sleep, lest we have 1564 * dirty data in our caches when we come back up. 1565 */ 1566 static inline void mwait_play_dead(void) 1567 { 1568 unsigned int eax, ebx, ecx, edx; 1569 unsigned int highest_cstate = 0; 1570 unsigned int highest_subcstate = 0; 1571 void *mwait_ptr; 1572 int i; 1573 1574 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1575 return; 1576 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1577 return; 1578 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1579 return; 1580 1581 eax = CPUID_MWAIT_LEAF; 1582 ecx = 0; 1583 native_cpuid(&eax, &ebx, &ecx, &edx); 1584 1585 /* 1586 * eax will be 0 if EDX enumeration is not valid. 1587 * Initialized below to cstate, sub_cstate value when EDX is valid. 1588 */ 1589 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1590 eax = 0; 1591 } else { 1592 edx >>= MWAIT_SUBSTATE_SIZE; 1593 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1594 if (edx & MWAIT_SUBSTATE_MASK) { 1595 highest_cstate = i; 1596 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1597 } 1598 } 1599 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1600 (highest_subcstate - 1); 1601 } 1602 1603 /* 1604 * This should be a memory location in a cache line which is 1605 * unlikely to be touched by other processors. The actual 1606 * content is immaterial as it is not actually modified in any way. 1607 */ 1608 mwait_ptr = ¤t_thread_info()->flags; 1609 1610 wbinvd(); 1611 1612 while (1) { 1613 /* 1614 * The CLFLUSH is a workaround for erratum AAI65 for 1615 * the Xeon 7400 series. It's not clear it is actually 1616 * needed, but it should be harmless in either case. 1617 * The WBINVD is insufficient due to the spurious-wakeup 1618 * case where we return around the loop. 1619 */ 1620 mb(); 1621 clflush(mwait_ptr); 1622 mb(); 1623 __monitor(mwait_ptr, 0, 0); 1624 mb(); 1625 __mwait(eax, 0); 1626 /* 1627 * If NMI wants to wake up CPU0, start CPU0. 1628 */ 1629 if (wakeup_cpu0()) 1630 start_cpu0(); 1631 } 1632 } 1633 1634 void hlt_play_dead(void) 1635 { 1636 if (__this_cpu_read(cpu_info.x86) >= 4) 1637 wbinvd(); 1638 1639 while (1) { 1640 native_halt(); 1641 /* 1642 * If NMI wants to wake up CPU0, start CPU0. 1643 */ 1644 if (wakeup_cpu0()) 1645 start_cpu0(); 1646 } 1647 } 1648 1649 void native_play_dead(void) 1650 { 1651 play_dead_common(); 1652 tboot_shutdown(TB_SHUTDOWN_WFS); 1653 1654 mwait_play_dead(); /* Only returns on failure */ 1655 if (cpuidle_play_dead()) 1656 hlt_play_dead(); 1657 } 1658 1659 #else /* ... !CONFIG_HOTPLUG_CPU */ 1660 int native_cpu_disable(void) 1661 { 1662 return -ENOSYS; 1663 } 1664 1665 void native_cpu_die(unsigned int cpu) 1666 { 1667 /* We said "no" in __cpu_disable */ 1668 BUG(); 1669 } 1670 1671 void native_play_dead(void) 1672 { 1673 BUG(); 1674 } 1675 1676 #endif 1677