1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 #include <linux/acpi.h> 64 65 #include <asm/acpi.h> 66 #include <asm/cacheinfo.h> 67 #include <asm/desc.h> 68 #include <asm/nmi.h> 69 #include <asm/irq.h> 70 #include <asm/realmode.h> 71 #include <asm/cpu.h> 72 #include <asm/numa.h> 73 #include <asm/tlbflush.h> 74 #include <asm/mtrr.h> 75 #include <asm/mwait.h> 76 #include <asm/apic.h> 77 #include <asm/io_apic.h> 78 #include <asm/fpu/api.h> 79 #include <asm/setup.h> 80 #include <asm/uv/uv.h> 81 #include <asm/microcode.h> 82 #include <asm/i8259.h> 83 #include <asm/misc.h> 84 #include <asm/qspinlock.h> 85 #include <asm/intel-family.h> 86 #include <asm/cpu_device_id.h> 87 #include <asm/spec-ctrl.h> 88 #include <asm/hw_irq.h> 89 #include <asm/stackprotector.h> 90 #include <asm/sev.h> 91 92 /* representing HT siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 95 96 /* representing HT and core siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 99 100 /* representing HT, core, and die siblings of each logical CPU */ 101 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 102 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 103 104 /* Per CPU bogomips and other parameters */ 105 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 106 EXPORT_PER_CPU_SYMBOL(cpu_info); 107 108 /* CPUs which are the primary SMT threads */ 109 struct cpumask __cpu_primary_thread_mask __read_mostly; 110 111 /* Representing CPUs for which sibling maps can be computed */ 112 static cpumask_var_t cpu_sibling_setup_mask; 113 114 struct mwait_cpu_dead { 115 unsigned int control; 116 unsigned int status; 117 }; 118 119 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 120 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 121 122 /* 123 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 124 * that it's unlikely to be touched by other CPUs. 125 */ 126 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 127 128 /* Logical package management. We might want to allocate that dynamically */ 129 unsigned int __max_logical_packages __read_mostly; 130 EXPORT_SYMBOL(__max_logical_packages); 131 static unsigned int logical_packages __read_mostly; 132 static unsigned int logical_die __read_mostly; 133 134 /* Maximum number of SMT threads on any online core */ 135 int __read_mostly __max_smt_threads = 1; 136 137 /* Flag to indicate if a complete sched domain rebuild is required */ 138 bool x86_topology_update; 139 140 int arch_update_cpu_topology(void) 141 { 142 int retval = x86_topology_update; 143 144 x86_topology_update = false; 145 return retval; 146 } 147 148 static unsigned int smpboot_warm_reset_vector_count; 149 150 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 151 { 152 unsigned long flags; 153 154 spin_lock_irqsave(&rtc_lock, flags); 155 if (!smpboot_warm_reset_vector_count++) { 156 CMOS_WRITE(0xa, 0xf); 157 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 158 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 159 } 160 spin_unlock_irqrestore(&rtc_lock, flags); 161 } 162 163 static inline void smpboot_restore_warm_reset_vector(void) 164 { 165 unsigned long flags; 166 167 /* 168 * Paranoid: Set warm reset code and vector here back 169 * to default values. 170 */ 171 spin_lock_irqsave(&rtc_lock, flags); 172 if (!--smpboot_warm_reset_vector_count) { 173 CMOS_WRITE(0, 0xf); 174 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 175 } 176 spin_unlock_irqrestore(&rtc_lock, flags); 177 178 } 179 180 /* Run the next set of setup steps for the upcoming CPU */ 181 static void ap_starting(void) 182 { 183 int cpuid = smp_processor_id(); 184 185 /* Mop up eventual mwait_play_dead() wreckage */ 186 this_cpu_write(mwait_cpu_dead.status, 0); 187 this_cpu_write(mwait_cpu_dead.control, 0); 188 189 /* 190 * If woken up by an INIT in an 82489DX configuration the alive 191 * synchronization guarantees that the CPU does not reach this 192 * point before an INIT_deassert IPI reaches the local APIC, so it 193 * is now safe to touch the local APIC. 194 * 195 * Set up this CPU, first the APIC, which is probably redundant on 196 * most boards. 197 */ 198 apic_ap_setup(); 199 200 /* Save the processor parameters. */ 201 smp_store_cpu_info(cpuid); 202 203 /* 204 * The topology information must be up to date before 205 * notify_cpu_starting(). 206 */ 207 set_cpu_sibling_map(cpuid); 208 209 ap_init_aperfmperf(); 210 211 pr_debug("Stack at about %p\n", &cpuid); 212 213 wmb(); 214 215 /* 216 * This runs the AP through all the cpuhp states to its target 217 * state CPUHP_ONLINE. 218 */ 219 notify_cpu_starting(cpuid); 220 } 221 222 static void ap_calibrate_delay(void) 223 { 224 /* 225 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 226 * smp_store_cpu_info() stored a value that is close but not as 227 * accurate as the value just calculated. 228 * 229 * As this is invoked after the TSC synchronization check, 230 * calibrate_delay_is_known() will skip the calibration routine 231 * when TSC is synchronized across sockets. 232 */ 233 calibrate_delay(); 234 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 235 } 236 237 /* 238 * Activate a secondary processor. 239 */ 240 static void notrace start_secondary(void *unused) 241 { 242 /* 243 * Don't put *anything* except direct CPU state initialization 244 * before cpu_init(), SMP booting is too fragile that we want to 245 * limit the things done here to the most necessary things. 246 */ 247 cr4_init(); 248 249 /* 250 * 32-bit specific. 64-bit reaches this code with the correct page 251 * table established. Yet another historical divergence. 252 */ 253 if (IS_ENABLED(CONFIG_X86_32)) { 254 /* switch away from the initial page table */ 255 load_cr3(swapper_pg_dir); 256 __flush_tlb_all(); 257 } 258 259 cpu_init_exception_handling(); 260 261 /* 262 * 32-bit systems load the microcode from the ASM startup code for 263 * historical reasons. 264 * 265 * On 64-bit systems load it before reaching the AP alive 266 * synchronization point below so it is not part of the full per 267 * CPU serialized bringup part when "parallel" bringup is enabled. 268 * 269 * That's even safe when hyperthreading is enabled in the CPU as 270 * the core code starts the primary threads first and leaves the 271 * secondary threads waiting for SIPI. Loading microcode on 272 * physical cores concurrently is a safe operation. 273 * 274 * This covers both the Intel specific issue that concurrent 275 * microcode loading on SMT siblings must be prohibited and the 276 * vendor independent issue`that microcode loading which changes 277 * CPUID, MSRs etc. must be strictly serialized to maintain 278 * software state correctness. 279 */ 280 if (IS_ENABLED(CONFIG_X86_64)) 281 load_ucode_ap(); 282 283 /* 284 * Synchronization point with the hotplug core. Sets this CPUs 285 * synchronization state to ALIVE and spin-waits for the control CPU to 286 * release this CPU for further bringup. 287 */ 288 cpuhp_ap_sync_alive(); 289 290 cpu_init(); 291 fpu__init_cpu(); 292 rcu_cpu_starting(raw_smp_processor_id()); 293 x86_cpuinit.early_percpu_clock_init(); 294 295 ap_starting(); 296 297 /* Check TSC synchronization with the control CPU. */ 298 check_tsc_sync_target(); 299 300 /* 301 * Calibrate the delay loop after the TSC synchronization check. 302 * This allows to skip the calibration when TSC is synchronized 303 * across sockets. 304 */ 305 ap_calibrate_delay(); 306 307 speculative_store_bypass_ht_init(); 308 309 /* 310 * Lock vector_lock, set CPU online and bring the vector 311 * allocator online. Online must be set with vector_lock held 312 * to prevent a concurrent irq setup/teardown from seeing a 313 * half valid vector space. 314 */ 315 lock_vector_lock(); 316 set_cpu_online(smp_processor_id(), true); 317 lapic_online(); 318 unlock_vector_lock(); 319 x86_platform.nmi_init(); 320 321 /* enable local interrupts */ 322 local_irq_enable(); 323 324 x86_cpuinit.setup_percpu_clockev(); 325 326 wmb(); 327 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 328 } 329 330 /** 331 * topology_phys_to_logical_pkg - Map a physical package id to a logical 332 * @phys_pkg: The physical package id to map 333 * 334 * Returns logical package id or -1 if not found 335 */ 336 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 337 { 338 int cpu; 339 340 for_each_possible_cpu(cpu) { 341 struct cpuinfo_x86 *c = &cpu_data(cpu); 342 343 if (c->initialized && c->phys_proc_id == phys_pkg) 344 return c->logical_proc_id; 345 } 346 return -1; 347 } 348 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 349 350 /** 351 * topology_phys_to_logical_die - Map a physical die id to logical 352 * @die_id: The physical die id to map 353 * @cur_cpu: The CPU for which the mapping is done 354 * 355 * Returns logical die id or -1 if not found 356 */ 357 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 358 { 359 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 360 361 for_each_possible_cpu(cpu) { 362 struct cpuinfo_x86 *c = &cpu_data(cpu); 363 364 if (c->initialized && c->cpu_die_id == die_id && 365 c->phys_proc_id == proc_id) 366 return c->logical_die_id; 367 } 368 return -1; 369 } 370 371 /** 372 * topology_update_package_map - Update the physical to logical package map 373 * @pkg: The physical package id as retrieved via CPUID 374 * @cpu: The cpu for which this is updated 375 */ 376 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 377 { 378 int new; 379 380 /* Already available somewhere? */ 381 new = topology_phys_to_logical_pkg(pkg); 382 if (new >= 0) 383 goto found; 384 385 new = logical_packages++; 386 if (new != pkg) { 387 pr_info("CPU %u Converting physical %u to logical package %u\n", 388 cpu, pkg, new); 389 } 390 found: 391 cpu_data(cpu).logical_proc_id = new; 392 return 0; 393 } 394 /** 395 * topology_update_die_map - Update the physical to logical die map 396 * @die: The die id as retrieved via CPUID 397 * @cpu: The cpu for which this is updated 398 */ 399 int topology_update_die_map(unsigned int die, unsigned int cpu) 400 { 401 int new; 402 403 /* Already available somewhere? */ 404 new = topology_phys_to_logical_die(die, cpu); 405 if (new >= 0) 406 goto found; 407 408 new = logical_die++; 409 if (new != die) { 410 pr_info("CPU %u Converting physical %u to logical die %u\n", 411 cpu, die, new); 412 } 413 found: 414 cpu_data(cpu).logical_die_id = new; 415 return 0; 416 } 417 418 static void __init smp_store_boot_cpu_info(void) 419 { 420 int id = 0; /* CPU 0 */ 421 struct cpuinfo_x86 *c = &cpu_data(id); 422 423 *c = boot_cpu_data; 424 c->cpu_index = id; 425 topology_update_package_map(c->phys_proc_id, id); 426 topology_update_die_map(c->cpu_die_id, id); 427 c->initialized = true; 428 } 429 430 /* 431 * The bootstrap kernel entry code has set these up. Save them for 432 * a given CPU 433 */ 434 void smp_store_cpu_info(int id) 435 { 436 struct cpuinfo_x86 *c = &cpu_data(id); 437 438 /* Copy boot_cpu_data only on the first bringup */ 439 if (!c->initialized) 440 *c = boot_cpu_data; 441 c->cpu_index = id; 442 /* 443 * During boot time, CPU0 has this setup already. Save the info when 444 * bringing up an AP. 445 */ 446 identify_secondary_cpu(c); 447 c->initialized = true; 448 } 449 450 static bool 451 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 452 { 453 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 454 455 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 456 } 457 458 static bool 459 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 460 { 461 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 462 463 return !WARN_ONCE(!topology_same_node(c, o), 464 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 465 "[node: %d != %d]. Ignoring dependency.\n", 466 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 467 } 468 469 #define link_mask(mfunc, c1, c2) \ 470 do { \ 471 cpumask_set_cpu((c1), mfunc(c2)); \ 472 cpumask_set_cpu((c2), mfunc(c1)); \ 473 } while (0) 474 475 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 476 { 477 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 478 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 479 480 if (c->phys_proc_id == o->phys_proc_id && 481 c->cpu_die_id == o->cpu_die_id && 482 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 483 if (c->cpu_core_id == o->cpu_core_id) 484 return topology_sane(c, o, "smt"); 485 486 if ((c->cu_id != 0xff) && 487 (o->cu_id != 0xff) && 488 (c->cu_id == o->cu_id)) 489 return topology_sane(c, o, "smt"); 490 } 491 492 } else if (c->phys_proc_id == o->phys_proc_id && 493 c->cpu_die_id == o->cpu_die_id && 494 c->cpu_core_id == o->cpu_core_id) { 495 return topology_sane(c, o, "smt"); 496 } 497 498 return false; 499 } 500 501 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 502 { 503 if (c->phys_proc_id == o->phys_proc_id && 504 c->cpu_die_id == o->cpu_die_id) 505 return true; 506 return false; 507 } 508 509 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 510 { 511 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 512 513 /* If the arch didn't set up l2c_id, fall back to SMT */ 514 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 515 return match_smt(c, o); 516 517 /* Do not match if L2 cache id does not match: */ 518 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 519 return false; 520 521 return topology_sane(c, o, "l2c"); 522 } 523 524 /* 525 * Unlike the other levels, we do not enforce keeping a 526 * multicore group inside a NUMA node. If this happens, we will 527 * discard the MC level of the topology later. 528 */ 529 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 530 { 531 if (c->phys_proc_id == o->phys_proc_id) 532 return true; 533 return false; 534 } 535 536 /* 537 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 538 * 539 * Any Intel CPU that has multiple nodes per package and does not 540 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 541 * 542 * When in SNC mode, these CPUs enumerate an LLC that is shared 543 * by multiple NUMA nodes. The LLC is shared for off-package data 544 * access but private to the NUMA node (half of the package) for 545 * on-package access. CPUID (the source of the information about 546 * the LLC) can only enumerate the cache as shared or unshared, 547 * but not this particular configuration. 548 */ 549 550 static const struct x86_cpu_id intel_cod_cpu[] = { 551 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 552 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 553 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 554 {} 555 }; 556 557 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 558 { 559 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 560 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 561 bool intel_snc = id && id->driver_data; 562 563 /* Do not match if we do not have a valid APICID for cpu: */ 564 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 565 return false; 566 567 /* Do not match if LLC id does not match: */ 568 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 569 return false; 570 571 /* 572 * Allow the SNC topology without warning. Return of false 573 * means 'c' does not share the LLC of 'o'. This will be 574 * reflected to userspace. 575 */ 576 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 577 return false; 578 579 return topology_sane(c, o, "llc"); 580 } 581 582 583 static inline int x86_sched_itmt_flags(void) 584 { 585 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 586 } 587 588 #ifdef CONFIG_SCHED_MC 589 static int x86_core_flags(void) 590 { 591 return cpu_core_flags() | x86_sched_itmt_flags(); 592 } 593 #endif 594 #ifdef CONFIG_SCHED_SMT 595 static int x86_smt_flags(void) 596 { 597 return cpu_smt_flags(); 598 } 599 #endif 600 #ifdef CONFIG_SCHED_CLUSTER 601 static int x86_cluster_flags(void) 602 { 603 return cpu_cluster_flags() | x86_sched_itmt_flags(); 604 } 605 #endif 606 607 /* 608 * Set if a package/die has multiple NUMA nodes inside. 609 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 610 * Sub-NUMA Clustering have this. 611 */ 612 static bool x86_has_numa_in_package; 613 614 static struct sched_domain_topology_level x86_topology[6]; 615 616 static void __init build_sched_topology(void) 617 { 618 int i = 0; 619 620 #ifdef CONFIG_SCHED_SMT 621 x86_topology[i++] = (struct sched_domain_topology_level){ 622 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 623 }; 624 #endif 625 #ifdef CONFIG_SCHED_CLUSTER 626 x86_topology[i++] = (struct sched_domain_topology_level){ 627 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 628 }; 629 #endif 630 #ifdef CONFIG_SCHED_MC 631 x86_topology[i++] = (struct sched_domain_topology_level){ 632 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 633 }; 634 #endif 635 /* 636 * When there is NUMA topology inside the package skip the PKG domain 637 * since the NUMA domains will auto-magically create the right spanning 638 * domains based on the SLIT. 639 */ 640 if (!x86_has_numa_in_package) { 641 x86_topology[i++] = (struct sched_domain_topology_level){ 642 cpu_cpu_mask, x86_sched_itmt_flags, SD_INIT_NAME(PKG) 643 }; 644 } 645 646 /* 647 * There must be one trailing NULL entry left. 648 */ 649 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 650 651 set_sched_topology(x86_topology); 652 } 653 654 void set_cpu_sibling_map(int cpu) 655 { 656 bool has_smt = smp_num_siblings > 1; 657 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 658 struct cpuinfo_x86 *c = &cpu_data(cpu); 659 struct cpuinfo_x86 *o; 660 int i, threads; 661 662 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 663 664 if (!has_mp) { 665 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 666 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 667 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 668 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 669 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 670 c->booted_cores = 1; 671 return; 672 } 673 674 for_each_cpu(i, cpu_sibling_setup_mask) { 675 o = &cpu_data(i); 676 677 if (match_pkg(c, o) && !topology_same_node(c, o)) 678 x86_has_numa_in_package = true; 679 680 if ((i == cpu) || (has_smt && match_smt(c, o))) 681 link_mask(topology_sibling_cpumask, cpu, i); 682 683 if ((i == cpu) || (has_mp && match_llc(c, o))) 684 link_mask(cpu_llc_shared_mask, cpu, i); 685 686 if ((i == cpu) || (has_mp && match_l2c(c, o))) 687 link_mask(cpu_l2c_shared_mask, cpu, i); 688 689 if ((i == cpu) || (has_mp && match_die(c, o))) 690 link_mask(topology_die_cpumask, cpu, i); 691 } 692 693 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 694 if (threads > __max_smt_threads) 695 __max_smt_threads = threads; 696 697 for_each_cpu(i, topology_sibling_cpumask(cpu)) 698 cpu_data(i).smt_active = threads > 1; 699 700 /* 701 * This needs a separate iteration over the cpus because we rely on all 702 * topology_sibling_cpumask links to be set-up. 703 */ 704 for_each_cpu(i, cpu_sibling_setup_mask) { 705 o = &cpu_data(i); 706 707 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 708 link_mask(topology_core_cpumask, cpu, i); 709 710 /* 711 * Does this new cpu bringup a new core? 712 */ 713 if (threads == 1) { 714 /* 715 * for each core in package, increment 716 * the booted_cores for this new cpu 717 */ 718 if (cpumask_first( 719 topology_sibling_cpumask(i)) == i) 720 c->booted_cores++; 721 /* 722 * increment the core count for all 723 * the other cpus in this package 724 */ 725 if (i != cpu) 726 cpu_data(i).booted_cores++; 727 } else if (i != cpu && !c->booted_cores) 728 c->booted_cores = cpu_data(i).booted_cores; 729 } 730 } 731 } 732 733 /* maps the cpu to the sched domain representing multi-core */ 734 const struct cpumask *cpu_coregroup_mask(int cpu) 735 { 736 return cpu_llc_shared_mask(cpu); 737 } 738 739 const struct cpumask *cpu_clustergroup_mask(int cpu) 740 { 741 return cpu_l2c_shared_mask(cpu); 742 } 743 744 static void impress_friends(void) 745 { 746 int cpu; 747 unsigned long bogosum = 0; 748 /* 749 * Allow the user to impress friends. 750 */ 751 pr_debug("Before bogomips\n"); 752 for_each_online_cpu(cpu) 753 bogosum += cpu_data(cpu).loops_per_jiffy; 754 755 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 756 num_online_cpus(), 757 bogosum/(500000/HZ), 758 (bogosum/(5000/HZ))%100); 759 760 pr_debug("Before bogocount - setting activated=1\n"); 761 } 762 763 /* 764 * The Multiprocessor Specification 1.4 (1997) example code suggests 765 * that there should be a 10ms delay between the BSP asserting INIT 766 * and de-asserting INIT, when starting a remote processor. 767 * But that slows boot and resume on modern processors, which include 768 * many cores and don't require that delay. 769 * 770 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 771 * Modern processor families are quirked to remove the delay entirely. 772 */ 773 #define UDELAY_10MS_DEFAULT 10000 774 775 static unsigned int init_udelay = UINT_MAX; 776 777 static int __init cpu_init_udelay(char *str) 778 { 779 get_option(&str, &init_udelay); 780 781 return 0; 782 } 783 early_param("cpu_init_udelay", cpu_init_udelay); 784 785 static void __init smp_quirk_init_udelay(void) 786 { 787 /* if cmdline changed it from default, leave it alone */ 788 if (init_udelay != UINT_MAX) 789 return; 790 791 /* if modern processor, use no delay */ 792 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 793 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 794 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 795 init_udelay = 0; 796 return; 797 } 798 /* else, use legacy delay */ 799 init_udelay = UDELAY_10MS_DEFAULT; 800 } 801 802 /* 803 * Wake up AP by INIT, INIT, STARTUP sequence. 804 */ 805 static void send_init_sequence(int phys_apicid) 806 { 807 int maxlvt = lapic_get_maxlvt(); 808 809 /* Be paranoid about clearing APIC errors. */ 810 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 811 /* Due to the Pentium erratum 3AP. */ 812 if (maxlvt > 3) 813 apic_write(APIC_ESR, 0); 814 apic_read(APIC_ESR); 815 } 816 817 /* Assert INIT on the target CPU */ 818 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 819 safe_apic_wait_icr_idle(); 820 821 udelay(init_udelay); 822 823 /* Deassert INIT on the target CPU */ 824 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 825 safe_apic_wait_icr_idle(); 826 } 827 828 /* 829 * Wake up AP by INIT, INIT, STARTUP sequence. 830 */ 831 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 832 { 833 unsigned long send_status = 0, accept_status = 0; 834 int num_starts, j, maxlvt; 835 836 preempt_disable(); 837 maxlvt = lapic_get_maxlvt(); 838 send_init_sequence(phys_apicid); 839 840 mb(); 841 842 /* 843 * Should we send STARTUP IPIs ? 844 * 845 * Determine this based on the APIC version. 846 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 847 */ 848 if (APIC_INTEGRATED(boot_cpu_apic_version)) 849 num_starts = 2; 850 else 851 num_starts = 0; 852 853 /* 854 * Run STARTUP IPI loop. 855 */ 856 pr_debug("#startup loops: %d\n", num_starts); 857 858 for (j = 1; j <= num_starts; j++) { 859 pr_debug("Sending STARTUP #%d\n", j); 860 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 861 apic_write(APIC_ESR, 0); 862 apic_read(APIC_ESR); 863 pr_debug("After apic_write\n"); 864 865 /* 866 * STARTUP IPI 867 */ 868 869 /* Target chip */ 870 /* Boot on the stack */ 871 /* Kick the second */ 872 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 873 phys_apicid); 874 875 /* 876 * Give the other CPU some time to accept the IPI. 877 */ 878 if (init_udelay == 0) 879 udelay(10); 880 else 881 udelay(300); 882 883 pr_debug("Startup point 1\n"); 884 885 pr_debug("Waiting for send to finish...\n"); 886 send_status = safe_apic_wait_icr_idle(); 887 888 /* 889 * Give the other CPU some time to accept the IPI. 890 */ 891 if (init_udelay == 0) 892 udelay(10); 893 else 894 udelay(200); 895 896 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 897 apic_write(APIC_ESR, 0); 898 accept_status = (apic_read(APIC_ESR) & 0xEF); 899 if (send_status || accept_status) 900 break; 901 } 902 pr_debug("After Startup\n"); 903 904 if (send_status) 905 pr_err("APIC never delivered???\n"); 906 if (accept_status) 907 pr_err("APIC delivery error (%lx)\n", accept_status); 908 909 preempt_enable(); 910 return (send_status | accept_status); 911 } 912 913 /* reduce the number of lines printed when booting a large cpu count system */ 914 static void announce_cpu(int cpu, int apicid) 915 { 916 static int width, node_width, first = 1; 917 static int current_node = NUMA_NO_NODE; 918 int node = early_cpu_to_node(cpu); 919 920 if (!width) 921 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 922 923 if (!node_width) 924 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 925 926 if (system_state < SYSTEM_RUNNING) { 927 if (first) 928 pr_info("x86: Booting SMP configuration:\n"); 929 930 if (node != current_node) { 931 if (current_node > (-1)) 932 pr_cont("\n"); 933 current_node = node; 934 935 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 936 node_width - num_digits(node), " ", node); 937 } 938 939 /* Add padding for the BSP */ 940 if (first) 941 pr_cont("%*s", width + 1, " "); 942 first = 0; 943 944 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 945 } else 946 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 947 node, cpu, apicid); 948 } 949 950 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 951 { 952 int ret; 953 954 /* Just in case we booted with a single CPU. */ 955 alternatives_enable_smp(); 956 957 per_cpu(pcpu_hot.current_task, cpu) = idle; 958 cpu_init_stack_canary(cpu, idle); 959 960 /* Initialize the interrupt stack(s) */ 961 ret = irq_init_percpu_irqstack(cpu); 962 if (ret) 963 return ret; 964 965 #ifdef CONFIG_X86_32 966 /* Stack for startup_32 can be just as for start_secondary onwards */ 967 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 968 #endif 969 return 0; 970 } 971 972 /* 973 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 974 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 975 * Returns zero if startup was successfully sent, else error code from 976 * ->wakeup_secondary_cpu. 977 */ 978 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 979 { 980 unsigned long start_ip = real_mode_header->trampoline_start; 981 int ret; 982 983 #ifdef CONFIG_X86_64 984 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 985 if (apic->wakeup_secondary_cpu_64) 986 start_ip = real_mode_header->trampoline_start64; 987 #endif 988 idle->thread.sp = (unsigned long)task_pt_regs(idle); 989 initial_code = (unsigned long)start_secondary; 990 991 if (IS_ENABLED(CONFIG_X86_32)) { 992 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 993 initial_stack = idle->thread.sp; 994 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 995 smpboot_control = cpu; 996 } 997 998 /* Enable the espfix hack for this CPU */ 999 init_espfix_ap(cpu); 1000 1001 /* So we see what's up */ 1002 announce_cpu(cpu, apicid); 1003 1004 /* 1005 * This grunge runs the startup process for 1006 * the targeted processor. 1007 */ 1008 if (x86_platform.legacy.warm_reset) { 1009 1010 pr_debug("Setting warm reset code and vector.\n"); 1011 1012 smpboot_setup_warm_reset_vector(start_ip); 1013 /* 1014 * Be paranoid about clearing APIC errors. 1015 */ 1016 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1017 apic_write(APIC_ESR, 0); 1018 apic_read(APIC_ESR); 1019 } 1020 } 1021 1022 smp_mb(); 1023 1024 /* 1025 * Wake up a CPU in difference cases: 1026 * - Use a method from the APIC driver if one defined, with wakeup 1027 * straight to 64-bit mode preferred over wakeup to RM. 1028 * Otherwise, 1029 * - Use an INIT boot APIC message 1030 */ 1031 if (apic->wakeup_secondary_cpu_64) 1032 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1033 else if (apic->wakeup_secondary_cpu) 1034 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1035 else 1036 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1037 1038 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1039 if (ret) 1040 arch_cpuhp_cleanup_kick_cpu(cpu); 1041 return ret; 1042 } 1043 1044 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1045 { 1046 int apicid = apic->cpu_present_to_apicid(cpu); 1047 int err; 1048 1049 lockdep_assert_irqs_enabled(); 1050 1051 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1052 1053 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) || 1054 !apic_id_valid(apicid)) { 1055 pr_err("%s: bad cpu %d\n", __func__, cpu); 1056 return -EINVAL; 1057 } 1058 1059 /* 1060 * Save current MTRR state in case it was changed since early boot 1061 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1062 */ 1063 mtrr_save_state(); 1064 1065 /* the FPU context is blank, nobody can own it */ 1066 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1067 1068 err = common_cpu_up(cpu, tidle); 1069 if (err) 1070 return err; 1071 1072 err = do_boot_cpu(apicid, cpu, tidle); 1073 if (err) 1074 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1075 1076 return err; 1077 } 1078 1079 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1080 { 1081 return smp_ops.kick_ap_alive(cpu, tidle); 1082 } 1083 1084 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1085 { 1086 /* Cleanup possible dangling ends... */ 1087 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1088 smpboot_restore_warm_reset_vector(); 1089 } 1090 1091 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1092 { 1093 if (smp_ops.cleanup_dead_cpu) 1094 smp_ops.cleanup_dead_cpu(cpu); 1095 1096 if (system_state == SYSTEM_RUNNING) 1097 pr_info("CPU %u is now offline\n", cpu); 1098 } 1099 1100 void arch_cpuhp_sync_state_poll(void) 1101 { 1102 if (smp_ops.poll_sync_state) 1103 smp_ops.poll_sync_state(); 1104 } 1105 1106 /** 1107 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1108 */ 1109 void __init arch_disable_smp_support(void) 1110 { 1111 disable_ioapic_support(); 1112 } 1113 1114 /* 1115 * Fall back to non SMP mode after errors. 1116 * 1117 * RED-PEN audit/test this more. I bet there is more state messed up here. 1118 */ 1119 static __init void disable_smp(void) 1120 { 1121 pr_info("SMP disabled\n"); 1122 1123 disable_ioapic_support(); 1124 1125 init_cpu_present(cpumask_of(0)); 1126 init_cpu_possible(cpumask_of(0)); 1127 1128 if (smp_found_config) 1129 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1130 else 1131 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1132 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1133 cpumask_set_cpu(0, topology_core_cpumask(0)); 1134 cpumask_set_cpu(0, topology_die_cpumask(0)); 1135 } 1136 1137 static void __init smp_cpu_index_default(void) 1138 { 1139 int i; 1140 struct cpuinfo_x86 *c; 1141 1142 for_each_possible_cpu(i) { 1143 c = &cpu_data(i); 1144 /* mark all to hotplug */ 1145 c->cpu_index = nr_cpu_ids; 1146 } 1147 } 1148 1149 void __init smp_prepare_cpus_common(void) 1150 { 1151 unsigned int i; 1152 1153 smp_cpu_index_default(); 1154 1155 /* 1156 * Setup boot CPU information 1157 */ 1158 smp_store_boot_cpu_info(); /* Final full version of the data */ 1159 mb(); 1160 1161 for_each_possible_cpu(i) { 1162 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1163 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1164 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1165 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1166 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1167 } 1168 1169 set_cpu_sibling_map(0); 1170 } 1171 1172 #ifdef CONFIG_X86_64 1173 /* Establish whether parallel bringup can be supported. */ 1174 bool __init arch_cpuhp_init_parallel_bringup(void) 1175 { 1176 if (!x86_cpuinit.parallel_bringup) { 1177 pr_info("Parallel CPU startup disabled by the platform\n"); 1178 return false; 1179 } 1180 1181 smpboot_control = STARTUP_READ_APICID; 1182 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1183 return true; 1184 } 1185 #endif 1186 1187 /* 1188 * Prepare for SMP bootup. 1189 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1190 * for common interface support. 1191 */ 1192 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1193 { 1194 smp_prepare_cpus_common(); 1195 1196 switch (apic_intr_mode) { 1197 case APIC_PIC: 1198 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1199 disable_smp(); 1200 return; 1201 case APIC_SYMMETRIC_IO_NO_ROUTING: 1202 disable_smp(); 1203 /* Setup local timer */ 1204 x86_init.timers.setup_percpu_clockev(); 1205 return; 1206 case APIC_VIRTUAL_WIRE: 1207 case APIC_SYMMETRIC_IO: 1208 break; 1209 } 1210 1211 /* Setup local timer */ 1212 x86_init.timers.setup_percpu_clockev(); 1213 1214 pr_info("CPU0: "); 1215 print_cpu_info(&cpu_data(0)); 1216 1217 uv_system_init(); 1218 1219 smp_quirk_init_udelay(); 1220 1221 speculative_store_bypass_ht_init(); 1222 1223 snp_set_wakeup_secondary_cpu(); 1224 } 1225 1226 void arch_thaw_secondary_cpus_begin(void) 1227 { 1228 set_cache_aps_delayed_init(true); 1229 } 1230 1231 void arch_thaw_secondary_cpus_end(void) 1232 { 1233 cache_aps_init(); 1234 } 1235 1236 /* 1237 * Early setup to make printk work. 1238 */ 1239 void __init native_smp_prepare_boot_cpu(void) 1240 { 1241 int me = smp_processor_id(); 1242 1243 /* SMP handles this from setup_per_cpu_areas() */ 1244 if (!IS_ENABLED(CONFIG_SMP)) 1245 switch_gdt_and_percpu_base(me); 1246 1247 native_pv_lock_init(); 1248 } 1249 1250 void __init calculate_max_logical_packages(void) 1251 { 1252 int ncpus; 1253 1254 /* 1255 * Today neither Intel nor AMD support heterogeneous systems so 1256 * extrapolate the boot cpu's data to all packages. 1257 */ 1258 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1259 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1260 pr_info("Max logical packages: %u\n", __max_logical_packages); 1261 } 1262 1263 void __init native_smp_cpus_done(unsigned int max_cpus) 1264 { 1265 pr_debug("Boot done\n"); 1266 1267 calculate_max_logical_packages(); 1268 build_sched_topology(); 1269 nmi_selftest(); 1270 impress_friends(); 1271 cache_aps_init(); 1272 } 1273 1274 static int __initdata setup_possible_cpus = -1; 1275 static int __init _setup_possible_cpus(char *str) 1276 { 1277 get_option(&str, &setup_possible_cpus); 1278 return 0; 1279 } 1280 early_param("possible_cpus", _setup_possible_cpus); 1281 1282 1283 /* 1284 * cpu_possible_mask should be static, it cannot change as cpu's 1285 * are onlined, or offlined. The reason is per-cpu data-structures 1286 * are allocated by some modules at init time, and don't expect to 1287 * do this dynamically on cpu arrival/departure. 1288 * cpu_present_mask on the other hand can change dynamically. 1289 * In case when cpu_hotplug is not compiled, then we resort to current 1290 * behaviour, which is cpu_possible == cpu_present. 1291 * - Ashok Raj 1292 * 1293 * Three ways to find out the number of additional hotplug CPUs: 1294 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1295 * - The user can overwrite it with possible_cpus=NUM 1296 * - Otherwise don't reserve additional CPUs. 1297 * We do this because additional CPUs waste a lot of memory. 1298 * -AK 1299 */ 1300 __init void prefill_possible_map(void) 1301 { 1302 int i, possible; 1303 1304 i = setup_max_cpus ?: 1; 1305 if (setup_possible_cpus == -1) { 1306 possible = num_processors; 1307 #ifdef CONFIG_HOTPLUG_CPU 1308 if (setup_max_cpus) 1309 possible += disabled_cpus; 1310 #else 1311 if (possible > i) 1312 possible = i; 1313 #endif 1314 } else 1315 possible = setup_possible_cpus; 1316 1317 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1318 1319 /* nr_cpu_ids could be reduced via nr_cpus= */ 1320 if (possible > nr_cpu_ids) { 1321 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1322 possible, nr_cpu_ids); 1323 possible = nr_cpu_ids; 1324 } 1325 1326 #ifdef CONFIG_HOTPLUG_CPU 1327 if (!setup_max_cpus) 1328 #endif 1329 if (possible > i) { 1330 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1331 possible, setup_max_cpus); 1332 possible = i; 1333 } 1334 1335 set_nr_cpu_ids(possible); 1336 1337 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1338 possible, max_t(int, possible - num_processors, 0)); 1339 1340 reset_cpu_possible_mask(); 1341 1342 for (i = 0; i < possible; i++) 1343 set_cpu_possible(i, true); 1344 } 1345 1346 /* correctly size the local cpu masks */ 1347 void __init setup_cpu_local_masks(void) 1348 { 1349 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1350 } 1351 1352 #ifdef CONFIG_HOTPLUG_CPU 1353 1354 /* Recompute SMT state for all CPUs on offline */ 1355 static void recompute_smt_state(void) 1356 { 1357 int max_threads, cpu; 1358 1359 max_threads = 0; 1360 for_each_online_cpu (cpu) { 1361 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1362 1363 if (threads > max_threads) 1364 max_threads = threads; 1365 } 1366 __max_smt_threads = max_threads; 1367 } 1368 1369 static void remove_siblinginfo(int cpu) 1370 { 1371 int sibling; 1372 struct cpuinfo_x86 *c = &cpu_data(cpu); 1373 1374 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1375 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1376 /*/ 1377 * last thread sibling in this cpu core going down 1378 */ 1379 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1380 cpu_data(sibling).booted_cores--; 1381 } 1382 1383 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1384 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1385 1386 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1387 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1388 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1389 cpu_data(sibling).smt_active = false; 1390 } 1391 1392 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1393 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1394 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1395 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1396 cpumask_clear(cpu_llc_shared_mask(cpu)); 1397 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1398 cpumask_clear(topology_sibling_cpumask(cpu)); 1399 cpumask_clear(topology_core_cpumask(cpu)); 1400 cpumask_clear(topology_die_cpumask(cpu)); 1401 c->cpu_core_id = 0; 1402 c->booted_cores = 0; 1403 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1404 recompute_smt_state(); 1405 } 1406 1407 static void remove_cpu_from_maps(int cpu) 1408 { 1409 set_cpu_online(cpu, false); 1410 numa_remove_cpu(cpu); 1411 } 1412 1413 void cpu_disable_common(void) 1414 { 1415 int cpu = smp_processor_id(); 1416 1417 remove_siblinginfo(cpu); 1418 1419 /* It's now safe to remove this processor from the online map */ 1420 lock_vector_lock(); 1421 remove_cpu_from_maps(cpu); 1422 unlock_vector_lock(); 1423 fixup_irqs(); 1424 lapic_offline(); 1425 } 1426 1427 int native_cpu_disable(void) 1428 { 1429 int ret; 1430 1431 ret = lapic_can_unplug_cpu(); 1432 if (ret) 1433 return ret; 1434 1435 cpu_disable_common(); 1436 1437 /* 1438 * Disable the local APIC. Otherwise IPI broadcasts will reach 1439 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1440 * messages. 1441 * 1442 * Disabling the APIC must happen after cpu_disable_common() 1443 * which invokes fixup_irqs(). 1444 * 1445 * Disabling the APIC preserves already set bits in IRR, but 1446 * an interrupt arriving after disabling the local APIC does not 1447 * set the corresponding IRR bit. 1448 * 1449 * fixup_irqs() scans IRR for set bits so it can raise a not 1450 * yet handled interrupt on the new destination CPU via an IPI 1451 * but obviously it can't do so for IRR bits which are not set. 1452 * IOW, interrupts arriving after disabling the local APIC will 1453 * be lost. 1454 */ 1455 apic_soft_disable(); 1456 1457 return 0; 1458 } 1459 1460 void play_dead_common(void) 1461 { 1462 idle_task_exit(); 1463 1464 cpuhp_ap_report_dead(); 1465 1466 local_irq_disable(); 1467 } 1468 1469 /* 1470 * We need to flush the caches before going to sleep, lest we have 1471 * dirty data in our caches when we come back up. 1472 */ 1473 static inline void mwait_play_dead(void) 1474 { 1475 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1476 unsigned int eax, ebx, ecx, edx; 1477 unsigned int highest_cstate = 0; 1478 unsigned int highest_subcstate = 0; 1479 int i; 1480 1481 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1482 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1483 return; 1484 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1485 return; 1486 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1487 return; 1488 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1489 return; 1490 1491 eax = CPUID_MWAIT_LEAF; 1492 ecx = 0; 1493 native_cpuid(&eax, &ebx, &ecx, &edx); 1494 1495 /* 1496 * eax will be 0 if EDX enumeration is not valid. 1497 * Initialized below to cstate, sub_cstate value when EDX is valid. 1498 */ 1499 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1500 eax = 0; 1501 } else { 1502 edx >>= MWAIT_SUBSTATE_SIZE; 1503 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1504 if (edx & MWAIT_SUBSTATE_MASK) { 1505 highest_cstate = i; 1506 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1507 } 1508 } 1509 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1510 (highest_subcstate - 1); 1511 } 1512 1513 /* Set up state for the kexec() hack below */ 1514 md->status = CPUDEAD_MWAIT_WAIT; 1515 md->control = CPUDEAD_MWAIT_WAIT; 1516 1517 wbinvd(); 1518 1519 while (1) { 1520 /* 1521 * The CLFLUSH is a workaround for erratum AAI65 for 1522 * the Xeon 7400 series. It's not clear it is actually 1523 * needed, but it should be harmless in either case. 1524 * The WBINVD is insufficient due to the spurious-wakeup 1525 * case where we return around the loop. 1526 */ 1527 mb(); 1528 clflush(md); 1529 mb(); 1530 __monitor(md, 0, 0); 1531 mb(); 1532 __mwait(eax, 0); 1533 1534 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1535 /* 1536 * Kexec is about to happen. Don't go back into mwait() as 1537 * the kexec kernel might overwrite text and data including 1538 * page tables and stack. So mwait() would resume when the 1539 * monitor cache line is written to and then the CPU goes 1540 * south due to overwritten text, page tables and stack. 1541 * 1542 * Note: This does _NOT_ protect against a stray MCE, NMI, 1543 * SMI. They will resume execution at the instruction 1544 * following the HLT instruction and run into the problem 1545 * which this is trying to prevent. 1546 */ 1547 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1548 while(1) 1549 native_halt(); 1550 } 1551 } 1552 } 1553 1554 /* 1555 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1556 * mwait_play_dead(). 1557 */ 1558 void smp_kick_mwait_play_dead(void) 1559 { 1560 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1561 struct mwait_cpu_dead *md; 1562 unsigned int cpu, i; 1563 1564 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1565 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1566 1567 /* Does it sit in mwait_play_dead() ? */ 1568 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1569 continue; 1570 1571 /* Wait up to 5ms */ 1572 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1573 /* Bring it out of mwait */ 1574 WRITE_ONCE(md->control, newstate); 1575 udelay(5); 1576 } 1577 1578 if (READ_ONCE(md->status) != newstate) 1579 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1580 } 1581 } 1582 1583 void __noreturn hlt_play_dead(void) 1584 { 1585 if (__this_cpu_read(cpu_info.x86) >= 4) 1586 wbinvd(); 1587 1588 while (1) 1589 native_halt(); 1590 } 1591 1592 void native_play_dead(void) 1593 { 1594 play_dead_common(); 1595 tboot_shutdown(TB_SHUTDOWN_WFS); 1596 1597 mwait_play_dead(); 1598 if (cpuidle_play_dead()) 1599 hlt_play_dead(); 1600 } 1601 1602 #else /* ... !CONFIG_HOTPLUG_CPU */ 1603 int native_cpu_disable(void) 1604 { 1605 return -ENOSYS; 1606 } 1607 1608 void native_play_dead(void) 1609 { 1610 BUG(); 1611 } 1612 1613 #endif 1614