1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/io_apic.h> 68 #include <asm/setup.h> 69 #include <asm/uv/uv.h> 70 #include <linux/mc146818rtc.h> 71 72 #include <asm/smpboot_hooks.h> 73 #include <asm/i8259.h> 74 75 #ifdef CONFIG_X86_32 76 u8 apicid_2_node[MAX_APICID]; 77 #endif 78 79 /* State of each CPU */ 80 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 81 82 /* Store all idle threads, this can be reused instead of creating 83 * a new thread. Also avoids complicated thread destroy functionality 84 * for idle threads. 85 */ 86 #ifdef CONFIG_HOTPLUG_CPU 87 /* 88 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 89 * removed after init for !CONFIG_HOTPLUG_CPU. 90 */ 91 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 92 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 93 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 94 95 /* 96 * We need this for trampoline_base protection from concurrent accesses when 97 * off- and onlining cores wildly. 98 */ 99 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 100 101 void cpu_hotplug_driver_lock(void) 102 { 103 mutex_lock(&x86_cpu_hotplug_driver_mutex); 104 } 105 106 void cpu_hotplug_driver_unlock(void) 107 { 108 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 109 } 110 111 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 112 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 113 #else 114 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 115 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 116 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 117 #endif 118 119 /* Number of siblings per CPU package */ 120 int smp_num_siblings = 1; 121 EXPORT_SYMBOL(smp_num_siblings); 122 123 /* Last level cache ID of each logical CPU */ 124 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 125 126 /* representing HT siblings of each logical CPU */ 127 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 128 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 129 130 /* representing HT and core siblings of each logical CPU */ 131 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 132 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 133 134 /* Per CPU bogomips and other parameters */ 135 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 136 EXPORT_PER_CPU_SYMBOL(cpu_info); 137 138 atomic_t init_deasserted; 139 140 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 141 /* which node each logical CPU is on */ 142 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 143 EXPORT_SYMBOL(cpu_to_node_map); 144 145 /* set up a mapping between cpu and node. */ 146 static void map_cpu_to_node(int cpu, int node) 147 { 148 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 149 cpumask_set_cpu(cpu, node_to_cpumask_map[node]); 150 cpu_to_node_map[cpu] = node; 151 } 152 153 /* undo a mapping between cpu and node. */ 154 static void unmap_cpu_to_node(int cpu) 155 { 156 int node; 157 158 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 159 for (node = 0; node < MAX_NUMNODES; node++) 160 cpumask_clear_cpu(cpu, node_to_cpumask_map[node]); 161 cpu_to_node_map[cpu] = 0; 162 } 163 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 164 #define map_cpu_to_node(cpu, node) ({}) 165 #define unmap_cpu_to_node(cpu) ({}) 166 #endif 167 168 #ifdef CONFIG_X86_32 169 static int boot_cpu_logical_apicid; 170 171 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 172 { [0 ... NR_CPUS-1] = BAD_APICID }; 173 174 static void map_cpu_to_logical_apicid(void) 175 { 176 int cpu = smp_processor_id(); 177 int apicid = logical_smp_processor_id(); 178 int node = apic->apicid_to_node(apicid); 179 180 if (!node_online(node)) 181 node = first_online_node; 182 183 cpu_2_logical_apicid[cpu] = apicid; 184 map_cpu_to_node(cpu, node); 185 } 186 187 void numa_remove_cpu(int cpu) 188 { 189 cpu_2_logical_apicid[cpu] = BAD_APICID; 190 unmap_cpu_to_node(cpu); 191 } 192 #else 193 #define map_cpu_to_logical_apicid() do {} while (0) 194 #endif 195 196 /* 197 * Report back to the Boot Processor. 198 * Running on AP. 199 */ 200 static void __cpuinit smp_callin(void) 201 { 202 int cpuid, phys_id; 203 unsigned long timeout; 204 205 /* 206 * If waken up by an INIT in an 82489DX configuration 207 * we may get here before an INIT-deassert IPI reaches 208 * our local APIC. We have to wait for the IPI or we'll 209 * lock up on an APIC access. 210 */ 211 if (apic->wait_for_init_deassert) 212 apic->wait_for_init_deassert(&init_deasserted); 213 214 /* 215 * (This works even if the APIC is not enabled.) 216 */ 217 phys_id = read_apic_id(); 218 cpuid = smp_processor_id(); 219 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 220 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 221 phys_id, cpuid); 222 } 223 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 224 225 /* 226 * STARTUP IPIs are fragile beasts as they might sometimes 227 * trigger some glue motherboard logic. Complete APIC bus 228 * silence for 1 second, this overestimates the time the 229 * boot CPU is spending to send the up to 2 STARTUP IPIs 230 * by a factor of two. This should be enough. 231 */ 232 233 /* 234 * Waiting 2s total for startup (udelay is not yet working) 235 */ 236 timeout = jiffies + 2*HZ; 237 while (time_before(jiffies, timeout)) { 238 /* 239 * Has the boot CPU finished it's STARTUP sequence? 240 */ 241 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 242 break; 243 cpu_relax(); 244 } 245 246 if (!time_before(jiffies, timeout)) { 247 panic("%s: CPU%d started up but did not get a callout!\n", 248 __func__, cpuid); 249 } 250 251 /* 252 * the boot CPU has finished the init stage and is spinning 253 * on callin_map until we finish. We are free to set up this 254 * CPU, first the APIC. (this is probably redundant on most 255 * boards) 256 */ 257 258 pr_debug("CALLIN, before setup_local_APIC().\n"); 259 if (apic->smp_callin_clear_local_apic) 260 apic->smp_callin_clear_local_apic(); 261 setup_local_APIC(); 262 end_local_APIC_setup(); 263 map_cpu_to_logical_apicid(); 264 265 /* 266 * Need to setup vector mappings before we enable interrupts. 267 */ 268 setup_vector_irq(smp_processor_id()); 269 /* 270 * Get our bogomips. 271 * 272 * Need to enable IRQs because it can take longer and then 273 * the NMI watchdog might kill us. 274 */ 275 local_irq_enable(); 276 calibrate_delay(); 277 local_irq_disable(); 278 pr_debug("Stack at about %p\n", &cpuid); 279 280 /* 281 * Save our processor parameters 282 */ 283 smp_store_cpu_info(cpuid); 284 285 /* 286 * This must be done before setting cpu_online_mask 287 * or calling notify_cpu_starting. 288 */ 289 set_cpu_sibling_map(raw_smp_processor_id()); 290 wmb(); 291 292 notify_cpu_starting(cpuid); 293 294 /* 295 * Allow the master to continue. 296 */ 297 cpumask_set_cpu(cpuid, cpu_callin_mask); 298 } 299 300 /* 301 * Activate a secondary processor. 302 */ 303 notrace static void __cpuinit start_secondary(void *unused) 304 { 305 /* 306 * Don't put *anything* before cpu_init(), SMP booting is too 307 * fragile that we want to limit the things done here to the 308 * most necessary things. 309 */ 310 cpu_init(); 311 preempt_disable(); 312 smp_callin(); 313 314 #ifdef CONFIG_X86_32 315 /* switch away from the initial page table */ 316 load_cr3(swapper_pg_dir); 317 __flush_tlb_all(); 318 #endif 319 320 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 321 barrier(); 322 /* 323 * Check TSC synchronization with the BP: 324 */ 325 check_tsc_sync_target(); 326 327 /* 328 * We need to hold call_lock, so there is no inconsistency 329 * between the time smp_call_function() determines number of 330 * IPI recipients, and the time when the determination is made 331 * for which cpus receive the IPI. Holding this 332 * lock helps us to not include this cpu in a currently in progress 333 * smp_call_function(). 334 * 335 * We need to hold vector_lock so there the set of online cpus 336 * does not change while we are assigning vectors to cpus. Holding 337 * this lock ensures we don't half assign or remove an irq from a cpu. 338 */ 339 ipi_call_lock(); 340 lock_vector_lock(); 341 set_cpu_online(smp_processor_id(), true); 342 unlock_vector_lock(); 343 ipi_call_unlock(); 344 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 345 x86_platform.nmi_init(); 346 347 /* enable local interrupts */ 348 local_irq_enable(); 349 350 /* to prevent fake stack check failure in clock setup */ 351 boot_init_stack_canary(); 352 353 x86_cpuinit.setup_percpu_clockev(); 354 355 wmb(); 356 cpu_idle(); 357 } 358 359 #ifdef CONFIG_CPUMASK_OFFSTACK 360 /* In this case, llc_shared_map is a pointer to a cpumask. */ 361 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 362 const struct cpuinfo_x86 *src) 363 { 364 struct cpumask *llc = dst->llc_shared_map; 365 *dst = *src; 366 dst->llc_shared_map = llc; 367 } 368 #else 369 static inline void copy_cpuinfo_x86(struct cpuinfo_x86 *dst, 370 const struct cpuinfo_x86 *src) 371 { 372 *dst = *src; 373 } 374 #endif /* CONFIG_CPUMASK_OFFSTACK */ 375 376 /* 377 * The bootstrap kernel entry code has set these up. Save them for 378 * a given CPU 379 */ 380 381 void __cpuinit smp_store_cpu_info(int id) 382 { 383 struct cpuinfo_x86 *c = &cpu_data(id); 384 385 copy_cpuinfo_x86(c, &boot_cpu_data); 386 c->cpu_index = id; 387 if (id != 0) 388 identify_secondary_cpu(c); 389 } 390 391 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 392 { 393 struct cpuinfo_x86 *c1 = &cpu_data(cpu1); 394 struct cpuinfo_x86 *c2 = &cpu_data(cpu2); 395 396 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 397 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 398 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 399 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 400 cpumask_set_cpu(cpu1, c2->llc_shared_map); 401 cpumask_set_cpu(cpu2, c1->llc_shared_map); 402 } 403 404 405 void __cpuinit set_cpu_sibling_map(int cpu) 406 { 407 int i; 408 struct cpuinfo_x86 *c = &cpu_data(cpu); 409 410 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 411 412 if (smp_num_siblings > 1) { 413 for_each_cpu(i, cpu_sibling_setup_mask) { 414 struct cpuinfo_x86 *o = &cpu_data(i); 415 416 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 417 if (c->phys_proc_id == o->phys_proc_id && 418 c->compute_unit_id == o->compute_unit_id) 419 link_thread_siblings(cpu, i); 420 } else if (c->phys_proc_id == o->phys_proc_id && 421 c->cpu_core_id == o->cpu_core_id) { 422 link_thread_siblings(cpu, i); 423 } 424 } 425 } else { 426 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 427 } 428 429 cpumask_set_cpu(cpu, c->llc_shared_map); 430 431 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { 432 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 433 c->booted_cores = 1; 434 return; 435 } 436 437 for_each_cpu(i, cpu_sibling_setup_mask) { 438 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 439 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 440 cpumask_set_cpu(i, c->llc_shared_map); 441 cpumask_set_cpu(cpu, cpu_data(i).llc_shared_map); 442 } 443 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 444 cpumask_set_cpu(i, cpu_core_mask(cpu)); 445 cpumask_set_cpu(cpu, cpu_core_mask(i)); 446 /* 447 * Does this new cpu bringup a new core? 448 */ 449 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 450 /* 451 * for each core in package, increment 452 * the booted_cores for this new cpu 453 */ 454 if (cpumask_first(cpu_sibling_mask(i)) == i) 455 c->booted_cores++; 456 /* 457 * increment the core count for all 458 * the other cpus in this package 459 */ 460 if (i != cpu) 461 cpu_data(i).booted_cores++; 462 } else if (i != cpu && !c->booted_cores) 463 c->booted_cores = cpu_data(i).booted_cores; 464 } 465 } 466 } 467 468 /* maps the cpu to the sched domain representing multi-core */ 469 const struct cpumask *cpu_coregroup_mask(int cpu) 470 { 471 struct cpuinfo_x86 *c = &cpu_data(cpu); 472 /* 473 * For perf, we return last level cache shared map. 474 * And for power savings, we return cpu_core_map 475 */ 476 if ((sched_mc_power_savings || sched_smt_power_savings) && 477 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 478 return cpu_core_mask(cpu); 479 else 480 return c->llc_shared_map; 481 } 482 483 static void impress_friends(void) 484 { 485 int cpu; 486 unsigned long bogosum = 0; 487 /* 488 * Allow the user to impress friends. 489 */ 490 pr_debug("Before bogomips.\n"); 491 for_each_possible_cpu(cpu) 492 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 493 bogosum += cpu_data(cpu).loops_per_jiffy; 494 printk(KERN_INFO 495 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 496 num_online_cpus(), 497 bogosum/(500000/HZ), 498 (bogosum/(5000/HZ))%100); 499 500 pr_debug("Before bogocount - setting activated=1.\n"); 501 } 502 503 void __inquire_remote_apic(int apicid) 504 { 505 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 506 char *names[] = { "ID", "VERSION", "SPIV" }; 507 int timeout; 508 u32 status; 509 510 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 511 512 for (i = 0; i < ARRAY_SIZE(regs); i++) { 513 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 514 515 /* 516 * Wait for idle. 517 */ 518 status = safe_apic_wait_icr_idle(); 519 if (status) 520 printk(KERN_CONT 521 "a previous APIC delivery may have failed\n"); 522 523 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 524 525 timeout = 0; 526 do { 527 udelay(100); 528 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 529 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 530 531 switch (status) { 532 case APIC_ICR_RR_VALID: 533 status = apic_read(APIC_RRR); 534 printk(KERN_CONT "%08x\n", status); 535 break; 536 default: 537 printk(KERN_CONT "failed\n"); 538 } 539 } 540 } 541 542 /* 543 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 544 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 545 * won't ... remember to clear down the APIC, etc later. 546 */ 547 int __cpuinit 548 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 549 { 550 unsigned long send_status, accept_status = 0; 551 int maxlvt; 552 553 /* Target chip */ 554 /* Boot on the stack */ 555 /* Kick the second */ 556 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 557 558 pr_debug("Waiting for send to finish...\n"); 559 send_status = safe_apic_wait_icr_idle(); 560 561 /* 562 * Give the other CPU some time to accept the IPI. 563 */ 564 udelay(200); 565 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 566 maxlvt = lapic_get_maxlvt(); 567 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 568 apic_write(APIC_ESR, 0); 569 accept_status = (apic_read(APIC_ESR) & 0xEF); 570 } 571 pr_debug("NMI sent.\n"); 572 573 if (send_status) 574 printk(KERN_ERR "APIC never delivered???\n"); 575 if (accept_status) 576 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 577 578 return (send_status | accept_status); 579 } 580 581 static int __cpuinit 582 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 583 { 584 unsigned long send_status, accept_status = 0; 585 int maxlvt, num_starts, j; 586 587 maxlvt = lapic_get_maxlvt(); 588 589 /* 590 * Be paranoid about clearing APIC errors. 591 */ 592 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 593 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 594 apic_write(APIC_ESR, 0); 595 apic_read(APIC_ESR); 596 } 597 598 pr_debug("Asserting INIT.\n"); 599 600 /* 601 * Turn INIT on target chip 602 */ 603 /* 604 * Send IPI 605 */ 606 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 607 phys_apicid); 608 609 pr_debug("Waiting for send to finish...\n"); 610 send_status = safe_apic_wait_icr_idle(); 611 612 mdelay(10); 613 614 pr_debug("Deasserting INIT.\n"); 615 616 /* Target chip */ 617 /* Send IPI */ 618 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 619 620 pr_debug("Waiting for send to finish...\n"); 621 send_status = safe_apic_wait_icr_idle(); 622 623 mb(); 624 atomic_set(&init_deasserted, 1); 625 626 /* 627 * Should we send STARTUP IPIs ? 628 * 629 * Determine this based on the APIC version. 630 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 631 */ 632 if (APIC_INTEGRATED(apic_version[phys_apicid])) 633 num_starts = 2; 634 else 635 num_starts = 0; 636 637 /* 638 * Paravirt / VMI wants a startup IPI hook here to set up the 639 * target processor state. 640 */ 641 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 642 stack_start); 643 644 /* 645 * Run STARTUP IPI loop. 646 */ 647 pr_debug("#startup loops: %d.\n", num_starts); 648 649 for (j = 1; j <= num_starts; j++) { 650 pr_debug("Sending STARTUP #%d.\n", j); 651 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 652 apic_write(APIC_ESR, 0); 653 apic_read(APIC_ESR); 654 pr_debug("After apic_write.\n"); 655 656 /* 657 * STARTUP IPI 658 */ 659 660 /* Target chip */ 661 /* Boot on the stack */ 662 /* Kick the second */ 663 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 664 phys_apicid); 665 666 /* 667 * Give the other CPU some time to accept the IPI. 668 */ 669 udelay(300); 670 671 pr_debug("Startup point 1.\n"); 672 673 pr_debug("Waiting for send to finish...\n"); 674 send_status = safe_apic_wait_icr_idle(); 675 676 /* 677 * Give the other CPU some time to accept the IPI. 678 */ 679 udelay(200); 680 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 681 apic_write(APIC_ESR, 0); 682 accept_status = (apic_read(APIC_ESR) & 0xEF); 683 if (send_status || accept_status) 684 break; 685 } 686 pr_debug("After Startup.\n"); 687 688 if (send_status) 689 printk(KERN_ERR "APIC never delivered???\n"); 690 if (accept_status) 691 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 692 693 return (send_status | accept_status); 694 } 695 696 struct create_idle { 697 struct work_struct work; 698 struct task_struct *idle; 699 struct completion done; 700 int cpu; 701 }; 702 703 static void __cpuinit do_fork_idle(struct work_struct *work) 704 { 705 struct create_idle *c_idle = 706 container_of(work, struct create_idle, work); 707 708 c_idle->idle = fork_idle(c_idle->cpu); 709 complete(&c_idle->done); 710 } 711 712 /* reduce the number of lines printed when booting a large cpu count system */ 713 static void __cpuinit announce_cpu(int cpu, int apicid) 714 { 715 static int current_node = -1; 716 int node = early_cpu_to_node(cpu); 717 718 if (system_state == SYSTEM_BOOTING) { 719 if (node != current_node) { 720 if (current_node > (-1)) 721 pr_cont(" Ok.\n"); 722 current_node = node; 723 pr_info("Booting Node %3d, Processors ", node); 724 } 725 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 726 return; 727 } else 728 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 729 node, cpu, apicid); 730 } 731 732 /* 733 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 734 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 735 * Returns zero if CPU booted OK, else error code from 736 * ->wakeup_secondary_cpu. 737 */ 738 static int __cpuinit do_boot_cpu(int apicid, int cpu) 739 { 740 unsigned long boot_error = 0; 741 unsigned long start_ip; 742 int timeout; 743 struct create_idle c_idle = { 744 .cpu = cpu, 745 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 746 }; 747 748 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); 749 750 alternatives_smp_switch(1); 751 752 c_idle.idle = get_idle_for_cpu(cpu); 753 754 /* 755 * We can't use kernel_thread since we must avoid to 756 * reschedule the child. 757 */ 758 if (c_idle.idle) { 759 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 760 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 761 init_idle(c_idle.idle, cpu); 762 goto do_rest; 763 } 764 765 schedule_work(&c_idle.work); 766 wait_for_completion(&c_idle.done); 767 768 if (IS_ERR(c_idle.idle)) { 769 printk("failed fork for CPU %d\n", cpu); 770 destroy_work_on_stack(&c_idle.work); 771 return PTR_ERR(c_idle.idle); 772 } 773 774 set_idle_for_cpu(cpu, c_idle.idle); 775 do_rest: 776 per_cpu(current_task, cpu) = c_idle.idle; 777 #ifdef CONFIG_X86_32 778 /* Stack for startup_32 can be just as for start_secondary onwards */ 779 irq_ctx_init(cpu); 780 #else 781 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 782 initial_gs = per_cpu_offset(cpu); 783 per_cpu(kernel_stack, cpu) = 784 (unsigned long)task_stack_page(c_idle.idle) - 785 KERNEL_STACK_OFFSET + THREAD_SIZE; 786 #endif 787 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 788 initial_code = (unsigned long)start_secondary; 789 stack_start = c_idle.idle->thread.sp; 790 791 /* start_ip had better be page-aligned! */ 792 start_ip = setup_trampoline(); 793 794 /* So we see what's up */ 795 announce_cpu(cpu, apicid); 796 797 /* 798 * This grunge runs the startup process for 799 * the targeted processor. 800 */ 801 802 atomic_set(&init_deasserted, 0); 803 804 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 805 806 pr_debug("Setting warm reset code and vector.\n"); 807 808 smpboot_setup_warm_reset_vector(start_ip); 809 /* 810 * Be paranoid about clearing APIC errors. 811 */ 812 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 813 apic_write(APIC_ESR, 0); 814 apic_read(APIC_ESR); 815 } 816 } 817 818 /* 819 * Kick the secondary CPU. Use the method in the APIC driver 820 * if it's defined - or use an INIT boot APIC message otherwise: 821 */ 822 if (apic->wakeup_secondary_cpu) 823 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 824 else 825 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 826 827 if (!boot_error) { 828 /* 829 * allow APs to start initializing. 830 */ 831 pr_debug("Before Callout %d.\n", cpu); 832 cpumask_set_cpu(cpu, cpu_callout_mask); 833 pr_debug("After Callout %d.\n", cpu); 834 835 /* 836 * Wait 5s total for a response 837 */ 838 for (timeout = 0; timeout < 50000; timeout++) { 839 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 840 break; /* It has booted */ 841 udelay(100); 842 /* 843 * Allow other tasks to run while we wait for the 844 * AP to come online. This also gives a chance 845 * for the MTRR work(triggered by the AP coming online) 846 * to be completed in the stop machine context. 847 */ 848 schedule(); 849 } 850 851 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 852 pr_debug("CPU%d: has booted.\n", cpu); 853 else { 854 boot_error = 1; 855 if (*((volatile unsigned char *)trampoline_base) 856 == 0xA5) 857 /* trampoline started but...? */ 858 pr_err("CPU%d: Stuck ??\n", cpu); 859 else 860 /* trampoline code not run */ 861 pr_err("CPU%d: Not responding.\n", cpu); 862 if (apic->inquire_remote_apic) 863 apic->inquire_remote_apic(apicid); 864 } 865 } 866 867 if (boot_error) { 868 /* Try to put things back the way they were before ... */ 869 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 870 871 /* was set by do_boot_cpu() */ 872 cpumask_clear_cpu(cpu, cpu_callout_mask); 873 874 /* was set by cpu_init() */ 875 cpumask_clear_cpu(cpu, cpu_initialized_mask); 876 877 set_cpu_present(cpu, false); 878 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 879 } 880 881 /* mark "stuck" area as not stuck */ 882 *((volatile unsigned long *)trampoline_base) = 0; 883 884 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 885 /* 886 * Cleanup possible dangling ends... 887 */ 888 smpboot_restore_warm_reset_vector(); 889 } 890 891 destroy_work_on_stack(&c_idle.work); 892 return boot_error; 893 } 894 895 int __cpuinit native_cpu_up(unsigned int cpu) 896 { 897 int apicid = apic->cpu_present_to_apicid(cpu); 898 unsigned long flags; 899 int err; 900 901 WARN_ON(irqs_disabled()); 902 903 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 904 905 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 906 !physid_isset(apicid, phys_cpu_present_map)) { 907 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 908 return -EINVAL; 909 } 910 911 /* 912 * Already booted CPU? 913 */ 914 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 915 pr_debug("do_boot_cpu %d Already started\n", cpu); 916 return -ENOSYS; 917 } 918 919 /* 920 * Save current MTRR state in case it was changed since early boot 921 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 922 */ 923 mtrr_save_state(); 924 925 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 926 927 err = do_boot_cpu(apicid, cpu); 928 if (err) { 929 pr_debug("do_boot_cpu failed %d\n", err); 930 return -EIO; 931 } 932 933 /* 934 * Check TSC synchronization with the AP (keep irqs disabled 935 * while doing so): 936 */ 937 local_irq_save(flags); 938 check_tsc_sync_source(cpu); 939 local_irq_restore(flags); 940 941 while (!cpu_online(cpu)) { 942 cpu_relax(); 943 touch_nmi_watchdog(); 944 } 945 946 return 0; 947 } 948 949 /** 950 * arch_disable_smp_support() - disables SMP support for x86 at runtime 951 */ 952 void arch_disable_smp_support(void) 953 { 954 disable_ioapic_support(); 955 } 956 957 /* 958 * Fall back to non SMP mode after errors. 959 * 960 * RED-PEN audit/test this more. I bet there is more state messed up here. 961 */ 962 static __init void disable_smp(void) 963 { 964 init_cpu_present(cpumask_of(0)); 965 init_cpu_possible(cpumask_of(0)); 966 smpboot_clear_io_apic_irqs(); 967 968 if (smp_found_config) 969 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 970 else 971 physid_set_mask_of_physid(0, &phys_cpu_present_map); 972 map_cpu_to_logical_apicid(); 973 cpumask_set_cpu(0, cpu_sibling_mask(0)); 974 cpumask_set_cpu(0, cpu_core_mask(0)); 975 } 976 977 /* 978 * Various sanity checks. 979 */ 980 static int __init smp_sanity_check(unsigned max_cpus) 981 { 982 preempt_disable(); 983 984 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 985 if (def_to_bigsmp && nr_cpu_ids > 8) { 986 unsigned int cpu; 987 unsigned nr; 988 989 printk(KERN_WARNING 990 "More than 8 CPUs detected - skipping them.\n" 991 "Use CONFIG_X86_BIGSMP.\n"); 992 993 nr = 0; 994 for_each_present_cpu(cpu) { 995 if (nr >= 8) 996 set_cpu_present(cpu, false); 997 nr++; 998 } 999 1000 nr = 0; 1001 for_each_possible_cpu(cpu) { 1002 if (nr >= 8) 1003 set_cpu_possible(cpu, false); 1004 nr++; 1005 } 1006 1007 nr_cpu_ids = 8; 1008 } 1009 #endif 1010 1011 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1012 printk(KERN_WARNING 1013 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1014 hard_smp_processor_id()); 1015 1016 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1017 } 1018 1019 /* 1020 * If we couldn't find an SMP configuration at boot time, 1021 * get out of here now! 1022 */ 1023 if (!smp_found_config && !acpi_lapic) { 1024 preempt_enable(); 1025 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1026 disable_smp(); 1027 if (APIC_init_uniprocessor()) 1028 printk(KERN_NOTICE "Local APIC not detected." 1029 " Using dummy APIC emulation.\n"); 1030 return -1; 1031 } 1032 1033 /* 1034 * Should not be necessary because the MP table should list the boot 1035 * CPU too, but we do it for the sake of robustness anyway. 1036 */ 1037 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1038 printk(KERN_NOTICE 1039 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1040 boot_cpu_physical_apicid); 1041 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1042 } 1043 preempt_enable(); 1044 1045 /* 1046 * If we couldn't find a local APIC, then get out of here now! 1047 */ 1048 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1049 !cpu_has_apic) { 1050 if (!disable_apic) { 1051 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1052 boot_cpu_physical_apicid); 1053 pr_err("... forcing use of dummy APIC emulation." 1054 "(tell your hw vendor)\n"); 1055 } 1056 smpboot_clear_io_apic(); 1057 disable_ioapic_support(); 1058 return -1; 1059 } 1060 1061 verify_local_APIC(); 1062 1063 /* 1064 * If SMP should be disabled, then really disable it! 1065 */ 1066 if (!max_cpus) { 1067 printk(KERN_INFO "SMP mode deactivated.\n"); 1068 smpboot_clear_io_apic(); 1069 1070 connect_bsp_APIC(); 1071 setup_local_APIC(); 1072 bsp_end_local_APIC_setup(); 1073 return -1; 1074 } 1075 1076 return 0; 1077 } 1078 1079 static void __init smp_cpu_index_default(void) 1080 { 1081 int i; 1082 struct cpuinfo_x86 *c; 1083 1084 for_each_possible_cpu(i) { 1085 c = &cpu_data(i); 1086 /* mark all to hotplug */ 1087 c->cpu_index = nr_cpu_ids; 1088 } 1089 } 1090 1091 /* 1092 * Prepare for SMP bootup. The MP table or ACPI has been read 1093 * earlier. Just do some sanity checking here and enable APIC mode. 1094 */ 1095 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1096 { 1097 unsigned int i; 1098 1099 preempt_disable(); 1100 smp_cpu_index_default(); 1101 memcpy(__this_cpu_ptr(&cpu_info), &boot_cpu_data, sizeof(cpu_info)); 1102 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1103 mb(); 1104 /* 1105 * Setup boot CPU information 1106 */ 1107 smp_store_cpu_info(0); /* Final full version of the data */ 1108 #ifdef CONFIG_X86_32 1109 boot_cpu_logical_apicid = logical_smp_processor_id(); 1110 #endif 1111 current_thread_info()->cpu = 0; /* needed? */ 1112 for_each_possible_cpu(i) { 1113 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1114 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1115 zalloc_cpumask_var(&cpu_data(i).llc_shared_map, GFP_KERNEL); 1116 } 1117 set_cpu_sibling_map(0); 1118 1119 1120 if (smp_sanity_check(max_cpus) < 0) { 1121 printk(KERN_INFO "SMP disabled\n"); 1122 disable_smp(); 1123 goto out; 1124 } 1125 1126 default_setup_apic_routing(); 1127 1128 preempt_disable(); 1129 if (read_apic_id() != boot_cpu_physical_apicid) { 1130 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1131 read_apic_id(), boot_cpu_physical_apicid); 1132 /* Or can we switch back to PIC here? */ 1133 } 1134 preempt_enable(); 1135 1136 connect_bsp_APIC(); 1137 1138 /* 1139 * Switch from PIC to APIC mode. 1140 */ 1141 setup_local_APIC(); 1142 1143 /* 1144 * Enable IO APIC before setting up error vector 1145 */ 1146 if (!skip_ioapic_setup && nr_ioapics) 1147 enable_IO_APIC(); 1148 1149 bsp_end_local_APIC_setup(); 1150 1151 map_cpu_to_logical_apicid(); 1152 1153 if (apic->setup_portio_remap) 1154 apic->setup_portio_remap(); 1155 1156 smpboot_setup_io_apic(); 1157 /* 1158 * Set up local APIC timer on boot CPU. 1159 */ 1160 1161 printk(KERN_INFO "CPU%d: ", 0); 1162 print_cpu_info(&cpu_data(0)); 1163 x86_init.timers.setup_percpu_clockev(); 1164 1165 if (is_uv_system()) 1166 uv_system_init(); 1167 1168 set_mtrr_aps_delayed_init(); 1169 out: 1170 preempt_enable(); 1171 } 1172 1173 void arch_disable_nonboot_cpus_begin(void) 1174 { 1175 /* 1176 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1177 * In the suspend path, we will be back in the SMP mode shortly anyways. 1178 */ 1179 skip_smp_alternatives = true; 1180 } 1181 1182 void arch_disable_nonboot_cpus_end(void) 1183 { 1184 skip_smp_alternatives = false; 1185 } 1186 1187 void arch_enable_nonboot_cpus_begin(void) 1188 { 1189 set_mtrr_aps_delayed_init(); 1190 } 1191 1192 void arch_enable_nonboot_cpus_end(void) 1193 { 1194 mtrr_aps_init(); 1195 } 1196 1197 /* 1198 * Early setup to make printk work. 1199 */ 1200 void __init native_smp_prepare_boot_cpu(void) 1201 { 1202 int me = smp_processor_id(); 1203 switch_to_new_gdt(me); 1204 /* already set me in cpu_online_mask in boot_cpu_init() */ 1205 cpumask_set_cpu(me, cpu_callout_mask); 1206 per_cpu(cpu_state, me) = CPU_ONLINE; 1207 } 1208 1209 void __init native_smp_cpus_done(unsigned int max_cpus) 1210 { 1211 pr_debug("Boot done.\n"); 1212 1213 impress_friends(); 1214 #ifdef CONFIG_X86_IO_APIC 1215 setup_ioapic_dest(); 1216 #endif 1217 mtrr_aps_init(); 1218 } 1219 1220 static int __initdata setup_possible_cpus = -1; 1221 static int __init _setup_possible_cpus(char *str) 1222 { 1223 get_option(&str, &setup_possible_cpus); 1224 return 0; 1225 } 1226 early_param("possible_cpus", _setup_possible_cpus); 1227 1228 1229 /* 1230 * cpu_possible_mask should be static, it cannot change as cpu's 1231 * are onlined, or offlined. The reason is per-cpu data-structures 1232 * are allocated by some modules at init time, and dont expect to 1233 * do this dynamically on cpu arrival/departure. 1234 * cpu_present_mask on the other hand can change dynamically. 1235 * In case when cpu_hotplug is not compiled, then we resort to current 1236 * behaviour, which is cpu_possible == cpu_present. 1237 * - Ashok Raj 1238 * 1239 * Three ways to find out the number of additional hotplug CPUs: 1240 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1241 * - The user can overwrite it with possible_cpus=NUM 1242 * - Otherwise don't reserve additional CPUs. 1243 * We do this because additional CPUs waste a lot of memory. 1244 * -AK 1245 */ 1246 __init void prefill_possible_map(void) 1247 { 1248 int i, possible; 1249 1250 /* no processor from mptable or madt */ 1251 if (!num_processors) 1252 num_processors = 1; 1253 1254 i = setup_max_cpus ?: 1; 1255 if (setup_possible_cpus == -1) { 1256 possible = num_processors; 1257 #ifdef CONFIG_HOTPLUG_CPU 1258 if (setup_max_cpus) 1259 possible += disabled_cpus; 1260 #else 1261 if (possible > i) 1262 possible = i; 1263 #endif 1264 } else 1265 possible = setup_possible_cpus; 1266 1267 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1268 1269 /* nr_cpu_ids could be reduced via nr_cpus= */ 1270 if (possible > nr_cpu_ids) { 1271 printk(KERN_WARNING 1272 "%d Processors exceeds NR_CPUS limit of %d\n", 1273 possible, nr_cpu_ids); 1274 possible = nr_cpu_ids; 1275 } 1276 1277 #ifdef CONFIG_HOTPLUG_CPU 1278 if (!setup_max_cpus) 1279 #endif 1280 if (possible > i) { 1281 printk(KERN_WARNING 1282 "%d Processors exceeds max_cpus limit of %u\n", 1283 possible, setup_max_cpus); 1284 possible = i; 1285 } 1286 1287 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1288 possible, max_t(int, possible - num_processors, 0)); 1289 1290 for (i = 0; i < possible; i++) 1291 set_cpu_possible(i, true); 1292 for (; i < NR_CPUS; i++) 1293 set_cpu_possible(i, false); 1294 1295 nr_cpu_ids = possible; 1296 } 1297 1298 #ifdef CONFIG_HOTPLUG_CPU 1299 1300 static void remove_siblinginfo(int cpu) 1301 { 1302 int sibling; 1303 struct cpuinfo_x86 *c = &cpu_data(cpu); 1304 1305 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1306 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1307 /*/ 1308 * last thread sibling in this cpu core going down 1309 */ 1310 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1311 cpu_data(sibling).booted_cores--; 1312 } 1313 1314 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1315 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1316 cpumask_clear(cpu_sibling_mask(cpu)); 1317 cpumask_clear(cpu_core_mask(cpu)); 1318 c->phys_proc_id = 0; 1319 c->cpu_core_id = 0; 1320 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1321 } 1322 1323 static void __ref remove_cpu_from_maps(int cpu) 1324 { 1325 set_cpu_online(cpu, false); 1326 cpumask_clear_cpu(cpu, cpu_callout_mask); 1327 cpumask_clear_cpu(cpu, cpu_callin_mask); 1328 /* was set by cpu_init() */ 1329 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1330 numa_remove_cpu(cpu); 1331 } 1332 1333 void cpu_disable_common(void) 1334 { 1335 int cpu = smp_processor_id(); 1336 1337 remove_siblinginfo(cpu); 1338 1339 /* It's now safe to remove this processor from the online map */ 1340 lock_vector_lock(); 1341 remove_cpu_from_maps(cpu); 1342 unlock_vector_lock(); 1343 fixup_irqs(); 1344 } 1345 1346 int native_cpu_disable(void) 1347 { 1348 int cpu = smp_processor_id(); 1349 1350 /* 1351 * Perhaps use cpufreq to drop frequency, but that could go 1352 * into generic code. 1353 * 1354 * We won't take down the boot processor on i386 due to some 1355 * interrupts only being able to be serviced by the BSP. 1356 * Especially so if we're not using an IOAPIC -zwane 1357 */ 1358 if (cpu == 0) 1359 return -EBUSY; 1360 1361 clear_local_APIC(); 1362 1363 cpu_disable_common(); 1364 return 0; 1365 } 1366 1367 void native_cpu_die(unsigned int cpu) 1368 { 1369 /* We don't do anything here: idle task is faking death itself. */ 1370 unsigned int i; 1371 1372 for (i = 0; i < 10; i++) { 1373 /* They ack this in play_dead by setting CPU_DEAD */ 1374 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1375 if (system_state == SYSTEM_RUNNING) 1376 pr_info("CPU %u is now offline\n", cpu); 1377 1378 if (1 == num_online_cpus()) 1379 alternatives_smp_switch(0); 1380 return; 1381 } 1382 msleep(100); 1383 } 1384 pr_err("CPU %u didn't die...\n", cpu); 1385 } 1386 1387 void play_dead_common(void) 1388 { 1389 idle_task_exit(); 1390 reset_lazy_tlbstate(); 1391 c1e_remove_cpu(raw_smp_processor_id()); 1392 1393 mb(); 1394 /* Ack it */ 1395 __this_cpu_write(cpu_state, CPU_DEAD); 1396 1397 /* 1398 * With physical CPU hotplug, we should halt the cpu 1399 */ 1400 local_irq_disable(); 1401 } 1402 1403 /* 1404 * We need to flush the caches before going to sleep, lest we have 1405 * dirty data in our caches when we come back up. 1406 */ 1407 static inline void mwait_play_dead(void) 1408 { 1409 unsigned int eax, ebx, ecx, edx; 1410 unsigned int highest_cstate = 0; 1411 unsigned int highest_subcstate = 0; 1412 int i; 1413 void *mwait_ptr; 1414 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1415 1416 if (!(cpu_has(c, X86_FEATURE_MWAIT) && mwait_usable(c))) 1417 return; 1418 if (!cpu_has(__this_cpu_ptr(&cpu_info), X86_FEATURE_CLFLSH)) 1419 return; 1420 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1421 return; 1422 1423 eax = CPUID_MWAIT_LEAF; 1424 ecx = 0; 1425 native_cpuid(&eax, &ebx, &ecx, &edx); 1426 1427 /* 1428 * eax will be 0 if EDX enumeration is not valid. 1429 * Initialized below to cstate, sub_cstate value when EDX is valid. 1430 */ 1431 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1432 eax = 0; 1433 } else { 1434 edx >>= MWAIT_SUBSTATE_SIZE; 1435 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1436 if (edx & MWAIT_SUBSTATE_MASK) { 1437 highest_cstate = i; 1438 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1439 } 1440 } 1441 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1442 (highest_subcstate - 1); 1443 } 1444 1445 /* 1446 * This should be a memory location in a cache line which is 1447 * unlikely to be touched by other processors. The actual 1448 * content is immaterial as it is not actually modified in any way. 1449 */ 1450 mwait_ptr = ¤t_thread_info()->flags; 1451 1452 wbinvd(); 1453 1454 while (1) { 1455 /* 1456 * The CLFLUSH is a workaround for erratum AAI65 for 1457 * the Xeon 7400 series. It's not clear it is actually 1458 * needed, but it should be harmless in either case. 1459 * The WBINVD is insufficient due to the spurious-wakeup 1460 * case where we return around the loop. 1461 */ 1462 clflush(mwait_ptr); 1463 __monitor(mwait_ptr, 0, 0); 1464 mb(); 1465 __mwait(eax, 0); 1466 } 1467 } 1468 1469 static inline void hlt_play_dead(void) 1470 { 1471 if (__this_cpu_read(cpu_info.x86) >= 4) 1472 wbinvd(); 1473 1474 while (1) { 1475 native_halt(); 1476 } 1477 } 1478 1479 void native_play_dead(void) 1480 { 1481 play_dead_common(); 1482 tboot_shutdown(TB_SHUTDOWN_WFS); 1483 1484 mwait_play_dead(); /* Only returns on failure */ 1485 hlt_play_dead(); 1486 } 1487 1488 #else /* ... !CONFIG_HOTPLUG_CPU */ 1489 int native_cpu_disable(void) 1490 { 1491 return -ENOSYS; 1492 } 1493 1494 void native_cpu_die(unsigned int cpu) 1495 { 1496 /* We said "no" in __cpu_disable */ 1497 BUG(); 1498 } 1499 1500 void native_play_dead(void) 1501 { 1502 BUG(); 1503 } 1504 1505 #endif 1506