1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 /* representing HT, core, and die siblings of each logical CPU */ 100 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 101 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 102 103 /* Per CPU bogomips and other parameters */ 104 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 105 EXPORT_PER_CPU_SYMBOL(cpu_info); 106 107 /* CPUs which are the primary SMT threads */ 108 struct cpumask __cpu_primary_thread_mask __read_mostly; 109 110 /* Representing CPUs for which sibling maps can be computed */ 111 static cpumask_var_t cpu_sibling_setup_mask; 112 113 struct mwait_cpu_dead { 114 unsigned int control; 115 unsigned int status; 116 }; 117 118 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 119 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 120 121 /* 122 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 123 * that it's unlikely to be touched by other CPUs. 124 */ 125 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 126 127 /* Logical package management. We might want to allocate that dynamically */ 128 unsigned int __max_logical_packages __read_mostly; 129 EXPORT_SYMBOL(__max_logical_packages); 130 static unsigned int logical_packages __read_mostly; 131 static unsigned int logical_die __read_mostly; 132 133 /* Maximum number of SMT threads on any online core */ 134 int __read_mostly __max_smt_threads = 1; 135 136 /* Flag to indicate if a complete sched domain rebuild is required */ 137 bool x86_topology_update; 138 139 int arch_update_cpu_topology(void) 140 { 141 int retval = x86_topology_update; 142 143 x86_topology_update = false; 144 return retval; 145 } 146 147 static unsigned int smpboot_warm_reset_vector_count; 148 149 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&rtc_lock, flags); 154 if (!smpboot_warm_reset_vector_count++) { 155 CMOS_WRITE(0xa, 0xf); 156 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 157 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 158 } 159 spin_unlock_irqrestore(&rtc_lock, flags); 160 } 161 162 static inline void smpboot_restore_warm_reset_vector(void) 163 { 164 unsigned long flags; 165 166 /* 167 * Paranoid: Set warm reset code and vector here back 168 * to default values. 169 */ 170 spin_lock_irqsave(&rtc_lock, flags); 171 if (!--smpboot_warm_reset_vector_count) { 172 CMOS_WRITE(0, 0xf); 173 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 174 } 175 spin_unlock_irqrestore(&rtc_lock, flags); 176 177 } 178 179 /* Run the next set of setup steps for the upcoming CPU */ 180 static void ap_starting(void) 181 { 182 int cpuid = smp_processor_id(); 183 184 /* Mop up eventual mwait_play_dead() wreckage */ 185 this_cpu_write(mwait_cpu_dead.status, 0); 186 this_cpu_write(mwait_cpu_dead.control, 0); 187 188 /* 189 * If woken up by an INIT in an 82489DX configuration the alive 190 * synchronization guarantees that the CPU does not reach this 191 * point before an INIT_deassert IPI reaches the local APIC, so it 192 * is now safe to touch the local APIC. 193 * 194 * Set up this CPU, first the APIC, which is probably redundant on 195 * most boards. 196 */ 197 apic_ap_setup(); 198 199 /* Save the processor parameters. */ 200 smp_store_cpu_info(cpuid); 201 202 /* 203 * The topology information must be up to date before 204 * notify_cpu_starting(). 205 */ 206 set_cpu_sibling_map(cpuid); 207 208 ap_init_aperfmperf(); 209 210 pr_debug("Stack at about %p\n", &cpuid); 211 212 wmb(); 213 214 /* 215 * This runs the AP through all the cpuhp states to its target 216 * state CPUHP_ONLINE. 217 */ 218 notify_cpu_starting(cpuid); 219 } 220 221 static void ap_calibrate_delay(void) 222 { 223 /* 224 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 225 * smp_store_cpu_info() stored a value that is close but not as 226 * accurate as the value just calculated. 227 * 228 * As this is invoked after the TSC synchronization check, 229 * calibrate_delay_is_known() will skip the calibration routine 230 * when TSC is synchronized across sockets. 231 */ 232 calibrate_delay(); 233 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 234 } 235 236 /* 237 * Activate a secondary processor. 238 */ 239 static void notrace start_secondary(void *unused) 240 { 241 /* 242 * Don't put *anything* except direct CPU state initialization 243 * before cpu_init(), SMP booting is too fragile that we want to 244 * limit the things done here to the most necessary things. 245 */ 246 cr4_init(); 247 248 /* 249 * 32-bit specific. 64-bit reaches this code with the correct page 250 * table established. Yet another historical divergence. 251 */ 252 if (IS_ENABLED(CONFIG_X86_32)) { 253 /* switch away from the initial page table */ 254 load_cr3(swapper_pg_dir); 255 __flush_tlb_all(); 256 } 257 258 cpu_init_exception_handling(); 259 260 /* 261 * 32-bit systems load the microcode from the ASM startup code for 262 * historical reasons. 263 * 264 * On 64-bit systems load it before reaching the AP alive 265 * synchronization point below so it is not part of the full per 266 * CPU serialized bringup part when "parallel" bringup is enabled. 267 * 268 * That's even safe when hyperthreading is enabled in the CPU as 269 * the core code starts the primary threads first and leaves the 270 * secondary threads waiting for SIPI. Loading microcode on 271 * physical cores concurrently is a safe operation. 272 * 273 * This covers both the Intel specific issue that concurrent 274 * microcode loading on SMT siblings must be prohibited and the 275 * vendor independent issue`that microcode loading which changes 276 * CPUID, MSRs etc. must be strictly serialized to maintain 277 * software state correctness. 278 */ 279 if (IS_ENABLED(CONFIG_X86_64)) 280 load_ucode_ap(); 281 282 /* 283 * Synchronization point with the hotplug core. Sets this CPUs 284 * synchronization state to ALIVE and spin-waits for the control CPU to 285 * release this CPU for further bringup. 286 */ 287 cpuhp_ap_sync_alive(); 288 289 cpu_init(); 290 fpu__init_cpu(); 291 rcu_cpu_starting(raw_smp_processor_id()); 292 x86_cpuinit.early_percpu_clock_init(); 293 294 ap_starting(); 295 296 /* Check TSC synchronization with the control CPU. */ 297 check_tsc_sync_target(); 298 299 /* 300 * Calibrate the delay loop after the TSC synchronization check. 301 * This allows to skip the calibration when TSC is synchronized 302 * across sockets. 303 */ 304 ap_calibrate_delay(); 305 306 speculative_store_bypass_ht_init(); 307 308 /* 309 * Lock vector_lock, set CPU online and bring the vector 310 * allocator online. Online must be set with vector_lock held 311 * to prevent a concurrent irq setup/teardown from seeing a 312 * half valid vector space. 313 */ 314 lock_vector_lock(); 315 set_cpu_online(smp_processor_id(), true); 316 lapic_online(); 317 unlock_vector_lock(); 318 x86_platform.nmi_init(); 319 320 /* enable local interrupts */ 321 local_irq_enable(); 322 323 x86_cpuinit.setup_percpu_clockev(); 324 325 wmb(); 326 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 327 } 328 329 /** 330 * topology_phys_to_logical_pkg - Map a physical package id to a logical 331 * @phys_pkg: The physical package id to map 332 * 333 * Returns logical package id or -1 if not found 334 */ 335 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 336 { 337 int cpu; 338 339 for_each_possible_cpu(cpu) { 340 struct cpuinfo_x86 *c = &cpu_data(cpu); 341 342 if (c->initialized && c->phys_proc_id == phys_pkg) 343 return c->logical_proc_id; 344 } 345 return -1; 346 } 347 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 348 349 /** 350 * topology_phys_to_logical_die - Map a physical die id to logical 351 * @die_id: The physical die id to map 352 * @cur_cpu: The CPU for which the mapping is done 353 * 354 * Returns logical die id or -1 if not found 355 */ 356 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 357 { 358 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 359 360 for_each_possible_cpu(cpu) { 361 struct cpuinfo_x86 *c = &cpu_data(cpu); 362 363 if (c->initialized && c->cpu_die_id == die_id && 364 c->phys_proc_id == proc_id) 365 return c->logical_die_id; 366 } 367 return -1; 368 } 369 370 /** 371 * topology_update_package_map - Update the physical to logical package map 372 * @pkg: The physical package id as retrieved via CPUID 373 * @cpu: The cpu for which this is updated 374 */ 375 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 376 { 377 int new; 378 379 /* Already available somewhere? */ 380 new = topology_phys_to_logical_pkg(pkg); 381 if (new >= 0) 382 goto found; 383 384 new = logical_packages++; 385 if (new != pkg) { 386 pr_info("CPU %u Converting physical %u to logical package %u\n", 387 cpu, pkg, new); 388 } 389 found: 390 cpu_data(cpu).logical_proc_id = new; 391 return 0; 392 } 393 /** 394 * topology_update_die_map - Update the physical to logical die map 395 * @die: The die id as retrieved via CPUID 396 * @cpu: The cpu for which this is updated 397 */ 398 int topology_update_die_map(unsigned int die, unsigned int cpu) 399 { 400 int new; 401 402 /* Already available somewhere? */ 403 new = topology_phys_to_logical_die(die, cpu); 404 if (new >= 0) 405 goto found; 406 407 new = logical_die++; 408 if (new != die) { 409 pr_info("CPU %u Converting physical %u to logical die %u\n", 410 cpu, die, new); 411 } 412 found: 413 cpu_data(cpu).logical_die_id = new; 414 return 0; 415 } 416 417 void __init smp_store_boot_cpu_info(void) 418 { 419 int id = 0; /* CPU 0 */ 420 struct cpuinfo_x86 *c = &cpu_data(id); 421 422 *c = boot_cpu_data; 423 c->cpu_index = id; 424 topology_update_package_map(c->phys_proc_id, id); 425 topology_update_die_map(c->cpu_die_id, id); 426 c->initialized = true; 427 } 428 429 /* 430 * The bootstrap kernel entry code has set these up. Save them for 431 * a given CPU 432 */ 433 void smp_store_cpu_info(int id) 434 { 435 struct cpuinfo_x86 *c = &cpu_data(id); 436 437 /* Copy boot_cpu_data only on the first bringup */ 438 if (!c->initialized) 439 *c = boot_cpu_data; 440 c->cpu_index = id; 441 /* 442 * During boot time, CPU0 has this setup already. Save the info when 443 * bringing up an AP. 444 */ 445 identify_secondary_cpu(c); 446 c->initialized = true; 447 } 448 449 static bool 450 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 451 { 452 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 453 454 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 455 } 456 457 static bool 458 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 459 { 460 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 461 462 return !WARN_ONCE(!topology_same_node(c, o), 463 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 464 "[node: %d != %d]. Ignoring dependency.\n", 465 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 466 } 467 468 #define link_mask(mfunc, c1, c2) \ 469 do { \ 470 cpumask_set_cpu((c1), mfunc(c2)); \ 471 cpumask_set_cpu((c2), mfunc(c1)); \ 472 } while (0) 473 474 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 475 { 476 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 477 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 478 479 if (c->phys_proc_id == o->phys_proc_id && 480 c->cpu_die_id == o->cpu_die_id && 481 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 482 if (c->cpu_core_id == o->cpu_core_id) 483 return topology_sane(c, o, "smt"); 484 485 if ((c->cu_id != 0xff) && 486 (o->cu_id != 0xff) && 487 (c->cu_id == o->cu_id)) 488 return topology_sane(c, o, "smt"); 489 } 490 491 } else if (c->phys_proc_id == o->phys_proc_id && 492 c->cpu_die_id == o->cpu_die_id && 493 c->cpu_core_id == o->cpu_core_id) { 494 return topology_sane(c, o, "smt"); 495 } 496 497 return false; 498 } 499 500 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 501 { 502 if (c->phys_proc_id == o->phys_proc_id && 503 c->cpu_die_id == o->cpu_die_id) 504 return true; 505 return false; 506 } 507 508 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 509 { 510 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 511 512 /* If the arch didn't set up l2c_id, fall back to SMT */ 513 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 514 return match_smt(c, o); 515 516 /* Do not match if L2 cache id does not match: */ 517 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 518 return false; 519 520 return topology_sane(c, o, "l2c"); 521 } 522 523 /* 524 * Unlike the other levels, we do not enforce keeping a 525 * multicore group inside a NUMA node. If this happens, we will 526 * discard the MC level of the topology later. 527 */ 528 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 529 { 530 if (c->phys_proc_id == o->phys_proc_id) 531 return true; 532 return false; 533 } 534 535 /* 536 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 537 * 538 * Any Intel CPU that has multiple nodes per package and does not 539 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 540 * 541 * When in SNC mode, these CPUs enumerate an LLC that is shared 542 * by multiple NUMA nodes. The LLC is shared for off-package data 543 * access but private to the NUMA node (half of the package) for 544 * on-package access. CPUID (the source of the information about 545 * the LLC) can only enumerate the cache as shared or unshared, 546 * but not this particular configuration. 547 */ 548 549 static const struct x86_cpu_id intel_cod_cpu[] = { 550 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 551 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 552 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 553 {} 554 }; 555 556 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 557 { 558 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 559 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 560 bool intel_snc = id && id->driver_data; 561 562 /* Do not match if we do not have a valid APICID for cpu: */ 563 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 564 return false; 565 566 /* Do not match if LLC id does not match: */ 567 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 568 return false; 569 570 /* 571 * Allow the SNC topology without warning. Return of false 572 * means 'c' does not share the LLC of 'o'. This will be 573 * reflected to userspace. 574 */ 575 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 576 return false; 577 578 return topology_sane(c, o, "llc"); 579 } 580 581 582 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 583 static inline int x86_sched_itmt_flags(void) 584 { 585 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 586 } 587 588 #ifdef CONFIG_SCHED_MC 589 static int x86_core_flags(void) 590 { 591 return cpu_core_flags() | x86_sched_itmt_flags(); 592 } 593 #endif 594 #ifdef CONFIG_SCHED_SMT 595 static int x86_smt_flags(void) 596 { 597 return cpu_smt_flags(); 598 } 599 #endif 600 #ifdef CONFIG_SCHED_CLUSTER 601 static int x86_cluster_flags(void) 602 { 603 return cpu_cluster_flags() | x86_sched_itmt_flags(); 604 } 605 #endif 606 #endif 607 608 /* 609 * Set if a package/die has multiple NUMA nodes inside. 610 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 611 * Sub-NUMA Clustering have this. 612 */ 613 static bool x86_has_numa_in_package; 614 615 static struct sched_domain_topology_level x86_topology[6]; 616 617 static void __init build_sched_topology(void) 618 { 619 int i = 0; 620 621 #ifdef CONFIG_SCHED_SMT 622 x86_topology[i++] = (struct sched_domain_topology_level){ 623 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 624 }; 625 #endif 626 #ifdef CONFIG_SCHED_CLUSTER 627 /* 628 * For now, skip the cluster domain on Hybrid. 629 */ 630 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 631 x86_topology[i++] = (struct sched_domain_topology_level){ 632 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 633 }; 634 } 635 #endif 636 #ifdef CONFIG_SCHED_MC 637 x86_topology[i++] = (struct sched_domain_topology_level){ 638 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 639 }; 640 #endif 641 /* 642 * When there is NUMA topology inside the package skip the DIE domain 643 * since the NUMA domains will auto-magically create the right spanning 644 * domains based on the SLIT. 645 */ 646 if (!x86_has_numa_in_package) { 647 x86_topology[i++] = (struct sched_domain_topology_level){ 648 cpu_cpu_mask, SD_INIT_NAME(DIE) 649 }; 650 } 651 652 /* 653 * There must be one trailing NULL entry left. 654 */ 655 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 656 657 set_sched_topology(x86_topology); 658 } 659 660 void set_cpu_sibling_map(int cpu) 661 { 662 bool has_smt = smp_num_siblings > 1; 663 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 664 struct cpuinfo_x86 *c = &cpu_data(cpu); 665 struct cpuinfo_x86 *o; 666 int i, threads; 667 668 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 669 670 if (!has_mp) { 671 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 672 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 673 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 674 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 675 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 676 c->booted_cores = 1; 677 return; 678 } 679 680 for_each_cpu(i, cpu_sibling_setup_mask) { 681 o = &cpu_data(i); 682 683 if (match_pkg(c, o) && !topology_same_node(c, o)) 684 x86_has_numa_in_package = true; 685 686 if ((i == cpu) || (has_smt && match_smt(c, o))) 687 link_mask(topology_sibling_cpumask, cpu, i); 688 689 if ((i == cpu) || (has_mp && match_llc(c, o))) 690 link_mask(cpu_llc_shared_mask, cpu, i); 691 692 if ((i == cpu) || (has_mp && match_l2c(c, o))) 693 link_mask(cpu_l2c_shared_mask, cpu, i); 694 695 if ((i == cpu) || (has_mp && match_die(c, o))) 696 link_mask(topology_die_cpumask, cpu, i); 697 } 698 699 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 700 if (threads > __max_smt_threads) 701 __max_smt_threads = threads; 702 703 for_each_cpu(i, topology_sibling_cpumask(cpu)) 704 cpu_data(i).smt_active = threads > 1; 705 706 /* 707 * This needs a separate iteration over the cpus because we rely on all 708 * topology_sibling_cpumask links to be set-up. 709 */ 710 for_each_cpu(i, cpu_sibling_setup_mask) { 711 o = &cpu_data(i); 712 713 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 714 link_mask(topology_core_cpumask, cpu, i); 715 716 /* 717 * Does this new cpu bringup a new core? 718 */ 719 if (threads == 1) { 720 /* 721 * for each core in package, increment 722 * the booted_cores for this new cpu 723 */ 724 if (cpumask_first( 725 topology_sibling_cpumask(i)) == i) 726 c->booted_cores++; 727 /* 728 * increment the core count for all 729 * the other cpus in this package 730 */ 731 if (i != cpu) 732 cpu_data(i).booted_cores++; 733 } else if (i != cpu && !c->booted_cores) 734 c->booted_cores = cpu_data(i).booted_cores; 735 } 736 } 737 } 738 739 /* maps the cpu to the sched domain representing multi-core */ 740 const struct cpumask *cpu_coregroup_mask(int cpu) 741 { 742 return cpu_llc_shared_mask(cpu); 743 } 744 745 const struct cpumask *cpu_clustergroup_mask(int cpu) 746 { 747 return cpu_l2c_shared_mask(cpu); 748 } 749 750 static void impress_friends(void) 751 { 752 int cpu; 753 unsigned long bogosum = 0; 754 /* 755 * Allow the user to impress friends. 756 */ 757 pr_debug("Before bogomips\n"); 758 for_each_online_cpu(cpu) 759 bogosum += cpu_data(cpu).loops_per_jiffy; 760 761 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 762 num_online_cpus(), 763 bogosum/(500000/HZ), 764 (bogosum/(5000/HZ))%100); 765 766 pr_debug("Before bogocount - setting activated=1\n"); 767 } 768 769 void __inquire_remote_apic(int apicid) 770 { 771 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 772 const char * const names[] = { "ID", "VERSION", "SPIV" }; 773 int timeout; 774 u32 status; 775 776 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 777 778 for (i = 0; i < ARRAY_SIZE(regs); i++) { 779 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 780 781 /* 782 * Wait for idle. 783 */ 784 status = safe_apic_wait_icr_idle(); 785 if (status) 786 pr_cont("a previous APIC delivery may have failed\n"); 787 788 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 789 790 timeout = 0; 791 do { 792 udelay(100); 793 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 794 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 795 796 switch (status) { 797 case APIC_ICR_RR_VALID: 798 status = apic_read(APIC_RRR); 799 pr_cont("%08x\n", status); 800 break; 801 default: 802 pr_cont("failed\n"); 803 } 804 } 805 } 806 807 /* 808 * The Multiprocessor Specification 1.4 (1997) example code suggests 809 * that there should be a 10ms delay between the BSP asserting INIT 810 * and de-asserting INIT, when starting a remote processor. 811 * But that slows boot and resume on modern processors, which include 812 * many cores and don't require that delay. 813 * 814 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 815 * Modern processor families are quirked to remove the delay entirely. 816 */ 817 #define UDELAY_10MS_DEFAULT 10000 818 819 static unsigned int init_udelay = UINT_MAX; 820 821 static int __init cpu_init_udelay(char *str) 822 { 823 get_option(&str, &init_udelay); 824 825 return 0; 826 } 827 early_param("cpu_init_udelay", cpu_init_udelay); 828 829 static void __init smp_quirk_init_udelay(void) 830 { 831 /* if cmdline changed it from default, leave it alone */ 832 if (init_udelay != UINT_MAX) 833 return; 834 835 /* if modern processor, use no delay */ 836 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 837 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 838 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 839 init_udelay = 0; 840 return; 841 } 842 /* else, use legacy delay */ 843 init_udelay = UDELAY_10MS_DEFAULT; 844 } 845 846 /* 847 * Wake up AP by INIT, INIT, STARTUP sequence. 848 */ 849 static void send_init_sequence(int phys_apicid) 850 { 851 int maxlvt = lapic_get_maxlvt(); 852 853 /* Be paranoid about clearing APIC errors. */ 854 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 855 /* Due to the Pentium erratum 3AP. */ 856 if (maxlvt > 3) 857 apic_write(APIC_ESR, 0); 858 apic_read(APIC_ESR); 859 } 860 861 /* Assert INIT on the target CPU */ 862 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 863 safe_apic_wait_icr_idle(); 864 865 udelay(init_udelay); 866 867 /* Deassert INIT on the target CPU */ 868 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 869 safe_apic_wait_icr_idle(); 870 } 871 872 /* 873 * Wake up AP by INIT, INIT, STARTUP sequence. 874 */ 875 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 876 { 877 unsigned long send_status = 0, accept_status = 0; 878 int num_starts, j, maxlvt; 879 880 preempt_disable(); 881 maxlvt = lapic_get_maxlvt(); 882 send_init_sequence(phys_apicid); 883 884 mb(); 885 886 /* 887 * Should we send STARTUP IPIs ? 888 * 889 * Determine this based on the APIC version. 890 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 891 */ 892 if (APIC_INTEGRATED(boot_cpu_apic_version)) 893 num_starts = 2; 894 else 895 num_starts = 0; 896 897 /* 898 * Run STARTUP IPI loop. 899 */ 900 pr_debug("#startup loops: %d\n", num_starts); 901 902 for (j = 1; j <= num_starts; j++) { 903 pr_debug("Sending STARTUP #%d\n", j); 904 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 905 apic_write(APIC_ESR, 0); 906 apic_read(APIC_ESR); 907 pr_debug("After apic_write\n"); 908 909 /* 910 * STARTUP IPI 911 */ 912 913 /* Target chip */ 914 /* Boot on the stack */ 915 /* Kick the second */ 916 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 917 phys_apicid); 918 919 /* 920 * Give the other CPU some time to accept the IPI. 921 */ 922 if (init_udelay == 0) 923 udelay(10); 924 else 925 udelay(300); 926 927 pr_debug("Startup point 1\n"); 928 929 pr_debug("Waiting for send to finish...\n"); 930 send_status = safe_apic_wait_icr_idle(); 931 932 /* 933 * Give the other CPU some time to accept the IPI. 934 */ 935 if (init_udelay == 0) 936 udelay(10); 937 else 938 udelay(200); 939 940 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 941 apic_write(APIC_ESR, 0); 942 accept_status = (apic_read(APIC_ESR) & 0xEF); 943 if (send_status || accept_status) 944 break; 945 } 946 pr_debug("After Startup\n"); 947 948 if (send_status) 949 pr_err("APIC never delivered???\n"); 950 if (accept_status) 951 pr_err("APIC delivery error (%lx)\n", accept_status); 952 953 preempt_enable(); 954 return (send_status | accept_status); 955 } 956 957 /* reduce the number of lines printed when booting a large cpu count system */ 958 static void announce_cpu(int cpu, int apicid) 959 { 960 static int width, node_width, first = 1; 961 static int current_node = NUMA_NO_NODE; 962 int node = early_cpu_to_node(cpu); 963 964 if (!width) 965 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 966 967 if (!node_width) 968 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 969 970 if (system_state < SYSTEM_RUNNING) { 971 if (first) 972 pr_info("x86: Booting SMP configuration:\n"); 973 974 if (node != current_node) { 975 if (current_node > (-1)) 976 pr_cont("\n"); 977 current_node = node; 978 979 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 980 node_width - num_digits(node), " ", node); 981 } 982 983 /* Add padding for the BSP */ 984 if (first) 985 pr_cont("%*s", width + 1, " "); 986 first = 0; 987 988 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 989 } else 990 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 991 node, cpu, apicid); 992 } 993 994 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 995 { 996 int ret; 997 998 /* Just in case we booted with a single CPU. */ 999 alternatives_enable_smp(); 1000 1001 per_cpu(pcpu_hot.current_task, cpu) = idle; 1002 cpu_init_stack_canary(cpu, idle); 1003 1004 /* Initialize the interrupt stack(s) */ 1005 ret = irq_init_percpu_irqstack(cpu); 1006 if (ret) 1007 return ret; 1008 1009 #ifdef CONFIG_X86_32 1010 /* Stack for startup_32 can be just as for start_secondary onwards */ 1011 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 1012 #endif 1013 return 0; 1014 } 1015 1016 /* 1017 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1018 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1019 * Returns zero if startup was successfully sent, else error code from 1020 * ->wakeup_secondary_cpu. 1021 */ 1022 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 1023 { 1024 unsigned long start_ip = real_mode_header->trampoline_start; 1025 int ret; 1026 1027 #ifdef CONFIG_X86_64 1028 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1029 if (apic->wakeup_secondary_cpu_64) 1030 start_ip = real_mode_header->trampoline_start64; 1031 #endif 1032 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1033 initial_code = (unsigned long)start_secondary; 1034 1035 if (IS_ENABLED(CONFIG_X86_32)) { 1036 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1037 initial_stack = idle->thread.sp; 1038 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 1039 smpboot_control = cpu; 1040 } 1041 1042 /* Enable the espfix hack for this CPU */ 1043 init_espfix_ap(cpu); 1044 1045 /* So we see what's up */ 1046 announce_cpu(cpu, apicid); 1047 1048 /* 1049 * This grunge runs the startup process for 1050 * the targeted processor. 1051 */ 1052 if (x86_platform.legacy.warm_reset) { 1053 1054 pr_debug("Setting warm reset code and vector.\n"); 1055 1056 smpboot_setup_warm_reset_vector(start_ip); 1057 /* 1058 * Be paranoid about clearing APIC errors. 1059 */ 1060 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1061 apic_write(APIC_ESR, 0); 1062 apic_read(APIC_ESR); 1063 } 1064 } 1065 1066 smp_mb(); 1067 1068 /* 1069 * Wake up a CPU in difference cases: 1070 * - Use a method from the APIC driver if one defined, with wakeup 1071 * straight to 64-bit mode preferred over wakeup to RM. 1072 * Otherwise, 1073 * - Use an INIT boot APIC message 1074 */ 1075 if (apic->wakeup_secondary_cpu_64) 1076 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1077 else if (apic->wakeup_secondary_cpu) 1078 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1079 else 1080 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1081 1082 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1083 if (ret) 1084 arch_cpuhp_cleanup_kick_cpu(cpu); 1085 return ret; 1086 } 1087 1088 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1089 { 1090 int apicid = apic->cpu_present_to_apicid(cpu); 1091 int err; 1092 1093 lockdep_assert_irqs_enabled(); 1094 1095 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1096 1097 if (apicid == BAD_APICID || 1098 !physid_isset(apicid, phys_cpu_present_map) || 1099 !apic->apic_id_valid(apicid)) { 1100 pr_err("%s: bad cpu %d\n", __func__, cpu); 1101 return -EINVAL; 1102 } 1103 1104 /* 1105 * Save current MTRR state in case it was changed since early boot 1106 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1107 */ 1108 mtrr_save_state(); 1109 1110 /* the FPU context is blank, nobody can own it */ 1111 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1112 1113 err = common_cpu_up(cpu, tidle); 1114 if (err) 1115 return err; 1116 1117 err = do_boot_cpu(apicid, cpu, tidle); 1118 if (err) 1119 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1120 1121 return err; 1122 } 1123 1124 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1125 { 1126 return smp_ops.kick_ap_alive(cpu, tidle); 1127 } 1128 1129 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1130 { 1131 /* Cleanup possible dangling ends... */ 1132 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1133 smpboot_restore_warm_reset_vector(); 1134 } 1135 1136 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1137 { 1138 if (smp_ops.cleanup_dead_cpu) 1139 smp_ops.cleanup_dead_cpu(cpu); 1140 1141 if (system_state == SYSTEM_RUNNING) 1142 pr_info("CPU %u is now offline\n", cpu); 1143 } 1144 1145 void arch_cpuhp_sync_state_poll(void) 1146 { 1147 if (smp_ops.poll_sync_state) 1148 smp_ops.poll_sync_state(); 1149 } 1150 1151 /** 1152 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1153 */ 1154 void __init arch_disable_smp_support(void) 1155 { 1156 disable_ioapic_support(); 1157 } 1158 1159 /* 1160 * Fall back to non SMP mode after errors. 1161 * 1162 * RED-PEN audit/test this more. I bet there is more state messed up here. 1163 */ 1164 static __init void disable_smp(void) 1165 { 1166 pr_info("SMP disabled\n"); 1167 1168 disable_ioapic_support(); 1169 1170 init_cpu_present(cpumask_of(0)); 1171 init_cpu_possible(cpumask_of(0)); 1172 1173 if (smp_found_config) 1174 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1175 else 1176 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1177 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1178 cpumask_set_cpu(0, topology_core_cpumask(0)); 1179 cpumask_set_cpu(0, topology_die_cpumask(0)); 1180 } 1181 1182 /* 1183 * Various sanity checks. 1184 */ 1185 static void __init smp_sanity_check(void) 1186 { 1187 preempt_disable(); 1188 1189 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1190 if (def_to_bigsmp && nr_cpu_ids > 8) { 1191 unsigned int cpu; 1192 unsigned nr; 1193 1194 pr_warn("More than 8 CPUs detected - skipping them\n" 1195 "Use CONFIG_X86_BIGSMP\n"); 1196 1197 nr = 0; 1198 for_each_present_cpu(cpu) { 1199 if (nr >= 8) 1200 set_cpu_present(cpu, false); 1201 nr++; 1202 } 1203 1204 nr = 0; 1205 for_each_possible_cpu(cpu) { 1206 if (nr >= 8) 1207 set_cpu_possible(cpu, false); 1208 nr++; 1209 } 1210 1211 set_nr_cpu_ids(8); 1212 } 1213 #endif 1214 1215 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1216 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1217 hard_smp_processor_id()); 1218 1219 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1220 } 1221 1222 /* 1223 * Should not be necessary because the MP table should list the boot 1224 * CPU too, but we do it for the sake of robustness anyway. 1225 */ 1226 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1227 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1228 boot_cpu_physical_apicid); 1229 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1230 } 1231 preempt_enable(); 1232 } 1233 1234 static void __init smp_cpu_index_default(void) 1235 { 1236 int i; 1237 struct cpuinfo_x86 *c; 1238 1239 for_each_possible_cpu(i) { 1240 c = &cpu_data(i); 1241 /* mark all to hotplug */ 1242 c->cpu_index = nr_cpu_ids; 1243 } 1244 } 1245 1246 void __init smp_prepare_cpus_common(void) 1247 { 1248 unsigned int i; 1249 1250 smp_cpu_index_default(); 1251 1252 /* 1253 * Setup boot CPU information 1254 */ 1255 smp_store_boot_cpu_info(); /* Final full version of the data */ 1256 mb(); 1257 1258 for_each_possible_cpu(i) { 1259 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1260 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1261 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1262 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1263 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1264 } 1265 1266 set_cpu_sibling_map(0); 1267 } 1268 1269 #ifdef CONFIG_X86_64 1270 /* Establish whether parallel bringup can be supported. */ 1271 bool __init arch_cpuhp_init_parallel_bringup(void) 1272 { 1273 if (!x86_cpuinit.parallel_bringup) { 1274 pr_info("Parallel CPU startup disabled by the platform\n"); 1275 return false; 1276 } 1277 1278 smpboot_control = STARTUP_READ_APICID; 1279 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1280 return true; 1281 } 1282 #endif 1283 1284 /* 1285 * Prepare for SMP bootup. 1286 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1287 * for common interface support. 1288 */ 1289 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1290 { 1291 smp_prepare_cpus_common(); 1292 1293 smp_sanity_check(); 1294 1295 switch (apic_intr_mode) { 1296 case APIC_PIC: 1297 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1298 disable_smp(); 1299 return; 1300 case APIC_SYMMETRIC_IO_NO_ROUTING: 1301 disable_smp(); 1302 /* Setup local timer */ 1303 x86_init.timers.setup_percpu_clockev(); 1304 return; 1305 case APIC_VIRTUAL_WIRE: 1306 case APIC_SYMMETRIC_IO: 1307 break; 1308 } 1309 1310 /* Setup local timer */ 1311 x86_init.timers.setup_percpu_clockev(); 1312 1313 pr_info("CPU0: "); 1314 print_cpu_info(&cpu_data(0)); 1315 1316 uv_system_init(); 1317 1318 smp_quirk_init_udelay(); 1319 1320 speculative_store_bypass_ht_init(); 1321 1322 snp_set_wakeup_secondary_cpu(); 1323 } 1324 1325 void arch_thaw_secondary_cpus_begin(void) 1326 { 1327 set_cache_aps_delayed_init(true); 1328 } 1329 1330 void arch_thaw_secondary_cpus_end(void) 1331 { 1332 cache_aps_init(); 1333 } 1334 1335 bool smp_park_other_cpus_in_init(void) 1336 { 1337 unsigned int cpu, this_cpu = smp_processor_id(); 1338 unsigned int apicid; 1339 1340 if (apic->wakeup_secondary_cpu_64 || apic->wakeup_secondary_cpu) 1341 return false; 1342 1343 /* 1344 * If this is a crash stop which does not execute on the boot CPU, 1345 * then this cannot use the INIT mechanism because INIT to the boot 1346 * CPU will reset the machine. 1347 */ 1348 if (this_cpu) 1349 return false; 1350 1351 for_each_present_cpu(cpu) { 1352 if (cpu == this_cpu) 1353 continue; 1354 apicid = apic->cpu_present_to_apicid(cpu); 1355 if (apicid == BAD_APICID) 1356 continue; 1357 send_init_sequence(apicid); 1358 } 1359 return true; 1360 } 1361 1362 /* 1363 * Early setup to make printk work. 1364 */ 1365 void __init native_smp_prepare_boot_cpu(void) 1366 { 1367 int me = smp_processor_id(); 1368 1369 /* SMP handles this from setup_per_cpu_areas() */ 1370 if (!IS_ENABLED(CONFIG_SMP)) 1371 switch_gdt_and_percpu_base(me); 1372 1373 native_pv_lock_init(); 1374 } 1375 1376 void __init calculate_max_logical_packages(void) 1377 { 1378 int ncpus; 1379 1380 /* 1381 * Today neither Intel nor AMD support heterogeneous systems so 1382 * extrapolate the boot cpu's data to all packages. 1383 */ 1384 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1385 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1386 pr_info("Max logical packages: %u\n", __max_logical_packages); 1387 } 1388 1389 void __init native_smp_cpus_done(unsigned int max_cpus) 1390 { 1391 pr_debug("Boot done\n"); 1392 1393 calculate_max_logical_packages(); 1394 build_sched_topology(); 1395 nmi_selftest(); 1396 impress_friends(); 1397 cache_aps_init(); 1398 } 1399 1400 static int __initdata setup_possible_cpus = -1; 1401 static int __init _setup_possible_cpus(char *str) 1402 { 1403 get_option(&str, &setup_possible_cpus); 1404 return 0; 1405 } 1406 early_param("possible_cpus", _setup_possible_cpus); 1407 1408 1409 /* 1410 * cpu_possible_mask should be static, it cannot change as cpu's 1411 * are onlined, or offlined. The reason is per-cpu data-structures 1412 * are allocated by some modules at init time, and don't expect to 1413 * do this dynamically on cpu arrival/departure. 1414 * cpu_present_mask on the other hand can change dynamically. 1415 * In case when cpu_hotplug is not compiled, then we resort to current 1416 * behaviour, which is cpu_possible == cpu_present. 1417 * - Ashok Raj 1418 * 1419 * Three ways to find out the number of additional hotplug CPUs: 1420 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1421 * - The user can overwrite it with possible_cpus=NUM 1422 * - Otherwise don't reserve additional CPUs. 1423 * We do this because additional CPUs waste a lot of memory. 1424 * -AK 1425 */ 1426 __init void prefill_possible_map(void) 1427 { 1428 int i, possible; 1429 1430 /* No boot processor was found in mptable or ACPI MADT */ 1431 if (!num_processors) { 1432 if (boot_cpu_has(X86_FEATURE_APIC)) { 1433 int apicid = boot_cpu_physical_apicid; 1434 int cpu = hard_smp_processor_id(); 1435 1436 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1437 1438 /* Make sure boot cpu is enumerated */ 1439 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1440 apic->apic_id_valid(apicid)) 1441 generic_processor_info(apicid, boot_cpu_apic_version); 1442 } 1443 1444 if (!num_processors) 1445 num_processors = 1; 1446 } 1447 1448 i = setup_max_cpus ?: 1; 1449 if (setup_possible_cpus == -1) { 1450 possible = num_processors; 1451 #ifdef CONFIG_HOTPLUG_CPU 1452 if (setup_max_cpus) 1453 possible += disabled_cpus; 1454 #else 1455 if (possible > i) 1456 possible = i; 1457 #endif 1458 } else 1459 possible = setup_possible_cpus; 1460 1461 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1462 1463 /* nr_cpu_ids could be reduced via nr_cpus= */ 1464 if (possible > nr_cpu_ids) { 1465 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1466 possible, nr_cpu_ids); 1467 possible = nr_cpu_ids; 1468 } 1469 1470 #ifdef CONFIG_HOTPLUG_CPU 1471 if (!setup_max_cpus) 1472 #endif 1473 if (possible > i) { 1474 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1475 possible, setup_max_cpus); 1476 possible = i; 1477 } 1478 1479 set_nr_cpu_ids(possible); 1480 1481 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1482 possible, max_t(int, possible - num_processors, 0)); 1483 1484 reset_cpu_possible_mask(); 1485 1486 for (i = 0; i < possible; i++) 1487 set_cpu_possible(i, true); 1488 } 1489 1490 /* correctly size the local cpu masks */ 1491 void __init setup_cpu_local_masks(void) 1492 { 1493 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1494 } 1495 1496 #ifdef CONFIG_HOTPLUG_CPU 1497 1498 /* Recompute SMT state for all CPUs on offline */ 1499 static void recompute_smt_state(void) 1500 { 1501 int max_threads, cpu; 1502 1503 max_threads = 0; 1504 for_each_online_cpu (cpu) { 1505 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1506 1507 if (threads > max_threads) 1508 max_threads = threads; 1509 } 1510 __max_smt_threads = max_threads; 1511 } 1512 1513 static void remove_siblinginfo(int cpu) 1514 { 1515 int sibling; 1516 struct cpuinfo_x86 *c = &cpu_data(cpu); 1517 1518 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1519 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1520 /*/ 1521 * last thread sibling in this cpu core going down 1522 */ 1523 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1524 cpu_data(sibling).booted_cores--; 1525 } 1526 1527 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1528 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1529 1530 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1531 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1532 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1533 cpu_data(sibling).smt_active = false; 1534 } 1535 1536 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1537 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1538 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1539 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1540 cpumask_clear(cpu_llc_shared_mask(cpu)); 1541 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1542 cpumask_clear(topology_sibling_cpumask(cpu)); 1543 cpumask_clear(topology_core_cpumask(cpu)); 1544 cpumask_clear(topology_die_cpumask(cpu)); 1545 c->cpu_core_id = 0; 1546 c->booted_cores = 0; 1547 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1548 recompute_smt_state(); 1549 } 1550 1551 static void remove_cpu_from_maps(int cpu) 1552 { 1553 set_cpu_online(cpu, false); 1554 numa_remove_cpu(cpu); 1555 } 1556 1557 void cpu_disable_common(void) 1558 { 1559 int cpu = smp_processor_id(); 1560 1561 remove_siblinginfo(cpu); 1562 1563 /* It's now safe to remove this processor from the online map */ 1564 lock_vector_lock(); 1565 remove_cpu_from_maps(cpu); 1566 unlock_vector_lock(); 1567 fixup_irqs(); 1568 lapic_offline(); 1569 } 1570 1571 int native_cpu_disable(void) 1572 { 1573 int ret; 1574 1575 ret = lapic_can_unplug_cpu(); 1576 if (ret) 1577 return ret; 1578 1579 cpu_disable_common(); 1580 1581 /* 1582 * Disable the local APIC. Otherwise IPI broadcasts will reach 1583 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1584 * messages. 1585 * 1586 * Disabling the APIC must happen after cpu_disable_common() 1587 * which invokes fixup_irqs(). 1588 * 1589 * Disabling the APIC preserves already set bits in IRR, but 1590 * an interrupt arriving after disabling the local APIC does not 1591 * set the corresponding IRR bit. 1592 * 1593 * fixup_irqs() scans IRR for set bits so it can raise a not 1594 * yet handled interrupt on the new destination CPU via an IPI 1595 * but obviously it can't do so for IRR bits which are not set. 1596 * IOW, interrupts arriving after disabling the local APIC will 1597 * be lost. 1598 */ 1599 apic_soft_disable(); 1600 1601 return 0; 1602 } 1603 1604 void play_dead_common(void) 1605 { 1606 idle_task_exit(); 1607 1608 cpuhp_ap_report_dead(); 1609 /* 1610 * With physical CPU hotplug, we should halt the cpu 1611 */ 1612 local_irq_disable(); 1613 } 1614 1615 /* 1616 * We need to flush the caches before going to sleep, lest we have 1617 * dirty data in our caches when we come back up. 1618 */ 1619 static inline void mwait_play_dead(void) 1620 { 1621 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1622 unsigned int eax, ebx, ecx, edx; 1623 unsigned int highest_cstate = 0; 1624 unsigned int highest_subcstate = 0; 1625 int i; 1626 1627 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1628 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1629 return; 1630 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1631 return; 1632 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1633 return; 1634 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1635 return; 1636 1637 eax = CPUID_MWAIT_LEAF; 1638 ecx = 0; 1639 native_cpuid(&eax, &ebx, &ecx, &edx); 1640 1641 /* 1642 * eax will be 0 if EDX enumeration is not valid. 1643 * Initialized below to cstate, sub_cstate value when EDX is valid. 1644 */ 1645 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1646 eax = 0; 1647 } else { 1648 edx >>= MWAIT_SUBSTATE_SIZE; 1649 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1650 if (edx & MWAIT_SUBSTATE_MASK) { 1651 highest_cstate = i; 1652 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1653 } 1654 } 1655 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1656 (highest_subcstate - 1); 1657 } 1658 1659 /* Set up state for the kexec() hack below */ 1660 md->status = CPUDEAD_MWAIT_WAIT; 1661 md->control = CPUDEAD_MWAIT_WAIT; 1662 1663 wbinvd(); 1664 1665 while (1) { 1666 /* 1667 * The CLFLUSH is a workaround for erratum AAI65 for 1668 * the Xeon 7400 series. It's not clear it is actually 1669 * needed, but it should be harmless in either case. 1670 * The WBINVD is insufficient due to the spurious-wakeup 1671 * case where we return around the loop. 1672 */ 1673 mb(); 1674 clflush(md); 1675 mb(); 1676 __monitor(md, 0, 0); 1677 mb(); 1678 __mwait(eax, 0); 1679 1680 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1681 /* 1682 * Kexec is about to happen. Don't go back into mwait() as 1683 * the kexec kernel might overwrite text and data including 1684 * page tables and stack. So mwait() would resume when the 1685 * monitor cache line is written to and then the CPU goes 1686 * south due to overwritten text, page tables and stack. 1687 * 1688 * Note: This does _NOT_ protect against a stray MCE, NMI, 1689 * SMI. They will resume execution at the instruction 1690 * following the HLT instruction and run into the problem 1691 * which this is trying to prevent. 1692 */ 1693 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1694 while(1) 1695 native_halt(); 1696 } 1697 } 1698 } 1699 1700 /* 1701 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1702 * mwait_play_dead(). 1703 */ 1704 void smp_kick_mwait_play_dead(void) 1705 { 1706 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1707 struct mwait_cpu_dead *md; 1708 unsigned int cpu, i; 1709 1710 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1711 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1712 1713 /* Does it sit in mwait_play_dead() ? */ 1714 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1715 continue; 1716 1717 /* Wait up to 5ms */ 1718 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1719 /* Bring it out of mwait */ 1720 WRITE_ONCE(md->control, newstate); 1721 udelay(5); 1722 } 1723 1724 if (READ_ONCE(md->status) != newstate) 1725 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1726 } 1727 } 1728 1729 void __noreturn hlt_play_dead(void) 1730 { 1731 if (__this_cpu_read(cpu_info.x86) >= 4) 1732 wbinvd(); 1733 1734 while (1) 1735 native_halt(); 1736 } 1737 1738 void native_play_dead(void) 1739 { 1740 play_dead_common(); 1741 tboot_shutdown(TB_SHUTDOWN_WFS); 1742 1743 mwait_play_dead(); 1744 if (cpuidle_play_dead()) 1745 hlt_play_dead(); 1746 } 1747 1748 #else /* ... !CONFIG_HOTPLUG_CPU */ 1749 int native_cpu_disable(void) 1750 { 1751 return -ENOSYS; 1752 } 1753 1754 void native_play_dead(void) 1755 { 1756 BUG(); 1757 } 1758 1759 #endif 1760