1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 51 #include <asm/acpi.h> 52 #include <asm/desc.h> 53 #include <asm/nmi.h> 54 #include <asm/irq.h> 55 #include <asm/idle.h> 56 #include <asm/trampoline.h> 57 #include <asm/cpu.h> 58 #include <asm/numa.h> 59 #include <asm/pgtable.h> 60 #include <asm/tlbflush.h> 61 #include <asm/mtrr.h> 62 #include <asm/vmi.h> 63 #include <asm/apic.h> 64 #include <asm/setup.h> 65 #include <asm/uv/uv.h> 66 #include <linux/mc146818rtc.h> 67 68 #include <asm/smpboot_hooks.h> 69 70 #ifdef CONFIG_X86_32 71 u8 apicid_2_node[MAX_APICID]; 72 static int low_mappings; 73 #endif 74 75 /* State of each CPU */ 76 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 77 78 /* Store all idle threads, this can be reused instead of creating 79 * a new thread. Also avoids complicated thread destroy functionality 80 * for idle threads. 81 */ 82 #ifdef CONFIG_HOTPLUG_CPU 83 /* 84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 85 * removed after init for !CONFIG_HOTPLUG_CPU. 86 */ 87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 90 #else 91 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 92 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 93 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 94 #endif 95 96 /* Number of siblings per CPU package */ 97 int smp_num_siblings = 1; 98 EXPORT_SYMBOL(smp_num_siblings); 99 100 /* Last level cache ID of each logical CPU */ 101 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 102 103 /* representing HT siblings of each logical CPU */ 104 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); 105 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 106 107 /* representing HT and core siblings of each logical CPU */ 108 DEFINE_PER_CPU(cpumask_t, cpu_core_map); 109 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 110 111 /* Per CPU bogomips and other parameters */ 112 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 113 EXPORT_PER_CPU_SYMBOL(cpu_info); 114 115 atomic_t init_deasserted; 116 117 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 118 119 /* which logical CPUs are on which nodes */ 120 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = 121 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; 122 EXPORT_SYMBOL(node_to_cpumask_map); 123 /* which node each logical CPU is on */ 124 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 125 EXPORT_SYMBOL(cpu_to_node_map); 126 127 /* set up a mapping between cpu and node. */ 128 static void map_cpu_to_node(int cpu, int node) 129 { 130 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 131 cpumask_set_cpu(cpu, &node_to_cpumask_map[node]); 132 cpu_to_node_map[cpu] = node; 133 } 134 135 /* undo a mapping between cpu and node. */ 136 static void unmap_cpu_to_node(int cpu) 137 { 138 int node; 139 140 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 141 for (node = 0; node < MAX_NUMNODES; node++) 142 cpumask_clear_cpu(cpu, &node_to_cpumask_map[node]); 143 cpu_to_node_map[cpu] = 0; 144 } 145 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 146 #define map_cpu_to_node(cpu, node) ({}) 147 #define unmap_cpu_to_node(cpu) ({}) 148 #endif 149 150 #ifdef CONFIG_X86_32 151 static int boot_cpu_logical_apicid; 152 153 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 154 { [0 ... NR_CPUS-1] = BAD_APICID }; 155 156 static void map_cpu_to_logical_apicid(void) 157 { 158 int cpu = smp_processor_id(); 159 int apicid = logical_smp_processor_id(); 160 int node = apic->apicid_to_node(apicid); 161 162 if (!node_online(node)) 163 node = first_online_node; 164 165 cpu_2_logical_apicid[cpu] = apicid; 166 map_cpu_to_node(cpu, node); 167 } 168 169 void numa_remove_cpu(int cpu) 170 { 171 cpu_2_logical_apicid[cpu] = BAD_APICID; 172 unmap_cpu_to_node(cpu); 173 } 174 #else 175 #define map_cpu_to_logical_apicid() do {} while (0) 176 #endif 177 178 /* 179 * Report back to the Boot Processor. 180 * Running on AP. 181 */ 182 static void __cpuinit smp_callin(void) 183 { 184 int cpuid, phys_id; 185 unsigned long timeout; 186 187 /* 188 * If waken up by an INIT in an 82489DX configuration 189 * we may get here before an INIT-deassert IPI reaches 190 * our local APIC. We have to wait for the IPI or we'll 191 * lock up on an APIC access. 192 */ 193 if (apic->wait_for_init_deassert) 194 apic->wait_for_init_deassert(&init_deasserted); 195 196 /* 197 * (This works even if the APIC is not enabled.) 198 */ 199 phys_id = read_apic_id(); 200 cpuid = smp_processor_id(); 201 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 202 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 203 phys_id, cpuid); 204 } 205 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 206 207 /* 208 * STARTUP IPIs are fragile beasts as they might sometimes 209 * trigger some glue motherboard logic. Complete APIC bus 210 * silence for 1 second, this overestimates the time the 211 * boot CPU is spending to send the up to 2 STARTUP IPIs 212 * by a factor of two. This should be enough. 213 */ 214 215 /* 216 * Waiting 2s total for startup (udelay is not yet working) 217 */ 218 timeout = jiffies + 2*HZ; 219 while (time_before(jiffies, timeout)) { 220 /* 221 * Has the boot CPU finished it's STARTUP sequence? 222 */ 223 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 224 break; 225 cpu_relax(); 226 } 227 228 if (!time_before(jiffies, timeout)) { 229 panic("%s: CPU%d started up but did not get a callout!\n", 230 __func__, cpuid); 231 } 232 233 /* 234 * the boot CPU has finished the init stage and is spinning 235 * on callin_map until we finish. We are free to set up this 236 * CPU, first the APIC. (this is probably redundant on most 237 * boards) 238 */ 239 240 pr_debug("CALLIN, before setup_local_APIC().\n"); 241 if (apic->smp_callin_clear_local_apic) 242 apic->smp_callin_clear_local_apic(); 243 setup_local_APIC(); 244 end_local_APIC_setup(); 245 map_cpu_to_logical_apicid(); 246 247 notify_cpu_starting(cpuid); 248 /* 249 * Get our bogomips. 250 * 251 * Need to enable IRQs because it can take longer and then 252 * the NMI watchdog might kill us. 253 */ 254 local_irq_enable(); 255 calibrate_delay(); 256 local_irq_disable(); 257 pr_debug("Stack at about %p\n", &cpuid); 258 259 /* 260 * Save our processor parameters 261 */ 262 smp_store_cpu_info(cpuid); 263 264 /* 265 * Allow the master to continue. 266 */ 267 cpumask_set_cpu(cpuid, cpu_callin_mask); 268 } 269 270 /* 271 * Activate a secondary processor. 272 */ 273 notrace static void __cpuinit start_secondary(void *unused) 274 { 275 /* 276 * Don't put *anything* before cpu_init(), SMP booting is too 277 * fragile that we want to limit the things done here to the 278 * most necessary things. 279 */ 280 vmi_bringup(); 281 cpu_init(); 282 preempt_disable(); 283 smp_callin(); 284 285 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 286 barrier(); 287 /* 288 * Check TSC synchronization with the BP: 289 */ 290 check_tsc_sync_target(); 291 292 if (nmi_watchdog == NMI_IO_APIC) { 293 disable_8259A_irq(0); 294 enable_NMI_through_LVT0(); 295 enable_8259A_irq(0); 296 } 297 298 #ifdef CONFIG_X86_32 299 while (low_mappings) 300 cpu_relax(); 301 __flush_tlb_all(); 302 #endif 303 304 /* This must be done before setting cpu_online_map */ 305 set_cpu_sibling_map(raw_smp_processor_id()); 306 wmb(); 307 308 /* 309 * We need to hold call_lock, so there is no inconsistency 310 * between the time smp_call_function() determines number of 311 * IPI recipients, and the time when the determination is made 312 * for which cpus receive the IPI. Holding this 313 * lock helps us to not include this cpu in a currently in progress 314 * smp_call_function(). 315 * 316 * We need to hold vector_lock so there the set of online cpus 317 * does not change while we are assigning vectors to cpus. Holding 318 * this lock ensures we don't half assign or remove an irq from a cpu. 319 */ 320 ipi_call_lock(); 321 lock_vector_lock(); 322 __setup_vector_irq(smp_processor_id()); 323 set_cpu_online(smp_processor_id(), true); 324 unlock_vector_lock(); 325 ipi_call_unlock(); 326 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 327 328 /* enable local interrupts */ 329 local_irq_enable(); 330 331 setup_secondary_clock(); 332 333 wmb(); 334 cpu_idle(); 335 } 336 337 /* 338 * The bootstrap kernel entry code has set these up. Save them for 339 * a given CPU 340 */ 341 342 void __cpuinit smp_store_cpu_info(int id) 343 { 344 struct cpuinfo_x86 *c = &cpu_data(id); 345 346 *c = boot_cpu_data; 347 c->cpu_index = id; 348 if (id != 0) 349 identify_secondary_cpu(c); 350 } 351 352 353 void __cpuinit set_cpu_sibling_map(int cpu) 354 { 355 int i; 356 struct cpuinfo_x86 *c = &cpu_data(cpu); 357 358 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 359 360 if (smp_num_siblings > 1) { 361 for_each_cpu(i, cpu_sibling_setup_mask) { 362 struct cpuinfo_x86 *o = &cpu_data(i); 363 364 if (c->phys_proc_id == o->phys_proc_id && 365 c->cpu_core_id == o->cpu_core_id) { 366 cpumask_set_cpu(i, cpu_sibling_mask(cpu)); 367 cpumask_set_cpu(cpu, cpu_sibling_mask(i)); 368 cpumask_set_cpu(i, cpu_core_mask(cpu)); 369 cpumask_set_cpu(cpu, cpu_core_mask(i)); 370 cpumask_set_cpu(i, &c->llc_shared_map); 371 cpumask_set_cpu(cpu, &o->llc_shared_map); 372 } 373 } 374 } else { 375 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 376 } 377 378 cpumask_set_cpu(cpu, &c->llc_shared_map); 379 380 if (current_cpu_data.x86_max_cores == 1) { 381 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 382 c->booted_cores = 1; 383 return; 384 } 385 386 for_each_cpu(i, cpu_sibling_setup_mask) { 387 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 388 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 389 cpumask_set_cpu(i, &c->llc_shared_map); 390 cpumask_set_cpu(cpu, &cpu_data(i).llc_shared_map); 391 } 392 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 393 cpumask_set_cpu(i, cpu_core_mask(cpu)); 394 cpumask_set_cpu(cpu, cpu_core_mask(i)); 395 /* 396 * Does this new cpu bringup a new core? 397 */ 398 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 399 /* 400 * for each core in package, increment 401 * the booted_cores for this new cpu 402 */ 403 if (cpumask_first(cpu_sibling_mask(i)) == i) 404 c->booted_cores++; 405 /* 406 * increment the core count for all 407 * the other cpus in this package 408 */ 409 if (i != cpu) 410 cpu_data(i).booted_cores++; 411 } else if (i != cpu && !c->booted_cores) 412 c->booted_cores = cpu_data(i).booted_cores; 413 } 414 } 415 } 416 417 /* maps the cpu to the sched domain representing multi-core */ 418 const struct cpumask *cpu_coregroup_mask(int cpu) 419 { 420 struct cpuinfo_x86 *c = &cpu_data(cpu); 421 /* 422 * For perf, we return last level cache shared map. 423 * And for power savings, we return cpu_core_map 424 */ 425 if (sched_mc_power_savings || sched_smt_power_savings) 426 return cpu_core_mask(cpu); 427 else 428 return &c->llc_shared_map; 429 } 430 431 cpumask_t cpu_coregroup_map(int cpu) 432 { 433 return *cpu_coregroup_mask(cpu); 434 } 435 436 static void impress_friends(void) 437 { 438 int cpu; 439 unsigned long bogosum = 0; 440 /* 441 * Allow the user to impress friends. 442 */ 443 pr_debug("Before bogomips.\n"); 444 for_each_possible_cpu(cpu) 445 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 446 bogosum += cpu_data(cpu).loops_per_jiffy; 447 printk(KERN_INFO 448 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 449 num_online_cpus(), 450 bogosum/(500000/HZ), 451 (bogosum/(5000/HZ))%100); 452 453 pr_debug("Before bogocount - setting activated=1.\n"); 454 } 455 456 void __inquire_remote_apic(int apicid) 457 { 458 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 459 char *names[] = { "ID", "VERSION", "SPIV" }; 460 int timeout; 461 u32 status; 462 463 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 464 465 for (i = 0; i < ARRAY_SIZE(regs); i++) { 466 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 467 468 /* 469 * Wait for idle. 470 */ 471 status = safe_apic_wait_icr_idle(); 472 if (status) 473 printk(KERN_CONT 474 "a previous APIC delivery may have failed\n"); 475 476 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 477 478 timeout = 0; 479 do { 480 udelay(100); 481 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 482 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 483 484 switch (status) { 485 case APIC_ICR_RR_VALID: 486 status = apic_read(APIC_RRR); 487 printk(KERN_CONT "%08x\n", status); 488 break; 489 default: 490 printk(KERN_CONT "failed\n"); 491 } 492 } 493 } 494 495 /* 496 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 497 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 498 * won't ... remember to clear down the APIC, etc later. 499 */ 500 int __devinit 501 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 502 { 503 unsigned long send_status, accept_status = 0; 504 int maxlvt; 505 506 /* Target chip */ 507 /* Boot on the stack */ 508 /* Kick the second */ 509 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 510 511 pr_debug("Waiting for send to finish...\n"); 512 send_status = safe_apic_wait_icr_idle(); 513 514 /* 515 * Give the other CPU some time to accept the IPI. 516 */ 517 udelay(200); 518 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 519 maxlvt = lapic_get_maxlvt(); 520 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 521 apic_write(APIC_ESR, 0); 522 accept_status = (apic_read(APIC_ESR) & 0xEF); 523 } 524 pr_debug("NMI sent.\n"); 525 526 if (send_status) 527 printk(KERN_ERR "APIC never delivered???\n"); 528 if (accept_status) 529 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 530 531 return (send_status | accept_status); 532 } 533 534 int __devinit 535 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 536 { 537 unsigned long send_status, accept_status = 0; 538 int maxlvt, num_starts, j; 539 540 maxlvt = lapic_get_maxlvt(); 541 542 /* 543 * Be paranoid about clearing APIC errors. 544 */ 545 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 546 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 547 apic_write(APIC_ESR, 0); 548 apic_read(APIC_ESR); 549 } 550 551 pr_debug("Asserting INIT.\n"); 552 553 /* 554 * Turn INIT on target chip 555 */ 556 /* 557 * Send IPI 558 */ 559 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 560 phys_apicid); 561 562 pr_debug("Waiting for send to finish...\n"); 563 send_status = safe_apic_wait_icr_idle(); 564 565 mdelay(10); 566 567 pr_debug("Deasserting INIT.\n"); 568 569 /* Target chip */ 570 /* Send IPI */ 571 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 572 573 pr_debug("Waiting for send to finish...\n"); 574 send_status = safe_apic_wait_icr_idle(); 575 576 mb(); 577 atomic_set(&init_deasserted, 1); 578 579 /* 580 * Should we send STARTUP IPIs ? 581 * 582 * Determine this based on the APIC version. 583 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 584 */ 585 if (APIC_INTEGRATED(apic_version[phys_apicid])) 586 num_starts = 2; 587 else 588 num_starts = 0; 589 590 /* 591 * Paravirt / VMI wants a startup IPI hook here to set up the 592 * target processor state. 593 */ 594 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 595 (unsigned long)stack_start.sp); 596 597 /* 598 * Run STARTUP IPI loop. 599 */ 600 pr_debug("#startup loops: %d.\n", num_starts); 601 602 for (j = 1; j <= num_starts; j++) { 603 pr_debug("Sending STARTUP #%d.\n", j); 604 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 605 apic_write(APIC_ESR, 0); 606 apic_read(APIC_ESR); 607 pr_debug("After apic_write.\n"); 608 609 /* 610 * STARTUP IPI 611 */ 612 613 /* Target chip */ 614 /* Boot on the stack */ 615 /* Kick the second */ 616 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 617 phys_apicid); 618 619 /* 620 * Give the other CPU some time to accept the IPI. 621 */ 622 udelay(300); 623 624 pr_debug("Startup point 1.\n"); 625 626 pr_debug("Waiting for send to finish...\n"); 627 send_status = safe_apic_wait_icr_idle(); 628 629 /* 630 * Give the other CPU some time to accept the IPI. 631 */ 632 udelay(200); 633 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 634 apic_write(APIC_ESR, 0); 635 accept_status = (apic_read(APIC_ESR) & 0xEF); 636 if (send_status || accept_status) 637 break; 638 } 639 pr_debug("After Startup.\n"); 640 641 if (send_status) 642 printk(KERN_ERR "APIC never delivered???\n"); 643 if (accept_status) 644 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 645 646 return (send_status | accept_status); 647 } 648 649 struct create_idle { 650 struct work_struct work; 651 struct task_struct *idle; 652 struct completion done; 653 int cpu; 654 }; 655 656 static void __cpuinit do_fork_idle(struct work_struct *work) 657 { 658 struct create_idle *c_idle = 659 container_of(work, struct create_idle, work); 660 661 c_idle->idle = fork_idle(c_idle->cpu); 662 complete(&c_idle->done); 663 } 664 665 /* 666 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 667 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 668 * Returns zero if CPU booted OK, else error code from 669 * ->wakeup_secondary_cpu. 670 */ 671 static int __cpuinit do_boot_cpu(int apicid, int cpu) 672 { 673 unsigned long boot_error = 0; 674 unsigned long start_ip; 675 int timeout; 676 struct create_idle c_idle = { 677 .cpu = cpu, 678 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 679 }; 680 681 INIT_WORK(&c_idle.work, do_fork_idle); 682 683 alternatives_smp_switch(1); 684 685 c_idle.idle = get_idle_for_cpu(cpu); 686 687 /* 688 * We can't use kernel_thread since we must avoid to 689 * reschedule the child. 690 */ 691 if (c_idle.idle) { 692 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 693 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 694 init_idle(c_idle.idle, cpu); 695 goto do_rest; 696 } 697 698 if (!keventd_up() || current_is_keventd()) 699 c_idle.work.func(&c_idle.work); 700 else { 701 schedule_work(&c_idle.work); 702 wait_for_completion(&c_idle.done); 703 } 704 705 if (IS_ERR(c_idle.idle)) { 706 printk("failed fork for CPU %d\n", cpu); 707 return PTR_ERR(c_idle.idle); 708 } 709 710 set_idle_for_cpu(cpu, c_idle.idle); 711 do_rest: 712 per_cpu(current_task, cpu) = c_idle.idle; 713 #ifdef CONFIG_X86_32 714 /* Stack for startup_32 can be just as for start_secondary onwards */ 715 irq_ctx_init(cpu); 716 #else 717 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 718 initial_gs = per_cpu_offset(cpu); 719 per_cpu(kernel_stack, cpu) = 720 (unsigned long)task_stack_page(c_idle.idle) - 721 KERNEL_STACK_OFFSET + THREAD_SIZE; 722 #endif 723 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 724 initial_code = (unsigned long)start_secondary; 725 stack_start.sp = (void *) c_idle.idle->thread.sp; 726 727 /* start_ip had better be page-aligned! */ 728 start_ip = setup_trampoline(); 729 730 /* So we see what's up */ 731 printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", 732 cpu, apicid, start_ip); 733 734 /* 735 * This grunge runs the startup process for 736 * the targeted processor. 737 */ 738 739 atomic_set(&init_deasserted, 0); 740 741 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 742 743 pr_debug("Setting warm reset code and vector.\n"); 744 745 smpboot_setup_warm_reset_vector(start_ip); 746 /* 747 * Be paranoid about clearing APIC errors. 748 */ 749 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 750 apic_write(APIC_ESR, 0); 751 apic_read(APIC_ESR); 752 } 753 } 754 755 /* 756 * Kick the secondary CPU. Use the method in the APIC driver 757 * if it's defined - or use an INIT boot APIC message otherwise: 758 */ 759 if (apic->wakeup_secondary_cpu) 760 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 761 else 762 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 763 764 if (!boot_error) { 765 /* 766 * allow APs to start initializing. 767 */ 768 pr_debug("Before Callout %d.\n", cpu); 769 cpumask_set_cpu(cpu, cpu_callout_mask); 770 pr_debug("After Callout %d.\n", cpu); 771 772 /* 773 * Wait 5s total for a response 774 */ 775 for (timeout = 0; timeout < 50000; timeout++) { 776 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 777 break; /* It has booted */ 778 udelay(100); 779 } 780 781 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 782 /* number CPUs logically, starting from 1 (BSP is 0) */ 783 pr_debug("OK.\n"); 784 printk(KERN_INFO "CPU%d: ", cpu); 785 print_cpu_info(&cpu_data(cpu)); 786 pr_debug("CPU has booted.\n"); 787 } else { 788 boot_error = 1; 789 if (*((volatile unsigned char *)trampoline_base) 790 == 0xA5) 791 /* trampoline started but...? */ 792 printk(KERN_ERR "Stuck ??\n"); 793 else 794 /* trampoline code not run */ 795 printk(KERN_ERR "Not responding.\n"); 796 if (apic->inquire_remote_apic) 797 apic->inquire_remote_apic(apicid); 798 } 799 } 800 801 if (boot_error) { 802 /* Try to put things back the way they were before ... */ 803 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 804 805 /* was set by do_boot_cpu() */ 806 cpumask_clear_cpu(cpu, cpu_callout_mask); 807 808 /* was set by cpu_init() */ 809 cpumask_clear_cpu(cpu, cpu_initialized_mask); 810 811 set_cpu_present(cpu, false); 812 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 813 } 814 815 /* mark "stuck" area as not stuck */ 816 *((volatile unsigned long *)trampoline_base) = 0; 817 818 /* 819 * Cleanup possible dangling ends... 820 */ 821 smpboot_restore_warm_reset_vector(); 822 823 return boot_error; 824 } 825 826 int __cpuinit native_cpu_up(unsigned int cpu) 827 { 828 int apicid = apic->cpu_present_to_apicid(cpu); 829 unsigned long flags; 830 int err; 831 832 WARN_ON(irqs_disabled()); 833 834 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 835 836 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 837 !physid_isset(apicid, phys_cpu_present_map)) { 838 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 839 return -EINVAL; 840 } 841 842 /* 843 * Already booted CPU? 844 */ 845 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 846 pr_debug("do_boot_cpu %d Already started\n", cpu); 847 return -ENOSYS; 848 } 849 850 /* 851 * Save current MTRR state in case it was changed since early boot 852 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 853 */ 854 mtrr_save_state(); 855 856 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 857 858 #ifdef CONFIG_X86_32 859 /* init low mem mapping */ 860 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, 861 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); 862 flush_tlb_all(); 863 low_mappings = 1; 864 865 err = do_boot_cpu(apicid, cpu); 866 867 zap_low_mappings(); 868 low_mappings = 0; 869 #else 870 err = do_boot_cpu(apicid, cpu); 871 #endif 872 if (err) { 873 pr_debug("do_boot_cpu failed %d\n", err); 874 return -EIO; 875 } 876 877 /* 878 * Check TSC synchronization with the AP (keep irqs disabled 879 * while doing so): 880 */ 881 local_irq_save(flags); 882 check_tsc_sync_source(cpu); 883 local_irq_restore(flags); 884 885 while (!cpu_online(cpu)) { 886 cpu_relax(); 887 touch_nmi_watchdog(); 888 } 889 890 return 0; 891 } 892 893 /* 894 * Fall back to non SMP mode after errors. 895 * 896 * RED-PEN audit/test this more. I bet there is more state messed up here. 897 */ 898 static __init void disable_smp(void) 899 { 900 /* use the read/write pointers to the present and possible maps */ 901 cpumask_copy(&cpu_present_map, cpumask_of(0)); 902 cpumask_copy(&cpu_possible_map, cpumask_of(0)); 903 smpboot_clear_io_apic_irqs(); 904 905 if (smp_found_config) 906 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 907 else 908 physid_set_mask_of_physid(0, &phys_cpu_present_map); 909 map_cpu_to_logical_apicid(); 910 cpumask_set_cpu(0, cpu_sibling_mask(0)); 911 cpumask_set_cpu(0, cpu_core_mask(0)); 912 } 913 914 /* 915 * Various sanity checks. 916 */ 917 static int __init smp_sanity_check(unsigned max_cpus) 918 { 919 preempt_disable(); 920 921 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 922 if (def_to_bigsmp && nr_cpu_ids > 8) { 923 unsigned int cpu; 924 unsigned nr; 925 926 printk(KERN_WARNING 927 "More than 8 CPUs detected - skipping them.\n" 928 "Use CONFIG_X86_BIGSMP.\n"); 929 930 nr = 0; 931 for_each_present_cpu(cpu) { 932 if (nr >= 8) 933 set_cpu_present(cpu, false); 934 nr++; 935 } 936 937 nr = 0; 938 for_each_possible_cpu(cpu) { 939 if (nr >= 8) 940 set_cpu_possible(cpu, false); 941 nr++; 942 } 943 944 nr_cpu_ids = 8; 945 } 946 #endif 947 948 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 949 printk(KERN_WARNING 950 "weird, boot CPU (#%d) not listed by the BIOS.\n", 951 hard_smp_processor_id()); 952 953 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 954 } 955 956 /* 957 * If we couldn't find an SMP configuration at boot time, 958 * get out of here now! 959 */ 960 if (!smp_found_config && !acpi_lapic) { 961 preempt_enable(); 962 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 963 disable_smp(); 964 if (APIC_init_uniprocessor()) 965 printk(KERN_NOTICE "Local APIC not detected." 966 " Using dummy APIC emulation.\n"); 967 return -1; 968 } 969 970 /* 971 * Should not be necessary because the MP table should list the boot 972 * CPU too, but we do it for the sake of robustness anyway. 973 */ 974 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 975 printk(KERN_NOTICE 976 "weird, boot CPU (#%d) not listed by the BIOS.\n", 977 boot_cpu_physical_apicid); 978 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 979 } 980 preempt_enable(); 981 982 /* 983 * If we couldn't find a local APIC, then get out of here now! 984 */ 985 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 986 !cpu_has_apic) { 987 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", 988 boot_cpu_physical_apicid); 989 printk(KERN_ERR "... forcing use of dummy APIC emulation." 990 "(tell your hw vendor)\n"); 991 smpboot_clear_io_apic(); 992 arch_disable_smp_support(); 993 return -1; 994 } 995 996 verify_local_APIC(); 997 998 /* 999 * If SMP should be disabled, then really disable it! 1000 */ 1001 if (!max_cpus) { 1002 printk(KERN_INFO "SMP mode deactivated.\n"); 1003 smpboot_clear_io_apic(); 1004 1005 localise_nmi_watchdog(); 1006 1007 connect_bsp_APIC(); 1008 setup_local_APIC(); 1009 end_local_APIC_setup(); 1010 return -1; 1011 } 1012 1013 return 0; 1014 } 1015 1016 static void __init smp_cpu_index_default(void) 1017 { 1018 int i; 1019 struct cpuinfo_x86 *c; 1020 1021 for_each_possible_cpu(i) { 1022 c = &cpu_data(i); 1023 /* mark all to hotplug */ 1024 c->cpu_index = nr_cpu_ids; 1025 } 1026 } 1027 1028 /* 1029 * Prepare for SMP bootup. The MP table or ACPI has been read 1030 * earlier. Just do some sanity checking here and enable APIC mode. 1031 */ 1032 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1033 { 1034 preempt_disable(); 1035 smp_cpu_index_default(); 1036 current_cpu_data = boot_cpu_data; 1037 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1038 mb(); 1039 /* 1040 * Setup boot CPU information 1041 */ 1042 smp_store_cpu_info(0); /* Final full version of the data */ 1043 #ifdef CONFIG_X86_32 1044 boot_cpu_logical_apicid = logical_smp_processor_id(); 1045 #endif 1046 current_thread_info()->cpu = 0; /* needed? */ 1047 set_cpu_sibling_map(0); 1048 1049 enable_IR_x2apic(); 1050 #ifdef CONFIG_X86_64 1051 default_setup_apic_routing(); 1052 #endif 1053 1054 if (smp_sanity_check(max_cpus) < 0) { 1055 printk(KERN_INFO "SMP disabled\n"); 1056 disable_smp(); 1057 goto out; 1058 } 1059 1060 preempt_disable(); 1061 if (read_apic_id() != boot_cpu_physical_apicid) { 1062 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1063 read_apic_id(), boot_cpu_physical_apicid); 1064 /* Or can we switch back to PIC here? */ 1065 } 1066 preempt_enable(); 1067 1068 connect_bsp_APIC(); 1069 1070 /* 1071 * Switch from PIC to APIC mode. 1072 */ 1073 setup_local_APIC(); 1074 1075 /* 1076 * Enable IO APIC before setting up error vector 1077 */ 1078 if (!skip_ioapic_setup && nr_ioapics) 1079 enable_IO_APIC(); 1080 1081 end_local_APIC_setup(); 1082 1083 map_cpu_to_logical_apicid(); 1084 1085 if (apic->setup_portio_remap) 1086 apic->setup_portio_remap(); 1087 1088 smpboot_setup_io_apic(); 1089 /* 1090 * Set up local APIC timer on boot CPU. 1091 */ 1092 1093 printk(KERN_INFO "CPU%d: ", 0); 1094 print_cpu_info(&cpu_data(0)); 1095 setup_boot_clock(); 1096 1097 if (is_uv_system()) 1098 uv_system_init(); 1099 out: 1100 preempt_enable(); 1101 } 1102 /* 1103 * Early setup to make printk work. 1104 */ 1105 void __init native_smp_prepare_boot_cpu(void) 1106 { 1107 int me = smp_processor_id(); 1108 switch_to_new_gdt(me); 1109 /* already set me in cpu_online_mask in boot_cpu_init() */ 1110 cpumask_set_cpu(me, cpu_callout_mask); 1111 per_cpu(cpu_state, me) = CPU_ONLINE; 1112 } 1113 1114 void __init native_smp_cpus_done(unsigned int max_cpus) 1115 { 1116 pr_debug("Boot done.\n"); 1117 1118 impress_friends(); 1119 #ifdef CONFIG_X86_IO_APIC 1120 setup_ioapic_dest(); 1121 #endif 1122 check_nmi_watchdog(); 1123 } 1124 1125 static int __initdata setup_possible_cpus = -1; 1126 static int __init _setup_possible_cpus(char *str) 1127 { 1128 get_option(&str, &setup_possible_cpus); 1129 return 0; 1130 } 1131 early_param("possible_cpus", _setup_possible_cpus); 1132 1133 1134 /* 1135 * cpu_possible_map should be static, it cannot change as cpu's 1136 * are onlined, or offlined. The reason is per-cpu data-structures 1137 * are allocated by some modules at init time, and dont expect to 1138 * do this dynamically on cpu arrival/departure. 1139 * cpu_present_map on the other hand can change dynamically. 1140 * In case when cpu_hotplug is not compiled, then we resort to current 1141 * behaviour, which is cpu_possible == cpu_present. 1142 * - Ashok Raj 1143 * 1144 * Three ways to find out the number of additional hotplug CPUs: 1145 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1146 * - The user can overwrite it with possible_cpus=NUM 1147 * - Otherwise don't reserve additional CPUs. 1148 * We do this because additional CPUs waste a lot of memory. 1149 * -AK 1150 */ 1151 __init void prefill_possible_map(void) 1152 { 1153 int i, possible; 1154 1155 /* no processor from mptable or madt */ 1156 if (!num_processors) 1157 num_processors = 1; 1158 1159 if (setup_possible_cpus == -1) 1160 possible = num_processors + disabled_cpus; 1161 else 1162 possible = setup_possible_cpus; 1163 1164 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1165 1166 if (possible > CONFIG_NR_CPUS) { 1167 printk(KERN_WARNING 1168 "%d Processors exceeds NR_CPUS limit of %d\n", 1169 possible, CONFIG_NR_CPUS); 1170 possible = CONFIG_NR_CPUS; 1171 } 1172 1173 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1174 possible, max_t(int, possible - num_processors, 0)); 1175 1176 for (i = 0; i < possible; i++) 1177 set_cpu_possible(i, true); 1178 1179 nr_cpu_ids = possible; 1180 } 1181 1182 #ifdef CONFIG_HOTPLUG_CPU 1183 1184 static void remove_siblinginfo(int cpu) 1185 { 1186 int sibling; 1187 struct cpuinfo_x86 *c = &cpu_data(cpu); 1188 1189 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1190 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1191 /*/ 1192 * last thread sibling in this cpu core going down 1193 */ 1194 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1195 cpu_data(sibling).booted_cores--; 1196 } 1197 1198 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1199 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1200 cpumask_clear(cpu_sibling_mask(cpu)); 1201 cpumask_clear(cpu_core_mask(cpu)); 1202 c->phys_proc_id = 0; 1203 c->cpu_core_id = 0; 1204 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1205 } 1206 1207 static void __ref remove_cpu_from_maps(int cpu) 1208 { 1209 set_cpu_online(cpu, false); 1210 cpumask_clear_cpu(cpu, cpu_callout_mask); 1211 cpumask_clear_cpu(cpu, cpu_callin_mask); 1212 /* was set by cpu_init() */ 1213 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1214 numa_remove_cpu(cpu); 1215 } 1216 1217 void cpu_disable_common(void) 1218 { 1219 int cpu = smp_processor_id(); 1220 /* 1221 * HACK: 1222 * Allow any queued timer interrupts to get serviced 1223 * This is only a temporary solution until we cleanup 1224 * fixup_irqs as we do for IA64. 1225 */ 1226 local_irq_enable(); 1227 mdelay(1); 1228 1229 local_irq_disable(); 1230 remove_siblinginfo(cpu); 1231 1232 /* It's now safe to remove this processor from the online map */ 1233 lock_vector_lock(); 1234 remove_cpu_from_maps(cpu); 1235 unlock_vector_lock(); 1236 fixup_irqs(); 1237 } 1238 1239 int native_cpu_disable(void) 1240 { 1241 int cpu = smp_processor_id(); 1242 1243 /* 1244 * Perhaps use cpufreq to drop frequency, but that could go 1245 * into generic code. 1246 * 1247 * We won't take down the boot processor on i386 due to some 1248 * interrupts only being able to be serviced by the BSP. 1249 * Especially so if we're not using an IOAPIC -zwane 1250 */ 1251 if (cpu == 0) 1252 return -EBUSY; 1253 1254 if (nmi_watchdog == NMI_LOCAL_APIC) 1255 stop_apic_nmi_watchdog(NULL); 1256 clear_local_APIC(); 1257 1258 cpu_disable_common(); 1259 return 0; 1260 } 1261 1262 void native_cpu_die(unsigned int cpu) 1263 { 1264 /* We don't do anything here: idle task is faking death itself. */ 1265 unsigned int i; 1266 1267 for (i = 0; i < 10; i++) { 1268 /* They ack this in play_dead by setting CPU_DEAD */ 1269 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1270 printk(KERN_INFO "CPU %d is now offline\n", cpu); 1271 if (1 == num_online_cpus()) 1272 alternatives_smp_switch(0); 1273 return; 1274 } 1275 msleep(100); 1276 } 1277 printk(KERN_ERR "CPU %u didn't die...\n", cpu); 1278 } 1279 1280 void play_dead_common(void) 1281 { 1282 idle_task_exit(); 1283 reset_lazy_tlbstate(); 1284 irq_ctx_exit(raw_smp_processor_id()); 1285 c1e_remove_cpu(raw_smp_processor_id()); 1286 1287 mb(); 1288 /* Ack it */ 1289 __get_cpu_var(cpu_state) = CPU_DEAD; 1290 1291 /* 1292 * With physical CPU hotplug, we should halt the cpu 1293 */ 1294 local_irq_disable(); 1295 } 1296 1297 void native_play_dead(void) 1298 { 1299 play_dead_common(); 1300 wbinvd_halt(); 1301 } 1302 1303 #else /* ... !CONFIG_HOTPLUG_CPU */ 1304 int native_cpu_disable(void) 1305 { 1306 return -ENOSYS; 1307 } 1308 1309 void native_cpu_die(unsigned int cpu) 1310 { 1311 /* We said "no" in __cpu_disable */ 1312 BUG(); 1313 } 1314 1315 void native_play_dead(void) 1316 { 1317 BUG(); 1318 } 1319 1320 #endif 1321