1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/stackprotector.h> 55 #include <linux/gfp.h> 56 #include <linux/cpuidle.h> 57 #include <linux/numa.h> 58 59 #include <asm/acpi.h> 60 #include <asm/desc.h> 61 #include <asm/nmi.h> 62 #include <asm/irq.h> 63 #include <asm/realmode.h> 64 #include <asm/cpu.h> 65 #include <asm/numa.h> 66 #include <asm/pgtable.h> 67 #include <asm/tlbflush.h> 68 #include <asm/mtrr.h> 69 #include <asm/mwait.h> 70 #include <asm/apic.h> 71 #include <asm/io_apic.h> 72 #include <asm/fpu/internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 #include <asm/i8259.h> 77 #include <asm/misc.h> 78 #include <asm/qspinlock.h> 79 #include <asm/intel-family.h> 80 #include <asm/cpu_device_id.h> 81 #include <asm/spec-ctrl.h> 82 #include <asm/hw_irq.h> 83 84 /* representing HT siblings of each logical CPU */ 85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 87 88 /* representing HT and core siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 91 92 /* representing HT, core, and die siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 95 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 97 98 /* Per CPU bogomips and other parameters */ 99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 100 EXPORT_PER_CPU_SYMBOL(cpu_info); 101 102 /* Logical package management. We might want to allocate that dynamically */ 103 unsigned int __max_logical_packages __read_mostly; 104 EXPORT_SYMBOL(__max_logical_packages); 105 static unsigned int logical_packages __read_mostly; 106 static unsigned int logical_die __read_mostly; 107 108 /* Maximum number of SMT threads on any online core */ 109 int __read_mostly __max_smt_threads = 1; 110 111 /* Flag to indicate if a complete sched domain rebuild is required */ 112 bool x86_topology_update; 113 114 int arch_update_cpu_topology(void) 115 { 116 int retval = x86_topology_update; 117 118 x86_topology_update = false; 119 return retval; 120 } 121 122 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 123 { 124 unsigned long flags; 125 126 spin_lock_irqsave(&rtc_lock, flags); 127 CMOS_WRITE(0xa, 0xf); 128 spin_unlock_irqrestore(&rtc_lock, flags); 129 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 130 start_eip >> 4; 131 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 132 start_eip & 0xf; 133 } 134 135 static inline void smpboot_restore_warm_reset_vector(void) 136 { 137 unsigned long flags; 138 139 /* 140 * Paranoid: Set warm reset code and vector here back 141 * to default values. 142 */ 143 spin_lock_irqsave(&rtc_lock, flags); 144 CMOS_WRITE(0, 0xf); 145 spin_unlock_irqrestore(&rtc_lock, flags); 146 147 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 148 } 149 150 static void init_freq_invariance(void); 151 152 /* 153 * Report back to the Boot Processor during boot time or to the caller processor 154 * during CPU online. 155 */ 156 static void smp_callin(void) 157 { 158 int cpuid; 159 160 /* 161 * If waken up by an INIT in an 82489DX configuration 162 * cpu_callout_mask guarantees we don't get here before 163 * an INIT_deassert IPI reaches our local APIC, so it is 164 * now safe to touch our local APIC. 165 */ 166 cpuid = smp_processor_id(); 167 168 /* 169 * the boot CPU has finished the init stage and is spinning 170 * on callin_map until we finish. We are free to set up this 171 * CPU, first the APIC. (this is probably redundant on most 172 * boards) 173 */ 174 apic_ap_setup(); 175 176 /* 177 * Save our processor parameters. Note: this information 178 * is needed for clock calibration. 179 */ 180 smp_store_cpu_info(cpuid); 181 182 /* 183 * The topology information must be up to date before 184 * calibrate_delay() and notify_cpu_starting(). 185 */ 186 set_cpu_sibling_map(raw_smp_processor_id()); 187 188 init_freq_invariance(); 189 190 /* 191 * Get our bogomips. 192 * Update loops_per_jiffy in cpu_data. Previous call to 193 * smp_store_cpu_info() stored a value that is close but not as 194 * accurate as the value just calculated. 195 */ 196 calibrate_delay(); 197 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 198 pr_debug("Stack at about %p\n", &cpuid); 199 200 wmb(); 201 202 notify_cpu_starting(cpuid); 203 204 /* 205 * Allow the master to continue. 206 */ 207 cpumask_set_cpu(cpuid, cpu_callin_mask); 208 } 209 210 static int cpu0_logical_apicid; 211 static int enable_start_cpu0; 212 /* 213 * Activate a secondary processor. 214 */ 215 static void notrace start_secondary(void *unused) 216 { 217 /* 218 * Don't put *anything* except direct CPU state initialization 219 * before cpu_init(), SMP booting is too fragile that we want to 220 * limit the things done here to the most necessary things. 221 */ 222 cr4_init(); 223 224 #ifdef CONFIG_X86_32 225 /* switch away from the initial page table */ 226 load_cr3(swapper_pg_dir); 227 __flush_tlb_all(); 228 #endif 229 load_current_idt(); 230 cpu_init(); 231 x86_cpuinit.early_percpu_clock_init(); 232 preempt_disable(); 233 smp_callin(); 234 235 enable_start_cpu0 = 0; 236 237 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 238 barrier(); 239 /* 240 * Check TSC synchronization with the boot CPU: 241 */ 242 check_tsc_sync_target(); 243 244 speculative_store_bypass_ht_init(); 245 246 /* 247 * Lock vector_lock, set CPU online and bring the vector 248 * allocator online. Online must be set with vector_lock held 249 * to prevent a concurrent irq setup/teardown from seeing a 250 * half valid vector space. 251 */ 252 lock_vector_lock(); 253 set_cpu_online(smp_processor_id(), true); 254 lapic_online(); 255 unlock_vector_lock(); 256 cpu_set_state_online(smp_processor_id()); 257 x86_platform.nmi_init(); 258 259 /* enable local interrupts */ 260 local_irq_enable(); 261 262 /* to prevent fake stack check failure in clock setup */ 263 boot_init_stack_canary(); 264 265 x86_cpuinit.setup_percpu_clockev(); 266 267 wmb(); 268 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 269 } 270 271 /** 272 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 273 * @cpu: CPU to check 274 */ 275 bool topology_is_primary_thread(unsigned int cpu) 276 { 277 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 278 } 279 280 /** 281 * topology_smt_supported - Check whether SMT is supported by the CPUs 282 */ 283 bool topology_smt_supported(void) 284 { 285 return smp_num_siblings > 1; 286 } 287 288 /** 289 * topology_phys_to_logical_pkg - Map a physical package id to a logical 290 * 291 * Returns logical package id or -1 if not found 292 */ 293 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 294 { 295 int cpu; 296 297 for_each_possible_cpu(cpu) { 298 struct cpuinfo_x86 *c = &cpu_data(cpu); 299 300 if (c->initialized && c->phys_proc_id == phys_pkg) 301 return c->logical_proc_id; 302 } 303 return -1; 304 } 305 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 306 /** 307 * topology_phys_to_logical_die - Map a physical die id to logical 308 * 309 * Returns logical die id or -1 if not found 310 */ 311 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 312 { 313 int cpu; 314 int proc_id = cpu_data(cur_cpu).phys_proc_id; 315 316 for_each_possible_cpu(cpu) { 317 struct cpuinfo_x86 *c = &cpu_data(cpu); 318 319 if (c->initialized && c->cpu_die_id == die_id && 320 c->phys_proc_id == proc_id) 321 return c->logical_die_id; 322 } 323 return -1; 324 } 325 EXPORT_SYMBOL(topology_phys_to_logical_die); 326 327 /** 328 * topology_update_package_map - Update the physical to logical package map 329 * @pkg: The physical package id as retrieved via CPUID 330 * @cpu: The cpu for which this is updated 331 */ 332 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 333 { 334 int new; 335 336 /* Already available somewhere? */ 337 new = topology_phys_to_logical_pkg(pkg); 338 if (new >= 0) 339 goto found; 340 341 new = logical_packages++; 342 if (new != pkg) { 343 pr_info("CPU %u Converting physical %u to logical package %u\n", 344 cpu, pkg, new); 345 } 346 found: 347 cpu_data(cpu).logical_proc_id = new; 348 return 0; 349 } 350 /** 351 * topology_update_die_map - Update the physical to logical die map 352 * @die: The die id as retrieved via CPUID 353 * @cpu: The cpu for which this is updated 354 */ 355 int topology_update_die_map(unsigned int die, unsigned int cpu) 356 { 357 int new; 358 359 /* Already available somewhere? */ 360 new = topology_phys_to_logical_die(die, cpu); 361 if (new >= 0) 362 goto found; 363 364 new = logical_die++; 365 if (new != die) { 366 pr_info("CPU %u Converting physical %u to logical die %u\n", 367 cpu, die, new); 368 } 369 found: 370 cpu_data(cpu).logical_die_id = new; 371 return 0; 372 } 373 374 void __init smp_store_boot_cpu_info(void) 375 { 376 int id = 0; /* CPU 0 */ 377 struct cpuinfo_x86 *c = &cpu_data(id); 378 379 *c = boot_cpu_data; 380 c->cpu_index = id; 381 topology_update_package_map(c->phys_proc_id, id); 382 topology_update_die_map(c->cpu_die_id, id); 383 c->initialized = true; 384 } 385 386 /* 387 * The bootstrap kernel entry code has set these up. Save them for 388 * a given CPU 389 */ 390 void smp_store_cpu_info(int id) 391 { 392 struct cpuinfo_x86 *c = &cpu_data(id); 393 394 /* Copy boot_cpu_data only on the first bringup */ 395 if (!c->initialized) 396 *c = boot_cpu_data; 397 c->cpu_index = id; 398 /* 399 * During boot time, CPU0 has this setup already. Save the info when 400 * bringing up AP or offlined CPU0. 401 */ 402 identify_secondary_cpu(c); 403 c->initialized = true; 404 } 405 406 static bool 407 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 408 { 409 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 410 411 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 412 } 413 414 static bool 415 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 416 { 417 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 418 419 return !WARN_ONCE(!topology_same_node(c, o), 420 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 421 "[node: %d != %d]. Ignoring dependency.\n", 422 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 423 } 424 425 #define link_mask(mfunc, c1, c2) \ 426 do { \ 427 cpumask_set_cpu((c1), mfunc(c2)); \ 428 cpumask_set_cpu((c2), mfunc(c1)); \ 429 } while (0) 430 431 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 432 { 433 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 434 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 435 436 if (c->phys_proc_id == o->phys_proc_id && 437 c->cpu_die_id == o->cpu_die_id && 438 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 439 if (c->cpu_core_id == o->cpu_core_id) 440 return topology_sane(c, o, "smt"); 441 442 if ((c->cu_id != 0xff) && 443 (o->cu_id != 0xff) && 444 (c->cu_id == o->cu_id)) 445 return topology_sane(c, o, "smt"); 446 } 447 448 } else if (c->phys_proc_id == o->phys_proc_id && 449 c->cpu_die_id == o->cpu_die_id && 450 c->cpu_core_id == o->cpu_core_id) { 451 return topology_sane(c, o, "smt"); 452 } 453 454 return false; 455 } 456 457 /* 458 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 459 * 460 * These are Intel CPUs that enumerate an LLC that is shared by 461 * multiple NUMA nodes. The LLC on these systems is shared for 462 * off-package data access but private to the NUMA node (half 463 * of the package) for on-package access. 464 * 465 * CPUID (the source of the information about the LLC) can only 466 * enumerate the cache as being shared *or* unshared, but not 467 * this particular configuration. The CPU in this case enumerates 468 * the cache to be shared across the entire package (spanning both 469 * NUMA nodes). 470 */ 471 472 static const struct x86_cpu_id snc_cpu[] = { 473 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), 474 {} 475 }; 476 477 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 478 { 479 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 480 481 /* Do not match if we do not have a valid APICID for cpu: */ 482 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 483 return false; 484 485 /* Do not match if LLC id does not match: */ 486 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 487 return false; 488 489 /* 490 * Allow the SNC topology without warning. Return of false 491 * means 'c' does not share the LLC of 'o'. This will be 492 * reflected to userspace. 493 */ 494 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 495 return false; 496 497 return topology_sane(c, o, "llc"); 498 } 499 500 /* 501 * Unlike the other levels, we do not enforce keeping a 502 * multicore group inside a NUMA node. If this happens, we will 503 * discard the MC level of the topology later. 504 */ 505 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 506 { 507 if (c->phys_proc_id == o->phys_proc_id) 508 return true; 509 return false; 510 } 511 512 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 513 { 514 if ((c->phys_proc_id == o->phys_proc_id) && 515 (c->cpu_die_id == o->cpu_die_id)) 516 return true; 517 return false; 518 } 519 520 521 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 522 static inline int x86_sched_itmt_flags(void) 523 { 524 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 525 } 526 527 #ifdef CONFIG_SCHED_MC 528 static int x86_core_flags(void) 529 { 530 return cpu_core_flags() | x86_sched_itmt_flags(); 531 } 532 #endif 533 #ifdef CONFIG_SCHED_SMT 534 static int x86_smt_flags(void) 535 { 536 return cpu_smt_flags() | x86_sched_itmt_flags(); 537 } 538 #endif 539 #endif 540 541 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 542 #ifdef CONFIG_SCHED_SMT 543 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 544 #endif 545 #ifdef CONFIG_SCHED_MC 546 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 547 #endif 548 { NULL, }, 549 }; 550 551 static struct sched_domain_topology_level x86_topology[] = { 552 #ifdef CONFIG_SCHED_SMT 553 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 554 #endif 555 #ifdef CONFIG_SCHED_MC 556 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 557 #endif 558 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 559 { NULL, }, 560 }; 561 562 /* 563 * Set if a package/die has multiple NUMA nodes inside. 564 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 565 * Sub-NUMA Clustering have this. 566 */ 567 static bool x86_has_numa_in_package; 568 569 void set_cpu_sibling_map(int cpu) 570 { 571 bool has_smt = smp_num_siblings > 1; 572 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 573 struct cpuinfo_x86 *c = &cpu_data(cpu); 574 struct cpuinfo_x86 *o; 575 int i, threads; 576 577 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 578 579 if (!has_mp) { 580 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 581 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 582 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 583 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 584 c->booted_cores = 1; 585 return; 586 } 587 588 for_each_cpu(i, cpu_sibling_setup_mask) { 589 o = &cpu_data(i); 590 591 if ((i == cpu) || (has_smt && match_smt(c, o))) 592 link_mask(topology_sibling_cpumask, cpu, i); 593 594 if ((i == cpu) || (has_mp && match_llc(c, o))) 595 link_mask(cpu_llc_shared_mask, cpu, i); 596 597 } 598 599 /* 600 * This needs a separate iteration over the cpus because we rely on all 601 * topology_sibling_cpumask links to be set-up. 602 */ 603 for_each_cpu(i, cpu_sibling_setup_mask) { 604 o = &cpu_data(i); 605 606 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 607 link_mask(topology_core_cpumask, cpu, i); 608 609 /* 610 * Does this new cpu bringup a new core? 611 */ 612 if (cpumask_weight( 613 topology_sibling_cpumask(cpu)) == 1) { 614 /* 615 * for each core in package, increment 616 * the booted_cores for this new cpu 617 */ 618 if (cpumask_first( 619 topology_sibling_cpumask(i)) == i) 620 c->booted_cores++; 621 /* 622 * increment the core count for all 623 * the other cpus in this package 624 */ 625 if (i != cpu) 626 cpu_data(i).booted_cores++; 627 } else if (i != cpu && !c->booted_cores) 628 c->booted_cores = cpu_data(i).booted_cores; 629 } 630 if (match_pkg(c, o) && !topology_same_node(c, o)) 631 x86_has_numa_in_package = true; 632 633 if ((i == cpu) || (has_mp && match_die(c, o))) 634 link_mask(topology_die_cpumask, cpu, i); 635 } 636 637 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 638 if (threads > __max_smt_threads) 639 __max_smt_threads = threads; 640 } 641 642 /* maps the cpu to the sched domain representing multi-core */ 643 const struct cpumask *cpu_coregroup_mask(int cpu) 644 { 645 return cpu_llc_shared_mask(cpu); 646 } 647 648 static void impress_friends(void) 649 { 650 int cpu; 651 unsigned long bogosum = 0; 652 /* 653 * Allow the user to impress friends. 654 */ 655 pr_debug("Before bogomips\n"); 656 for_each_possible_cpu(cpu) 657 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 658 bogosum += cpu_data(cpu).loops_per_jiffy; 659 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 660 num_online_cpus(), 661 bogosum/(500000/HZ), 662 (bogosum/(5000/HZ))%100); 663 664 pr_debug("Before bogocount - setting activated=1\n"); 665 } 666 667 void __inquire_remote_apic(int apicid) 668 { 669 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 670 const char * const names[] = { "ID", "VERSION", "SPIV" }; 671 int timeout; 672 u32 status; 673 674 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 675 676 for (i = 0; i < ARRAY_SIZE(regs); i++) { 677 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 678 679 /* 680 * Wait for idle. 681 */ 682 status = safe_apic_wait_icr_idle(); 683 if (status) 684 pr_cont("a previous APIC delivery may have failed\n"); 685 686 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 687 688 timeout = 0; 689 do { 690 udelay(100); 691 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 692 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 693 694 switch (status) { 695 case APIC_ICR_RR_VALID: 696 status = apic_read(APIC_RRR); 697 pr_cont("%08x\n", status); 698 break; 699 default: 700 pr_cont("failed\n"); 701 } 702 } 703 } 704 705 /* 706 * The Multiprocessor Specification 1.4 (1997) example code suggests 707 * that there should be a 10ms delay between the BSP asserting INIT 708 * and de-asserting INIT, when starting a remote processor. 709 * But that slows boot and resume on modern processors, which include 710 * many cores and don't require that delay. 711 * 712 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 713 * Modern processor families are quirked to remove the delay entirely. 714 */ 715 #define UDELAY_10MS_DEFAULT 10000 716 717 static unsigned int init_udelay = UINT_MAX; 718 719 static int __init cpu_init_udelay(char *str) 720 { 721 get_option(&str, &init_udelay); 722 723 return 0; 724 } 725 early_param("cpu_init_udelay", cpu_init_udelay); 726 727 static void __init smp_quirk_init_udelay(void) 728 { 729 /* if cmdline changed it from default, leave it alone */ 730 if (init_udelay != UINT_MAX) 731 return; 732 733 /* if modern processor, use no delay */ 734 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 735 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 736 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 737 init_udelay = 0; 738 return; 739 } 740 /* else, use legacy delay */ 741 init_udelay = UDELAY_10MS_DEFAULT; 742 } 743 744 /* 745 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 746 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 747 * won't ... remember to clear down the APIC, etc later. 748 */ 749 int 750 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 751 { 752 unsigned long send_status, accept_status = 0; 753 int maxlvt; 754 755 /* Target chip */ 756 /* Boot on the stack */ 757 /* Kick the second */ 758 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 759 760 pr_debug("Waiting for send to finish...\n"); 761 send_status = safe_apic_wait_icr_idle(); 762 763 /* 764 * Give the other CPU some time to accept the IPI. 765 */ 766 udelay(200); 767 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 768 maxlvt = lapic_get_maxlvt(); 769 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 770 apic_write(APIC_ESR, 0); 771 accept_status = (apic_read(APIC_ESR) & 0xEF); 772 } 773 pr_debug("NMI sent\n"); 774 775 if (send_status) 776 pr_err("APIC never delivered???\n"); 777 if (accept_status) 778 pr_err("APIC delivery error (%lx)\n", accept_status); 779 780 return (send_status | accept_status); 781 } 782 783 static int 784 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 785 { 786 unsigned long send_status = 0, accept_status = 0; 787 int maxlvt, num_starts, j; 788 789 maxlvt = lapic_get_maxlvt(); 790 791 /* 792 * Be paranoid about clearing APIC errors. 793 */ 794 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 795 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 796 apic_write(APIC_ESR, 0); 797 apic_read(APIC_ESR); 798 } 799 800 pr_debug("Asserting INIT\n"); 801 802 /* 803 * Turn INIT on target chip 804 */ 805 /* 806 * Send IPI 807 */ 808 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 809 phys_apicid); 810 811 pr_debug("Waiting for send to finish...\n"); 812 send_status = safe_apic_wait_icr_idle(); 813 814 udelay(init_udelay); 815 816 pr_debug("Deasserting INIT\n"); 817 818 /* Target chip */ 819 /* Send IPI */ 820 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 821 822 pr_debug("Waiting for send to finish...\n"); 823 send_status = safe_apic_wait_icr_idle(); 824 825 mb(); 826 827 /* 828 * Should we send STARTUP IPIs ? 829 * 830 * Determine this based on the APIC version. 831 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 832 */ 833 if (APIC_INTEGRATED(boot_cpu_apic_version)) 834 num_starts = 2; 835 else 836 num_starts = 0; 837 838 /* 839 * Run STARTUP IPI loop. 840 */ 841 pr_debug("#startup loops: %d\n", num_starts); 842 843 for (j = 1; j <= num_starts; j++) { 844 pr_debug("Sending STARTUP #%d\n", j); 845 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 846 apic_write(APIC_ESR, 0); 847 apic_read(APIC_ESR); 848 pr_debug("After apic_write\n"); 849 850 /* 851 * STARTUP IPI 852 */ 853 854 /* Target chip */ 855 /* Boot on the stack */ 856 /* Kick the second */ 857 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 858 phys_apicid); 859 860 /* 861 * Give the other CPU some time to accept the IPI. 862 */ 863 if (init_udelay == 0) 864 udelay(10); 865 else 866 udelay(300); 867 868 pr_debug("Startup point 1\n"); 869 870 pr_debug("Waiting for send to finish...\n"); 871 send_status = safe_apic_wait_icr_idle(); 872 873 /* 874 * Give the other CPU some time to accept the IPI. 875 */ 876 if (init_udelay == 0) 877 udelay(10); 878 else 879 udelay(200); 880 881 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 882 apic_write(APIC_ESR, 0); 883 accept_status = (apic_read(APIC_ESR) & 0xEF); 884 if (send_status || accept_status) 885 break; 886 } 887 pr_debug("After Startup\n"); 888 889 if (send_status) 890 pr_err("APIC never delivered???\n"); 891 if (accept_status) 892 pr_err("APIC delivery error (%lx)\n", accept_status); 893 894 return (send_status | accept_status); 895 } 896 897 /* reduce the number of lines printed when booting a large cpu count system */ 898 static void announce_cpu(int cpu, int apicid) 899 { 900 static int current_node = NUMA_NO_NODE; 901 int node = early_cpu_to_node(cpu); 902 static int width, node_width; 903 904 if (!width) 905 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 906 907 if (!node_width) 908 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 909 910 if (cpu == 1) 911 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 912 913 if (system_state < SYSTEM_RUNNING) { 914 if (node != current_node) { 915 if (current_node > (-1)) 916 pr_cont("\n"); 917 current_node = node; 918 919 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 920 node_width - num_digits(node), " ", node); 921 } 922 923 /* Add padding for the BSP */ 924 if (cpu == 1) 925 pr_cont("%*s", width + 1, " "); 926 927 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 928 929 } else 930 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 931 node, cpu, apicid); 932 } 933 934 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 935 { 936 int cpu; 937 938 cpu = smp_processor_id(); 939 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 940 return NMI_HANDLED; 941 942 return NMI_DONE; 943 } 944 945 /* 946 * Wake up AP by INIT, INIT, STARTUP sequence. 947 * 948 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 949 * boot-strap code which is not a desired behavior for waking up BSP. To 950 * void the boot-strap code, wake up CPU0 by NMI instead. 951 * 952 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 953 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 954 * We'll change this code in the future to wake up hard offlined CPU0 if 955 * real platform and request are available. 956 */ 957 static int 958 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 959 int *cpu0_nmi_registered) 960 { 961 int id; 962 int boot_error; 963 964 preempt_disable(); 965 966 /* 967 * Wake up AP by INIT, INIT, STARTUP sequence. 968 */ 969 if (cpu) { 970 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 971 goto out; 972 } 973 974 /* 975 * Wake up BSP by nmi. 976 * 977 * Register a NMI handler to help wake up CPU0. 978 */ 979 boot_error = register_nmi_handler(NMI_LOCAL, 980 wakeup_cpu0_nmi, 0, "wake_cpu0"); 981 982 if (!boot_error) { 983 enable_start_cpu0 = 1; 984 *cpu0_nmi_registered = 1; 985 if (apic->dest_logical == APIC_DEST_LOGICAL) 986 id = cpu0_logical_apicid; 987 else 988 id = apicid; 989 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 990 } 991 992 out: 993 preempt_enable(); 994 995 return boot_error; 996 } 997 998 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 999 { 1000 int ret; 1001 1002 /* Just in case we booted with a single CPU. */ 1003 alternatives_enable_smp(); 1004 1005 per_cpu(current_task, cpu) = idle; 1006 1007 /* Initialize the interrupt stack(s) */ 1008 ret = irq_init_percpu_irqstack(cpu); 1009 if (ret) 1010 return ret; 1011 1012 #ifdef CONFIG_X86_32 1013 /* Stack for startup_32 can be just as for start_secondary onwards */ 1014 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 1015 #else 1016 initial_gs = per_cpu_offset(cpu); 1017 #endif 1018 return 0; 1019 } 1020 1021 /* 1022 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1023 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1024 * Returns zero if CPU booted OK, else error code from 1025 * ->wakeup_secondary_cpu. 1026 */ 1027 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1028 int *cpu0_nmi_registered) 1029 { 1030 /* start_ip had better be page-aligned! */ 1031 unsigned long start_ip = real_mode_header->trampoline_start; 1032 1033 unsigned long boot_error = 0; 1034 unsigned long timeout; 1035 1036 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1037 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1038 initial_code = (unsigned long)start_secondary; 1039 initial_stack = idle->thread.sp; 1040 1041 /* Enable the espfix hack for this CPU */ 1042 init_espfix_ap(cpu); 1043 1044 /* So we see what's up */ 1045 announce_cpu(cpu, apicid); 1046 1047 /* 1048 * This grunge runs the startup process for 1049 * the targeted processor. 1050 */ 1051 1052 if (x86_platform.legacy.warm_reset) { 1053 1054 pr_debug("Setting warm reset code and vector.\n"); 1055 1056 smpboot_setup_warm_reset_vector(start_ip); 1057 /* 1058 * Be paranoid about clearing APIC errors. 1059 */ 1060 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1061 apic_write(APIC_ESR, 0); 1062 apic_read(APIC_ESR); 1063 } 1064 } 1065 1066 /* 1067 * AP might wait on cpu_callout_mask in cpu_init() with 1068 * cpu_initialized_mask set if previous attempt to online 1069 * it timed-out. Clear cpu_initialized_mask so that after 1070 * INIT/SIPI it could start with a clean state. 1071 */ 1072 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1073 smp_mb(); 1074 1075 /* 1076 * Wake up a CPU in difference cases: 1077 * - Use the method in the APIC driver if it's defined 1078 * Otherwise, 1079 * - Use an INIT boot APIC message for APs or NMI for BSP. 1080 */ 1081 if (apic->wakeup_secondary_cpu) 1082 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1083 else 1084 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1085 cpu0_nmi_registered); 1086 1087 if (!boot_error) { 1088 /* 1089 * Wait 10s total for first sign of life from AP 1090 */ 1091 boot_error = -1; 1092 timeout = jiffies + 10*HZ; 1093 while (time_before(jiffies, timeout)) { 1094 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1095 /* 1096 * Tell AP to proceed with initialization 1097 */ 1098 cpumask_set_cpu(cpu, cpu_callout_mask); 1099 boot_error = 0; 1100 break; 1101 } 1102 schedule(); 1103 } 1104 } 1105 1106 if (!boot_error) { 1107 /* 1108 * Wait till AP completes initial initialization 1109 */ 1110 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1111 /* 1112 * Allow other tasks to run while we wait for the 1113 * AP to come online. This also gives a chance 1114 * for the MTRR work(triggered by the AP coming online) 1115 * to be completed in the stop machine context. 1116 */ 1117 schedule(); 1118 } 1119 } 1120 1121 if (x86_platform.legacy.warm_reset) { 1122 /* 1123 * Cleanup possible dangling ends... 1124 */ 1125 smpboot_restore_warm_reset_vector(); 1126 } 1127 1128 return boot_error; 1129 } 1130 1131 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1132 { 1133 int apicid = apic->cpu_present_to_apicid(cpu); 1134 int cpu0_nmi_registered = 0; 1135 unsigned long flags; 1136 int err, ret = 0; 1137 1138 lockdep_assert_irqs_enabled(); 1139 1140 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1141 1142 if (apicid == BAD_APICID || 1143 !physid_isset(apicid, phys_cpu_present_map) || 1144 !apic->apic_id_valid(apicid)) { 1145 pr_err("%s: bad cpu %d\n", __func__, cpu); 1146 return -EINVAL; 1147 } 1148 1149 /* 1150 * Already booted CPU? 1151 */ 1152 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1153 pr_debug("do_boot_cpu %d Already started\n", cpu); 1154 return -ENOSYS; 1155 } 1156 1157 /* 1158 * Save current MTRR state in case it was changed since early boot 1159 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1160 */ 1161 mtrr_save_state(); 1162 1163 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1164 err = cpu_check_up_prepare(cpu); 1165 if (err && err != -EBUSY) 1166 return err; 1167 1168 /* the FPU context is blank, nobody can own it */ 1169 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1170 1171 err = common_cpu_up(cpu, tidle); 1172 if (err) 1173 return err; 1174 1175 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1176 if (err) { 1177 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1178 ret = -EIO; 1179 goto unreg_nmi; 1180 } 1181 1182 /* 1183 * Check TSC synchronization with the AP (keep irqs disabled 1184 * while doing so): 1185 */ 1186 local_irq_save(flags); 1187 check_tsc_sync_source(cpu); 1188 local_irq_restore(flags); 1189 1190 while (!cpu_online(cpu)) { 1191 cpu_relax(); 1192 touch_nmi_watchdog(); 1193 } 1194 1195 unreg_nmi: 1196 /* 1197 * Clean up the nmi handler. Do this after the callin and callout sync 1198 * to avoid impact of possible long unregister time. 1199 */ 1200 if (cpu0_nmi_registered) 1201 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1202 1203 return ret; 1204 } 1205 1206 /** 1207 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1208 */ 1209 void arch_disable_smp_support(void) 1210 { 1211 disable_ioapic_support(); 1212 } 1213 1214 /* 1215 * Fall back to non SMP mode after errors. 1216 * 1217 * RED-PEN audit/test this more. I bet there is more state messed up here. 1218 */ 1219 static __init void disable_smp(void) 1220 { 1221 pr_info("SMP disabled\n"); 1222 1223 disable_ioapic_support(); 1224 1225 init_cpu_present(cpumask_of(0)); 1226 init_cpu_possible(cpumask_of(0)); 1227 1228 if (smp_found_config) 1229 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1230 else 1231 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1232 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1233 cpumask_set_cpu(0, topology_core_cpumask(0)); 1234 cpumask_set_cpu(0, topology_die_cpumask(0)); 1235 } 1236 1237 /* 1238 * Various sanity checks. 1239 */ 1240 static void __init smp_sanity_check(void) 1241 { 1242 preempt_disable(); 1243 1244 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1245 if (def_to_bigsmp && nr_cpu_ids > 8) { 1246 unsigned int cpu; 1247 unsigned nr; 1248 1249 pr_warn("More than 8 CPUs detected - skipping them\n" 1250 "Use CONFIG_X86_BIGSMP\n"); 1251 1252 nr = 0; 1253 for_each_present_cpu(cpu) { 1254 if (nr >= 8) 1255 set_cpu_present(cpu, false); 1256 nr++; 1257 } 1258 1259 nr = 0; 1260 for_each_possible_cpu(cpu) { 1261 if (nr >= 8) 1262 set_cpu_possible(cpu, false); 1263 nr++; 1264 } 1265 1266 nr_cpu_ids = 8; 1267 } 1268 #endif 1269 1270 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1271 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1272 hard_smp_processor_id()); 1273 1274 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1275 } 1276 1277 /* 1278 * Should not be necessary because the MP table should list the boot 1279 * CPU too, but we do it for the sake of robustness anyway. 1280 */ 1281 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1282 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1283 boot_cpu_physical_apicid); 1284 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1285 } 1286 preempt_enable(); 1287 } 1288 1289 static void __init smp_cpu_index_default(void) 1290 { 1291 int i; 1292 struct cpuinfo_x86 *c; 1293 1294 for_each_possible_cpu(i) { 1295 c = &cpu_data(i); 1296 /* mark all to hotplug */ 1297 c->cpu_index = nr_cpu_ids; 1298 } 1299 } 1300 1301 static void __init smp_get_logical_apicid(void) 1302 { 1303 if (x2apic_mode) 1304 cpu0_logical_apicid = apic_read(APIC_LDR); 1305 else 1306 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1307 } 1308 1309 /* 1310 * Prepare for SMP bootup. 1311 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1312 * for common interface support. 1313 */ 1314 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1315 { 1316 unsigned int i; 1317 1318 smp_cpu_index_default(); 1319 1320 /* 1321 * Setup boot CPU information 1322 */ 1323 smp_store_boot_cpu_info(); /* Final full version of the data */ 1324 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1325 mb(); 1326 1327 for_each_possible_cpu(i) { 1328 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1329 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1330 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1331 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1332 } 1333 1334 /* 1335 * Set 'default' x86 topology, this matches default_topology() in that 1336 * it has NUMA nodes as a topology level. See also 1337 * native_smp_cpus_done(). 1338 * 1339 * Must be done before set_cpus_sibling_map() is ran. 1340 */ 1341 set_sched_topology(x86_topology); 1342 1343 set_cpu_sibling_map(0); 1344 init_freq_invariance(); 1345 smp_sanity_check(); 1346 1347 switch (apic_intr_mode) { 1348 case APIC_PIC: 1349 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1350 disable_smp(); 1351 return; 1352 case APIC_SYMMETRIC_IO_NO_ROUTING: 1353 disable_smp(); 1354 /* Setup local timer */ 1355 x86_init.timers.setup_percpu_clockev(); 1356 return; 1357 case APIC_VIRTUAL_WIRE: 1358 case APIC_SYMMETRIC_IO: 1359 break; 1360 } 1361 1362 /* Setup local timer */ 1363 x86_init.timers.setup_percpu_clockev(); 1364 1365 smp_get_logical_apicid(); 1366 1367 pr_info("CPU0: "); 1368 print_cpu_info(&cpu_data(0)); 1369 1370 uv_system_init(); 1371 1372 set_mtrr_aps_delayed_init(); 1373 1374 smp_quirk_init_udelay(); 1375 1376 speculative_store_bypass_ht_init(); 1377 } 1378 1379 void arch_enable_nonboot_cpus_begin(void) 1380 { 1381 set_mtrr_aps_delayed_init(); 1382 } 1383 1384 void arch_enable_nonboot_cpus_end(void) 1385 { 1386 mtrr_aps_init(); 1387 } 1388 1389 /* 1390 * Early setup to make printk work. 1391 */ 1392 void __init native_smp_prepare_boot_cpu(void) 1393 { 1394 int me = smp_processor_id(); 1395 switch_to_new_gdt(me); 1396 /* already set me in cpu_online_mask in boot_cpu_init() */ 1397 cpumask_set_cpu(me, cpu_callout_mask); 1398 cpu_set_state_online(me); 1399 native_pv_lock_init(); 1400 } 1401 1402 void __init calculate_max_logical_packages(void) 1403 { 1404 int ncpus; 1405 1406 /* 1407 * Today neither Intel nor AMD support heterogenous systems so 1408 * extrapolate the boot cpu's data to all packages. 1409 */ 1410 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1411 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1412 pr_info("Max logical packages: %u\n", __max_logical_packages); 1413 } 1414 1415 void __init native_smp_cpus_done(unsigned int max_cpus) 1416 { 1417 pr_debug("Boot done\n"); 1418 1419 calculate_max_logical_packages(); 1420 1421 if (x86_has_numa_in_package) 1422 set_sched_topology(x86_numa_in_package_topology); 1423 1424 nmi_selftest(); 1425 impress_friends(); 1426 mtrr_aps_init(); 1427 } 1428 1429 static int __initdata setup_possible_cpus = -1; 1430 static int __init _setup_possible_cpus(char *str) 1431 { 1432 get_option(&str, &setup_possible_cpus); 1433 return 0; 1434 } 1435 early_param("possible_cpus", _setup_possible_cpus); 1436 1437 1438 /* 1439 * cpu_possible_mask should be static, it cannot change as cpu's 1440 * are onlined, or offlined. The reason is per-cpu data-structures 1441 * are allocated by some modules at init time, and don't expect to 1442 * do this dynamically on cpu arrival/departure. 1443 * cpu_present_mask on the other hand can change dynamically. 1444 * In case when cpu_hotplug is not compiled, then we resort to current 1445 * behaviour, which is cpu_possible == cpu_present. 1446 * - Ashok Raj 1447 * 1448 * Three ways to find out the number of additional hotplug CPUs: 1449 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1450 * - The user can overwrite it with possible_cpus=NUM 1451 * - Otherwise don't reserve additional CPUs. 1452 * We do this because additional CPUs waste a lot of memory. 1453 * -AK 1454 */ 1455 __init void prefill_possible_map(void) 1456 { 1457 int i, possible; 1458 1459 /* No boot processor was found in mptable or ACPI MADT */ 1460 if (!num_processors) { 1461 if (boot_cpu_has(X86_FEATURE_APIC)) { 1462 int apicid = boot_cpu_physical_apicid; 1463 int cpu = hard_smp_processor_id(); 1464 1465 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1466 1467 /* Make sure boot cpu is enumerated */ 1468 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1469 apic->apic_id_valid(apicid)) 1470 generic_processor_info(apicid, boot_cpu_apic_version); 1471 } 1472 1473 if (!num_processors) 1474 num_processors = 1; 1475 } 1476 1477 i = setup_max_cpus ?: 1; 1478 if (setup_possible_cpus == -1) { 1479 possible = num_processors; 1480 #ifdef CONFIG_HOTPLUG_CPU 1481 if (setup_max_cpus) 1482 possible += disabled_cpus; 1483 #else 1484 if (possible > i) 1485 possible = i; 1486 #endif 1487 } else 1488 possible = setup_possible_cpus; 1489 1490 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1491 1492 /* nr_cpu_ids could be reduced via nr_cpus= */ 1493 if (possible > nr_cpu_ids) { 1494 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1495 possible, nr_cpu_ids); 1496 possible = nr_cpu_ids; 1497 } 1498 1499 #ifdef CONFIG_HOTPLUG_CPU 1500 if (!setup_max_cpus) 1501 #endif 1502 if (possible > i) { 1503 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1504 possible, setup_max_cpus); 1505 possible = i; 1506 } 1507 1508 nr_cpu_ids = possible; 1509 1510 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1511 possible, max_t(int, possible - num_processors, 0)); 1512 1513 reset_cpu_possible_mask(); 1514 1515 for (i = 0; i < possible; i++) 1516 set_cpu_possible(i, true); 1517 } 1518 1519 #ifdef CONFIG_HOTPLUG_CPU 1520 1521 /* Recompute SMT state for all CPUs on offline */ 1522 static void recompute_smt_state(void) 1523 { 1524 int max_threads, cpu; 1525 1526 max_threads = 0; 1527 for_each_online_cpu (cpu) { 1528 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1529 1530 if (threads > max_threads) 1531 max_threads = threads; 1532 } 1533 __max_smt_threads = max_threads; 1534 } 1535 1536 static void remove_siblinginfo(int cpu) 1537 { 1538 int sibling; 1539 struct cpuinfo_x86 *c = &cpu_data(cpu); 1540 1541 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1542 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1543 /*/ 1544 * last thread sibling in this cpu core going down 1545 */ 1546 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1547 cpu_data(sibling).booted_cores--; 1548 } 1549 1550 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1551 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1552 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1553 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1554 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1555 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1556 cpumask_clear(cpu_llc_shared_mask(cpu)); 1557 cpumask_clear(topology_sibling_cpumask(cpu)); 1558 cpumask_clear(topology_core_cpumask(cpu)); 1559 cpumask_clear(topology_die_cpumask(cpu)); 1560 c->cpu_core_id = 0; 1561 c->booted_cores = 0; 1562 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1563 recompute_smt_state(); 1564 } 1565 1566 static void remove_cpu_from_maps(int cpu) 1567 { 1568 set_cpu_online(cpu, false); 1569 cpumask_clear_cpu(cpu, cpu_callout_mask); 1570 cpumask_clear_cpu(cpu, cpu_callin_mask); 1571 /* was set by cpu_init() */ 1572 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1573 numa_remove_cpu(cpu); 1574 } 1575 1576 void cpu_disable_common(void) 1577 { 1578 int cpu = smp_processor_id(); 1579 1580 remove_siblinginfo(cpu); 1581 1582 /* It's now safe to remove this processor from the online map */ 1583 lock_vector_lock(); 1584 remove_cpu_from_maps(cpu); 1585 unlock_vector_lock(); 1586 fixup_irqs(); 1587 lapic_offline(); 1588 } 1589 1590 int native_cpu_disable(void) 1591 { 1592 int ret; 1593 1594 ret = lapic_can_unplug_cpu(); 1595 if (ret) 1596 return ret; 1597 1598 /* 1599 * Disable the local APIC. Otherwise IPI broadcasts will reach 1600 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1601 * messages. 1602 */ 1603 apic_soft_disable(); 1604 cpu_disable_common(); 1605 1606 return 0; 1607 } 1608 1609 int common_cpu_die(unsigned int cpu) 1610 { 1611 int ret = 0; 1612 1613 /* We don't do anything here: idle task is faking death itself. */ 1614 1615 /* They ack this in play_dead() by setting CPU_DEAD */ 1616 if (cpu_wait_death(cpu, 5)) { 1617 if (system_state == SYSTEM_RUNNING) 1618 pr_info("CPU %u is now offline\n", cpu); 1619 } else { 1620 pr_err("CPU %u didn't die...\n", cpu); 1621 ret = -1; 1622 } 1623 1624 return ret; 1625 } 1626 1627 void native_cpu_die(unsigned int cpu) 1628 { 1629 common_cpu_die(cpu); 1630 } 1631 1632 void play_dead_common(void) 1633 { 1634 idle_task_exit(); 1635 1636 /* Ack it */ 1637 (void)cpu_report_death(); 1638 1639 /* 1640 * With physical CPU hotplug, we should halt the cpu 1641 */ 1642 local_irq_disable(); 1643 } 1644 1645 static bool wakeup_cpu0(void) 1646 { 1647 if (smp_processor_id() == 0 && enable_start_cpu0) 1648 return true; 1649 1650 return false; 1651 } 1652 1653 /* 1654 * We need to flush the caches before going to sleep, lest we have 1655 * dirty data in our caches when we come back up. 1656 */ 1657 static inline void mwait_play_dead(void) 1658 { 1659 unsigned int eax, ebx, ecx, edx; 1660 unsigned int highest_cstate = 0; 1661 unsigned int highest_subcstate = 0; 1662 void *mwait_ptr; 1663 int i; 1664 1665 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1666 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1667 return; 1668 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1669 return; 1670 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1671 return; 1672 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1673 return; 1674 1675 eax = CPUID_MWAIT_LEAF; 1676 ecx = 0; 1677 native_cpuid(&eax, &ebx, &ecx, &edx); 1678 1679 /* 1680 * eax will be 0 if EDX enumeration is not valid. 1681 * Initialized below to cstate, sub_cstate value when EDX is valid. 1682 */ 1683 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1684 eax = 0; 1685 } else { 1686 edx >>= MWAIT_SUBSTATE_SIZE; 1687 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1688 if (edx & MWAIT_SUBSTATE_MASK) { 1689 highest_cstate = i; 1690 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1691 } 1692 } 1693 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1694 (highest_subcstate - 1); 1695 } 1696 1697 /* 1698 * This should be a memory location in a cache line which is 1699 * unlikely to be touched by other processors. The actual 1700 * content is immaterial as it is not actually modified in any way. 1701 */ 1702 mwait_ptr = ¤t_thread_info()->flags; 1703 1704 wbinvd(); 1705 1706 while (1) { 1707 /* 1708 * The CLFLUSH is a workaround for erratum AAI65 for 1709 * the Xeon 7400 series. It's not clear it is actually 1710 * needed, but it should be harmless in either case. 1711 * The WBINVD is insufficient due to the spurious-wakeup 1712 * case where we return around the loop. 1713 */ 1714 mb(); 1715 clflush(mwait_ptr); 1716 mb(); 1717 __monitor(mwait_ptr, 0, 0); 1718 mb(); 1719 __mwait(eax, 0); 1720 /* 1721 * If NMI wants to wake up CPU0, start CPU0. 1722 */ 1723 if (wakeup_cpu0()) 1724 start_cpu0(); 1725 } 1726 } 1727 1728 void hlt_play_dead(void) 1729 { 1730 if (__this_cpu_read(cpu_info.x86) >= 4) 1731 wbinvd(); 1732 1733 while (1) { 1734 native_halt(); 1735 /* 1736 * If NMI wants to wake up CPU0, start CPU0. 1737 */ 1738 if (wakeup_cpu0()) 1739 start_cpu0(); 1740 } 1741 } 1742 1743 void native_play_dead(void) 1744 { 1745 play_dead_common(); 1746 tboot_shutdown(TB_SHUTDOWN_WFS); 1747 1748 mwait_play_dead(); /* Only returns on failure */ 1749 if (cpuidle_play_dead()) 1750 hlt_play_dead(); 1751 } 1752 1753 #else /* ... !CONFIG_HOTPLUG_CPU */ 1754 int native_cpu_disable(void) 1755 { 1756 return -ENOSYS; 1757 } 1758 1759 void native_cpu_die(unsigned int cpu) 1760 { 1761 /* We said "no" in __cpu_disable */ 1762 BUG(); 1763 } 1764 1765 void native_play_dead(void) 1766 { 1767 BUG(); 1768 } 1769 1770 #endif 1771 1772 /* 1773 * APERF/MPERF frequency ratio computation. 1774 * 1775 * The scheduler wants to do frequency invariant accounting and needs a <1 1776 * ratio to account for the 'current' frequency, corresponding to 1777 * freq_curr / freq_max. 1778 * 1779 * Since the frequency freq_curr on x86 is controlled by micro-controller and 1780 * our P-state setting is little more than a request/hint, we need to observe 1781 * the effective frequency 'BusyMHz', i.e. the average frequency over a time 1782 * interval after discarding idle time. This is given by: 1783 * 1784 * BusyMHz = delta_APERF / delta_MPERF * freq_base 1785 * 1786 * where freq_base is the max non-turbo P-state. 1787 * 1788 * The freq_max term has to be set to a somewhat arbitrary value, because we 1789 * can't know which turbo states will be available at a given point in time: 1790 * it all depends on the thermal headroom of the entire package. We set it to 1791 * the turbo level with 4 cores active. 1792 * 1793 * Benchmarks show that's a good compromise between the 1C turbo ratio 1794 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, 1795 * which would ignore the entire turbo range (a conspicuous part, making 1796 * freq_curr/freq_max always maxed out). 1797 * 1798 * An exception to the heuristic above is the Atom uarch, where we choose the 1799 * highest turbo level for freq_max since Atom's are generally oriented towards 1800 * power efficiency. 1801 * 1802 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio 1803 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. 1804 */ 1805 1806 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); 1807 1808 static DEFINE_PER_CPU(u64, arch_prev_aperf); 1809 static DEFINE_PER_CPU(u64, arch_prev_mperf); 1810 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; 1811 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; 1812 1813 void arch_set_max_freq_ratio(bool turbo_disabled) 1814 { 1815 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : 1816 arch_turbo_freq_ratio; 1817 } 1818 1819 static bool turbo_disabled(void) 1820 { 1821 u64 misc_en; 1822 int err; 1823 1824 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); 1825 if (err) 1826 return false; 1827 1828 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 1829 } 1830 1831 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1832 { 1833 int err; 1834 1835 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); 1836 if (err) 1837 return false; 1838 1839 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); 1840 if (err) 1841 return false; 1842 1843 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ 1844 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ 1845 1846 return true; 1847 } 1848 1849 #include <asm/cpu_device_id.h> 1850 #include <asm/intel-family.h> 1851 1852 #define ICPU(model) \ 1853 {X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF, 0} 1854 1855 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { 1856 ICPU(INTEL_FAM6_XEON_PHI_KNL), 1857 ICPU(INTEL_FAM6_XEON_PHI_KNM), 1858 {} 1859 }; 1860 1861 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { 1862 ICPU(INTEL_FAM6_SKYLAKE_X), 1863 {} 1864 }; 1865 1866 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { 1867 ICPU(INTEL_FAM6_ATOM_GOLDMONT), 1868 ICPU(INTEL_FAM6_ATOM_GOLDMONT_D), 1869 ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS), 1870 {} 1871 }; 1872 1873 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, 1874 int num_delta_fratio) 1875 { 1876 int fratio, delta_fratio, found; 1877 int err, i; 1878 u64 msr; 1879 1880 if (!x86_match_cpu(has_knl_turbo_ratio_limits)) 1881 return false; 1882 1883 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1884 if (err) 1885 return false; 1886 1887 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1888 1889 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 1890 if (err) 1891 return false; 1892 1893 fratio = (msr >> 8) & 0xFF; 1894 i = 16; 1895 found = 0; 1896 do { 1897 if (found >= num_delta_fratio) { 1898 *turbo_freq = fratio; 1899 return true; 1900 } 1901 1902 delta_fratio = (msr >> (i + 5)) & 0x7; 1903 1904 if (delta_fratio) { 1905 found += 1; 1906 fratio -= delta_fratio; 1907 } 1908 1909 i += 8; 1910 } while (i < 64); 1911 1912 return true; 1913 } 1914 1915 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) 1916 { 1917 u64 ratios, counts; 1918 u32 group_size; 1919 int err, i; 1920 1921 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1922 if (err) 1923 return false; 1924 1925 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1926 1927 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); 1928 if (err) 1929 return false; 1930 1931 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); 1932 if (err) 1933 return false; 1934 1935 for (i = 0; i < 64; i += 8) { 1936 group_size = (counts >> i) & 0xFF; 1937 if (group_size >= size) { 1938 *turbo_freq = (ratios >> i) & 0xFF; 1939 return true; 1940 } 1941 } 1942 1943 return false; 1944 } 1945 1946 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1947 { 1948 int err; 1949 1950 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1951 if (err) 1952 return false; 1953 1954 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, turbo_freq); 1955 if (err) 1956 return false; 1957 1958 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1959 *turbo_freq = (*turbo_freq >> 24) & 0xFF; /* 4C turbo */ 1960 1961 return true; 1962 } 1963 1964 static bool intel_set_max_freq_ratio(void) 1965 { 1966 u64 base_freq, turbo_freq; 1967 1968 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) 1969 goto out; 1970 1971 if (x86_match_cpu(has_glm_turbo_ratio_limits) && 1972 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 1973 goto out; 1974 1975 if (knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 1976 goto out; 1977 1978 if (x86_match_cpu(has_skx_turbo_ratio_limits) && 1979 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) 1980 goto out; 1981 1982 if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) 1983 goto out; 1984 1985 return false; 1986 1987 out: 1988 arch_turbo_freq_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, 1989 base_freq); 1990 arch_set_max_freq_ratio(turbo_disabled()); 1991 return true; 1992 } 1993 1994 static void init_counter_refs(void *arg) 1995 { 1996 u64 aperf, mperf; 1997 1998 rdmsrl(MSR_IA32_APERF, aperf); 1999 rdmsrl(MSR_IA32_MPERF, mperf); 2000 2001 this_cpu_write(arch_prev_aperf, aperf); 2002 this_cpu_write(arch_prev_mperf, mperf); 2003 } 2004 2005 static void init_freq_invariance(void) 2006 { 2007 bool ret = false; 2008 2009 if (smp_processor_id() != 0 || !boot_cpu_has(X86_FEATURE_APERFMPERF)) 2010 return; 2011 2012 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 2013 ret = intel_set_max_freq_ratio(); 2014 2015 if (ret) { 2016 on_each_cpu(init_counter_refs, NULL, 1); 2017 static_branch_enable(&arch_scale_freq_key); 2018 } else { 2019 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); 2020 } 2021 } 2022 2023 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; 2024 2025 void arch_scale_freq_tick(void) 2026 { 2027 u64 freq_scale; 2028 u64 aperf, mperf; 2029 u64 acnt, mcnt; 2030 2031 if (!arch_scale_freq_invariant()) 2032 return; 2033 2034 rdmsrl(MSR_IA32_APERF, aperf); 2035 rdmsrl(MSR_IA32_MPERF, mperf); 2036 2037 acnt = aperf - this_cpu_read(arch_prev_aperf); 2038 mcnt = mperf - this_cpu_read(arch_prev_mperf); 2039 if (!mcnt) 2040 return; 2041 2042 this_cpu_write(arch_prev_aperf, aperf); 2043 this_cpu_write(arch_prev_mperf, mperf); 2044 2045 acnt <<= 2*SCHED_CAPACITY_SHIFT; 2046 mcnt *= arch_max_freq_ratio; 2047 2048 freq_scale = div64_u64(acnt, mcnt); 2049 2050 if (freq_scale > SCHED_CAPACITY_SCALE) 2051 freq_scale = SCHED_CAPACITY_SCALE; 2052 2053 this_cpu_write(arch_freq_scale, freq_scale); 2054 } 2055