1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/stackprotector.h> 60 61 #include <asm/acpi.h> 62 #include <asm/cacheinfo.h> 63 #include <asm/desc.h> 64 #include <asm/nmi.h> 65 #include <asm/irq.h> 66 #include <asm/realmode.h> 67 #include <asm/cpu.h> 68 #include <asm/numa.h> 69 #include <asm/tlbflush.h> 70 #include <asm/mtrr.h> 71 #include <asm/mwait.h> 72 #include <asm/apic.h> 73 #include <asm/io_apic.h> 74 #include <asm/fpu/api.h> 75 #include <asm/setup.h> 76 #include <asm/uv/uv.h> 77 #include <linux/mc146818rtc.h> 78 #include <asm/i8259.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 #include <asm/intel-family.h> 82 #include <asm/cpu_device_id.h> 83 #include <asm/spec-ctrl.h> 84 #include <asm/hw_irq.h> 85 #include <asm/stackprotector.h> 86 #include <asm/sev.h> 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 /* representing HT, core, and die siblings of each logical CPU */ 97 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 98 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 99 100 /* Per CPU bogomips and other parameters */ 101 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 102 EXPORT_PER_CPU_SYMBOL(cpu_info); 103 104 /* Logical package management. We might want to allocate that dynamically */ 105 unsigned int __max_logical_packages __read_mostly; 106 EXPORT_SYMBOL(__max_logical_packages); 107 static unsigned int logical_packages __read_mostly; 108 static unsigned int logical_die __read_mostly; 109 110 /* Maximum number of SMT threads on any online core */ 111 int __read_mostly __max_smt_threads = 1; 112 113 /* Flag to indicate if a complete sched domain rebuild is required */ 114 bool x86_topology_update; 115 116 int arch_update_cpu_topology(void) 117 { 118 int retval = x86_topology_update; 119 120 x86_topology_update = false; 121 return retval; 122 } 123 124 125 static unsigned int smpboot_warm_reset_vector_count; 126 127 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 128 { 129 unsigned long flags; 130 131 spin_lock_irqsave(&rtc_lock, flags); 132 if (!smpboot_warm_reset_vector_count++) { 133 CMOS_WRITE(0xa, 0xf); 134 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 135 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 136 } 137 spin_unlock_irqrestore(&rtc_lock, flags); 138 } 139 140 static inline void smpboot_restore_warm_reset_vector(void) 141 { 142 unsigned long flags; 143 144 /* 145 * Paranoid: Set warm reset code and vector here back 146 * to default values. 147 */ 148 spin_lock_irqsave(&rtc_lock, flags); 149 if (!--smpboot_warm_reset_vector_count) { 150 CMOS_WRITE(0, 0xf); 151 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 152 } 153 spin_unlock_irqrestore(&rtc_lock, flags); 154 155 } 156 157 /* 158 * Report back to the Boot Processor during boot time or to the caller processor 159 * during CPU online. 160 */ 161 static void smp_callin(void) 162 { 163 int cpuid; 164 165 /* 166 * If waken up by an INIT in an 82489DX configuration 167 * cpu_callout_mask guarantees we don't get here before 168 * an INIT_deassert IPI reaches our local APIC, so it is 169 * now safe to touch our local APIC. 170 */ 171 cpuid = smp_processor_id(); 172 173 /* 174 * the boot CPU has finished the init stage and is spinning 175 * on callin_map until we finish. We are free to set up this 176 * CPU, first the APIC. (this is probably redundant on most 177 * boards) 178 */ 179 apic_ap_setup(); 180 181 /* 182 * Save our processor parameters. Note: this information 183 * is needed for clock calibration. 184 */ 185 smp_store_cpu_info(cpuid); 186 187 /* 188 * The topology information must be up to date before 189 * calibrate_delay() and notify_cpu_starting(). 190 */ 191 set_cpu_sibling_map(raw_smp_processor_id()); 192 193 ap_init_aperfmperf(); 194 195 /* 196 * Get our bogomips. 197 * Update loops_per_jiffy in cpu_data. Previous call to 198 * smp_store_cpu_info() stored a value that is close but not as 199 * accurate as the value just calculated. 200 */ 201 calibrate_delay(); 202 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 203 pr_debug("Stack at about %p\n", &cpuid); 204 205 wmb(); 206 207 notify_cpu_starting(cpuid); 208 209 /* 210 * Allow the master to continue. 211 */ 212 cpumask_set_cpu(cpuid, cpu_callin_mask); 213 } 214 215 static int cpu0_logical_apicid; 216 static int enable_start_cpu0; 217 /* 218 * Activate a secondary processor. 219 */ 220 static void notrace start_secondary(void *unused) 221 { 222 /* 223 * Don't put *anything* except direct CPU state initialization 224 * before cpu_init(), SMP booting is too fragile that we want to 225 * limit the things done here to the most necessary things. 226 */ 227 cr4_init(); 228 229 #ifdef CONFIG_X86_32 230 /* switch away from the initial page table */ 231 load_cr3(swapper_pg_dir); 232 __flush_tlb_all(); 233 #endif 234 cpu_init_secondary(); 235 rcu_cpu_starting(raw_smp_processor_id()); 236 x86_cpuinit.early_percpu_clock_init(); 237 smp_callin(); 238 239 enable_start_cpu0 = 0; 240 241 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 242 barrier(); 243 /* 244 * Check TSC synchronization with the boot CPU: 245 */ 246 check_tsc_sync_target(); 247 248 speculative_store_bypass_ht_init(); 249 250 /* 251 * Lock vector_lock, set CPU online and bring the vector 252 * allocator online. Online must be set with vector_lock held 253 * to prevent a concurrent irq setup/teardown from seeing a 254 * half valid vector space. 255 */ 256 lock_vector_lock(); 257 set_cpu_online(smp_processor_id(), true); 258 lapic_online(); 259 unlock_vector_lock(); 260 cpu_set_state_online(smp_processor_id()); 261 x86_platform.nmi_init(); 262 263 /* enable local interrupts */ 264 local_irq_enable(); 265 266 x86_cpuinit.setup_percpu_clockev(); 267 268 wmb(); 269 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 270 } 271 272 /** 273 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 274 * @cpu: CPU to check 275 */ 276 bool topology_is_primary_thread(unsigned int cpu) 277 { 278 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 279 } 280 281 /** 282 * topology_smt_supported - Check whether SMT is supported by the CPUs 283 */ 284 bool topology_smt_supported(void) 285 { 286 return smp_num_siblings > 1; 287 } 288 289 /** 290 * topology_phys_to_logical_pkg - Map a physical package id to a logical 291 * 292 * Returns logical package id or -1 if not found 293 */ 294 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 295 { 296 int cpu; 297 298 for_each_possible_cpu(cpu) { 299 struct cpuinfo_x86 *c = &cpu_data(cpu); 300 301 if (c->initialized && c->phys_proc_id == phys_pkg) 302 return c->logical_proc_id; 303 } 304 return -1; 305 } 306 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 307 /** 308 * topology_phys_to_logical_die - Map a physical die id to logical 309 * 310 * Returns logical die id or -1 if not found 311 */ 312 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 313 { 314 int cpu; 315 int proc_id = cpu_data(cur_cpu).phys_proc_id; 316 317 for_each_possible_cpu(cpu) { 318 struct cpuinfo_x86 *c = &cpu_data(cpu); 319 320 if (c->initialized && c->cpu_die_id == die_id && 321 c->phys_proc_id == proc_id) 322 return c->logical_die_id; 323 } 324 return -1; 325 } 326 EXPORT_SYMBOL(topology_phys_to_logical_die); 327 328 /** 329 * topology_update_package_map - Update the physical to logical package map 330 * @pkg: The physical package id as retrieved via CPUID 331 * @cpu: The cpu for which this is updated 332 */ 333 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 334 { 335 int new; 336 337 /* Already available somewhere? */ 338 new = topology_phys_to_logical_pkg(pkg); 339 if (new >= 0) 340 goto found; 341 342 new = logical_packages++; 343 if (new != pkg) { 344 pr_info("CPU %u Converting physical %u to logical package %u\n", 345 cpu, pkg, new); 346 } 347 found: 348 cpu_data(cpu).logical_proc_id = new; 349 return 0; 350 } 351 /** 352 * topology_update_die_map - Update the physical to logical die map 353 * @die: The die id as retrieved via CPUID 354 * @cpu: The cpu for which this is updated 355 */ 356 int topology_update_die_map(unsigned int die, unsigned int cpu) 357 { 358 int new; 359 360 /* Already available somewhere? */ 361 new = topology_phys_to_logical_die(die, cpu); 362 if (new >= 0) 363 goto found; 364 365 new = logical_die++; 366 if (new != die) { 367 pr_info("CPU %u Converting physical %u to logical die %u\n", 368 cpu, die, new); 369 } 370 found: 371 cpu_data(cpu).logical_die_id = new; 372 return 0; 373 } 374 375 void __init smp_store_boot_cpu_info(void) 376 { 377 int id = 0; /* CPU 0 */ 378 struct cpuinfo_x86 *c = &cpu_data(id); 379 380 *c = boot_cpu_data; 381 c->cpu_index = id; 382 topology_update_package_map(c->phys_proc_id, id); 383 topology_update_die_map(c->cpu_die_id, id); 384 c->initialized = true; 385 } 386 387 /* 388 * The bootstrap kernel entry code has set these up. Save them for 389 * a given CPU 390 */ 391 void smp_store_cpu_info(int id) 392 { 393 struct cpuinfo_x86 *c = &cpu_data(id); 394 395 /* Copy boot_cpu_data only on the first bringup */ 396 if (!c->initialized) 397 *c = boot_cpu_data; 398 c->cpu_index = id; 399 /* 400 * During boot time, CPU0 has this setup already. Save the info when 401 * bringing up AP or offlined CPU0. 402 */ 403 identify_secondary_cpu(c); 404 c->initialized = true; 405 } 406 407 static bool 408 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 409 { 410 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 411 412 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 413 } 414 415 static bool 416 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 417 { 418 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 419 420 return !WARN_ONCE(!topology_same_node(c, o), 421 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 422 "[node: %d != %d]. Ignoring dependency.\n", 423 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 424 } 425 426 #define link_mask(mfunc, c1, c2) \ 427 do { \ 428 cpumask_set_cpu((c1), mfunc(c2)); \ 429 cpumask_set_cpu((c2), mfunc(c1)); \ 430 } while (0) 431 432 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 433 { 434 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 435 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 436 437 if (c->phys_proc_id == o->phys_proc_id && 438 c->cpu_die_id == o->cpu_die_id && 439 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 440 if (c->cpu_core_id == o->cpu_core_id) 441 return topology_sane(c, o, "smt"); 442 443 if ((c->cu_id != 0xff) && 444 (o->cu_id != 0xff) && 445 (c->cu_id == o->cu_id)) 446 return topology_sane(c, o, "smt"); 447 } 448 449 } else if (c->phys_proc_id == o->phys_proc_id && 450 c->cpu_die_id == o->cpu_die_id && 451 c->cpu_core_id == o->cpu_core_id) { 452 return topology_sane(c, o, "smt"); 453 } 454 455 return false; 456 } 457 458 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 459 { 460 if (c->phys_proc_id == o->phys_proc_id && 461 c->cpu_die_id == o->cpu_die_id) 462 return true; 463 return false; 464 } 465 466 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 467 { 468 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 469 470 /* If the arch didn't set up l2c_id, fall back to SMT */ 471 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 472 return match_smt(c, o); 473 474 /* Do not match if L2 cache id does not match: */ 475 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 476 return false; 477 478 return topology_sane(c, o, "l2c"); 479 } 480 481 /* 482 * Unlike the other levels, we do not enforce keeping a 483 * multicore group inside a NUMA node. If this happens, we will 484 * discard the MC level of the topology later. 485 */ 486 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 487 { 488 if (c->phys_proc_id == o->phys_proc_id) 489 return true; 490 return false; 491 } 492 493 /* 494 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 495 * 496 * Any Intel CPU that has multiple nodes per package and does not 497 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 498 * 499 * When in SNC mode, these CPUs enumerate an LLC that is shared 500 * by multiple NUMA nodes. The LLC is shared for off-package data 501 * access but private to the NUMA node (half of the package) for 502 * on-package access. CPUID (the source of the information about 503 * the LLC) can only enumerate the cache as shared or unshared, 504 * but not this particular configuration. 505 */ 506 507 static const struct x86_cpu_id intel_cod_cpu[] = { 508 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 509 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 510 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 511 {} 512 }; 513 514 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 515 { 516 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 517 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 518 bool intel_snc = id && id->driver_data; 519 520 /* Do not match if we do not have a valid APICID for cpu: */ 521 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 522 return false; 523 524 /* Do not match if LLC id does not match: */ 525 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 526 return false; 527 528 /* 529 * Allow the SNC topology without warning. Return of false 530 * means 'c' does not share the LLC of 'o'. This will be 531 * reflected to userspace. 532 */ 533 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 534 return false; 535 536 return topology_sane(c, o, "llc"); 537 } 538 539 540 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 541 static inline int x86_sched_itmt_flags(void) 542 { 543 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 544 } 545 546 #ifdef CONFIG_SCHED_MC 547 static int x86_core_flags(void) 548 { 549 return cpu_core_flags() | x86_sched_itmt_flags(); 550 } 551 #endif 552 #ifdef CONFIG_SCHED_SMT 553 static int x86_smt_flags(void) 554 { 555 return cpu_smt_flags() | x86_sched_itmt_flags(); 556 } 557 #endif 558 #ifdef CONFIG_SCHED_CLUSTER 559 static int x86_cluster_flags(void) 560 { 561 return cpu_cluster_flags() | x86_sched_itmt_flags(); 562 } 563 #endif 564 #endif 565 566 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 567 #ifdef CONFIG_SCHED_SMT 568 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 569 #endif 570 #ifdef CONFIG_SCHED_CLUSTER 571 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 572 #endif 573 #ifdef CONFIG_SCHED_MC 574 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 575 #endif 576 { NULL, }, 577 }; 578 579 static struct sched_domain_topology_level x86_hybrid_topology[] = { 580 #ifdef CONFIG_SCHED_SMT 581 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 582 #endif 583 #ifdef CONFIG_SCHED_MC 584 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 585 #endif 586 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 587 { NULL, }, 588 }; 589 590 static struct sched_domain_topology_level x86_topology[] = { 591 #ifdef CONFIG_SCHED_SMT 592 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 593 #endif 594 #ifdef CONFIG_SCHED_CLUSTER 595 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 596 #endif 597 #ifdef CONFIG_SCHED_MC 598 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 599 #endif 600 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 601 { NULL, }, 602 }; 603 604 /* 605 * Set if a package/die has multiple NUMA nodes inside. 606 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 607 * Sub-NUMA Clustering have this. 608 */ 609 static bool x86_has_numa_in_package; 610 611 void set_cpu_sibling_map(int cpu) 612 { 613 bool has_smt = smp_num_siblings > 1; 614 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 615 struct cpuinfo_x86 *c = &cpu_data(cpu); 616 struct cpuinfo_x86 *o; 617 int i, threads; 618 619 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 620 621 if (!has_mp) { 622 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 623 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 624 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 625 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 626 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 627 c->booted_cores = 1; 628 return; 629 } 630 631 for_each_cpu(i, cpu_sibling_setup_mask) { 632 o = &cpu_data(i); 633 634 if (match_pkg(c, o) && !topology_same_node(c, o)) 635 x86_has_numa_in_package = true; 636 637 if ((i == cpu) || (has_smt && match_smt(c, o))) 638 link_mask(topology_sibling_cpumask, cpu, i); 639 640 if ((i == cpu) || (has_mp && match_llc(c, o))) 641 link_mask(cpu_llc_shared_mask, cpu, i); 642 643 if ((i == cpu) || (has_mp && match_l2c(c, o))) 644 link_mask(cpu_l2c_shared_mask, cpu, i); 645 646 if ((i == cpu) || (has_mp && match_die(c, o))) 647 link_mask(topology_die_cpumask, cpu, i); 648 } 649 650 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 651 if (threads > __max_smt_threads) 652 __max_smt_threads = threads; 653 654 for_each_cpu(i, topology_sibling_cpumask(cpu)) 655 cpu_data(i).smt_active = threads > 1; 656 657 /* 658 * This needs a separate iteration over the cpus because we rely on all 659 * topology_sibling_cpumask links to be set-up. 660 */ 661 for_each_cpu(i, cpu_sibling_setup_mask) { 662 o = &cpu_data(i); 663 664 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 665 link_mask(topology_core_cpumask, cpu, i); 666 667 /* 668 * Does this new cpu bringup a new core? 669 */ 670 if (threads == 1) { 671 /* 672 * for each core in package, increment 673 * the booted_cores for this new cpu 674 */ 675 if (cpumask_first( 676 topology_sibling_cpumask(i)) == i) 677 c->booted_cores++; 678 /* 679 * increment the core count for all 680 * the other cpus in this package 681 */ 682 if (i != cpu) 683 cpu_data(i).booted_cores++; 684 } else if (i != cpu && !c->booted_cores) 685 c->booted_cores = cpu_data(i).booted_cores; 686 } 687 } 688 } 689 690 /* maps the cpu to the sched domain representing multi-core */ 691 const struct cpumask *cpu_coregroup_mask(int cpu) 692 { 693 return cpu_llc_shared_mask(cpu); 694 } 695 696 const struct cpumask *cpu_clustergroup_mask(int cpu) 697 { 698 return cpu_l2c_shared_mask(cpu); 699 } 700 701 static void impress_friends(void) 702 { 703 int cpu; 704 unsigned long bogosum = 0; 705 /* 706 * Allow the user to impress friends. 707 */ 708 pr_debug("Before bogomips\n"); 709 for_each_possible_cpu(cpu) 710 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 711 bogosum += cpu_data(cpu).loops_per_jiffy; 712 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 713 num_online_cpus(), 714 bogosum/(500000/HZ), 715 (bogosum/(5000/HZ))%100); 716 717 pr_debug("Before bogocount - setting activated=1\n"); 718 } 719 720 void __inquire_remote_apic(int apicid) 721 { 722 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 723 const char * const names[] = { "ID", "VERSION", "SPIV" }; 724 int timeout; 725 u32 status; 726 727 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 728 729 for (i = 0; i < ARRAY_SIZE(regs); i++) { 730 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 731 732 /* 733 * Wait for idle. 734 */ 735 status = safe_apic_wait_icr_idle(); 736 if (status) 737 pr_cont("a previous APIC delivery may have failed\n"); 738 739 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 740 741 timeout = 0; 742 do { 743 udelay(100); 744 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 745 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 746 747 switch (status) { 748 case APIC_ICR_RR_VALID: 749 status = apic_read(APIC_RRR); 750 pr_cont("%08x\n", status); 751 break; 752 default: 753 pr_cont("failed\n"); 754 } 755 } 756 } 757 758 /* 759 * The Multiprocessor Specification 1.4 (1997) example code suggests 760 * that there should be a 10ms delay between the BSP asserting INIT 761 * and de-asserting INIT, when starting a remote processor. 762 * But that slows boot and resume on modern processors, which include 763 * many cores and don't require that delay. 764 * 765 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 766 * Modern processor families are quirked to remove the delay entirely. 767 */ 768 #define UDELAY_10MS_DEFAULT 10000 769 770 static unsigned int init_udelay = UINT_MAX; 771 772 static int __init cpu_init_udelay(char *str) 773 { 774 get_option(&str, &init_udelay); 775 776 return 0; 777 } 778 early_param("cpu_init_udelay", cpu_init_udelay); 779 780 static void __init smp_quirk_init_udelay(void) 781 { 782 /* if cmdline changed it from default, leave it alone */ 783 if (init_udelay != UINT_MAX) 784 return; 785 786 /* if modern processor, use no delay */ 787 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 788 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 789 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 790 init_udelay = 0; 791 return; 792 } 793 /* else, use legacy delay */ 794 init_udelay = UDELAY_10MS_DEFAULT; 795 } 796 797 /* 798 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 799 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 800 * won't ... remember to clear down the APIC, etc later. 801 */ 802 int 803 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 804 { 805 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 806 unsigned long send_status, accept_status = 0; 807 int maxlvt; 808 809 /* Target chip */ 810 /* Boot on the stack */ 811 /* Kick the second */ 812 apic_icr_write(APIC_DM_NMI | dm, apicid); 813 814 pr_debug("Waiting for send to finish...\n"); 815 send_status = safe_apic_wait_icr_idle(); 816 817 /* 818 * Give the other CPU some time to accept the IPI. 819 */ 820 udelay(200); 821 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 822 maxlvt = lapic_get_maxlvt(); 823 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 824 apic_write(APIC_ESR, 0); 825 accept_status = (apic_read(APIC_ESR) & 0xEF); 826 } 827 pr_debug("NMI sent\n"); 828 829 if (send_status) 830 pr_err("APIC never delivered???\n"); 831 if (accept_status) 832 pr_err("APIC delivery error (%lx)\n", accept_status); 833 834 return (send_status | accept_status); 835 } 836 837 static int 838 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 839 { 840 unsigned long send_status = 0, accept_status = 0; 841 int maxlvt, num_starts, j; 842 843 maxlvt = lapic_get_maxlvt(); 844 845 /* 846 * Be paranoid about clearing APIC errors. 847 */ 848 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 849 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 850 apic_write(APIC_ESR, 0); 851 apic_read(APIC_ESR); 852 } 853 854 pr_debug("Asserting INIT\n"); 855 856 /* 857 * Turn INIT on target chip 858 */ 859 /* 860 * Send IPI 861 */ 862 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 863 phys_apicid); 864 865 pr_debug("Waiting for send to finish...\n"); 866 send_status = safe_apic_wait_icr_idle(); 867 868 udelay(init_udelay); 869 870 pr_debug("Deasserting INIT\n"); 871 872 /* Target chip */ 873 /* Send IPI */ 874 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 875 876 pr_debug("Waiting for send to finish...\n"); 877 send_status = safe_apic_wait_icr_idle(); 878 879 mb(); 880 881 /* 882 * Should we send STARTUP IPIs ? 883 * 884 * Determine this based on the APIC version. 885 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 886 */ 887 if (APIC_INTEGRATED(boot_cpu_apic_version)) 888 num_starts = 2; 889 else 890 num_starts = 0; 891 892 /* 893 * Run STARTUP IPI loop. 894 */ 895 pr_debug("#startup loops: %d\n", num_starts); 896 897 for (j = 1; j <= num_starts; j++) { 898 pr_debug("Sending STARTUP #%d\n", j); 899 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 900 apic_write(APIC_ESR, 0); 901 apic_read(APIC_ESR); 902 pr_debug("After apic_write\n"); 903 904 /* 905 * STARTUP IPI 906 */ 907 908 /* Target chip */ 909 /* Boot on the stack */ 910 /* Kick the second */ 911 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 912 phys_apicid); 913 914 /* 915 * Give the other CPU some time to accept the IPI. 916 */ 917 if (init_udelay == 0) 918 udelay(10); 919 else 920 udelay(300); 921 922 pr_debug("Startup point 1\n"); 923 924 pr_debug("Waiting for send to finish...\n"); 925 send_status = safe_apic_wait_icr_idle(); 926 927 /* 928 * Give the other CPU some time to accept the IPI. 929 */ 930 if (init_udelay == 0) 931 udelay(10); 932 else 933 udelay(200); 934 935 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 936 apic_write(APIC_ESR, 0); 937 accept_status = (apic_read(APIC_ESR) & 0xEF); 938 if (send_status || accept_status) 939 break; 940 } 941 pr_debug("After Startup\n"); 942 943 if (send_status) 944 pr_err("APIC never delivered???\n"); 945 if (accept_status) 946 pr_err("APIC delivery error (%lx)\n", accept_status); 947 948 return (send_status | accept_status); 949 } 950 951 /* reduce the number of lines printed when booting a large cpu count system */ 952 static void announce_cpu(int cpu, int apicid) 953 { 954 static int current_node = NUMA_NO_NODE; 955 int node = early_cpu_to_node(cpu); 956 static int width, node_width; 957 958 if (!width) 959 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 960 961 if (!node_width) 962 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 963 964 if (cpu == 1) 965 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 966 967 if (system_state < SYSTEM_RUNNING) { 968 if (node != current_node) { 969 if (current_node > (-1)) 970 pr_cont("\n"); 971 current_node = node; 972 973 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 974 node_width - num_digits(node), " ", node); 975 } 976 977 /* Add padding for the BSP */ 978 if (cpu == 1) 979 pr_cont("%*s", width + 1, " "); 980 981 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 982 983 } else 984 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 985 node, cpu, apicid); 986 } 987 988 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 989 { 990 int cpu; 991 992 cpu = smp_processor_id(); 993 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 994 return NMI_HANDLED; 995 996 return NMI_DONE; 997 } 998 999 /* 1000 * Wake up AP by INIT, INIT, STARTUP sequence. 1001 * 1002 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 1003 * boot-strap code which is not a desired behavior for waking up BSP. To 1004 * void the boot-strap code, wake up CPU0 by NMI instead. 1005 * 1006 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 1007 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 1008 * We'll change this code in the future to wake up hard offlined CPU0 if 1009 * real platform and request are available. 1010 */ 1011 static int 1012 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 1013 int *cpu0_nmi_registered) 1014 { 1015 int id; 1016 int boot_error; 1017 1018 preempt_disable(); 1019 1020 /* 1021 * Wake up AP by INIT, INIT, STARTUP sequence. 1022 */ 1023 if (cpu) { 1024 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 1025 goto out; 1026 } 1027 1028 /* 1029 * Wake up BSP by nmi. 1030 * 1031 * Register a NMI handler to help wake up CPU0. 1032 */ 1033 boot_error = register_nmi_handler(NMI_LOCAL, 1034 wakeup_cpu0_nmi, 0, "wake_cpu0"); 1035 1036 if (!boot_error) { 1037 enable_start_cpu0 = 1; 1038 *cpu0_nmi_registered = 1; 1039 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; 1040 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 1041 } 1042 1043 out: 1044 preempt_enable(); 1045 1046 return boot_error; 1047 } 1048 1049 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1050 { 1051 int ret; 1052 1053 /* Just in case we booted with a single CPU. */ 1054 alternatives_enable_smp(); 1055 1056 per_cpu(pcpu_hot.current_task, cpu) = idle; 1057 cpu_init_stack_canary(cpu, idle); 1058 1059 /* Initialize the interrupt stack(s) */ 1060 ret = irq_init_percpu_irqstack(cpu); 1061 if (ret) 1062 return ret; 1063 1064 #ifdef CONFIG_X86_32 1065 /* Stack for startup_32 can be just as for start_secondary onwards */ 1066 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 1067 #endif 1068 return 0; 1069 } 1070 1071 /* 1072 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1073 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1074 * Returns zero if CPU booted OK, else error code from 1075 * ->wakeup_secondary_cpu. 1076 */ 1077 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1078 int *cpu0_nmi_registered) 1079 { 1080 /* start_ip had better be page-aligned! */ 1081 unsigned long start_ip = real_mode_header->trampoline_start; 1082 1083 unsigned long boot_error = 0; 1084 unsigned long timeout; 1085 1086 #ifdef CONFIG_X86_64 1087 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 1088 if (apic->wakeup_secondary_cpu_64) 1089 start_ip = real_mode_header->trampoline_start64; 1090 #endif 1091 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1092 initial_code = (unsigned long)start_secondary; 1093 1094 if (IS_ENABLED(CONFIG_X86_32)) { 1095 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1096 initial_stack = idle->thread.sp; 1097 } else { 1098 smpboot_control = cpu; 1099 } 1100 1101 /* Enable the espfix hack for this CPU */ 1102 init_espfix_ap(cpu); 1103 1104 /* So we see what's up */ 1105 announce_cpu(cpu, apicid); 1106 1107 /* 1108 * This grunge runs the startup process for 1109 * the targeted processor. 1110 */ 1111 1112 if (x86_platform.legacy.warm_reset) { 1113 1114 pr_debug("Setting warm reset code and vector.\n"); 1115 1116 smpboot_setup_warm_reset_vector(start_ip); 1117 /* 1118 * Be paranoid about clearing APIC errors. 1119 */ 1120 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1121 apic_write(APIC_ESR, 0); 1122 apic_read(APIC_ESR); 1123 } 1124 } 1125 1126 /* 1127 * AP might wait on cpu_callout_mask in cpu_init() with 1128 * cpu_initialized_mask set if previous attempt to online 1129 * it timed-out. Clear cpu_initialized_mask so that after 1130 * INIT/SIPI it could start with a clean state. 1131 */ 1132 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1133 smp_mb(); 1134 1135 /* 1136 * Wake up a CPU in difference cases: 1137 * - Use a method from the APIC driver if one defined, with wakeup 1138 * straight to 64-bit mode preferred over wakeup to RM. 1139 * Otherwise, 1140 * - Use an INIT boot APIC message for APs or NMI for BSP. 1141 */ 1142 if (apic->wakeup_secondary_cpu_64) 1143 boot_error = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1144 else if (apic->wakeup_secondary_cpu) 1145 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1146 else 1147 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1148 cpu0_nmi_registered); 1149 1150 if (!boot_error) { 1151 /* 1152 * Wait 10s total for first sign of life from AP 1153 */ 1154 boot_error = -1; 1155 timeout = jiffies + 10*HZ; 1156 while (time_before(jiffies, timeout)) { 1157 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1158 /* 1159 * Tell AP to proceed with initialization 1160 */ 1161 cpumask_set_cpu(cpu, cpu_callout_mask); 1162 boot_error = 0; 1163 break; 1164 } 1165 schedule(); 1166 } 1167 } 1168 1169 if (!boot_error) { 1170 /* 1171 * Wait till AP completes initial initialization 1172 */ 1173 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1174 /* 1175 * Allow other tasks to run while we wait for the 1176 * AP to come online. This also gives a chance 1177 * for the MTRR work(triggered by the AP coming online) 1178 * to be completed in the stop machine context. 1179 */ 1180 schedule(); 1181 } 1182 } 1183 1184 if (x86_platform.legacy.warm_reset) { 1185 /* 1186 * Cleanup possible dangling ends... 1187 */ 1188 smpboot_restore_warm_reset_vector(); 1189 } 1190 1191 return boot_error; 1192 } 1193 1194 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1195 { 1196 int apicid = apic->cpu_present_to_apicid(cpu); 1197 int cpu0_nmi_registered = 0; 1198 unsigned long flags; 1199 int err, ret = 0; 1200 1201 lockdep_assert_irqs_enabled(); 1202 1203 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1204 1205 if (apicid == BAD_APICID || 1206 !physid_isset(apicid, phys_cpu_present_map) || 1207 !apic->apic_id_valid(apicid)) { 1208 pr_err("%s: bad cpu %d\n", __func__, cpu); 1209 return -EINVAL; 1210 } 1211 1212 /* 1213 * Already booted CPU? 1214 */ 1215 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1216 pr_debug("do_boot_cpu %d Already started\n", cpu); 1217 return -ENOSYS; 1218 } 1219 1220 /* 1221 * Save current MTRR state in case it was changed since early boot 1222 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1223 */ 1224 mtrr_save_state(); 1225 1226 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1227 err = cpu_check_up_prepare(cpu); 1228 if (err && err != -EBUSY) 1229 return err; 1230 1231 /* the FPU context is blank, nobody can own it */ 1232 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1233 1234 err = common_cpu_up(cpu, tidle); 1235 if (err) 1236 return err; 1237 1238 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1239 if (err) { 1240 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1241 ret = -EIO; 1242 goto unreg_nmi; 1243 } 1244 1245 /* 1246 * Check TSC synchronization with the AP (keep irqs disabled 1247 * while doing so): 1248 */ 1249 local_irq_save(flags); 1250 check_tsc_sync_source(cpu); 1251 local_irq_restore(flags); 1252 1253 while (!cpu_online(cpu)) { 1254 cpu_relax(); 1255 touch_nmi_watchdog(); 1256 } 1257 1258 unreg_nmi: 1259 /* 1260 * Clean up the nmi handler. Do this after the callin and callout sync 1261 * to avoid impact of possible long unregister time. 1262 */ 1263 if (cpu0_nmi_registered) 1264 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1265 1266 return ret; 1267 } 1268 1269 /** 1270 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1271 */ 1272 void arch_disable_smp_support(void) 1273 { 1274 disable_ioapic_support(); 1275 } 1276 1277 /* 1278 * Fall back to non SMP mode after errors. 1279 * 1280 * RED-PEN audit/test this more. I bet there is more state messed up here. 1281 */ 1282 static __init void disable_smp(void) 1283 { 1284 pr_info("SMP disabled\n"); 1285 1286 disable_ioapic_support(); 1287 1288 init_cpu_present(cpumask_of(0)); 1289 init_cpu_possible(cpumask_of(0)); 1290 1291 if (smp_found_config) 1292 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1293 else 1294 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1295 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1296 cpumask_set_cpu(0, topology_core_cpumask(0)); 1297 cpumask_set_cpu(0, topology_die_cpumask(0)); 1298 } 1299 1300 /* 1301 * Various sanity checks. 1302 */ 1303 static void __init smp_sanity_check(void) 1304 { 1305 preempt_disable(); 1306 1307 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1308 if (def_to_bigsmp && nr_cpu_ids > 8) { 1309 unsigned int cpu; 1310 unsigned nr; 1311 1312 pr_warn("More than 8 CPUs detected - skipping them\n" 1313 "Use CONFIG_X86_BIGSMP\n"); 1314 1315 nr = 0; 1316 for_each_present_cpu(cpu) { 1317 if (nr >= 8) 1318 set_cpu_present(cpu, false); 1319 nr++; 1320 } 1321 1322 nr = 0; 1323 for_each_possible_cpu(cpu) { 1324 if (nr >= 8) 1325 set_cpu_possible(cpu, false); 1326 nr++; 1327 } 1328 1329 set_nr_cpu_ids(8); 1330 } 1331 #endif 1332 1333 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1334 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1335 hard_smp_processor_id()); 1336 1337 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1338 } 1339 1340 /* 1341 * Should not be necessary because the MP table should list the boot 1342 * CPU too, but we do it for the sake of robustness anyway. 1343 */ 1344 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1345 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1346 boot_cpu_physical_apicid); 1347 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1348 } 1349 preempt_enable(); 1350 } 1351 1352 static void __init smp_cpu_index_default(void) 1353 { 1354 int i; 1355 struct cpuinfo_x86 *c; 1356 1357 for_each_possible_cpu(i) { 1358 c = &cpu_data(i); 1359 /* mark all to hotplug */ 1360 c->cpu_index = nr_cpu_ids; 1361 } 1362 } 1363 1364 static void __init smp_get_logical_apicid(void) 1365 { 1366 if (x2apic_mode) 1367 cpu0_logical_apicid = apic_read(APIC_LDR); 1368 else 1369 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1370 } 1371 1372 void __init smp_prepare_cpus_common(void) 1373 { 1374 unsigned int i; 1375 1376 smp_cpu_index_default(); 1377 1378 /* 1379 * Setup boot CPU information 1380 */ 1381 smp_store_boot_cpu_info(); /* Final full version of the data */ 1382 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1383 mb(); 1384 1385 for_each_possible_cpu(i) { 1386 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1387 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1388 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1389 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1390 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1391 } 1392 1393 /* 1394 * Set 'default' x86 topology, this matches default_topology() in that 1395 * it has NUMA nodes as a topology level. See also 1396 * native_smp_cpus_done(). 1397 * 1398 * Must be done before set_cpus_sibling_map() is ran. 1399 */ 1400 set_sched_topology(x86_topology); 1401 1402 set_cpu_sibling_map(0); 1403 } 1404 1405 /* 1406 * Prepare for SMP bootup. 1407 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1408 * for common interface support. 1409 */ 1410 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1411 { 1412 smp_prepare_cpus_common(); 1413 1414 smp_sanity_check(); 1415 1416 switch (apic_intr_mode) { 1417 case APIC_PIC: 1418 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1419 disable_smp(); 1420 return; 1421 case APIC_SYMMETRIC_IO_NO_ROUTING: 1422 disable_smp(); 1423 /* Setup local timer */ 1424 x86_init.timers.setup_percpu_clockev(); 1425 return; 1426 case APIC_VIRTUAL_WIRE: 1427 case APIC_SYMMETRIC_IO: 1428 break; 1429 } 1430 1431 /* Setup local timer */ 1432 x86_init.timers.setup_percpu_clockev(); 1433 1434 smp_get_logical_apicid(); 1435 1436 pr_info("CPU0: "); 1437 print_cpu_info(&cpu_data(0)); 1438 1439 uv_system_init(); 1440 1441 smp_quirk_init_udelay(); 1442 1443 speculative_store_bypass_ht_init(); 1444 1445 snp_set_wakeup_secondary_cpu(); 1446 } 1447 1448 void arch_thaw_secondary_cpus_begin(void) 1449 { 1450 set_cache_aps_delayed_init(true); 1451 } 1452 1453 void arch_thaw_secondary_cpus_end(void) 1454 { 1455 cache_aps_init(); 1456 } 1457 1458 /* 1459 * Early setup to make printk work. 1460 */ 1461 void __init native_smp_prepare_boot_cpu(void) 1462 { 1463 int me = smp_processor_id(); 1464 1465 /* SMP handles this from setup_per_cpu_areas() */ 1466 if (!IS_ENABLED(CONFIG_SMP)) 1467 switch_gdt_and_percpu_base(me); 1468 1469 /* already set me in cpu_online_mask in boot_cpu_init() */ 1470 cpumask_set_cpu(me, cpu_callout_mask); 1471 cpu_set_state_online(me); 1472 native_pv_lock_init(); 1473 } 1474 1475 void __init calculate_max_logical_packages(void) 1476 { 1477 int ncpus; 1478 1479 /* 1480 * Today neither Intel nor AMD support heterogeneous systems so 1481 * extrapolate the boot cpu's data to all packages. 1482 */ 1483 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1484 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1485 pr_info("Max logical packages: %u\n", __max_logical_packages); 1486 } 1487 1488 void __init native_smp_cpus_done(unsigned int max_cpus) 1489 { 1490 pr_debug("Boot done\n"); 1491 1492 calculate_max_logical_packages(); 1493 1494 /* XXX for now assume numa-in-package and hybrid don't overlap */ 1495 if (x86_has_numa_in_package) 1496 set_sched_topology(x86_numa_in_package_topology); 1497 if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) 1498 set_sched_topology(x86_hybrid_topology); 1499 1500 nmi_selftest(); 1501 impress_friends(); 1502 cache_aps_init(); 1503 } 1504 1505 static int __initdata setup_possible_cpus = -1; 1506 static int __init _setup_possible_cpus(char *str) 1507 { 1508 get_option(&str, &setup_possible_cpus); 1509 return 0; 1510 } 1511 early_param("possible_cpus", _setup_possible_cpus); 1512 1513 1514 /* 1515 * cpu_possible_mask should be static, it cannot change as cpu's 1516 * are onlined, or offlined. The reason is per-cpu data-structures 1517 * are allocated by some modules at init time, and don't expect to 1518 * do this dynamically on cpu arrival/departure. 1519 * cpu_present_mask on the other hand can change dynamically. 1520 * In case when cpu_hotplug is not compiled, then we resort to current 1521 * behaviour, which is cpu_possible == cpu_present. 1522 * - Ashok Raj 1523 * 1524 * Three ways to find out the number of additional hotplug CPUs: 1525 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1526 * - The user can overwrite it with possible_cpus=NUM 1527 * - Otherwise don't reserve additional CPUs. 1528 * We do this because additional CPUs waste a lot of memory. 1529 * -AK 1530 */ 1531 __init void prefill_possible_map(void) 1532 { 1533 int i, possible; 1534 1535 /* No boot processor was found in mptable or ACPI MADT */ 1536 if (!num_processors) { 1537 if (boot_cpu_has(X86_FEATURE_APIC)) { 1538 int apicid = boot_cpu_physical_apicid; 1539 int cpu = hard_smp_processor_id(); 1540 1541 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1542 1543 /* Make sure boot cpu is enumerated */ 1544 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1545 apic->apic_id_valid(apicid)) 1546 generic_processor_info(apicid, boot_cpu_apic_version); 1547 } 1548 1549 if (!num_processors) 1550 num_processors = 1; 1551 } 1552 1553 i = setup_max_cpus ?: 1; 1554 if (setup_possible_cpus == -1) { 1555 possible = num_processors; 1556 #ifdef CONFIG_HOTPLUG_CPU 1557 if (setup_max_cpus) 1558 possible += disabled_cpus; 1559 #else 1560 if (possible > i) 1561 possible = i; 1562 #endif 1563 } else 1564 possible = setup_possible_cpus; 1565 1566 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1567 1568 /* nr_cpu_ids could be reduced via nr_cpus= */ 1569 if (possible > nr_cpu_ids) { 1570 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1571 possible, nr_cpu_ids); 1572 possible = nr_cpu_ids; 1573 } 1574 1575 #ifdef CONFIG_HOTPLUG_CPU 1576 if (!setup_max_cpus) 1577 #endif 1578 if (possible > i) { 1579 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1580 possible, setup_max_cpus); 1581 possible = i; 1582 } 1583 1584 set_nr_cpu_ids(possible); 1585 1586 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1587 possible, max_t(int, possible - num_processors, 0)); 1588 1589 reset_cpu_possible_mask(); 1590 1591 for (i = 0; i < possible; i++) 1592 set_cpu_possible(i, true); 1593 } 1594 1595 #ifdef CONFIG_HOTPLUG_CPU 1596 1597 /* Recompute SMT state for all CPUs on offline */ 1598 static void recompute_smt_state(void) 1599 { 1600 int max_threads, cpu; 1601 1602 max_threads = 0; 1603 for_each_online_cpu (cpu) { 1604 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1605 1606 if (threads > max_threads) 1607 max_threads = threads; 1608 } 1609 __max_smt_threads = max_threads; 1610 } 1611 1612 static void remove_siblinginfo(int cpu) 1613 { 1614 int sibling; 1615 struct cpuinfo_x86 *c = &cpu_data(cpu); 1616 1617 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1618 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1619 /*/ 1620 * last thread sibling in this cpu core going down 1621 */ 1622 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1623 cpu_data(sibling).booted_cores--; 1624 } 1625 1626 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1627 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1628 1629 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1630 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1631 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1632 cpu_data(sibling).smt_active = false; 1633 } 1634 1635 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1636 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1637 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1638 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1639 cpumask_clear(cpu_llc_shared_mask(cpu)); 1640 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1641 cpumask_clear(topology_sibling_cpumask(cpu)); 1642 cpumask_clear(topology_core_cpumask(cpu)); 1643 cpumask_clear(topology_die_cpumask(cpu)); 1644 c->cpu_core_id = 0; 1645 c->booted_cores = 0; 1646 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1647 recompute_smt_state(); 1648 } 1649 1650 static void remove_cpu_from_maps(int cpu) 1651 { 1652 set_cpu_online(cpu, false); 1653 cpumask_clear_cpu(cpu, cpu_callout_mask); 1654 cpumask_clear_cpu(cpu, cpu_callin_mask); 1655 /* was set by cpu_init() */ 1656 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1657 numa_remove_cpu(cpu); 1658 } 1659 1660 void cpu_disable_common(void) 1661 { 1662 int cpu = smp_processor_id(); 1663 1664 remove_siblinginfo(cpu); 1665 1666 /* It's now safe to remove this processor from the online map */ 1667 lock_vector_lock(); 1668 remove_cpu_from_maps(cpu); 1669 unlock_vector_lock(); 1670 fixup_irqs(); 1671 lapic_offline(); 1672 } 1673 1674 int native_cpu_disable(void) 1675 { 1676 int ret; 1677 1678 ret = lapic_can_unplug_cpu(); 1679 if (ret) 1680 return ret; 1681 1682 cpu_disable_common(); 1683 1684 /* 1685 * Disable the local APIC. Otherwise IPI broadcasts will reach 1686 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1687 * messages. 1688 * 1689 * Disabling the APIC must happen after cpu_disable_common() 1690 * which invokes fixup_irqs(). 1691 * 1692 * Disabling the APIC preserves already set bits in IRR, but 1693 * an interrupt arriving after disabling the local APIC does not 1694 * set the corresponding IRR bit. 1695 * 1696 * fixup_irqs() scans IRR for set bits so it can raise a not 1697 * yet handled interrupt on the new destination CPU via an IPI 1698 * but obviously it can't do so for IRR bits which are not set. 1699 * IOW, interrupts arriving after disabling the local APIC will 1700 * be lost. 1701 */ 1702 apic_soft_disable(); 1703 1704 return 0; 1705 } 1706 1707 int common_cpu_die(unsigned int cpu) 1708 { 1709 int ret = 0; 1710 1711 /* We don't do anything here: idle task is faking death itself. */ 1712 1713 /* They ack this in play_dead() by setting CPU_DEAD */ 1714 if (cpu_wait_death(cpu, 5)) { 1715 if (system_state == SYSTEM_RUNNING) 1716 pr_info("CPU %u is now offline\n", cpu); 1717 } else { 1718 pr_err("CPU %u didn't die...\n", cpu); 1719 ret = -1; 1720 } 1721 1722 return ret; 1723 } 1724 1725 void native_cpu_die(unsigned int cpu) 1726 { 1727 common_cpu_die(cpu); 1728 } 1729 1730 void play_dead_common(void) 1731 { 1732 idle_task_exit(); 1733 1734 /* Ack it */ 1735 (void)cpu_report_death(); 1736 1737 /* 1738 * With physical CPU hotplug, we should halt the cpu 1739 */ 1740 local_irq_disable(); 1741 } 1742 1743 /** 1744 * cond_wakeup_cpu0 - Wake up CPU0 if needed. 1745 * 1746 * If NMI wants to wake up CPU0, start CPU0. 1747 */ 1748 void cond_wakeup_cpu0(void) 1749 { 1750 if (smp_processor_id() == 0 && enable_start_cpu0) 1751 start_cpu0(); 1752 } 1753 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0); 1754 1755 /* 1756 * We need to flush the caches before going to sleep, lest we have 1757 * dirty data in our caches when we come back up. 1758 */ 1759 static inline void mwait_play_dead(void) 1760 { 1761 unsigned int eax, ebx, ecx, edx; 1762 unsigned int highest_cstate = 0; 1763 unsigned int highest_subcstate = 0; 1764 void *mwait_ptr; 1765 int i; 1766 1767 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1768 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1769 return; 1770 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1771 return; 1772 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1773 return; 1774 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1775 return; 1776 1777 eax = CPUID_MWAIT_LEAF; 1778 ecx = 0; 1779 native_cpuid(&eax, &ebx, &ecx, &edx); 1780 1781 /* 1782 * eax will be 0 if EDX enumeration is not valid. 1783 * Initialized below to cstate, sub_cstate value when EDX is valid. 1784 */ 1785 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1786 eax = 0; 1787 } else { 1788 edx >>= MWAIT_SUBSTATE_SIZE; 1789 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1790 if (edx & MWAIT_SUBSTATE_MASK) { 1791 highest_cstate = i; 1792 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1793 } 1794 } 1795 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1796 (highest_subcstate - 1); 1797 } 1798 1799 /* 1800 * This should be a memory location in a cache line which is 1801 * unlikely to be touched by other processors. The actual 1802 * content is immaterial as it is not actually modified in any way. 1803 */ 1804 mwait_ptr = ¤t_thread_info()->flags; 1805 1806 wbinvd(); 1807 1808 while (1) { 1809 /* 1810 * The CLFLUSH is a workaround for erratum AAI65 for 1811 * the Xeon 7400 series. It's not clear it is actually 1812 * needed, but it should be harmless in either case. 1813 * The WBINVD is insufficient due to the spurious-wakeup 1814 * case where we return around the loop. 1815 */ 1816 mb(); 1817 clflush(mwait_ptr); 1818 mb(); 1819 __monitor(mwait_ptr, 0, 0); 1820 mb(); 1821 __mwait(eax, 0); 1822 1823 cond_wakeup_cpu0(); 1824 } 1825 } 1826 1827 void __noreturn hlt_play_dead(void) 1828 { 1829 if (__this_cpu_read(cpu_info.x86) >= 4) 1830 wbinvd(); 1831 1832 while (1) { 1833 native_halt(); 1834 1835 cond_wakeup_cpu0(); 1836 } 1837 } 1838 1839 void native_play_dead(void) 1840 { 1841 play_dead_common(); 1842 tboot_shutdown(TB_SHUTDOWN_WFS); 1843 1844 mwait_play_dead(); 1845 if (cpuidle_play_dead()) 1846 hlt_play_dead(); 1847 } 1848 1849 #else /* ... !CONFIG_HOTPLUG_CPU */ 1850 int native_cpu_disable(void) 1851 { 1852 return -ENOSYS; 1853 } 1854 1855 void native_cpu_die(unsigned int cpu) 1856 { 1857 /* We said "no" in __cpu_disable */ 1858 BUG(); 1859 } 1860 1861 void native_play_dead(void) 1862 { 1863 BUG(); 1864 } 1865 1866 #endif 1867