1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/bootmem.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/misc.h> 79 #include <asm/qspinlock.h> 80 #include <asm/intel-family.h> 81 #include <asm/cpu_device_id.h> 82 #include <asm/spec-ctrl.h> 83 84 /* representing HT siblings of each logical CPU */ 85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 87 88 /* representing HT and core siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 91 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 93 94 /* Per CPU bogomips and other parameters */ 95 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 96 EXPORT_PER_CPU_SYMBOL(cpu_info); 97 98 /* Logical package management. We might want to allocate that dynamically */ 99 unsigned int __max_logical_packages __read_mostly; 100 EXPORT_SYMBOL(__max_logical_packages); 101 static unsigned int logical_packages __read_mostly; 102 103 /* Maximum number of SMT threads on any online core */ 104 int __read_mostly __max_smt_threads = 1; 105 106 /* Flag to indicate if a complete sched domain rebuild is required */ 107 bool x86_topology_update; 108 109 int arch_update_cpu_topology(void) 110 { 111 int retval = x86_topology_update; 112 113 x86_topology_update = false; 114 return retval; 115 } 116 117 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 118 { 119 unsigned long flags; 120 121 spin_lock_irqsave(&rtc_lock, flags); 122 CMOS_WRITE(0xa, 0xf); 123 spin_unlock_irqrestore(&rtc_lock, flags); 124 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 125 start_eip >> 4; 126 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 127 start_eip & 0xf; 128 } 129 130 static inline void smpboot_restore_warm_reset_vector(void) 131 { 132 unsigned long flags; 133 134 /* 135 * Paranoid: Set warm reset code and vector here back 136 * to default values. 137 */ 138 spin_lock_irqsave(&rtc_lock, flags); 139 CMOS_WRITE(0, 0xf); 140 spin_unlock_irqrestore(&rtc_lock, flags); 141 142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 143 } 144 145 /* 146 * Report back to the Boot Processor during boot time or to the caller processor 147 * during CPU online. 148 */ 149 static void smp_callin(void) 150 { 151 int cpuid, phys_id; 152 153 /* 154 * If waken up by an INIT in an 82489DX configuration 155 * cpu_callout_mask guarantees we don't get here before 156 * an INIT_deassert IPI reaches our local APIC, so it is 157 * now safe to touch our local APIC. 158 */ 159 cpuid = smp_processor_id(); 160 161 /* 162 * (This works even if the APIC is not enabled.) 163 */ 164 phys_id = read_apic_id(); 165 166 /* 167 * the boot CPU has finished the init stage and is spinning 168 * on callin_map until we finish. We are free to set up this 169 * CPU, first the APIC. (this is probably redundant on most 170 * boards) 171 */ 172 apic_ap_setup(); 173 174 /* 175 * Save our processor parameters. Note: this information 176 * is needed for clock calibration. 177 */ 178 smp_store_cpu_info(cpuid); 179 180 /* 181 * The topology information must be up to date before 182 * calibrate_delay() and notify_cpu_starting(). 183 */ 184 set_cpu_sibling_map(raw_smp_processor_id()); 185 186 /* 187 * Get our bogomips. 188 * Update loops_per_jiffy in cpu_data. Previous call to 189 * smp_store_cpu_info() stored a value that is close but not as 190 * accurate as the value just calculated. 191 */ 192 calibrate_delay(); 193 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 194 pr_debug("Stack at about %p\n", &cpuid); 195 196 wmb(); 197 198 notify_cpu_starting(cpuid); 199 200 /* 201 * Allow the master to continue. 202 */ 203 cpumask_set_cpu(cpuid, cpu_callin_mask); 204 } 205 206 static int cpu0_logical_apicid; 207 static int enable_start_cpu0; 208 /* 209 * Activate a secondary processor. 210 */ 211 static void notrace start_secondary(void *unused) 212 { 213 /* 214 * Don't put *anything* except direct CPU state initialization 215 * before cpu_init(), SMP booting is too fragile that we want to 216 * limit the things done here to the most necessary things. 217 */ 218 if (boot_cpu_has(X86_FEATURE_PCID)) 219 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 220 221 #ifdef CONFIG_X86_32 222 /* switch away from the initial page table */ 223 load_cr3(swapper_pg_dir); 224 /* 225 * Initialize the CR4 shadow before doing anything that could 226 * try to read it. 227 */ 228 cr4_init_shadow(); 229 __flush_tlb_all(); 230 #endif 231 load_current_idt(); 232 cpu_init(); 233 x86_cpuinit.early_percpu_clock_init(); 234 preempt_disable(); 235 smp_callin(); 236 237 enable_start_cpu0 = 0; 238 239 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 240 barrier(); 241 /* 242 * Check TSC synchronization with the boot CPU: 243 */ 244 check_tsc_sync_target(); 245 246 speculative_store_bypass_ht_init(); 247 248 /* 249 * Lock vector_lock, set CPU online and bring the vector 250 * allocator online. Online must be set with vector_lock held 251 * to prevent a concurrent irq setup/teardown from seeing a 252 * half valid vector space. 253 */ 254 lock_vector_lock(); 255 set_cpu_online(smp_processor_id(), true); 256 lapic_online(); 257 unlock_vector_lock(); 258 cpu_set_state_online(smp_processor_id()); 259 x86_platform.nmi_init(); 260 261 /* enable local interrupts */ 262 local_irq_enable(); 263 264 /* to prevent fake stack check failure in clock setup */ 265 boot_init_stack_canary(); 266 267 x86_cpuinit.setup_percpu_clockev(); 268 269 wmb(); 270 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 271 } 272 273 /** 274 * topology_phys_to_logical_pkg - Map a physical package id to a logical 275 * 276 * Returns logical package id or -1 if not found 277 */ 278 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 279 { 280 int cpu; 281 282 for_each_possible_cpu(cpu) { 283 struct cpuinfo_x86 *c = &cpu_data(cpu); 284 285 if (c->initialized && c->phys_proc_id == phys_pkg) 286 return c->logical_proc_id; 287 } 288 return -1; 289 } 290 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 291 292 /** 293 * topology_update_package_map - Update the physical to logical package map 294 * @pkg: The physical package id as retrieved via CPUID 295 * @cpu: The cpu for which this is updated 296 */ 297 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 298 { 299 int new; 300 301 /* Already available somewhere? */ 302 new = topology_phys_to_logical_pkg(pkg); 303 if (new >= 0) 304 goto found; 305 306 new = logical_packages++; 307 if (new != pkg) { 308 pr_info("CPU %u Converting physical %u to logical package %u\n", 309 cpu, pkg, new); 310 } 311 found: 312 cpu_data(cpu).logical_proc_id = new; 313 return 0; 314 } 315 316 void __init smp_store_boot_cpu_info(void) 317 { 318 int id = 0; /* CPU 0 */ 319 struct cpuinfo_x86 *c = &cpu_data(id); 320 321 *c = boot_cpu_data; 322 c->cpu_index = id; 323 topology_update_package_map(c->phys_proc_id, id); 324 c->initialized = true; 325 } 326 327 /* 328 * The bootstrap kernel entry code has set these up. Save them for 329 * a given CPU 330 */ 331 void smp_store_cpu_info(int id) 332 { 333 struct cpuinfo_x86 *c = &cpu_data(id); 334 335 /* Copy boot_cpu_data only on the first bringup */ 336 if (!c->initialized) 337 *c = boot_cpu_data; 338 c->cpu_index = id; 339 /* 340 * During boot time, CPU0 has this setup already. Save the info when 341 * bringing up AP or offlined CPU0. 342 */ 343 identify_secondary_cpu(c); 344 c->initialized = true; 345 } 346 347 static bool 348 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 349 { 350 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 351 352 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 353 } 354 355 static bool 356 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 357 { 358 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 359 360 return !WARN_ONCE(!topology_same_node(c, o), 361 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 362 "[node: %d != %d]. Ignoring dependency.\n", 363 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 364 } 365 366 #define link_mask(mfunc, c1, c2) \ 367 do { \ 368 cpumask_set_cpu((c1), mfunc(c2)); \ 369 cpumask_set_cpu((c2), mfunc(c1)); \ 370 } while (0) 371 372 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 373 { 374 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 375 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 376 377 if (c->phys_proc_id == o->phys_proc_id && 378 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 379 if (c->cpu_core_id == o->cpu_core_id) 380 return topology_sane(c, o, "smt"); 381 382 if ((c->cu_id != 0xff) && 383 (o->cu_id != 0xff) && 384 (c->cu_id == o->cu_id)) 385 return topology_sane(c, o, "smt"); 386 } 387 388 } else if (c->phys_proc_id == o->phys_proc_id && 389 c->cpu_core_id == o->cpu_core_id) { 390 return topology_sane(c, o, "smt"); 391 } 392 393 return false; 394 } 395 396 /* 397 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 398 * 399 * These are Intel CPUs that enumerate an LLC that is shared by 400 * multiple NUMA nodes. The LLC on these systems is shared for 401 * off-package data access but private to the NUMA node (half 402 * of the package) for on-package access. 403 * 404 * CPUID (the source of the information about the LLC) can only 405 * enumerate the cache as being shared *or* unshared, but not 406 * this particular configuration. The CPU in this case enumerates 407 * the cache to be shared across the entire package (spanning both 408 * NUMA nodes). 409 */ 410 411 static const struct x86_cpu_id snc_cpu[] = { 412 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X }, 413 {} 414 }; 415 416 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 417 { 418 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 419 420 /* Do not match if we do not have a valid APICID for cpu: */ 421 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 422 return false; 423 424 /* Do not match if LLC id does not match: */ 425 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 426 return false; 427 428 /* 429 * Allow the SNC topology without warning. Return of false 430 * means 'c' does not share the LLC of 'o'. This will be 431 * reflected to userspace. 432 */ 433 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 434 return false; 435 436 return topology_sane(c, o, "llc"); 437 } 438 439 /* 440 * Unlike the other levels, we do not enforce keeping a 441 * multicore group inside a NUMA node. If this happens, we will 442 * discard the MC level of the topology later. 443 */ 444 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 445 { 446 if (c->phys_proc_id == o->phys_proc_id) 447 return true; 448 return false; 449 } 450 451 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 452 static inline int x86_sched_itmt_flags(void) 453 { 454 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 455 } 456 457 #ifdef CONFIG_SCHED_MC 458 static int x86_core_flags(void) 459 { 460 return cpu_core_flags() | x86_sched_itmt_flags(); 461 } 462 #endif 463 #ifdef CONFIG_SCHED_SMT 464 static int x86_smt_flags(void) 465 { 466 return cpu_smt_flags() | x86_sched_itmt_flags(); 467 } 468 #endif 469 #endif 470 471 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 472 #ifdef CONFIG_SCHED_SMT 473 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 474 #endif 475 #ifdef CONFIG_SCHED_MC 476 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 477 #endif 478 { NULL, }, 479 }; 480 481 static struct sched_domain_topology_level x86_topology[] = { 482 #ifdef CONFIG_SCHED_SMT 483 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 484 #endif 485 #ifdef CONFIG_SCHED_MC 486 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 487 #endif 488 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 489 { NULL, }, 490 }; 491 492 /* 493 * Set if a package/die has multiple NUMA nodes inside. 494 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 495 * Sub-NUMA Clustering have this. 496 */ 497 static bool x86_has_numa_in_package; 498 499 void set_cpu_sibling_map(int cpu) 500 { 501 bool has_smt = smp_num_siblings > 1; 502 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 503 struct cpuinfo_x86 *c = &cpu_data(cpu); 504 struct cpuinfo_x86 *o; 505 int i, threads; 506 507 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 508 509 if (!has_mp) { 510 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 511 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 512 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 513 c->booted_cores = 1; 514 return; 515 } 516 517 for_each_cpu(i, cpu_sibling_setup_mask) { 518 o = &cpu_data(i); 519 520 if ((i == cpu) || (has_smt && match_smt(c, o))) 521 link_mask(topology_sibling_cpumask, cpu, i); 522 523 if ((i == cpu) || (has_mp && match_llc(c, o))) 524 link_mask(cpu_llc_shared_mask, cpu, i); 525 526 } 527 528 /* 529 * This needs a separate iteration over the cpus because we rely on all 530 * topology_sibling_cpumask links to be set-up. 531 */ 532 for_each_cpu(i, cpu_sibling_setup_mask) { 533 o = &cpu_data(i); 534 535 if ((i == cpu) || (has_mp && match_die(c, o))) { 536 link_mask(topology_core_cpumask, cpu, i); 537 538 /* 539 * Does this new cpu bringup a new core? 540 */ 541 if (cpumask_weight( 542 topology_sibling_cpumask(cpu)) == 1) { 543 /* 544 * for each core in package, increment 545 * the booted_cores for this new cpu 546 */ 547 if (cpumask_first( 548 topology_sibling_cpumask(i)) == i) 549 c->booted_cores++; 550 /* 551 * increment the core count for all 552 * the other cpus in this package 553 */ 554 if (i != cpu) 555 cpu_data(i).booted_cores++; 556 } else if (i != cpu && !c->booted_cores) 557 c->booted_cores = cpu_data(i).booted_cores; 558 } 559 if (match_die(c, o) && !topology_same_node(c, o)) 560 x86_has_numa_in_package = true; 561 } 562 563 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 564 if (threads > __max_smt_threads) 565 __max_smt_threads = threads; 566 } 567 568 /* maps the cpu to the sched domain representing multi-core */ 569 const struct cpumask *cpu_coregroup_mask(int cpu) 570 { 571 return cpu_llc_shared_mask(cpu); 572 } 573 574 static void impress_friends(void) 575 { 576 int cpu; 577 unsigned long bogosum = 0; 578 /* 579 * Allow the user to impress friends. 580 */ 581 pr_debug("Before bogomips\n"); 582 for_each_possible_cpu(cpu) 583 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 584 bogosum += cpu_data(cpu).loops_per_jiffy; 585 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 586 num_online_cpus(), 587 bogosum/(500000/HZ), 588 (bogosum/(5000/HZ))%100); 589 590 pr_debug("Before bogocount - setting activated=1\n"); 591 } 592 593 void __inquire_remote_apic(int apicid) 594 { 595 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 596 const char * const names[] = { "ID", "VERSION", "SPIV" }; 597 int timeout; 598 u32 status; 599 600 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 601 602 for (i = 0; i < ARRAY_SIZE(regs); i++) { 603 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 604 605 /* 606 * Wait for idle. 607 */ 608 status = safe_apic_wait_icr_idle(); 609 if (status) 610 pr_cont("a previous APIC delivery may have failed\n"); 611 612 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 613 614 timeout = 0; 615 do { 616 udelay(100); 617 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 618 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 619 620 switch (status) { 621 case APIC_ICR_RR_VALID: 622 status = apic_read(APIC_RRR); 623 pr_cont("%08x\n", status); 624 break; 625 default: 626 pr_cont("failed\n"); 627 } 628 } 629 } 630 631 /* 632 * The Multiprocessor Specification 1.4 (1997) example code suggests 633 * that there should be a 10ms delay between the BSP asserting INIT 634 * and de-asserting INIT, when starting a remote processor. 635 * But that slows boot and resume on modern processors, which include 636 * many cores and don't require that delay. 637 * 638 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 639 * Modern processor families are quirked to remove the delay entirely. 640 */ 641 #define UDELAY_10MS_DEFAULT 10000 642 643 static unsigned int init_udelay = UINT_MAX; 644 645 static int __init cpu_init_udelay(char *str) 646 { 647 get_option(&str, &init_udelay); 648 649 return 0; 650 } 651 early_param("cpu_init_udelay", cpu_init_udelay); 652 653 static void __init smp_quirk_init_udelay(void) 654 { 655 /* if cmdline changed it from default, leave it alone */ 656 if (init_udelay != UINT_MAX) 657 return; 658 659 /* if modern processor, use no delay */ 660 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 661 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 662 init_udelay = 0; 663 return; 664 } 665 /* else, use legacy delay */ 666 init_udelay = UDELAY_10MS_DEFAULT; 667 } 668 669 /* 670 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 671 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 672 * won't ... remember to clear down the APIC, etc later. 673 */ 674 int 675 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 676 { 677 unsigned long send_status, accept_status = 0; 678 int maxlvt; 679 680 /* Target chip */ 681 /* Boot on the stack */ 682 /* Kick the second */ 683 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 684 685 pr_debug("Waiting for send to finish...\n"); 686 send_status = safe_apic_wait_icr_idle(); 687 688 /* 689 * Give the other CPU some time to accept the IPI. 690 */ 691 udelay(200); 692 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 693 maxlvt = lapic_get_maxlvt(); 694 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 695 apic_write(APIC_ESR, 0); 696 accept_status = (apic_read(APIC_ESR) & 0xEF); 697 } 698 pr_debug("NMI sent\n"); 699 700 if (send_status) 701 pr_err("APIC never delivered???\n"); 702 if (accept_status) 703 pr_err("APIC delivery error (%lx)\n", accept_status); 704 705 return (send_status | accept_status); 706 } 707 708 static int 709 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 710 { 711 unsigned long send_status = 0, accept_status = 0; 712 int maxlvt, num_starts, j; 713 714 maxlvt = lapic_get_maxlvt(); 715 716 /* 717 * Be paranoid about clearing APIC errors. 718 */ 719 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 720 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 721 apic_write(APIC_ESR, 0); 722 apic_read(APIC_ESR); 723 } 724 725 pr_debug("Asserting INIT\n"); 726 727 /* 728 * Turn INIT on target chip 729 */ 730 /* 731 * Send IPI 732 */ 733 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 734 phys_apicid); 735 736 pr_debug("Waiting for send to finish...\n"); 737 send_status = safe_apic_wait_icr_idle(); 738 739 udelay(init_udelay); 740 741 pr_debug("Deasserting INIT\n"); 742 743 /* Target chip */ 744 /* Send IPI */ 745 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 746 747 pr_debug("Waiting for send to finish...\n"); 748 send_status = safe_apic_wait_icr_idle(); 749 750 mb(); 751 752 /* 753 * Should we send STARTUP IPIs ? 754 * 755 * Determine this based on the APIC version. 756 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 757 */ 758 if (APIC_INTEGRATED(boot_cpu_apic_version)) 759 num_starts = 2; 760 else 761 num_starts = 0; 762 763 /* 764 * Run STARTUP IPI loop. 765 */ 766 pr_debug("#startup loops: %d\n", num_starts); 767 768 for (j = 1; j <= num_starts; j++) { 769 pr_debug("Sending STARTUP #%d\n", j); 770 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 771 apic_write(APIC_ESR, 0); 772 apic_read(APIC_ESR); 773 pr_debug("After apic_write\n"); 774 775 /* 776 * STARTUP IPI 777 */ 778 779 /* Target chip */ 780 /* Boot on the stack */ 781 /* Kick the second */ 782 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 783 phys_apicid); 784 785 /* 786 * Give the other CPU some time to accept the IPI. 787 */ 788 if (init_udelay == 0) 789 udelay(10); 790 else 791 udelay(300); 792 793 pr_debug("Startup point 1\n"); 794 795 pr_debug("Waiting for send to finish...\n"); 796 send_status = safe_apic_wait_icr_idle(); 797 798 /* 799 * Give the other CPU some time to accept the IPI. 800 */ 801 if (init_udelay == 0) 802 udelay(10); 803 else 804 udelay(200); 805 806 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 807 apic_write(APIC_ESR, 0); 808 accept_status = (apic_read(APIC_ESR) & 0xEF); 809 if (send_status || accept_status) 810 break; 811 } 812 pr_debug("After Startup\n"); 813 814 if (send_status) 815 pr_err("APIC never delivered???\n"); 816 if (accept_status) 817 pr_err("APIC delivery error (%lx)\n", accept_status); 818 819 return (send_status | accept_status); 820 } 821 822 /* reduce the number of lines printed when booting a large cpu count system */ 823 static void announce_cpu(int cpu, int apicid) 824 { 825 static int current_node = -1; 826 int node = early_cpu_to_node(cpu); 827 static int width, node_width; 828 829 if (!width) 830 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 831 832 if (!node_width) 833 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 834 835 if (cpu == 1) 836 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 837 838 if (system_state < SYSTEM_RUNNING) { 839 if (node != current_node) { 840 if (current_node > (-1)) 841 pr_cont("\n"); 842 current_node = node; 843 844 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 845 node_width - num_digits(node), " ", node); 846 } 847 848 /* Add padding for the BSP */ 849 if (cpu == 1) 850 pr_cont("%*s", width + 1, " "); 851 852 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 853 854 } else 855 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 856 node, cpu, apicid); 857 } 858 859 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 860 { 861 int cpu; 862 863 cpu = smp_processor_id(); 864 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 865 return NMI_HANDLED; 866 867 return NMI_DONE; 868 } 869 870 /* 871 * Wake up AP by INIT, INIT, STARTUP sequence. 872 * 873 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 874 * boot-strap code which is not a desired behavior for waking up BSP. To 875 * void the boot-strap code, wake up CPU0 by NMI instead. 876 * 877 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 878 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 879 * We'll change this code in the future to wake up hard offlined CPU0 if 880 * real platform and request are available. 881 */ 882 static int 883 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 884 int *cpu0_nmi_registered) 885 { 886 int id; 887 int boot_error; 888 889 preempt_disable(); 890 891 /* 892 * Wake up AP by INIT, INIT, STARTUP sequence. 893 */ 894 if (cpu) { 895 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 896 goto out; 897 } 898 899 /* 900 * Wake up BSP by nmi. 901 * 902 * Register a NMI handler to help wake up CPU0. 903 */ 904 boot_error = register_nmi_handler(NMI_LOCAL, 905 wakeup_cpu0_nmi, 0, "wake_cpu0"); 906 907 if (!boot_error) { 908 enable_start_cpu0 = 1; 909 *cpu0_nmi_registered = 1; 910 if (apic->dest_logical == APIC_DEST_LOGICAL) 911 id = cpu0_logical_apicid; 912 else 913 id = apicid; 914 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 915 } 916 917 out: 918 preempt_enable(); 919 920 return boot_error; 921 } 922 923 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 924 { 925 /* Just in case we booted with a single CPU. */ 926 alternatives_enable_smp(); 927 928 per_cpu(current_task, cpu) = idle; 929 930 #ifdef CONFIG_X86_32 931 /* Stack for startup_32 can be just as for start_secondary onwards */ 932 irq_ctx_init(cpu); 933 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 934 #else 935 initial_gs = per_cpu_offset(cpu); 936 #endif 937 } 938 939 /* 940 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 941 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 942 * Returns zero if CPU booted OK, else error code from 943 * ->wakeup_secondary_cpu. 944 */ 945 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 946 int *cpu0_nmi_registered) 947 { 948 volatile u32 *trampoline_status = 949 (volatile u32 *) __va(real_mode_header->trampoline_status); 950 /* start_ip had better be page-aligned! */ 951 unsigned long start_ip = real_mode_header->trampoline_start; 952 953 unsigned long boot_error = 0; 954 unsigned long timeout; 955 956 idle->thread.sp = (unsigned long)task_pt_regs(idle); 957 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 958 initial_code = (unsigned long)start_secondary; 959 initial_stack = idle->thread.sp; 960 961 /* Enable the espfix hack for this CPU */ 962 init_espfix_ap(cpu); 963 964 /* So we see what's up */ 965 announce_cpu(cpu, apicid); 966 967 /* 968 * This grunge runs the startup process for 969 * the targeted processor. 970 */ 971 972 if (x86_platform.legacy.warm_reset) { 973 974 pr_debug("Setting warm reset code and vector.\n"); 975 976 smpboot_setup_warm_reset_vector(start_ip); 977 /* 978 * Be paranoid about clearing APIC errors. 979 */ 980 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 981 apic_write(APIC_ESR, 0); 982 apic_read(APIC_ESR); 983 } 984 } 985 986 /* 987 * AP might wait on cpu_callout_mask in cpu_init() with 988 * cpu_initialized_mask set if previous attempt to online 989 * it timed-out. Clear cpu_initialized_mask so that after 990 * INIT/SIPI it could start with a clean state. 991 */ 992 cpumask_clear_cpu(cpu, cpu_initialized_mask); 993 smp_mb(); 994 995 /* 996 * Wake up a CPU in difference cases: 997 * - Use the method in the APIC driver if it's defined 998 * Otherwise, 999 * - Use an INIT boot APIC message for APs or NMI for BSP. 1000 */ 1001 if (apic->wakeup_secondary_cpu) 1002 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1003 else 1004 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1005 cpu0_nmi_registered); 1006 1007 if (!boot_error) { 1008 /* 1009 * Wait 10s total for first sign of life from AP 1010 */ 1011 boot_error = -1; 1012 timeout = jiffies + 10*HZ; 1013 while (time_before(jiffies, timeout)) { 1014 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1015 /* 1016 * Tell AP to proceed with initialization 1017 */ 1018 cpumask_set_cpu(cpu, cpu_callout_mask); 1019 boot_error = 0; 1020 break; 1021 } 1022 schedule(); 1023 } 1024 } 1025 1026 if (!boot_error) { 1027 /* 1028 * Wait till AP completes initial initialization 1029 */ 1030 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1031 /* 1032 * Allow other tasks to run while we wait for the 1033 * AP to come online. This also gives a chance 1034 * for the MTRR work(triggered by the AP coming online) 1035 * to be completed in the stop machine context. 1036 */ 1037 schedule(); 1038 } 1039 } 1040 1041 /* mark "stuck" area as not stuck */ 1042 *trampoline_status = 0; 1043 1044 if (x86_platform.legacy.warm_reset) { 1045 /* 1046 * Cleanup possible dangling ends... 1047 */ 1048 smpboot_restore_warm_reset_vector(); 1049 } 1050 1051 return boot_error; 1052 } 1053 1054 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1055 { 1056 int apicid = apic->cpu_present_to_apicid(cpu); 1057 int cpu0_nmi_registered = 0; 1058 unsigned long flags; 1059 int err, ret = 0; 1060 1061 lockdep_assert_irqs_enabled(); 1062 1063 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1064 1065 if (apicid == BAD_APICID || 1066 !physid_isset(apicid, phys_cpu_present_map) || 1067 !apic->apic_id_valid(apicid)) { 1068 pr_err("%s: bad cpu %d\n", __func__, cpu); 1069 return -EINVAL; 1070 } 1071 1072 /* 1073 * Already booted CPU? 1074 */ 1075 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1076 pr_debug("do_boot_cpu %d Already started\n", cpu); 1077 return -ENOSYS; 1078 } 1079 1080 /* 1081 * Save current MTRR state in case it was changed since early boot 1082 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1083 */ 1084 mtrr_save_state(); 1085 1086 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1087 err = cpu_check_up_prepare(cpu); 1088 if (err && err != -EBUSY) 1089 return err; 1090 1091 /* the FPU context is blank, nobody can own it */ 1092 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1093 1094 common_cpu_up(cpu, tidle); 1095 1096 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1097 if (err) { 1098 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1099 ret = -EIO; 1100 goto unreg_nmi; 1101 } 1102 1103 /* 1104 * Check TSC synchronization with the AP (keep irqs disabled 1105 * while doing so): 1106 */ 1107 local_irq_save(flags); 1108 check_tsc_sync_source(cpu); 1109 local_irq_restore(flags); 1110 1111 while (!cpu_online(cpu)) { 1112 cpu_relax(); 1113 touch_nmi_watchdog(); 1114 } 1115 1116 unreg_nmi: 1117 /* 1118 * Clean up the nmi handler. Do this after the callin and callout sync 1119 * to avoid impact of possible long unregister time. 1120 */ 1121 if (cpu0_nmi_registered) 1122 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1123 1124 return ret; 1125 } 1126 1127 /** 1128 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1129 */ 1130 void arch_disable_smp_support(void) 1131 { 1132 disable_ioapic_support(); 1133 } 1134 1135 /* 1136 * Fall back to non SMP mode after errors. 1137 * 1138 * RED-PEN audit/test this more. I bet there is more state messed up here. 1139 */ 1140 static __init void disable_smp(void) 1141 { 1142 pr_info("SMP disabled\n"); 1143 1144 disable_ioapic_support(); 1145 1146 init_cpu_present(cpumask_of(0)); 1147 init_cpu_possible(cpumask_of(0)); 1148 1149 if (smp_found_config) 1150 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1151 else 1152 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1153 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1154 cpumask_set_cpu(0, topology_core_cpumask(0)); 1155 } 1156 1157 /* 1158 * Various sanity checks. 1159 */ 1160 static void __init smp_sanity_check(void) 1161 { 1162 preempt_disable(); 1163 1164 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1165 if (def_to_bigsmp && nr_cpu_ids > 8) { 1166 unsigned int cpu; 1167 unsigned nr; 1168 1169 pr_warn("More than 8 CPUs detected - skipping them\n" 1170 "Use CONFIG_X86_BIGSMP\n"); 1171 1172 nr = 0; 1173 for_each_present_cpu(cpu) { 1174 if (nr >= 8) 1175 set_cpu_present(cpu, false); 1176 nr++; 1177 } 1178 1179 nr = 0; 1180 for_each_possible_cpu(cpu) { 1181 if (nr >= 8) 1182 set_cpu_possible(cpu, false); 1183 nr++; 1184 } 1185 1186 nr_cpu_ids = 8; 1187 } 1188 #endif 1189 1190 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1191 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1192 hard_smp_processor_id()); 1193 1194 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1195 } 1196 1197 /* 1198 * Should not be necessary because the MP table should list the boot 1199 * CPU too, but we do it for the sake of robustness anyway. 1200 */ 1201 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1202 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1203 boot_cpu_physical_apicid); 1204 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1205 } 1206 preempt_enable(); 1207 } 1208 1209 static void __init smp_cpu_index_default(void) 1210 { 1211 int i; 1212 struct cpuinfo_x86 *c; 1213 1214 for_each_possible_cpu(i) { 1215 c = &cpu_data(i); 1216 /* mark all to hotplug */ 1217 c->cpu_index = nr_cpu_ids; 1218 } 1219 } 1220 1221 static void __init smp_get_logical_apicid(void) 1222 { 1223 if (x2apic_mode) 1224 cpu0_logical_apicid = apic_read(APIC_LDR); 1225 else 1226 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1227 } 1228 1229 /* 1230 * Prepare for SMP bootup. 1231 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1232 * for common interface support. 1233 */ 1234 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1235 { 1236 unsigned int i; 1237 1238 smp_cpu_index_default(); 1239 1240 /* 1241 * Setup boot CPU information 1242 */ 1243 smp_store_boot_cpu_info(); /* Final full version of the data */ 1244 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1245 mb(); 1246 1247 for_each_possible_cpu(i) { 1248 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1249 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1250 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1251 } 1252 1253 /* 1254 * Set 'default' x86 topology, this matches default_topology() in that 1255 * it has NUMA nodes as a topology level. See also 1256 * native_smp_cpus_done(). 1257 * 1258 * Must be done before set_cpus_sibling_map() is ran. 1259 */ 1260 set_sched_topology(x86_topology); 1261 1262 set_cpu_sibling_map(0); 1263 1264 smp_sanity_check(); 1265 1266 switch (apic_intr_mode) { 1267 case APIC_PIC: 1268 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1269 disable_smp(); 1270 return; 1271 case APIC_SYMMETRIC_IO_NO_ROUTING: 1272 disable_smp(); 1273 /* Setup local timer */ 1274 x86_init.timers.setup_percpu_clockev(); 1275 return; 1276 case APIC_VIRTUAL_WIRE: 1277 case APIC_SYMMETRIC_IO: 1278 break; 1279 } 1280 1281 /* Setup local timer */ 1282 x86_init.timers.setup_percpu_clockev(); 1283 1284 smp_get_logical_apicid(); 1285 1286 pr_info("CPU0: "); 1287 print_cpu_info(&cpu_data(0)); 1288 1289 native_pv_lock_init(); 1290 1291 uv_system_init(); 1292 1293 set_mtrr_aps_delayed_init(); 1294 1295 smp_quirk_init_udelay(); 1296 1297 speculative_store_bypass_ht_init(); 1298 } 1299 1300 void arch_enable_nonboot_cpus_begin(void) 1301 { 1302 set_mtrr_aps_delayed_init(); 1303 } 1304 1305 void arch_enable_nonboot_cpus_end(void) 1306 { 1307 mtrr_aps_init(); 1308 } 1309 1310 /* 1311 * Early setup to make printk work. 1312 */ 1313 void __init native_smp_prepare_boot_cpu(void) 1314 { 1315 int me = smp_processor_id(); 1316 switch_to_new_gdt(me); 1317 /* already set me in cpu_online_mask in boot_cpu_init() */ 1318 cpumask_set_cpu(me, cpu_callout_mask); 1319 cpu_set_state_online(me); 1320 } 1321 1322 void __init calculate_max_logical_packages(void) 1323 { 1324 int ncpus; 1325 1326 /* 1327 * Today neither Intel nor AMD support heterogenous systems so 1328 * extrapolate the boot cpu's data to all packages. 1329 */ 1330 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1331 __max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus); 1332 pr_info("Max logical packages: %u\n", __max_logical_packages); 1333 } 1334 1335 void __init native_smp_cpus_done(unsigned int max_cpus) 1336 { 1337 pr_debug("Boot done\n"); 1338 1339 calculate_max_logical_packages(); 1340 1341 if (x86_has_numa_in_package) 1342 set_sched_topology(x86_numa_in_package_topology); 1343 1344 nmi_selftest(); 1345 impress_friends(); 1346 mtrr_aps_init(); 1347 } 1348 1349 static int __initdata setup_possible_cpus = -1; 1350 static int __init _setup_possible_cpus(char *str) 1351 { 1352 get_option(&str, &setup_possible_cpus); 1353 return 0; 1354 } 1355 early_param("possible_cpus", _setup_possible_cpus); 1356 1357 1358 /* 1359 * cpu_possible_mask should be static, it cannot change as cpu's 1360 * are onlined, or offlined. The reason is per-cpu data-structures 1361 * are allocated by some modules at init time, and dont expect to 1362 * do this dynamically on cpu arrival/departure. 1363 * cpu_present_mask on the other hand can change dynamically. 1364 * In case when cpu_hotplug is not compiled, then we resort to current 1365 * behaviour, which is cpu_possible == cpu_present. 1366 * - Ashok Raj 1367 * 1368 * Three ways to find out the number of additional hotplug CPUs: 1369 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1370 * - The user can overwrite it with possible_cpus=NUM 1371 * - Otherwise don't reserve additional CPUs. 1372 * We do this because additional CPUs waste a lot of memory. 1373 * -AK 1374 */ 1375 __init void prefill_possible_map(void) 1376 { 1377 int i, possible; 1378 1379 /* No boot processor was found in mptable or ACPI MADT */ 1380 if (!num_processors) { 1381 if (boot_cpu_has(X86_FEATURE_APIC)) { 1382 int apicid = boot_cpu_physical_apicid; 1383 int cpu = hard_smp_processor_id(); 1384 1385 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1386 1387 /* Make sure boot cpu is enumerated */ 1388 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1389 apic->apic_id_valid(apicid)) 1390 generic_processor_info(apicid, boot_cpu_apic_version); 1391 } 1392 1393 if (!num_processors) 1394 num_processors = 1; 1395 } 1396 1397 i = setup_max_cpus ?: 1; 1398 if (setup_possible_cpus == -1) { 1399 possible = num_processors; 1400 #ifdef CONFIG_HOTPLUG_CPU 1401 if (setup_max_cpus) 1402 possible += disabled_cpus; 1403 #else 1404 if (possible > i) 1405 possible = i; 1406 #endif 1407 } else 1408 possible = setup_possible_cpus; 1409 1410 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1411 1412 /* nr_cpu_ids could be reduced via nr_cpus= */ 1413 if (possible > nr_cpu_ids) { 1414 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1415 possible, nr_cpu_ids); 1416 possible = nr_cpu_ids; 1417 } 1418 1419 #ifdef CONFIG_HOTPLUG_CPU 1420 if (!setup_max_cpus) 1421 #endif 1422 if (possible > i) { 1423 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1424 possible, setup_max_cpus); 1425 possible = i; 1426 } 1427 1428 nr_cpu_ids = possible; 1429 1430 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1431 possible, max_t(int, possible - num_processors, 0)); 1432 1433 reset_cpu_possible_mask(); 1434 1435 for (i = 0; i < possible; i++) 1436 set_cpu_possible(i, true); 1437 } 1438 1439 #ifdef CONFIG_HOTPLUG_CPU 1440 1441 /* Recompute SMT state for all CPUs on offline */ 1442 static void recompute_smt_state(void) 1443 { 1444 int max_threads, cpu; 1445 1446 max_threads = 0; 1447 for_each_online_cpu (cpu) { 1448 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1449 1450 if (threads > max_threads) 1451 max_threads = threads; 1452 } 1453 __max_smt_threads = max_threads; 1454 } 1455 1456 static void remove_siblinginfo(int cpu) 1457 { 1458 int sibling; 1459 struct cpuinfo_x86 *c = &cpu_data(cpu); 1460 1461 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1462 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1463 /*/ 1464 * last thread sibling in this cpu core going down 1465 */ 1466 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1467 cpu_data(sibling).booted_cores--; 1468 } 1469 1470 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1471 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1472 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1473 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1474 cpumask_clear(cpu_llc_shared_mask(cpu)); 1475 cpumask_clear(topology_sibling_cpumask(cpu)); 1476 cpumask_clear(topology_core_cpumask(cpu)); 1477 c->cpu_core_id = 0; 1478 c->booted_cores = 0; 1479 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1480 recompute_smt_state(); 1481 } 1482 1483 static void remove_cpu_from_maps(int cpu) 1484 { 1485 set_cpu_online(cpu, false); 1486 cpumask_clear_cpu(cpu, cpu_callout_mask); 1487 cpumask_clear_cpu(cpu, cpu_callin_mask); 1488 /* was set by cpu_init() */ 1489 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1490 numa_remove_cpu(cpu); 1491 } 1492 1493 void cpu_disable_common(void) 1494 { 1495 int cpu = smp_processor_id(); 1496 1497 remove_siblinginfo(cpu); 1498 1499 /* It's now safe to remove this processor from the online map */ 1500 lock_vector_lock(); 1501 remove_cpu_from_maps(cpu); 1502 unlock_vector_lock(); 1503 fixup_irqs(); 1504 lapic_offline(); 1505 } 1506 1507 int native_cpu_disable(void) 1508 { 1509 int ret; 1510 1511 ret = lapic_can_unplug_cpu(); 1512 if (ret) 1513 return ret; 1514 1515 clear_local_APIC(); 1516 cpu_disable_common(); 1517 1518 return 0; 1519 } 1520 1521 int common_cpu_die(unsigned int cpu) 1522 { 1523 int ret = 0; 1524 1525 /* We don't do anything here: idle task is faking death itself. */ 1526 1527 /* They ack this in play_dead() by setting CPU_DEAD */ 1528 if (cpu_wait_death(cpu, 5)) { 1529 if (system_state == SYSTEM_RUNNING) 1530 pr_info("CPU %u is now offline\n", cpu); 1531 } else { 1532 pr_err("CPU %u didn't die...\n", cpu); 1533 ret = -1; 1534 } 1535 1536 return ret; 1537 } 1538 1539 void native_cpu_die(unsigned int cpu) 1540 { 1541 common_cpu_die(cpu); 1542 } 1543 1544 void play_dead_common(void) 1545 { 1546 idle_task_exit(); 1547 1548 /* Ack it */ 1549 (void)cpu_report_death(); 1550 1551 /* 1552 * With physical CPU hotplug, we should halt the cpu 1553 */ 1554 local_irq_disable(); 1555 } 1556 1557 static bool wakeup_cpu0(void) 1558 { 1559 if (smp_processor_id() == 0 && enable_start_cpu0) 1560 return true; 1561 1562 return false; 1563 } 1564 1565 /* 1566 * We need to flush the caches before going to sleep, lest we have 1567 * dirty data in our caches when we come back up. 1568 */ 1569 static inline void mwait_play_dead(void) 1570 { 1571 unsigned int eax, ebx, ecx, edx; 1572 unsigned int highest_cstate = 0; 1573 unsigned int highest_subcstate = 0; 1574 void *mwait_ptr; 1575 int i; 1576 1577 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) 1578 return; 1579 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1580 return; 1581 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1582 return; 1583 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1584 return; 1585 1586 eax = CPUID_MWAIT_LEAF; 1587 ecx = 0; 1588 native_cpuid(&eax, &ebx, &ecx, &edx); 1589 1590 /* 1591 * eax will be 0 if EDX enumeration is not valid. 1592 * Initialized below to cstate, sub_cstate value when EDX is valid. 1593 */ 1594 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1595 eax = 0; 1596 } else { 1597 edx >>= MWAIT_SUBSTATE_SIZE; 1598 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1599 if (edx & MWAIT_SUBSTATE_MASK) { 1600 highest_cstate = i; 1601 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1602 } 1603 } 1604 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1605 (highest_subcstate - 1); 1606 } 1607 1608 /* 1609 * This should be a memory location in a cache line which is 1610 * unlikely to be touched by other processors. The actual 1611 * content is immaterial as it is not actually modified in any way. 1612 */ 1613 mwait_ptr = ¤t_thread_info()->flags; 1614 1615 wbinvd(); 1616 1617 while (1) { 1618 /* 1619 * The CLFLUSH is a workaround for erratum AAI65 for 1620 * the Xeon 7400 series. It's not clear it is actually 1621 * needed, but it should be harmless in either case. 1622 * The WBINVD is insufficient due to the spurious-wakeup 1623 * case where we return around the loop. 1624 */ 1625 mb(); 1626 clflush(mwait_ptr); 1627 mb(); 1628 __monitor(mwait_ptr, 0, 0); 1629 mb(); 1630 __mwait(eax, 0); 1631 /* 1632 * If NMI wants to wake up CPU0, start CPU0. 1633 */ 1634 if (wakeup_cpu0()) 1635 start_cpu0(); 1636 } 1637 } 1638 1639 void hlt_play_dead(void) 1640 { 1641 if (__this_cpu_read(cpu_info.x86) >= 4) 1642 wbinvd(); 1643 1644 while (1) { 1645 native_halt(); 1646 /* 1647 * If NMI wants to wake up CPU0, start CPU0. 1648 */ 1649 if (wakeup_cpu0()) 1650 start_cpu0(); 1651 } 1652 } 1653 1654 void native_play_dead(void) 1655 { 1656 play_dead_common(); 1657 tboot_shutdown(TB_SHUTDOWN_WFS); 1658 1659 mwait_play_dead(); /* Only returns on failure */ 1660 if (cpuidle_play_dead()) 1661 hlt_play_dead(); 1662 } 1663 1664 #else /* ... !CONFIG_HOTPLUG_CPU */ 1665 int native_cpu_disable(void) 1666 { 1667 return -ENOSYS; 1668 } 1669 1670 void native_cpu_die(unsigned int cpu) 1671 { 1672 /* We said "no" in __cpu_disable */ 1673 BUG(); 1674 } 1675 1676 void native_play_dead(void) 1677 { 1678 BUG(); 1679 } 1680 1681 #endif 1682