xref: /openbmc/linux/arch/x86/kernel/smpboot.c (revision 98ddec80)
1  /*
2  *	x86 SMP booting functions
3  *
4  *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
5  *	(c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
6  *	Copyright 2001 Andi Kleen, SuSE Labs.
7  *
8  *	Much of the core SMP work is based on previous work by Thomas Radke, to
9  *	whom a great many thanks are extended.
10  *
11  *	Thanks to Intel for making available several different Pentium,
12  *	Pentium Pro and Pentium-II/Xeon MP machines.
13  *	Original development of Linux SMP code supported by Caldera.
14  *
15  *	This code is released under the GNU General Public License version 2 or
16  *	later.
17  *
18  *	Fixes
19  *		Felix Koop	:	NR_CPUS used properly
20  *		Jose Renau	:	Handle single CPU case.
21  *		Alan Cox	:	By repeated request 8) - Total BogoMIPS report.
22  *		Greg Wright	:	Fix for kernel stacks panic.
23  *		Erich Boleyn	:	MP v1.4 and additional changes.
24  *	Matthias Sattler	:	Changes for 2.1 kernel map.
25  *	Michel Lespinasse	:	Changes for 2.1 kernel map.
26  *	Michael Chastain	:	Change trampoline.S to gnu as.
27  *		Alan Cox	:	Dumb bug: 'B' step PPro's are fine
28  *		Ingo Molnar	:	Added APIC timers, based on code
29  *					from Jose Renau
30  *		Ingo Molnar	:	various cleanups and rewrites
31  *		Tigran Aivazian	:	fixed "0.00 in /proc/uptime on SMP" bug.
32  *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs
33  *	Andi Kleen		:	Changed for SMP boot into long mode.
34  *		Martin J. Bligh	: 	Added support for multi-quad systems
35  *		Dave Jones	:	Report invalid combinations of Athlon CPUs.
36  *		Rusty Russell	:	Hacked into shape for new "hotplug" boot process.
37  *      Andi Kleen              :       Converted to new state machine.
38  *	Ashok Raj		: 	CPU hotplug support
39  *	Glauber Costa		:	i386 and x86_64 integration
40  */
41 
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
43 
44 #include <linux/init.h>
45 #include <linux/smp.h>
46 #include <linux/export.h>
47 #include <linux/sched.h>
48 #include <linux/sched/topology.h>
49 #include <linux/sched/hotplug.h>
50 #include <linux/sched/task_stack.h>
51 #include <linux/percpu.h>
52 #include <linux/bootmem.h>
53 #include <linux/err.h>
54 #include <linux/nmi.h>
55 #include <linux/tboot.h>
56 #include <linux/stackprotector.h>
57 #include <linux/gfp.h>
58 #include <linux/cpuidle.h>
59 
60 #include <asm/acpi.h>
61 #include <asm/desc.h>
62 #include <asm/nmi.h>
63 #include <asm/irq.h>
64 #include <asm/realmode.h>
65 #include <asm/cpu.h>
66 #include <asm/numa.h>
67 #include <asm/pgtable.h>
68 #include <asm/tlbflush.h>
69 #include <asm/mtrr.h>
70 #include <asm/mwait.h>
71 #include <asm/apic.h>
72 #include <asm/io_apic.h>
73 #include <asm/fpu/internal.h>
74 #include <asm/setup.h>
75 #include <asm/uv/uv.h>
76 #include <linux/mc146818rtc.h>
77 #include <asm/i8259.h>
78 #include <asm/misc.h>
79 #include <asm/qspinlock.h>
80 #include <asm/intel-family.h>
81 #include <asm/cpu_device_id.h>
82 #include <asm/spec-ctrl.h>
83 
84 /* representing HT siblings of each logical CPU */
85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
87 
88 /* representing HT and core siblings of each logical CPU */
89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91 
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map);
93 
94 /* Per CPU bogomips and other parameters */
95 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
96 EXPORT_PER_CPU_SYMBOL(cpu_info);
97 
98 /* Logical package management. We might want to allocate that dynamically */
99 unsigned int __max_logical_packages __read_mostly;
100 EXPORT_SYMBOL(__max_logical_packages);
101 static unsigned int logical_packages __read_mostly;
102 
103 /* Maximum number of SMT threads on any online core */
104 int __read_mostly __max_smt_threads = 1;
105 
106 /* Flag to indicate if a complete sched domain rebuild is required */
107 bool x86_topology_update;
108 
109 int arch_update_cpu_topology(void)
110 {
111 	int retval = x86_topology_update;
112 
113 	x86_topology_update = false;
114 	return retval;
115 }
116 
117 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
118 {
119 	unsigned long flags;
120 
121 	spin_lock_irqsave(&rtc_lock, flags);
122 	CMOS_WRITE(0xa, 0xf);
123 	spin_unlock_irqrestore(&rtc_lock, flags);
124 	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) =
125 							start_eip >> 4;
126 	*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) =
127 							start_eip & 0xf;
128 }
129 
130 static inline void smpboot_restore_warm_reset_vector(void)
131 {
132 	unsigned long flags;
133 
134 	/*
135 	 * Paranoid:  Set warm reset code and vector here back
136 	 * to default values.
137 	 */
138 	spin_lock_irqsave(&rtc_lock, flags);
139 	CMOS_WRITE(0, 0xf);
140 	spin_unlock_irqrestore(&rtc_lock, flags);
141 
142 	*((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
143 }
144 
145 /*
146  * Report back to the Boot Processor during boot time or to the caller processor
147  * during CPU online.
148  */
149 static void smp_callin(void)
150 {
151 	int cpuid, phys_id;
152 
153 	/*
154 	 * If waken up by an INIT in an 82489DX configuration
155 	 * cpu_callout_mask guarantees we don't get here before
156 	 * an INIT_deassert IPI reaches our local APIC, so it is
157 	 * now safe to touch our local APIC.
158 	 */
159 	cpuid = smp_processor_id();
160 
161 	/*
162 	 * (This works even if the APIC is not enabled.)
163 	 */
164 	phys_id = read_apic_id();
165 
166 	/*
167 	 * the boot CPU has finished the init stage and is spinning
168 	 * on callin_map until we finish. We are free to set up this
169 	 * CPU, first the APIC. (this is probably redundant on most
170 	 * boards)
171 	 */
172 	apic_ap_setup();
173 
174 	/*
175 	 * Save our processor parameters. Note: this information
176 	 * is needed for clock calibration.
177 	 */
178 	smp_store_cpu_info(cpuid);
179 
180 	/*
181 	 * The topology information must be up to date before
182 	 * calibrate_delay() and notify_cpu_starting().
183 	 */
184 	set_cpu_sibling_map(raw_smp_processor_id());
185 
186 	/*
187 	 * Get our bogomips.
188 	 * Update loops_per_jiffy in cpu_data. Previous call to
189 	 * smp_store_cpu_info() stored a value that is close but not as
190 	 * accurate as the value just calculated.
191 	 */
192 	calibrate_delay();
193 	cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy;
194 	pr_debug("Stack at about %p\n", &cpuid);
195 
196 	wmb();
197 
198 	notify_cpu_starting(cpuid);
199 
200 	/*
201 	 * Allow the master to continue.
202 	 */
203 	cpumask_set_cpu(cpuid, cpu_callin_mask);
204 }
205 
206 static int cpu0_logical_apicid;
207 static int enable_start_cpu0;
208 /*
209  * Activate a secondary processor.
210  */
211 static void notrace start_secondary(void *unused)
212 {
213 	/*
214 	 * Don't put *anything* except direct CPU state initialization
215 	 * before cpu_init(), SMP booting is too fragile that we want to
216 	 * limit the things done here to the most necessary things.
217 	 */
218 	if (boot_cpu_has(X86_FEATURE_PCID))
219 		__write_cr4(__read_cr4() | X86_CR4_PCIDE);
220 
221 #ifdef CONFIG_X86_32
222 	/* switch away from the initial page table */
223 	load_cr3(swapper_pg_dir);
224 	__flush_tlb_all();
225 #endif
226 	load_current_idt();
227 	cpu_init();
228 	x86_cpuinit.early_percpu_clock_init();
229 	preempt_disable();
230 	smp_callin();
231 
232 	enable_start_cpu0 = 0;
233 
234 	/* otherwise gcc will move up smp_processor_id before the cpu_init */
235 	barrier();
236 	/*
237 	 * Check TSC synchronization with the boot CPU:
238 	 */
239 	check_tsc_sync_target();
240 
241 	speculative_store_bypass_ht_init();
242 
243 	/*
244 	 * Lock vector_lock, set CPU online and bring the vector
245 	 * allocator online. Online must be set with vector_lock held
246 	 * to prevent a concurrent irq setup/teardown from seeing a
247 	 * half valid vector space.
248 	 */
249 	lock_vector_lock();
250 	set_cpu_online(smp_processor_id(), true);
251 	lapic_online();
252 	unlock_vector_lock();
253 	cpu_set_state_online(smp_processor_id());
254 	x86_platform.nmi_init();
255 
256 	/* enable local interrupts */
257 	local_irq_enable();
258 
259 	/* to prevent fake stack check failure in clock setup */
260 	boot_init_stack_canary();
261 
262 	x86_cpuinit.setup_percpu_clockev();
263 
264 	wmb();
265 	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
266 }
267 
268 /**
269  * topology_phys_to_logical_pkg - Map a physical package id to a logical
270  *
271  * Returns logical package id or -1 if not found
272  */
273 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
274 {
275 	int cpu;
276 
277 	for_each_possible_cpu(cpu) {
278 		struct cpuinfo_x86 *c = &cpu_data(cpu);
279 
280 		if (c->initialized && c->phys_proc_id == phys_pkg)
281 			return c->logical_proc_id;
282 	}
283 	return -1;
284 }
285 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
286 
287 /**
288  * topology_update_package_map - Update the physical to logical package map
289  * @pkg:	The physical package id as retrieved via CPUID
290  * @cpu:	The cpu for which this is updated
291  */
292 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
293 {
294 	int new;
295 
296 	/* Already available somewhere? */
297 	new = topology_phys_to_logical_pkg(pkg);
298 	if (new >= 0)
299 		goto found;
300 
301 	new = logical_packages++;
302 	if (new != pkg) {
303 		pr_info("CPU %u Converting physical %u to logical package %u\n",
304 			cpu, pkg, new);
305 	}
306 found:
307 	cpu_data(cpu).logical_proc_id = new;
308 	return 0;
309 }
310 
311 void __init smp_store_boot_cpu_info(void)
312 {
313 	int id = 0; /* CPU 0 */
314 	struct cpuinfo_x86 *c = &cpu_data(id);
315 
316 	*c = boot_cpu_data;
317 	c->cpu_index = id;
318 	topology_update_package_map(c->phys_proc_id, id);
319 	c->initialized = true;
320 }
321 
322 /*
323  * The bootstrap kernel entry code has set these up. Save them for
324  * a given CPU
325  */
326 void smp_store_cpu_info(int id)
327 {
328 	struct cpuinfo_x86 *c = &cpu_data(id);
329 
330 	/* Copy boot_cpu_data only on the first bringup */
331 	if (!c->initialized)
332 		*c = boot_cpu_data;
333 	c->cpu_index = id;
334 	/*
335 	 * During boot time, CPU0 has this setup already. Save the info when
336 	 * bringing up AP or offlined CPU0.
337 	 */
338 	identify_secondary_cpu(c);
339 	c->initialized = true;
340 }
341 
342 static bool
343 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
344 {
345 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
346 
347 	return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
348 }
349 
350 static bool
351 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
352 {
353 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
354 
355 	return !WARN_ONCE(!topology_same_node(c, o),
356 		"sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
357 		"[node: %d != %d]. Ignoring dependency.\n",
358 		cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
359 }
360 
361 #define link_mask(mfunc, c1, c2)					\
362 do {									\
363 	cpumask_set_cpu((c1), mfunc(c2));				\
364 	cpumask_set_cpu((c2), mfunc(c1));				\
365 } while (0)
366 
367 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
368 {
369 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
370 		int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
371 
372 		if (c->phys_proc_id == o->phys_proc_id &&
373 		    per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
374 			if (c->cpu_core_id == o->cpu_core_id)
375 				return topology_sane(c, o, "smt");
376 
377 			if ((c->cu_id != 0xff) &&
378 			    (o->cu_id != 0xff) &&
379 			    (c->cu_id == o->cu_id))
380 				return topology_sane(c, o, "smt");
381 		}
382 
383 	} else if (c->phys_proc_id == o->phys_proc_id &&
384 		   c->cpu_core_id == o->cpu_core_id) {
385 		return topology_sane(c, o, "smt");
386 	}
387 
388 	return false;
389 }
390 
391 /*
392  * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs.
393  *
394  * These are Intel CPUs that enumerate an LLC that is shared by
395  * multiple NUMA nodes. The LLC on these systems is shared for
396  * off-package data access but private to the NUMA node (half
397  * of the package) for on-package access.
398  *
399  * CPUID (the source of the information about the LLC) can only
400  * enumerate the cache as being shared *or* unshared, but not
401  * this particular configuration. The CPU in this case enumerates
402  * the cache to be shared across the entire package (spanning both
403  * NUMA nodes).
404  */
405 
406 static const struct x86_cpu_id snc_cpu[] = {
407 	{ X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X },
408 	{}
409 };
410 
411 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
412 {
413 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
414 
415 	/* Do not match if we do not have a valid APICID for cpu: */
416 	if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
417 		return false;
418 
419 	/* Do not match if LLC id does not match: */
420 	if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
421 		return false;
422 
423 	/*
424 	 * Allow the SNC topology without warning. Return of false
425 	 * means 'c' does not share the LLC of 'o'. This will be
426 	 * reflected to userspace.
427 	 */
428 	if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu))
429 		return false;
430 
431 	return topology_sane(c, o, "llc");
432 }
433 
434 /*
435  * Unlike the other levels, we do not enforce keeping a
436  * multicore group inside a NUMA node.  If this happens, we will
437  * discard the MC level of the topology later.
438  */
439 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
440 {
441 	if (c->phys_proc_id == o->phys_proc_id)
442 		return true;
443 	return false;
444 }
445 
446 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC)
447 static inline int x86_sched_itmt_flags(void)
448 {
449 	return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
450 }
451 
452 #ifdef CONFIG_SCHED_MC
453 static int x86_core_flags(void)
454 {
455 	return cpu_core_flags() | x86_sched_itmt_flags();
456 }
457 #endif
458 #ifdef CONFIG_SCHED_SMT
459 static int x86_smt_flags(void)
460 {
461 	return cpu_smt_flags() | x86_sched_itmt_flags();
462 }
463 #endif
464 #endif
465 
466 static struct sched_domain_topology_level x86_numa_in_package_topology[] = {
467 #ifdef CONFIG_SCHED_SMT
468 	{ cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
469 #endif
470 #ifdef CONFIG_SCHED_MC
471 	{ cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
472 #endif
473 	{ NULL, },
474 };
475 
476 static struct sched_domain_topology_level x86_topology[] = {
477 #ifdef CONFIG_SCHED_SMT
478 	{ cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) },
479 #endif
480 #ifdef CONFIG_SCHED_MC
481 	{ cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) },
482 #endif
483 	{ cpu_cpu_mask, SD_INIT_NAME(DIE) },
484 	{ NULL, },
485 };
486 
487 /*
488  * Set if a package/die has multiple NUMA nodes inside.
489  * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
490  * Sub-NUMA Clustering have this.
491  */
492 static bool x86_has_numa_in_package;
493 
494 void set_cpu_sibling_map(int cpu)
495 {
496 	bool has_smt = smp_num_siblings > 1;
497 	bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
498 	struct cpuinfo_x86 *c = &cpu_data(cpu);
499 	struct cpuinfo_x86 *o;
500 	int i, threads;
501 
502 	cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
503 
504 	if (!has_mp) {
505 		cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
506 		cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
507 		cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
508 		c->booted_cores = 1;
509 		return;
510 	}
511 
512 	for_each_cpu(i, cpu_sibling_setup_mask) {
513 		o = &cpu_data(i);
514 
515 		if ((i == cpu) || (has_smt && match_smt(c, o)))
516 			link_mask(topology_sibling_cpumask, cpu, i);
517 
518 		if ((i == cpu) || (has_mp && match_llc(c, o)))
519 			link_mask(cpu_llc_shared_mask, cpu, i);
520 
521 	}
522 
523 	/*
524 	 * This needs a separate iteration over the cpus because we rely on all
525 	 * topology_sibling_cpumask links to be set-up.
526 	 */
527 	for_each_cpu(i, cpu_sibling_setup_mask) {
528 		o = &cpu_data(i);
529 
530 		if ((i == cpu) || (has_mp && match_die(c, o))) {
531 			link_mask(topology_core_cpumask, cpu, i);
532 
533 			/*
534 			 *  Does this new cpu bringup a new core?
535 			 */
536 			if (cpumask_weight(
537 			    topology_sibling_cpumask(cpu)) == 1) {
538 				/*
539 				 * for each core in package, increment
540 				 * the booted_cores for this new cpu
541 				 */
542 				if (cpumask_first(
543 				    topology_sibling_cpumask(i)) == i)
544 					c->booted_cores++;
545 				/*
546 				 * increment the core count for all
547 				 * the other cpus in this package
548 				 */
549 				if (i != cpu)
550 					cpu_data(i).booted_cores++;
551 			} else if (i != cpu && !c->booted_cores)
552 				c->booted_cores = cpu_data(i).booted_cores;
553 		}
554 		if (match_die(c, o) && !topology_same_node(c, o))
555 			x86_has_numa_in_package = true;
556 	}
557 
558 	threads = cpumask_weight(topology_sibling_cpumask(cpu));
559 	if (threads > __max_smt_threads)
560 		__max_smt_threads = threads;
561 }
562 
563 /* maps the cpu to the sched domain representing multi-core */
564 const struct cpumask *cpu_coregroup_mask(int cpu)
565 {
566 	return cpu_llc_shared_mask(cpu);
567 }
568 
569 static void impress_friends(void)
570 {
571 	int cpu;
572 	unsigned long bogosum = 0;
573 	/*
574 	 * Allow the user to impress friends.
575 	 */
576 	pr_debug("Before bogomips\n");
577 	for_each_possible_cpu(cpu)
578 		if (cpumask_test_cpu(cpu, cpu_callout_mask))
579 			bogosum += cpu_data(cpu).loops_per_jiffy;
580 	pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
581 		num_online_cpus(),
582 		bogosum/(500000/HZ),
583 		(bogosum/(5000/HZ))%100);
584 
585 	pr_debug("Before bogocount - setting activated=1\n");
586 }
587 
588 void __inquire_remote_apic(int apicid)
589 {
590 	unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
591 	const char * const names[] = { "ID", "VERSION", "SPIV" };
592 	int timeout;
593 	u32 status;
594 
595 	pr_info("Inquiring remote APIC 0x%x...\n", apicid);
596 
597 	for (i = 0; i < ARRAY_SIZE(regs); i++) {
598 		pr_info("... APIC 0x%x %s: ", apicid, names[i]);
599 
600 		/*
601 		 * Wait for idle.
602 		 */
603 		status = safe_apic_wait_icr_idle();
604 		if (status)
605 			pr_cont("a previous APIC delivery may have failed\n");
606 
607 		apic_icr_write(APIC_DM_REMRD | regs[i], apicid);
608 
609 		timeout = 0;
610 		do {
611 			udelay(100);
612 			status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
613 		} while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
614 
615 		switch (status) {
616 		case APIC_ICR_RR_VALID:
617 			status = apic_read(APIC_RRR);
618 			pr_cont("%08x\n", status);
619 			break;
620 		default:
621 			pr_cont("failed\n");
622 		}
623 	}
624 }
625 
626 /*
627  * The Multiprocessor Specification 1.4 (1997) example code suggests
628  * that there should be a 10ms delay between the BSP asserting INIT
629  * and de-asserting INIT, when starting a remote processor.
630  * But that slows boot and resume on modern processors, which include
631  * many cores and don't require that delay.
632  *
633  * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
634  * Modern processor families are quirked to remove the delay entirely.
635  */
636 #define UDELAY_10MS_DEFAULT 10000
637 
638 static unsigned int init_udelay = UINT_MAX;
639 
640 static int __init cpu_init_udelay(char *str)
641 {
642 	get_option(&str, &init_udelay);
643 
644 	return 0;
645 }
646 early_param("cpu_init_udelay", cpu_init_udelay);
647 
648 static void __init smp_quirk_init_udelay(void)
649 {
650 	/* if cmdline changed it from default, leave it alone */
651 	if (init_udelay != UINT_MAX)
652 		return;
653 
654 	/* if modern processor, use no delay */
655 	if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
656 	    ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
657 		init_udelay = 0;
658 		return;
659 	}
660 	/* else, use legacy delay */
661 	init_udelay = UDELAY_10MS_DEFAULT;
662 }
663 
664 /*
665  * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
666  * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
667  * won't ... remember to clear down the APIC, etc later.
668  */
669 int
670 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip)
671 {
672 	unsigned long send_status, accept_status = 0;
673 	int maxlvt;
674 
675 	/* Target chip */
676 	/* Boot on the stack */
677 	/* Kick the second */
678 	apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid);
679 
680 	pr_debug("Waiting for send to finish...\n");
681 	send_status = safe_apic_wait_icr_idle();
682 
683 	/*
684 	 * Give the other CPU some time to accept the IPI.
685 	 */
686 	udelay(200);
687 	if (APIC_INTEGRATED(boot_cpu_apic_version)) {
688 		maxlvt = lapic_get_maxlvt();
689 		if (maxlvt > 3)			/* Due to the Pentium erratum 3AP.  */
690 			apic_write(APIC_ESR, 0);
691 		accept_status = (apic_read(APIC_ESR) & 0xEF);
692 	}
693 	pr_debug("NMI sent\n");
694 
695 	if (send_status)
696 		pr_err("APIC never delivered???\n");
697 	if (accept_status)
698 		pr_err("APIC delivery error (%lx)\n", accept_status);
699 
700 	return (send_status | accept_status);
701 }
702 
703 static int
704 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
705 {
706 	unsigned long send_status = 0, accept_status = 0;
707 	int maxlvt, num_starts, j;
708 
709 	maxlvt = lapic_get_maxlvt();
710 
711 	/*
712 	 * Be paranoid about clearing APIC errors.
713 	 */
714 	if (APIC_INTEGRATED(boot_cpu_apic_version)) {
715 		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
716 			apic_write(APIC_ESR, 0);
717 		apic_read(APIC_ESR);
718 	}
719 
720 	pr_debug("Asserting INIT\n");
721 
722 	/*
723 	 * Turn INIT on target chip
724 	 */
725 	/*
726 	 * Send IPI
727 	 */
728 	apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT,
729 		       phys_apicid);
730 
731 	pr_debug("Waiting for send to finish...\n");
732 	send_status = safe_apic_wait_icr_idle();
733 
734 	udelay(init_udelay);
735 
736 	pr_debug("Deasserting INIT\n");
737 
738 	/* Target chip */
739 	/* Send IPI */
740 	apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
741 
742 	pr_debug("Waiting for send to finish...\n");
743 	send_status = safe_apic_wait_icr_idle();
744 
745 	mb();
746 
747 	/*
748 	 * Should we send STARTUP IPIs ?
749 	 *
750 	 * Determine this based on the APIC version.
751 	 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
752 	 */
753 	if (APIC_INTEGRATED(boot_cpu_apic_version))
754 		num_starts = 2;
755 	else
756 		num_starts = 0;
757 
758 	/*
759 	 * Run STARTUP IPI loop.
760 	 */
761 	pr_debug("#startup loops: %d\n", num_starts);
762 
763 	for (j = 1; j <= num_starts; j++) {
764 		pr_debug("Sending STARTUP #%d\n", j);
765 		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
766 			apic_write(APIC_ESR, 0);
767 		apic_read(APIC_ESR);
768 		pr_debug("After apic_write\n");
769 
770 		/*
771 		 * STARTUP IPI
772 		 */
773 
774 		/* Target chip */
775 		/* Boot on the stack */
776 		/* Kick the second */
777 		apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
778 			       phys_apicid);
779 
780 		/*
781 		 * Give the other CPU some time to accept the IPI.
782 		 */
783 		if (init_udelay == 0)
784 			udelay(10);
785 		else
786 			udelay(300);
787 
788 		pr_debug("Startup point 1\n");
789 
790 		pr_debug("Waiting for send to finish...\n");
791 		send_status = safe_apic_wait_icr_idle();
792 
793 		/*
794 		 * Give the other CPU some time to accept the IPI.
795 		 */
796 		if (init_udelay == 0)
797 			udelay(10);
798 		else
799 			udelay(200);
800 
801 		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
802 			apic_write(APIC_ESR, 0);
803 		accept_status = (apic_read(APIC_ESR) & 0xEF);
804 		if (send_status || accept_status)
805 			break;
806 	}
807 	pr_debug("After Startup\n");
808 
809 	if (send_status)
810 		pr_err("APIC never delivered???\n");
811 	if (accept_status)
812 		pr_err("APIC delivery error (%lx)\n", accept_status);
813 
814 	return (send_status | accept_status);
815 }
816 
817 /* reduce the number of lines printed when booting a large cpu count system */
818 static void announce_cpu(int cpu, int apicid)
819 {
820 	static int current_node = -1;
821 	int node = early_cpu_to_node(cpu);
822 	static int width, node_width;
823 
824 	if (!width)
825 		width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
826 
827 	if (!node_width)
828 		node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
829 
830 	if (cpu == 1)
831 		printk(KERN_INFO "x86: Booting SMP configuration:\n");
832 
833 	if (system_state < SYSTEM_RUNNING) {
834 		if (node != current_node) {
835 			if (current_node > (-1))
836 				pr_cont("\n");
837 			current_node = node;
838 
839 			printk(KERN_INFO ".... node %*s#%d, CPUs:  ",
840 			       node_width - num_digits(node), " ", node);
841 		}
842 
843 		/* Add padding for the BSP */
844 		if (cpu == 1)
845 			pr_cont("%*s", width + 1, " ");
846 
847 		pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
848 
849 	} else
850 		pr_info("Booting Node %d Processor %d APIC 0x%x\n",
851 			node, cpu, apicid);
852 }
853 
854 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs)
855 {
856 	int cpu;
857 
858 	cpu = smp_processor_id();
859 	if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0)
860 		return NMI_HANDLED;
861 
862 	return NMI_DONE;
863 }
864 
865 /*
866  * Wake up AP by INIT, INIT, STARTUP sequence.
867  *
868  * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS
869  * boot-strap code which is not a desired behavior for waking up BSP. To
870  * void the boot-strap code, wake up CPU0 by NMI instead.
871  *
872  * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined
873  * (i.e. physically hot removed and then hot added), NMI won't wake it up.
874  * We'll change this code in the future to wake up hard offlined CPU0 if
875  * real platform and request are available.
876  */
877 static int
878 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid,
879 	       int *cpu0_nmi_registered)
880 {
881 	int id;
882 	int boot_error;
883 
884 	preempt_disable();
885 
886 	/*
887 	 * Wake up AP by INIT, INIT, STARTUP sequence.
888 	 */
889 	if (cpu) {
890 		boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip);
891 		goto out;
892 	}
893 
894 	/*
895 	 * Wake up BSP by nmi.
896 	 *
897 	 * Register a NMI handler to help wake up CPU0.
898 	 */
899 	boot_error = register_nmi_handler(NMI_LOCAL,
900 					  wakeup_cpu0_nmi, 0, "wake_cpu0");
901 
902 	if (!boot_error) {
903 		enable_start_cpu0 = 1;
904 		*cpu0_nmi_registered = 1;
905 		if (apic->dest_logical == APIC_DEST_LOGICAL)
906 			id = cpu0_logical_apicid;
907 		else
908 			id = apicid;
909 		boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip);
910 	}
911 
912 out:
913 	preempt_enable();
914 
915 	return boot_error;
916 }
917 
918 void common_cpu_up(unsigned int cpu, struct task_struct *idle)
919 {
920 	/* Just in case we booted with a single CPU. */
921 	alternatives_enable_smp();
922 
923 	per_cpu(current_task, cpu) = idle;
924 
925 #ifdef CONFIG_X86_32
926 	/* Stack for startup_32 can be just as for start_secondary onwards */
927 	irq_ctx_init(cpu);
928 	per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle);
929 #else
930 	initial_gs = per_cpu_offset(cpu);
931 #endif
932 }
933 
934 /*
935  * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
936  * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
937  * Returns zero if CPU booted OK, else error code from
938  * ->wakeup_secondary_cpu.
939  */
940 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle,
941 		       int *cpu0_nmi_registered)
942 {
943 	volatile u32 *trampoline_status =
944 		(volatile u32 *) __va(real_mode_header->trampoline_status);
945 	/* start_ip had better be page-aligned! */
946 	unsigned long start_ip = real_mode_header->trampoline_start;
947 
948 	unsigned long boot_error = 0;
949 	unsigned long timeout;
950 
951 	idle->thread.sp = (unsigned long)task_pt_regs(idle);
952 	early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
953 	initial_code = (unsigned long)start_secondary;
954 	initial_stack  = idle->thread.sp;
955 
956 	/* Enable the espfix hack for this CPU */
957 	init_espfix_ap(cpu);
958 
959 	/* So we see what's up */
960 	announce_cpu(cpu, apicid);
961 
962 	/*
963 	 * This grunge runs the startup process for
964 	 * the targeted processor.
965 	 */
966 
967 	if (x86_platform.legacy.warm_reset) {
968 
969 		pr_debug("Setting warm reset code and vector.\n");
970 
971 		smpboot_setup_warm_reset_vector(start_ip);
972 		/*
973 		 * Be paranoid about clearing APIC errors.
974 		*/
975 		if (APIC_INTEGRATED(boot_cpu_apic_version)) {
976 			apic_write(APIC_ESR, 0);
977 			apic_read(APIC_ESR);
978 		}
979 	}
980 
981 	/*
982 	 * AP might wait on cpu_callout_mask in cpu_init() with
983 	 * cpu_initialized_mask set if previous attempt to online
984 	 * it timed-out. Clear cpu_initialized_mask so that after
985 	 * INIT/SIPI it could start with a clean state.
986 	 */
987 	cpumask_clear_cpu(cpu, cpu_initialized_mask);
988 	smp_mb();
989 
990 	/*
991 	 * Wake up a CPU in difference cases:
992 	 * - Use the method in the APIC driver if it's defined
993 	 * Otherwise,
994 	 * - Use an INIT boot APIC message for APs or NMI for BSP.
995 	 */
996 	if (apic->wakeup_secondary_cpu)
997 		boot_error = apic->wakeup_secondary_cpu(apicid, start_ip);
998 	else
999 		boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid,
1000 						     cpu0_nmi_registered);
1001 
1002 	if (!boot_error) {
1003 		/*
1004 		 * Wait 10s total for first sign of life from AP
1005 		 */
1006 		boot_error = -1;
1007 		timeout = jiffies + 10*HZ;
1008 		while (time_before(jiffies, timeout)) {
1009 			if (cpumask_test_cpu(cpu, cpu_initialized_mask)) {
1010 				/*
1011 				 * Tell AP to proceed with initialization
1012 				 */
1013 				cpumask_set_cpu(cpu, cpu_callout_mask);
1014 				boot_error = 0;
1015 				break;
1016 			}
1017 			schedule();
1018 		}
1019 	}
1020 
1021 	if (!boot_error) {
1022 		/*
1023 		 * Wait till AP completes initial initialization
1024 		 */
1025 		while (!cpumask_test_cpu(cpu, cpu_callin_mask)) {
1026 			/*
1027 			 * Allow other tasks to run while we wait for the
1028 			 * AP to come online. This also gives a chance
1029 			 * for the MTRR work(triggered by the AP coming online)
1030 			 * to be completed in the stop machine context.
1031 			 */
1032 			schedule();
1033 		}
1034 	}
1035 
1036 	/* mark "stuck" area as not stuck */
1037 	*trampoline_status = 0;
1038 
1039 	if (x86_platform.legacy.warm_reset) {
1040 		/*
1041 		 * Cleanup possible dangling ends...
1042 		 */
1043 		smpboot_restore_warm_reset_vector();
1044 	}
1045 
1046 	return boot_error;
1047 }
1048 
1049 int native_cpu_up(unsigned int cpu, struct task_struct *tidle)
1050 {
1051 	int apicid = apic->cpu_present_to_apicid(cpu);
1052 	int cpu0_nmi_registered = 0;
1053 	unsigned long flags;
1054 	int err, ret = 0;
1055 
1056 	lockdep_assert_irqs_enabled();
1057 
1058 	pr_debug("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
1059 
1060 	if (apicid == BAD_APICID ||
1061 	    !physid_isset(apicid, phys_cpu_present_map) ||
1062 	    !apic->apic_id_valid(apicid)) {
1063 		pr_err("%s: bad cpu %d\n", __func__, cpu);
1064 		return -EINVAL;
1065 	}
1066 
1067 	/*
1068 	 * Already booted CPU?
1069 	 */
1070 	if (cpumask_test_cpu(cpu, cpu_callin_mask)) {
1071 		pr_debug("do_boot_cpu %d Already started\n", cpu);
1072 		return -ENOSYS;
1073 	}
1074 
1075 	/*
1076 	 * Save current MTRR state in case it was changed since early boot
1077 	 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1078 	 */
1079 	mtrr_save_state();
1080 
1081 	/* x86 CPUs take themselves offline, so delayed offline is OK. */
1082 	err = cpu_check_up_prepare(cpu);
1083 	if (err && err != -EBUSY)
1084 		return err;
1085 
1086 	/* the FPU context is blank, nobody can own it */
1087 	per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1088 
1089 	common_cpu_up(cpu, tidle);
1090 
1091 	err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered);
1092 	if (err) {
1093 		pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1094 		ret = -EIO;
1095 		goto unreg_nmi;
1096 	}
1097 
1098 	/*
1099 	 * Check TSC synchronization with the AP (keep irqs disabled
1100 	 * while doing so):
1101 	 */
1102 	local_irq_save(flags);
1103 	check_tsc_sync_source(cpu);
1104 	local_irq_restore(flags);
1105 
1106 	while (!cpu_online(cpu)) {
1107 		cpu_relax();
1108 		touch_nmi_watchdog();
1109 	}
1110 
1111 unreg_nmi:
1112 	/*
1113 	 * Clean up the nmi handler. Do this after the callin and callout sync
1114 	 * to avoid impact of possible long unregister time.
1115 	 */
1116 	if (cpu0_nmi_registered)
1117 		unregister_nmi_handler(NMI_LOCAL, "wake_cpu0");
1118 
1119 	return ret;
1120 }
1121 
1122 /**
1123  * arch_disable_smp_support() - disables SMP support for x86 at runtime
1124  */
1125 void arch_disable_smp_support(void)
1126 {
1127 	disable_ioapic_support();
1128 }
1129 
1130 /*
1131  * Fall back to non SMP mode after errors.
1132  *
1133  * RED-PEN audit/test this more. I bet there is more state messed up here.
1134  */
1135 static __init void disable_smp(void)
1136 {
1137 	pr_info("SMP disabled\n");
1138 
1139 	disable_ioapic_support();
1140 
1141 	init_cpu_present(cpumask_of(0));
1142 	init_cpu_possible(cpumask_of(0));
1143 
1144 	if (smp_found_config)
1145 		physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1146 	else
1147 		physid_set_mask_of_physid(0, &phys_cpu_present_map);
1148 	cpumask_set_cpu(0, topology_sibling_cpumask(0));
1149 	cpumask_set_cpu(0, topology_core_cpumask(0));
1150 }
1151 
1152 /*
1153  * Various sanity checks.
1154  */
1155 static void __init smp_sanity_check(void)
1156 {
1157 	preempt_disable();
1158 
1159 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32)
1160 	if (def_to_bigsmp && nr_cpu_ids > 8) {
1161 		unsigned int cpu;
1162 		unsigned nr;
1163 
1164 		pr_warn("More than 8 CPUs detected - skipping them\n"
1165 			"Use CONFIG_X86_BIGSMP\n");
1166 
1167 		nr = 0;
1168 		for_each_present_cpu(cpu) {
1169 			if (nr >= 8)
1170 				set_cpu_present(cpu, false);
1171 			nr++;
1172 		}
1173 
1174 		nr = 0;
1175 		for_each_possible_cpu(cpu) {
1176 			if (nr >= 8)
1177 				set_cpu_possible(cpu, false);
1178 			nr++;
1179 		}
1180 
1181 		nr_cpu_ids = 8;
1182 	}
1183 #endif
1184 
1185 	if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
1186 		pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n",
1187 			hard_smp_processor_id());
1188 
1189 		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1190 	}
1191 
1192 	/*
1193 	 * Should not be necessary because the MP table should list the boot
1194 	 * CPU too, but we do it for the sake of robustness anyway.
1195 	 */
1196 	if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) {
1197 		pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n",
1198 			  boot_cpu_physical_apicid);
1199 		physid_set(hard_smp_processor_id(), phys_cpu_present_map);
1200 	}
1201 	preempt_enable();
1202 }
1203 
1204 static void __init smp_cpu_index_default(void)
1205 {
1206 	int i;
1207 	struct cpuinfo_x86 *c;
1208 
1209 	for_each_possible_cpu(i) {
1210 		c = &cpu_data(i);
1211 		/* mark all to hotplug */
1212 		c->cpu_index = nr_cpu_ids;
1213 	}
1214 }
1215 
1216 static void __init smp_get_logical_apicid(void)
1217 {
1218 	if (x2apic_mode)
1219 		cpu0_logical_apicid = apic_read(APIC_LDR);
1220 	else
1221 		cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR));
1222 }
1223 
1224 /*
1225  * Prepare for SMP bootup.
1226  * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1227  *            for common interface support.
1228  */
1229 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1230 {
1231 	unsigned int i;
1232 
1233 	smp_cpu_index_default();
1234 
1235 	/*
1236 	 * Setup boot CPU information
1237 	 */
1238 	smp_store_boot_cpu_info(); /* Final full version of the data */
1239 	cpumask_copy(cpu_callin_mask, cpumask_of(0));
1240 	mb();
1241 
1242 	for_each_possible_cpu(i) {
1243 		zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1244 		zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1245 		zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1246 	}
1247 
1248 	/*
1249 	 * Set 'default' x86 topology, this matches default_topology() in that
1250 	 * it has NUMA nodes as a topology level. See also
1251 	 * native_smp_cpus_done().
1252 	 *
1253 	 * Must be done before set_cpus_sibling_map() is ran.
1254 	 */
1255 	set_sched_topology(x86_topology);
1256 
1257 	set_cpu_sibling_map(0);
1258 
1259 	smp_sanity_check();
1260 
1261 	switch (apic_intr_mode) {
1262 	case APIC_PIC:
1263 	case APIC_VIRTUAL_WIRE_NO_CONFIG:
1264 		disable_smp();
1265 		return;
1266 	case APIC_SYMMETRIC_IO_NO_ROUTING:
1267 		disable_smp();
1268 		/* Setup local timer */
1269 		x86_init.timers.setup_percpu_clockev();
1270 		return;
1271 	case APIC_VIRTUAL_WIRE:
1272 	case APIC_SYMMETRIC_IO:
1273 		break;
1274 	}
1275 
1276 	/* Setup local timer */
1277 	x86_init.timers.setup_percpu_clockev();
1278 
1279 	smp_get_logical_apicid();
1280 
1281 	pr_info("CPU0: ");
1282 	print_cpu_info(&cpu_data(0));
1283 
1284 	native_pv_lock_init();
1285 
1286 	uv_system_init();
1287 
1288 	set_mtrr_aps_delayed_init();
1289 
1290 	smp_quirk_init_udelay();
1291 
1292 	speculative_store_bypass_ht_init();
1293 }
1294 
1295 void arch_enable_nonboot_cpus_begin(void)
1296 {
1297 	set_mtrr_aps_delayed_init();
1298 }
1299 
1300 void arch_enable_nonboot_cpus_end(void)
1301 {
1302 	mtrr_aps_init();
1303 }
1304 
1305 /*
1306  * Early setup to make printk work.
1307  */
1308 void __init native_smp_prepare_boot_cpu(void)
1309 {
1310 	int me = smp_processor_id();
1311 	switch_to_new_gdt(me);
1312 	/* already set me in cpu_online_mask in boot_cpu_init() */
1313 	cpumask_set_cpu(me, cpu_callout_mask);
1314 	cpu_set_state_online(me);
1315 }
1316 
1317 void __init calculate_max_logical_packages(void)
1318 {
1319 	int ncpus;
1320 
1321 	/*
1322 	 * Today neither Intel nor AMD support heterogenous systems so
1323 	 * extrapolate the boot cpu's data to all packages.
1324 	 */
1325 	ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1326 	__max_logical_packages = DIV_ROUND_UP(nr_cpu_ids, ncpus);
1327 	pr_info("Max logical packages: %u\n", __max_logical_packages);
1328 }
1329 
1330 void __init native_smp_cpus_done(unsigned int max_cpus)
1331 {
1332 	pr_debug("Boot done\n");
1333 
1334 	calculate_max_logical_packages();
1335 
1336 	if (x86_has_numa_in_package)
1337 		set_sched_topology(x86_numa_in_package_topology);
1338 
1339 	nmi_selftest();
1340 	impress_friends();
1341 	mtrr_aps_init();
1342 }
1343 
1344 static int __initdata setup_possible_cpus = -1;
1345 static int __init _setup_possible_cpus(char *str)
1346 {
1347 	get_option(&str, &setup_possible_cpus);
1348 	return 0;
1349 }
1350 early_param("possible_cpus", _setup_possible_cpus);
1351 
1352 
1353 /*
1354  * cpu_possible_mask should be static, it cannot change as cpu's
1355  * are onlined, or offlined. The reason is per-cpu data-structures
1356  * are allocated by some modules at init time, and dont expect to
1357  * do this dynamically on cpu arrival/departure.
1358  * cpu_present_mask on the other hand can change dynamically.
1359  * In case when cpu_hotplug is not compiled, then we resort to current
1360  * behaviour, which is cpu_possible == cpu_present.
1361  * - Ashok Raj
1362  *
1363  * Three ways to find out the number of additional hotplug CPUs:
1364  * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1365  * - The user can overwrite it with possible_cpus=NUM
1366  * - Otherwise don't reserve additional CPUs.
1367  * We do this because additional CPUs waste a lot of memory.
1368  * -AK
1369  */
1370 __init void prefill_possible_map(void)
1371 {
1372 	int i, possible;
1373 
1374 	/* No boot processor was found in mptable or ACPI MADT */
1375 	if (!num_processors) {
1376 		if (boot_cpu_has(X86_FEATURE_APIC)) {
1377 			int apicid = boot_cpu_physical_apicid;
1378 			int cpu = hard_smp_processor_id();
1379 
1380 			pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu);
1381 
1382 			/* Make sure boot cpu is enumerated */
1383 			if (apic->cpu_present_to_apicid(0) == BAD_APICID &&
1384 			    apic->apic_id_valid(apicid))
1385 				generic_processor_info(apicid, boot_cpu_apic_version);
1386 		}
1387 
1388 		if (!num_processors)
1389 			num_processors = 1;
1390 	}
1391 
1392 	i = setup_max_cpus ?: 1;
1393 	if (setup_possible_cpus == -1) {
1394 		possible = num_processors;
1395 #ifdef CONFIG_HOTPLUG_CPU
1396 		if (setup_max_cpus)
1397 			possible += disabled_cpus;
1398 #else
1399 		if (possible > i)
1400 			possible = i;
1401 #endif
1402 	} else
1403 		possible = setup_possible_cpus;
1404 
1405 	total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1406 
1407 	/* nr_cpu_ids could be reduced via nr_cpus= */
1408 	if (possible > nr_cpu_ids) {
1409 		pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1410 			possible, nr_cpu_ids);
1411 		possible = nr_cpu_ids;
1412 	}
1413 
1414 #ifdef CONFIG_HOTPLUG_CPU
1415 	if (!setup_max_cpus)
1416 #endif
1417 	if (possible > i) {
1418 		pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1419 			possible, setup_max_cpus);
1420 		possible = i;
1421 	}
1422 
1423 	nr_cpu_ids = possible;
1424 
1425 	pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1426 		possible, max_t(int, possible - num_processors, 0));
1427 
1428 	reset_cpu_possible_mask();
1429 
1430 	for (i = 0; i < possible; i++)
1431 		set_cpu_possible(i, true);
1432 }
1433 
1434 #ifdef CONFIG_HOTPLUG_CPU
1435 
1436 /* Recompute SMT state for all CPUs on offline */
1437 static void recompute_smt_state(void)
1438 {
1439 	int max_threads, cpu;
1440 
1441 	max_threads = 0;
1442 	for_each_online_cpu (cpu) {
1443 		int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1444 
1445 		if (threads > max_threads)
1446 			max_threads = threads;
1447 	}
1448 	__max_smt_threads = max_threads;
1449 }
1450 
1451 static void remove_siblinginfo(int cpu)
1452 {
1453 	int sibling;
1454 	struct cpuinfo_x86 *c = &cpu_data(cpu);
1455 
1456 	for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1457 		cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1458 		/*/
1459 		 * last thread sibling in this cpu core going down
1460 		 */
1461 		if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1462 			cpu_data(sibling).booted_cores--;
1463 	}
1464 
1465 	for_each_cpu(sibling, topology_sibling_cpumask(cpu))
1466 		cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1467 	for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1468 		cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1469 	cpumask_clear(cpu_llc_shared_mask(cpu));
1470 	cpumask_clear(topology_sibling_cpumask(cpu));
1471 	cpumask_clear(topology_core_cpumask(cpu));
1472 	c->cpu_core_id = 0;
1473 	c->booted_cores = 0;
1474 	cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1475 	recompute_smt_state();
1476 }
1477 
1478 static void remove_cpu_from_maps(int cpu)
1479 {
1480 	set_cpu_online(cpu, false);
1481 	cpumask_clear_cpu(cpu, cpu_callout_mask);
1482 	cpumask_clear_cpu(cpu, cpu_callin_mask);
1483 	/* was set by cpu_init() */
1484 	cpumask_clear_cpu(cpu, cpu_initialized_mask);
1485 	numa_remove_cpu(cpu);
1486 }
1487 
1488 void cpu_disable_common(void)
1489 {
1490 	int cpu = smp_processor_id();
1491 
1492 	remove_siblinginfo(cpu);
1493 
1494 	/* It's now safe to remove this processor from the online map */
1495 	lock_vector_lock();
1496 	remove_cpu_from_maps(cpu);
1497 	unlock_vector_lock();
1498 	fixup_irqs();
1499 	lapic_offline();
1500 }
1501 
1502 int native_cpu_disable(void)
1503 {
1504 	int ret;
1505 
1506 	ret = lapic_can_unplug_cpu();
1507 	if (ret)
1508 		return ret;
1509 
1510 	clear_local_APIC();
1511 	cpu_disable_common();
1512 
1513 	return 0;
1514 }
1515 
1516 int common_cpu_die(unsigned int cpu)
1517 {
1518 	int ret = 0;
1519 
1520 	/* We don't do anything here: idle task is faking death itself. */
1521 
1522 	/* They ack this in play_dead() by setting CPU_DEAD */
1523 	if (cpu_wait_death(cpu, 5)) {
1524 		if (system_state == SYSTEM_RUNNING)
1525 			pr_info("CPU %u is now offline\n", cpu);
1526 	} else {
1527 		pr_err("CPU %u didn't die...\n", cpu);
1528 		ret = -1;
1529 	}
1530 
1531 	return ret;
1532 }
1533 
1534 void native_cpu_die(unsigned int cpu)
1535 {
1536 	common_cpu_die(cpu);
1537 }
1538 
1539 void play_dead_common(void)
1540 {
1541 	idle_task_exit();
1542 
1543 	/* Ack it */
1544 	(void)cpu_report_death();
1545 
1546 	/*
1547 	 * With physical CPU hotplug, we should halt the cpu
1548 	 */
1549 	local_irq_disable();
1550 }
1551 
1552 static bool wakeup_cpu0(void)
1553 {
1554 	if (smp_processor_id() == 0 && enable_start_cpu0)
1555 		return true;
1556 
1557 	return false;
1558 }
1559 
1560 /*
1561  * We need to flush the caches before going to sleep, lest we have
1562  * dirty data in our caches when we come back up.
1563  */
1564 static inline void mwait_play_dead(void)
1565 {
1566 	unsigned int eax, ebx, ecx, edx;
1567 	unsigned int highest_cstate = 0;
1568 	unsigned int highest_subcstate = 0;
1569 	void *mwait_ptr;
1570 	int i;
1571 
1572 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD)
1573 		return;
1574 	if (!this_cpu_has(X86_FEATURE_MWAIT))
1575 		return;
1576 	if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1577 		return;
1578 	if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1579 		return;
1580 
1581 	eax = CPUID_MWAIT_LEAF;
1582 	ecx = 0;
1583 	native_cpuid(&eax, &ebx, &ecx, &edx);
1584 
1585 	/*
1586 	 * eax will be 0 if EDX enumeration is not valid.
1587 	 * Initialized below to cstate, sub_cstate value when EDX is valid.
1588 	 */
1589 	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1590 		eax = 0;
1591 	} else {
1592 		edx >>= MWAIT_SUBSTATE_SIZE;
1593 		for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1594 			if (edx & MWAIT_SUBSTATE_MASK) {
1595 				highest_cstate = i;
1596 				highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1597 			}
1598 		}
1599 		eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1600 			(highest_subcstate - 1);
1601 	}
1602 
1603 	/*
1604 	 * This should be a memory location in a cache line which is
1605 	 * unlikely to be touched by other processors.  The actual
1606 	 * content is immaterial as it is not actually modified in any way.
1607 	 */
1608 	mwait_ptr = &current_thread_info()->flags;
1609 
1610 	wbinvd();
1611 
1612 	while (1) {
1613 		/*
1614 		 * The CLFLUSH is a workaround for erratum AAI65 for
1615 		 * the Xeon 7400 series.  It's not clear it is actually
1616 		 * needed, but it should be harmless in either case.
1617 		 * The WBINVD is insufficient due to the spurious-wakeup
1618 		 * case where we return around the loop.
1619 		 */
1620 		mb();
1621 		clflush(mwait_ptr);
1622 		mb();
1623 		__monitor(mwait_ptr, 0, 0);
1624 		mb();
1625 		__mwait(eax, 0);
1626 		/*
1627 		 * If NMI wants to wake up CPU0, start CPU0.
1628 		 */
1629 		if (wakeup_cpu0())
1630 			start_cpu0();
1631 	}
1632 }
1633 
1634 void hlt_play_dead(void)
1635 {
1636 	if (__this_cpu_read(cpu_info.x86) >= 4)
1637 		wbinvd();
1638 
1639 	while (1) {
1640 		native_halt();
1641 		/*
1642 		 * If NMI wants to wake up CPU0, start CPU0.
1643 		 */
1644 		if (wakeup_cpu0())
1645 			start_cpu0();
1646 	}
1647 }
1648 
1649 void native_play_dead(void)
1650 {
1651 	play_dead_common();
1652 	tboot_shutdown(TB_SHUTDOWN_WFS);
1653 
1654 	mwait_play_dead();	/* Only returns on failure */
1655 	if (cpuidle_play_dead())
1656 		hlt_play_dead();
1657 }
1658 
1659 #else /* ... !CONFIG_HOTPLUG_CPU */
1660 int native_cpu_disable(void)
1661 {
1662 	return -ENOSYS;
1663 }
1664 
1665 void native_cpu_die(unsigned int cpu)
1666 {
1667 	/* We said "no" in __cpu_disable */
1668 	BUG();
1669 }
1670 
1671 void native_play_dead(void)
1672 {
1673 	BUG();
1674 }
1675 
1676 #endif
1677