1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/memblock.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 #include <linux/numa.h> 60 61 #include <asm/acpi.h> 62 #include <asm/desc.h> 63 #include <asm/nmi.h> 64 #include <asm/irq.h> 65 #include <asm/realmode.h> 66 #include <asm/cpu.h> 67 #include <asm/numa.h> 68 #include <asm/pgtable.h> 69 #include <asm/tlbflush.h> 70 #include <asm/mtrr.h> 71 #include <asm/mwait.h> 72 #include <asm/apic.h> 73 #include <asm/io_apic.h> 74 #include <asm/fpu/internal.h> 75 #include <asm/setup.h> 76 #include <asm/uv/uv.h> 77 #include <linux/mc146818rtc.h> 78 #include <asm/i8259.h> 79 #include <asm/misc.h> 80 #include <asm/qspinlock.h> 81 #include <asm/intel-family.h> 82 #include <asm/cpu_device_id.h> 83 #include <asm/spec-ctrl.h> 84 #include <asm/hw_irq.h> 85 86 /* representing HT siblings of each logical CPU */ 87 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 89 90 /* representing HT and core siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 93 94 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 95 96 /* Per CPU bogomips and other parameters */ 97 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 98 EXPORT_PER_CPU_SYMBOL(cpu_info); 99 100 /* Logical package management. We might want to allocate that dynamically */ 101 unsigned int __max_logical_packages __read_mostly; 102 EXPORT_SYMBOL(__max_logical_packages); 103 static unsigned int logical_packages __read_mostly; 104 105 /* Maximum number of SMT threads on any online core */ 106 int __read_mostly __max_smt_threads = 1; 107 108 /* Flag to indicate if a complete sched domain rebuild is required */ 109 bool x86_topology_update; 110 111 int arch_update_cpu_topology(void) 112 { 113 int retval = x86_topology_update; 114 115 x86_topology_update = false; 116 return retval; 117 } 118 119 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 120 { 121 unsigned long flags; 122 123 spin_lock_irqsave(&rtc_lock, flags); 124 CMOS_WRITE(0xa, 0xf); 125 spin_unlock_irqrestore(&rtc_lock, flags); 126 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 127 start_eip >> 4; 128 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 129 start_eip & 0xf; 130 } 131 132 static inline void smpboot_restore_warm_reset_vector(void) 133 { 134 unsigned long flags; 135 136 /* 137 * Paranoid: Set warm reset code and vector here back 138 * to default values. 139 */ 140 spin_lock_irqsave(&rtc_lock, flags); 141 CMOS_WRITE(0, 0xf); 142 spin_unlock_irqrestore(&rtc_lock, flags); 143 144 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 145 } 146 147 /* 148 * Report back to the Boot Processor during boot time or to the caller processor 149 * during CPU online. 150 */ 151 static void smp_callin(void) 152 { 153 int cpuid, phys_id; 154 155 /* 156 * If waken up by an INIT in an 82489DX configuration 157 * cpu_callout_mask guarantees we don't get here before 158 * an INIT_deassert IPI reaches our local APIC, so it is 159 * now safe to touch our local APIC. 160 */ 161 cpuid = smp_processor_id(); 162 163 /* 164 * (This works even if the APIC is not enabled.) 165 */ 166 phys_id = read_apic_id(); 167 168 /* 169 * the boot CPU has finished the init stage and is spinning 170 * on callin_map until we finish. We are free to set up this 171 * CPU, first the APIC. (this is probably redundant on most 172 * boards) 173 */ 174 apic_ap_setup(); 175 176 /* 177 * Save our processor parameters. Note: this information 178 * is needed for clock calibration. 179 */ 180 smp_store_cpu_info(cpuid); 181 182 /* 183 * The topology information must be up to date before 184 * calibrate_delay() and notify_cpu_starting(). 185 */ 186 set_cpu_sibling_map(raw_smp_processor_id()); 187 188 /* 189 * Get our bogomips. 190 * Update loops_per_jiffy in cpu_data. Previous call to 191 * smp_store_cpu_info() stored a value that is close but not as 192 * accurate as the value just calculated. 193 */ 194 calibrate_delay(); 195 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 196 pr_debug("Stack at about %p\n", &cpuid); 197 198 wmb(); 199 200 notify_cpu_starting(cpuid); 201 202 /* 203 * Allow the master to continue. 204 */ 205 cpumask_set_cpu(cpuid, cpu_callin_mask); 206 } 207 208 static int cpu0_logical_apicid; 209 static int enable_start_cpu0; 210 /* 211 * Activate a secondary processor. 212 */ 213 static void notrace start_secondary(void *unused) 214 { 215 /* 216 * Don't put *anything* except direct CPU state initialization 217 * before cpu_init(), SMP booting is too fragile that we want to 218 * limit the things done here to the most necessary things. 219 */ 220 if (boot_cpu_has(X86_FEATURE_PCID)) 221 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 222 223 #ifdef CONFIG_X86_32 224 /* switch away from the initial page table */ 225 load_cr3(swapper_pg_dir); 226 /* 227 * Initialize the CR4 shadow before doing anything that could 228 * try to read it. 229 */ 230 cr4_init_shadow(); 231 __flush_tlb_all(); 232 #endif 233 load_current_idt(); 234 cpu_init(); 235 x86_cpuinit.early_percpu_clock_init(); 236 preempt_disable(); 237 smp_callin(); 238 239 enable_start_cpu0 = 0; 240 241 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 242 barrier(); 243 /* 244 * Check TSC synchronization with the boot CPU: 245 */ 246 check_tsc_sync_target(); 247 248 speculative_store_bypass_ht_init(); 249 250 /* 251 * Lock vector_lock, set CPU online and bring the vector 252 * allocator online. Online must be set with vector_lock held 253 * to prevent a concurrent irq setup/teardown from seeing a 254 * half valid vector space. 255 */ 256 lock_vector_lock(); 257 set_cpu_online(smp_processor_id(), true); 258 lapic_online(); 259 unlock_vector_lock(); 260 cpu_set_state_online(smp_processor_id()); 261 x86_platform.nmi_init(); 262 263 /* enable local interrupts */ 264 local_irq_enable(); 265 266 /* to prevent fake stack check failure in clock setup */ 267 boot_init_stack_canary(); 268 269 x86_cpuinit.setup_percpu_clockev(); 270 271 wmb(); 272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 273 } 274 275 /** 276 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 277 * @cpu: CPU to check 278 */ 279 bool topology_is_primary_thread(unsigned int cpu) 280 { 281 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 282 } 283 284 /** 285 * topology_smt_supported - Check whether SMT is supported by the CPUs 286 */ 287 bool topology_smt_supported(void) 288 { 289 return smp_num_siblings > 1; 290 } 291 292 /** 293 * topology_phys_to_logical_pkg - Map a physical package id to a logical 294 * 295 * Returns logical package id or -1 if not found 296 */ 297 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 298 { 299 int cpu; 300 301 for_each_possible_cpu(cpu) { 302 struct cpuinfo_x86 *c = &cpu_data(cpu); 303 304 if (c->initialized && c->phys_proc_id == phys_pkg) 305 return c->logical_proc_id; 306 } 307 return -1; 308 } 309 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 310 311 /** 312 * topology_update_package_map - Update the physical to logical package map 313 * @pkg: The physical package id as retrieved via CPUID 314 * @cpu: The cpu for which this is updated 315 */ 316 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 317 { 318 int new; 319 320 /* Already available somewhere? */ 321 new = topology_phys_to_logical_pkg(pkg); 322 if (new >= 0) 323 goto found; 324 325 new = logical_packages++; 326 if (new != pkg) { 327 pr_info("CPU %u Converting physical %u to logical package %u\n", 328 cpu, pkg, new); 329 } 330 found: 331 cpu_data(cpu).logical_proc_id = new; 332 return 0; 333 } 334 335 void __init smp_store_boot_cpu_info(void) 336 { 337 int id = 0; /* CPU 0 */ 338 struct cpuinfo_x86 *c = &cpu_data(id); 339 340 *c = boot_cpu_data; 341 c->cpu_index = id; 342 topology_update_package_map(c->phys_proc_id, id); 343 c->initialized = true; 344 } 345 346 /* 347 * The bootstrap kernel entry code has set these up. Save them for 348 * a given CPU 349 */ 350 void smp_store_cpu_info(int id) 351 { 352 struct cpuinfo_x86 *c = &cpu_data(id); 353 354 /* Copy boot_cpu_data only on the first bringup */ 355 if (!c->initialized) 356 *c = boot_cpu_data; 357 c->cpu_index = id; 358 /* 359 * During boot time, CPU0 has this setup already. Save the info when 360 * bringing up AP or offlined CPU0. 361 */ 362 identify_secondary_cpu(c); 363 c->initialized = true; 364 } 365 366 static bool 367 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 368 { 369 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 370 371 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 372 } 373 374 static bool 375 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 376 { 377 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 378 379 return !WARN_ONCE(!topology_same_node(c, o), 380 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 381 "[node: %d != %d]. Ignoring dependency.\n", 382 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 383 } 384 385 #define link_mask(mfunc, c1, c2) \ 386 do { \ 387 cpumask_set_cpu((c1), mfunc(c2)); \ 388 cpumask_set_cpu((c2), mfunc(c1)); \ 389 } while (0) 390 391 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 392 { 393 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 394 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 395 396 if (c->phys_proc_id == o->phys_proc_id && 397 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 398 if (c->cpu_core_id == o->cpu_core_id) 399 return topology_sane(c, o, "smt"); 400 401 if ((c->cu_id != 0xff) && 402 (o->cu_id != 0xff) && 403 (c->cu_id == o->cu_id)) 404 return topology_sane(c, o, "smt"); 405 } 406 407 } else if (c->phys_proc_id == o->phys_proc_id && 408 c->cpu_core_id == o->cpu_core_id) { 409 return topology_sane(c, o, "smt"); 410 } 411 412 return false; 413 } 414 415 /* 416 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 417 * 418 * These are Intel CPUs that enumerate an LLC that is shared by 419 * multiple NUMA nodes. The LLC on these systems is shared for 420 * off-package data access but private to the NUMA node (half 421 * of the package) for on-package access. 422 * 423 * CPUID (the source of the information about the LLC) can only 424 * enumerate the cache as being shared *or* unshared, but not 425 * this particular configuration. The CPU in this case enumerates 426 * the cache to be shared across the entire package (spanning both 427 * NUMA nodes). 428 */ 429 430 static const struct x86_cpu_id snc_cpu[] = { 431 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X }, 432 {} 433 }; 434 435 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 436 { 437 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 438 439 /* Do not match if we do not have a valid APICID for cpu: */ 440 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 441 return false; 442 443 /* Do not match if LLC id does not match: */ 444 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 445 return false; 446 447 /* 448 * Allow the SNC topology without warning. Return of false 449 * means 'c' does not share the LLC of 'o'. This will be 450 * reflected to userspace. 451 */ 452 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 453 return false; 454 455 return topology_sane(c, o, "llc"); 456 } 457 458 /* 459 * Unlike the other levels, we do not enforce keeping a 460 * multicore group inside a NUMA node. If this happens, we will 461 * discard the MC level of the topology later. 462 */ 463 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 464 { 465 if (c->phys_proc_id == o->phys_proc_id) 466 return true; 467 return false; 468 } 469 470 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 471 static inline int x86_sched_itmt_flags(void) 472 { 473 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 474 } 475 476 #ifdef CONFIG_SCHED_MC 477 static int x86_core_flags(void) 478 { 479 return cpu_core_flags() | x86_sched_itmt_flags(); 480 } 481 #endif 482 #ifdef CONFIG_SCHED_SMT 483 static int x86_smt_flags(void) 484 { 485 return cpu_smt_flags() | x86_sched_itmt_flags(); 486 } 487 #endif 488 #endif 489 490 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 491 #ifdef CONFIG_SCHED_SMT 492 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 493 #endif 494 #ifdef CONFIG_SCHED_MC 495 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 496 #endif 497 { NULL, }, 498 }; 499 500 static struct sched_domain_topology_level x86_topology[] = { 501 #ifdef CONFIG_SCHED_SMT 502 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 503 #endif 504 #ifdef CONFIG_SCHED_MC 505 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 506 #endif 507 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 508 { NULL, }, 509 }; 510 511 /* 512 * Set if a package/die has multiple NUMA nodes inside. 513 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 514 * Sub-NUMA Clustering have this. 515 */ 516 static bool x86_has_numa_in_package; 517 518 void set_cpu_sibling_map(int cpu) 519 { 520 bool has_smt = smp_num_siblings > 1; 521 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 522 struct cpuinfo_x86 *c = &cpu_data(cpu); 523 struct cpuinfo_x86 *o; 524 int i, threads; 525 526 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 527 528 if (!has_mp) { 529 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 530 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 531 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 532 c->booted_cores = 1; 533 return; 534 } 535 536 for_each_cpu(i, cpu_sibling_setup_mask) { 537 o = &cpu_data(i); 538 539 if ((i == cpu) || (has_smt && match_smt(c, o))) 540 link_mask(topology_sibling_cpumask, cpu, i); 541 542 if ((i == cpu) || (has_mp && match_llc(c, o))) 543 link_mask(cpu_llc_shared_mask, cpu, i); 544 545 } 546 547 /* 548 * This needs a separate iteration over the cpus because we rely on all 549 * topology_sibling_cpumask links to be set-up. 550 */ 551 for_each_cpu(i, cpu_sibling_setup_mask) { 552 o = &cpu_data(i); 553 554 if ((i == cpu) || (has_mp && match_die(c, o))) { 555 link_mask(topology_core_cpumask, cpu, i); 556 557 /* 558 * Does this new cpu bringup a new core? 559 */ 560 if (cpumask_weight( 561 topology_sibling_cpumask(cpu)) == 1) { 562 /* 563 * for each core in package, increment 564 * the booted_cores for this new cpu 565 */ 566 if (cpumask_first( 567 topology_sibling_cpumask(i)) == i) 568 c->booted_cores++; 569 /* 570 * increment the core count for all 571 * the other cpus in this package 572 */ 573 if (i != cpu) 574 cpu_data(i).booted_cores++; 575 } else if (i != cpu && !c->booted_cores) 576 c->booted_cores = cpu_data(i).booted_cores; 577 } 578 if (match_die(c, o) && !topology_same_node(c, o)) 579 x86_has_numa_in_package = true; 580 } 581 582 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 583 if (threads > __max_smt_threads) 584 __max_smt_threads = threads; 585 } 586 587 /* maps the cpu to the sched domain representing multi-core */ 588 const struct cpumask *cpu_coregroup_mask(int cpu) 589 { 590 return cpu_llc_shared_mask(cpu); 591 } 592 593 static void impress_friends(void) 594 { 595 int cpu; 596 unsigned long bogosum = 0; 597 /* 598 * Allow the user to impress friends. 599 */ 600 pr_debug("Before bogomips\n"); 601 for_each_possible_cpu(cpu) 602 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 603 bogosum += cpu_data(cpu).loops_per_jiffy; 604 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 605 num_online_cpus(), 606 bogosum/(500000/HZ), 607 (bogosum/(5000/HZ))%100); 608 609 pr_debug("Before bogocount - setting activated=1\n"); 610 } 611 612 void __inquire_remote_apic(int apicid) 613 { 614 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 615 const char * const names[] = { "ID", "VERSION", "SPIV" }; 616 int timeout; 617 u32 status; 618 619 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 620 621 for (i = 0; i < ARRAY_SIZE(regs); i++) { 622 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 623 624 /* 625 * Wait for idle. 626 */ 627 status = safe_apic_wait_icr_idle(); 628 if (status) 629 pr_cont("a previous APIC delivery may have failed\n"); 630 631 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 632 633 timeout = 0; 634 do { 635 udelay(100); 636 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 637 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 638 639 switch (status) { 640 case APIC_ICR_RR_VALID: 641 status = apic_read(APIC_RRR); 642 pr_cont("%08x\n", status); 643 break; 644 default: 645 pr_cont("failed\n"); 646 } 647 } 648 } 649 650 /* 651 * The Multiprocessor Specification 1.4 (1997) example code suggests 652 * that there should be a 10ms delay between the BSP asserting INIT 653 * and de-asserting INIT, when starting a remote processor. 654 * But that slows boot and resume on modern processors, which include 655 * many cores and don't require that delay. 656 * 657 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 658 * Modern processor families are quirked to remove the delay entirely. 659 */ 660 #define UDELAY_10MS_DEFAULT 10000 661 662 static unsigned int init_udelay = UINT_MAX; 663 664 static int __init cpu_init_udelay(char *str) 665 { 666 get_option(&str, &init_udelay); 667 668 return 0; 669 } 670 early_param("cpu_init_udelay", cpu_init_udelay); 671 672 static void __init smp_quirk_init_udelay(void) 673 { 674 /* if cmdline changed it from default, leave it alone */ 675 if (init_udelay != UINT_MAX) 676 return; 677 678 /* if modern processor, use no delay */ 679 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 680 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 681 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 682 init_udelay = 0; 683 return; 684 } 685 /* else, use legacy delay */ 686 init_udelay = UDELAY_10MS_DEFAULT; 687 } 688 689 /* 690 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 691 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 692 * won't ... remember to clear down the APIC, etc later. 693 */ 694 int 695 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 696 { 697 unsigned long send_status, accept_status = 0; 698 int maxlvt; 699 700 /* Target chip */ 701 /* Boot on the stack */ 702 /* Kick the second */ 703 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 704 705 pr_debug("Waiting for send to finish...\n"); 706 send_status = safe_apic_wait_icr_idle(); 707 708 /* 709 * Give the other CPU some time to accept the IPI. 710 */ 711 udelay(200); 712 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 713 maxlvt = lapic_get_maxlvt(); 714 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 715 apic_write(APIC_ESR, 0); 716 accept_status = (apic_read(APIC_ESR) & 0xEF); 717 } 718 pr_debug("NMI sent\n"); 719 720 if (send_status) 721 pr_err("APIC never delivered???\n"); 722 if (accept_status) 723 pr_err("APIC delivery error (%lx)\n", accept_status); 724 725 return (send_status | accept_status); 726 } 727 728 static int 729 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 730 { 731 unsigned long send_status = 0, accept_status = 0; 732 int maxlvt, num_starts, j; 733 734 maxlvt = lapic_get_maxlvt(); 735 736 /* 737 * Be paranoid about clearing APIC errors. 738 */ 739 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 740 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 741 apic_write(APIC_ESR, 0); 742 apic_read(APIC_ESR); 743 } 744 745 pr_debug("Asserting INIT\n"); 746 747 /* 748 * Turn INIT on target chip 749 */ 750 /* 751 * Send IPI 752 */ 753 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 754 phys_apicid); 755 756 pr_debug("Waiting for send to finish...\n"); 757 send_status = safe_apic_wait_icr_idle(); 758 759 udelay(init_udelay); 760 761 pr_debug("Deasserting INIT\n"); 762 763 /* Target chip */ 764 /* Send IPI */ 765 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 766 767 pr_debug("Waiting for send to finish...\n"); 768 send_status = safe_apic_wait_icr_idle(); 769 770 mb(); 771 772 /* 773 * Should we send STARTUP IPIs ? 774 * 775 * Determine this based on the APIC version. 776 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 777 */ 778 if (APIC_INTEGRATED(boot_cpu_apic_version)) 779 num_starts = 2; 780 else 781 num_starts = 0; 782 783 /* 784 * Run STARTUP IPI loop. 785 */ 786 pr_debug("#startup loops: %d\n", num_starts); 787 788 for (j = 1; j <= num_starts; j++) { 789 pr_debug("Sending STARTUP #%d\n", j); 790 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 791 apic_write(APIC_ESR, 0); 792 apic_read(APIC_ESR); 793 pr_debug("After apic_write\n"); 794 795 /* 796 * STARTUP IPI 797 */ 798 799 /* Target chip */ 800 /* Boot on the stack */ 801 /* Kick the second */ 802 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 803 phys_apicid); 804 805 /* 806 * Give the other CPU some time to accept the IPI. 807 */ 808 if (init_udelay == 0) 809 udelay(10); 810 else 811 udelay(300); 812 813 pr_debug("Startup point 1\n"); 814 815 pr_debug("Waiting for send to finish...\n"); 816 send_status = safe_apic_wait_icr_idle(); 817 818 /* 819 * Give the other CPU some time to accept the IPI. 820 */ 821 if (init_udelay == 0) 822 udelay(10); 823 else 824 udelay(200); 825 826 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 827 apic_write(APIC_ESR, 0); 828 accept_status = (apic_read(APIC_ESR) & 0xEF); 829 if (send_status || accept_status) 830 break; 831 } 832 pr_debug("After Startup\n"); 833 834 if (send_status) 835 pr_err("APIC never delivered???\n"); 836 if (accept_status) 837 pr_err("APIC delivery error (%lx)\n", accept_status); 838 839 return (send_status | accept_status); 840 } 841 842 /* reduce the number of lines printed when booting a large cpu count system */ 843 static void announce_cpu(int cpu, int apicid) 844 { 845 static int current_node = NUMA_NO_NODE; 846 int node = early_cpu_to_node(cpu); 847 static int width, node_width; 848 849 if (!width) 850 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 851 852 if (!node_width) 853 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 854 855 if (cpu == 1) 856 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 857 858 if (system_state < SYSTEM_RUNNING) { 859 if (node != current_node) { 860 if (current_node > (-1)) 861 pr_cont("\n"); 862 current_node = node; 863 864 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 865 node_width - num_digits(node), " ", node); 866 } 867 868 /* Add padding for the BSP */ 869 if (cpu == 1) 870 pr_cont("%*s", width + 1, " "); 871 872 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 873 874 } else 875 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 876 node, cpu, apicid); 877 } 878 879 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 880 { 881 int cpu; 882 883 cpu = smp_processor_id(); 884 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 885 return NMI_HANDLED; 886 887 return NMI_DONE; 888 } 889 890 /* 891 * Wake up AP by INIT, INIT, STARTUP sequence. 892 * 893 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 894 * boot-strap code which is not a desired behavior for waking up BSP. To 895 * void the boot-strap code, wake up CPU0 by NMI instead. 896 * 897 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 898 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 899 * We'll change this code in the future to wake up hard offlined CPU0 if 900 * real platform and request are available. 901 */ 902 static int 903 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 904 int *cpu0_nmi_registered) 905 { 906 int id; 907 int boot_error; 908 909 preempt_disable(); 910 911 /* 912 * Wake up AP by INIT, INIT, STARTUP sequence. 913 */ 914 if (cpu) { 915 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 916 goto out; 917 } 918 919 /* 920 * Wake up BSP by nmi. 921 * 922 * Register a NMI handler to help wake up CPU0. 923 */ 924 boot_error = register_nmi_handler(NMI_LOCAL, 925 wakeup_cpu0_nmi, 0, "wake_cpu0"); 926 927 if (!boot_error) { 928 enable_start_cpu0 = 1; 929 *cpu0_nmi_registered = 1; 930 if (apic->dest_logical == APIC_DEST_LOGICAL) 931 id = cpu0_logical_apicid; 932 else 933 id = apicid; 934 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 935 } 936 937 out: 938 preempt_enable(); 939 940 return boot_error; 941 } 942 943 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 944 { 945 /* Just in case we booted with a single CPU. */ 946 alternatives_enable_smp(); 947 948 per_cpu(current_task, cpu) = idle; 949 950 #ifdef CONFIG_X86_32 951 /* Stack for startup_32 can be just as for start_secondary onwards */ 952 irq_ctx_init(cpu); 953 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 954 #else 955 initial_gs = per_cpu_offset(cpu); 956 #endif 957 } 958 959 /* 960 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 961 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 962 * Returns zero if CPU booted OK, else error code from 963 * ->wakeup_secondary_cpu. 964 */ 965 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 966 int *cpu0_nmi_registered) 967 { 968 volatile u32 *trampoline_status = 969 (volatile u32 *) __va(real_mode_header->trampoline_status); 970 /* start_ip had better be page-aligned! */ 971 unsigned long start_ip = real_mode_header->trampoline_start; 972 973 unsigned long boot_error = 0; 974 unsigned long timeout; 975 976 idle->thread.sp = (unsigned long)task_pt_regs(idle); 977 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 978 initial_code = (unsigned long)start_secondary; 979 initial_stack = idle->thread.sp; 980 981 /* Enable the espfix hack for this CPU */ 982 init_espfix_ap(cpu); 983 984 /* So we see what's up */ 985 announce_cpu(cpu, apicid); 986 987 /* 988 * This grunge runs the startup process for 989 * the targeted processor. 990 */ 991 992 if (x86_platform.legacy.warm_reset) { 993 994 pr_debug("Setting warm reset code and vector.\n"); 995 996 smpboot_setup_warm_reset_vector(start_ip); 997 /* 998 * Be paranoid about clearing APIC errors. 999 */ 1000 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1001 apic_write(APIC_ESR, 0); 1002 apic_read(APIC_ESR); 1003 } 1004 } 1005 1006 /* 1007 * AP might wait on cpu_callout_mask in cpu_init() with 1008 * cpu_initialized_mask set if previous attempt to online 1009 * it timed-out. Clear cpu_initialized_mask so that after 1010 * INIT/SIPI it could start with a clean state. 1011 */ 1012 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1013 smp_mb(); 1014 1015 /* 1016 * Wake up a CPU in difference cases: 1017 * - Use the method in the APIC driver if it's defined 1018 * Otherwise, 1019 * - Use an INIT boot APIC message for APs or NMI for BSP. 1020 */ 1021 if (apic->wakeup_secondary_cpu) 1022 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1023 else 1024 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1025 cpu0_nmi_registered); 1026 1027 if (!boot_error) { 1028 /* 1029 * Wait 10s total for first sign of life from AP 1030 */ 1031 boot_error = -1; 1032 timeout = jiffies + 10*HZ; 1033 while (time_before(jiffies, timeout)) { 1034 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1035 /* 1036 * Tell AP to proceed with initialization 1037 */ 1038 cpumask_set_cpu(cpu, cpu_callout_mask); 1039 boot_error = 0; 1040 break; 1041 } 1042 schedule(); 1043 } 1044 } 1045 1046 if (!boot_error) { 1047 /* 1048 * Wait till AP completes initial initialization 1049 */ 1050 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1051 /* 1052 * Allow other tasks to run while we wait for the 1053 * AP to come online. This also gives a chance 1054 * for the MTRR work(triggered by the AP coming online) 1055 * to be completed in the stop machine context. 1056 */ 1057 schedule(); 1058 } 1059 } 1060 1061 /* mark "stuck" area as not stuck */ 1062 *trampoline_status = 0; 1063 1064 if (x86_platform.legacy.warm_reset) { 1065 /* 1066 * Cleanup possible dangling ends... 1067 */ 1068 smpboot_restore_warm_reset_vector(); 1069 } 1070 1071 return boot_error; 1072 } 1073 1074 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1075 { 1076 int apicid = apic->cpu_present_to_apicid(cpu); 1077 int cpu0_nmi_registered = 0; 1078 unsigned long flags; 1079 int err, ret = 0; 1080 1081 lockdep_assert_irqs_enabled(); 1082 1083 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1084 1085 if (apicid == BAD_APICID || 1086 !physid_isset(apicid, phys_cpu_present_map) || 1087 !apic->apic_id_valid(apicid)) { 1088 pr_err("%s: bad cpu %d\n", __func__, cpu); 1089 return -EINVAL; 1090 } 1091 1092 /* 1093 * Already booted CPU? 1094 */ 1095 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1096 pr_debug("do_boot_cpu %d Already started\n", cpu); 1097 return -ENOSYS; 1098 } 1099 1100 /* 1101 * Save current MTRR state in case it was changed since early boot 1102 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1103 */ 1104 mtrr_save_state(); 1105 1106 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1107 err = cpu_check_up_prepare(cpu); 1108 if (err && err != -EBUSY) 1109 return err; 1110 1111 /* the FPU context is blank, nobody can own it */ 1112 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1113 1114 common_cpu_up(cpu, tidle); 1115 1116 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1117 if (err) { 1118 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1119 ret = -EIO; 1120 goto unreg_nmi; 1121 } 1122 1123 /* 1124 * Check TSC synchronization with the AP (keep irqs disabled 1125 * while doing so): 1126 */ 1127 local_irq_save(flags); 1128 check_tsc_sync_source(cpu); 1129 local_irq_restore(flags); 1130 1131 while (!cpu_online(cpu)) { 1132 cpu_relax(); 1133 touch_nmi_watchdog(); 1134 } 1135 1136 unreg_nmi: 1137 /* 1138 * Clean up the nmi handler. Do this after the callin and callout sync 1139 * to avoid impact of possible long unregister time. 1140 */ 1141 if (cpu0_nmi_registered) 1142 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1143 1144 return ret; 1145 } 1146 1147 /** 1148 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1149 */ 1150 void arch_disable_smp_support(void) 1151 { 1152 disable_ioapic_support(); 1153 } 1154 1155 /* 1156 * Fall back to non SMP mode after errors. 1157 * 1158 * RED-PEN audit/test this more. I bet there is more state messed up here. 1159 */ 1160 static __init void disable_smp(void) 1161 { 1162 pr_info("SMP disabled\n"); 1163 1164 disable_ioapic_support(); 1165 1166 init_cpu_present(cpumask_of(0)); 1167 init_cpu_possible(cpumask_of(0)); 1168 1169 if (smp_found_config) 1170 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1171 else 1172 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1173 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1174 cpumask_set_cpu(0, topology_core_cpumask(0)); 1175 } 1176 1177 /* 1178 * Various sanity checks. 1179 */ 1180 static void __init smp_sanity_check(void) 1181 { 1182 preempt_disable(); 1183 1184 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1185 if (def_to_bigsmp && nr_cpu_ids > 8) { 1186 unsigned int cpu; 1187 unsigned nr; 1188 1189 pr_warn("More than 8 CPUs detected - skipping them\n" 1190 "Use CONFIG_X86_BIGSMP\n"); 1191 1192 nr = 0; 1193 for_each_present_cpu(cpu) { 1194 if (nr >= 8) 1195 set_cpu_present(cpu, false); 1196 nr++; 1197 } 1198 1199 nr = 0; 1200 for_each_possible_cpu(cpu) { 1201 if (nr >= 8) 1202 set_cpu_possible(cpu, false); 1203 nr++; 1204 } 1205 1206 nr_cpu_ids = 8; 1207 } 1208 #endif 1209 1210 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1211 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1212 hard_smp_processor_id()); 1213 1214 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1215 } 1216 1217 /* 1218 * Should not be necessary because the MP table should list the boot 1219 * CPU too, but we do it for the sake of robustness anyway. 1220 */ 1221 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1222 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1223 boot_cpu_physical_apicid); 1224 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1225 } 1226 preempt_enable(); 1227 } 1228 1229 static void __init smp_cpu_index_default(void) 1230 { 1231 int i; 1232 struct cpuinfo_x86 *c; 1233 1234 for_each_possible_cpu(i) { 1235 c = &cpu_data(i); 1236 /* mark all to hotplug */ 1237 c->cpu_index = nr_cpu_ids; 1238 } 1239 } 1240 1241 static void __init smp_get_logical_apicid(void) 1242 { 1243 if (x2apic_mode) 1244 cpu0_logical_apicid = apic_read(APIC_LDR); 1245 else 1246 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1247 } 1248 1249 /* 1250 * Prepare for SMP bootup. 1251 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1252 * for common interface support. 1253 */ 1254 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1255 { 1256 unsigned int i; 1257 1258 smp_cpu_index_default(); 1259 1260 /* 1261 * Setup boot CPU information 1262 */ 1263 smp_store_boot_cpu_info(); /* Final full version of the data */ 1264 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1265 mb(); 1266 1267 for_each_possible_cpu(i) { 1268 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1269 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1270 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1271 } 1272 1273 /* 1274 * Set 'default' x86 topology, this matches default_topology() in that 1275 * it has NUMA nodes as a topology level. See also 1276 * native_smp_cpus_done(). 1277 * 1278 * Must be done before set_cpus_sibling_map() is ran. 1279 */ 1280 set_sched_topology(x86_topology); 1281 1282 set_cpu_sibling_map(0); 1283 1284 smp_sanity_check(); 1285 1286 switch (apic_intr_mode) { 1287 case APIC_PIC: 1288 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1289 disable_smp(); 1290 return; 1291 case APIC_SYMMETRIC_IO_NO_ROUTING: 1292 disable_smp(); 1293 /* Setup local timer */ 1294 x86_init.timers.setup_percpu_clockev(); 1295 return; 1296 case APIC_VIRTUAL_WIRE: 1297 case APIC_SYMMETRIC_IO: 1298 break; 1299 } 1300 1301 /* Setup local timer */ 1302 x86_init.timers.setup_percpu_clockev(); 1303 1304 smp_get_logical_apicid(); 1305 1306 pr_info("CPU0: "); 1307 print_cpu_info(&cpu_data(0)); 1308 1309 native_pv_lock_init(); 1310 1311 uv_system_init(); 1312 1313 set_mtrr_aps_delayed_init(); 1314 1315 smp_quirk_init_udelay(); 1316 1317 speculative_store_bypass_ht_init(); 1318 } 1319 1320 void arch_enable_nonboot_cpus_begin(void) 1321 { 1322 set_mtrr_aps_delayed_init(); 1323 } 1324 1325 void arch_enable_nonboot_cpus_end(void) 1326 { 1327 mtrr_aps_init(); 1328 } 1329 1330 /* 1331 * Early setup to make printk work. 1332 */ 1333 void __init native_smp_prepare_boot_cpu(void) 1334 { 1335 int me = smp_processor_id(); 1336 switch_to_new_gdt(me); 1337 /* already set me in cpu_online_mask in boot_cpu_init() */ 1338 cpumask_set_cpu(me, cpu_callout_mask); 1339 cpu_set_state_online(me); 1340 } 1341 1342 void __init calculate_max_logical_packages(void) 1343 { 1344 int ncpus; 1345 1346 /* 1347 * Today neither Intel nor AMD support heterogenous systems so 1348 * extrapolate the boot cpu's data to all packages. 1349 */ 1350 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1351 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1352 pr_info("Max logical packages: %u\n", __max_logical_packages); 1353 } 1354 1355 void __init native_smp_cpus_done(unsigned int max_cpus) 1356 { 1357 pr_debug("Boot done\n"); 1358 1359 calculate_max_logical_packages(); 1360 1361 if (x86_has_numa_in_package) 1362 set_sched_topology(x86_numa_in_package_topology); 1363 1364 nmi_selftest(); 1365 impress_friends(); 1366 mtrr_aps_init(); 1367 } 1368 1369 static int __initdata setup_possible_cpus = -1; 1370 static int __init _setup_possible_cpus(char *str) 1371 { 1372 get_option(&str, &setup_possible_cpus); 1373 return 0; 1374 } 1375 early_param("possible_cpus", _setup_possible_cpus); 1376 1377 1378 /* 1379 * cpu_possible_mask should be static, it cannot change as cpu's 1380 * are onlined, or offlined. The reason is per-cpu data-structures 1381 * are allocated by some modules at init time, and dont expect to 1382 * do this dynamically on cpu arrival/departure. 1383 * cpu_present_mask on the other hand can change dynamically. 1384 * In case when cpu_hotplug is not compiled, then we resort to current 1385 * behaviour, which is cpu_possible == cpu_present. 1386 * - Ashok Raj 1387 * 1388 * Three ways to find out the number of additional hotplug CPUs: 1389 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1390 * - The user can overwrite it with possible_cpus=NUM 1391 * - Otherwise don't reserve additional CPUs. 1392 * We do this because additional CPUs waste a lot of memory. 1393 * -AK 1394 */ 1395 __init void prefill_possible_map(void) 1396 { 1397 int i, possible; 1398 1399 /* No boot processor was found in mptable or ACPI MADT */ 1400 if (!num_processors) { 1401 if (boot_cpu_has(X86_FEATURE_APIC)) { 1402 int apicid = boot_cpu_physical_apicid; 1403 int cpu = hard_smp_processor_id(); 1404 1405 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1406 1407 /* Make sure boot cpu is enumerated */ 1408 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1409 apic->apic_id_valid(apicid)) 1410 generic_processor_info(apicid, boot_cpu_apic_version); 1411 } 1412 1413 if (!num_processors) 1414 num_processors = 1; 1415 } 1416 1417 i = setup_max_cpus ?: 1; 1418 if (setup_possible_cpus == -1) { 1419 possible = num_processors; 1420 #ifdef CONFIG_HOTPLUG_CPU 1421 if (setup_max_cpus) 1422 possible += disabled_cpus; 1423 #else 1424 if (possible > i) 1425 possible = i; 1426 #endif 1427 } else 1428 possible = setup_possible_cpus; 1429 1430 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1431 1432 /* nr_cpu_ids could be reduced via nr_cpus= */ 1433 if (possible > nr_cpu_ids) { 1434 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1435 possible, nr_cpu_ids); 1436 possible = nr_cpu_ids; 1437 } 1438 1439 #ifdef CONFIG_HOTPLUG_CPU 1440 if (!setup_max_cpus) 1441 #endif 1442 if (possible > i) { 1443 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1444 possible, setup_max_cpus); 1445 possible = i; 1446 } 1447 1448 nr_cpu_ids = possible; 1449 1450 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1451 possible, max_t(int, possible - num_processors, 0)); 1452 1453 reset_cpu_possible_mask(); 1454 1455 for (i = 0; i < possible; i++) 1456 set_cpu_possible(i, true); 1457 } 1458 1459 #ifdef CONFIG_HOTPLUG_CPU 1460 1461 /* Recompute SMT state for all CPUs on offline */ 1462 static void recompute_smt_state(void) 1463 { 1464 int max_threads, cpu; 1465 1466 max_threads = 0; 1467 for_each_online_cpu (cpu) { 1468 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1469 1470 if (threads > max_threads) 1471 max_threads = threads; 1472 } 1473 __max_smt_threads = max_threads; 1474 } 1475 1476 static void remove_siblinginfo(int cpu) 1477 { 1478 int sibling; 1479 struct cpuinfo_x86 *c = &cpu_data(cpu); 1480 1481 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1482 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1483 /*/ 1484 * last thread sibling in this cpu core going down 1485 */ 1486 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1487 cpu_data(sibling).booted_cores--; 1488 } 1489 1490 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1491 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1492 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1493 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1494 cpumask_clear(cpu_llc_shared_mask(cpu)); 1495 cpumask_clear(topology_sibling_cpumask(cpu)); 1496 cpumask_clear(topology_core_cpumask(cpu)); 1497 c->cpu_core_id = 0; 1498 c->booted_cores = 0; 1499 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1500 recompute_smt_state(); 1501 } 1502 1503 static void remove_cpu_from_maps(int cpu) 1504 { 1505 set_cpu_online(cpu, false); 1506 cpumask_clear_cpu(cpu, cpu_callout_mask); 1507 cpumask_clear_cpu(cpu, cpu_callin_mask); 1508 /* was set by cpu_init() */ 1509 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1510 numa_remove_cpu(cpu); 1511 } 1512 1513 void cpu_disable_common(void) 1514 { 1515 int cpu = smp_processor_id(); 1516 1517 remove_siblinginfo(cpu); 1518 1519 /* It's now safe to remove this processor from the online map */ 1520 lock_vector_lock(); 1521 remove_cpu_from_maps(cpu); 1522 unlock_vector_lock(); 1523 fixup_irqs(); 1524 lapic_offline(); 1525 } 1526 1527 int native_cpu_disable(void) 1528 { 1529 int ret; 1530 1531 ret = lapic_can_unplug_cpu(); 1532 if (ret) 1533 return ret; 1534 1535 clear_local_APIC(); 1536 cpu_disable_common(); 1537 1538 return 0; 1539 } 1540 1541 int common_cpu_die(unsigned int cpu) 1542 { 1543 int ret = 0; 1544 1545 /* We don't do anything here: idle task is faking death itself. */ 1546 1547 /* They ack this in play_dead() by setting CPU_DEAD */ 1548 if (cpu_wait_death(cpu, 5)) { 1549 if (system_state == SYSTEM_RUNNING) 1550 pr_info("CPU %u is now offline\n", cpu); 1551 } else { 1552 pr_err("CPU %u didn't die...\n", cpu); 1553 ret = -1; 1554 } 1555 1556 return ret; 1557 } 1558 1559 void native_cpu_die(unsigned int cpu) 1560 { 1561 common_cpu_die(cpu); 1562 } 1563 1564 void play_dead_common(void) 1565 { 1566 idle_task_exit(); 1567 1568 /* Ack it */ 1569 (void)cpu_report_death(); 1570 1571 /* 1572 * With physical CPU hotplug, we should halt the cpu 1573 */ 1574 local_irq_disable(); 1575 } 1576 1577 static bool wakeup_cpu0(void) 1578 { 1579 if (smp_processor_id() == 0 && enable_start_cpu0) 1580 return true; 1581 1582 return false; 1583 } 1584 1585 /* 1586 * We need to flush the caches before going to sleep, lest we have 1587 * dirty data in our caches when we come back up. 1588 */ 1589 static inline void mwait_play_dead(void) 1590 { 1591 unsigned int eax, ebx, ecx, edx; 1592 unsigned int highest_cstate = 0; 1593 unsigned int highest_subcstate = 0; 1594 void *mwait_ptr; 1595 int i; 1596 1597 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1598 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1599 return; 1600 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1601 return; 1602 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1603 return; 1604 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1605 return; 1606 1607 eax = CPUID_MWAIT_LEAF; 1608 ecx = 0; 1609 native_cpuid(&eax, &ebx, &ecx, &edx); 1610 1611 /* 1612 * eax will be 0 if EDX enumeration is not valid. 1613 * Initialized below to cstate, sub_cstate value when EDX is valid. 1614 */ 1615 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1616 eax = 0; 1617 } else { 1618 edx >>= MWAIT_SUBSTATE_SIZE; 1619 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1620 if (edx & MWAIT_SUBSTATE_MASK) { 1621 highest_cstate = i; 1622 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1623 } 1624 } 1625 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1626 (highest_subcstate - 1); 1627 } 1628 1629 /* 1630 * This should be a memory location in a cache line which is 1631 * unlikely to be touched by other processors. The actual 1632 * content is immaterial as it is not actually modified in any way. 1633 */ 1634 mwait_ptr = ¤t_thread_info()->flags; 1635 1636 wbinvd(); 1637 1638 while (1) { 1639 /* 1640 * The CLFLUSH is a workaround for erratum AAI65 for 1641 * the Xeon 7400 series. It's not clear it is actually 1642 * needed, but it should be harmless in either case. 1643 * The WBINVD is insufficient due to the spurious-wakeup 1644 * case where we return around the loop. 1645 */ 1646 mb(); 1647 clflush(mwait_ptr); 1648 mb(); 1649 __monitor(mwait_ptr, 0, 0); 1650 mb(); 1651 __mwait(eax, 0); 1652 /* 1653 * If NMI wants to wake up CPU0, start CPU0. 1654 */ 1655 if (wakeup_cpu0()) 1656 start_cpu0(); 1657 } 1658 } 1659 1660 void hlt_play_dead(void) 1661 { 1662 if (__this_cpu_read(cpu_info.x86) >= 4) 1663 wbinvd(); 1664 1665 while (1) { 1666 native_halt(); 1667 /* 1668 * If NMI wants to wake up CPU0, start CPU0. 1669 */ 1670 if (wakeup_cpu0()) 1671 start_cpu0(); 1672 } 1673 } 1674 1675 void native_play_dead(void) 1676 { 1677 play_dead_common(); 1678 tboot_shutdown(TB_SHUTDOWN_WFS); 1679 1680 mwait_play_dead(); /* Only returns on failure */ 1681 if (cpuidle_play_dead()) 1682 hlt_play_dead(); 1683 } 1684 1685 #else /* ... !CONFIG_HOTPLUG_CPU */ 1686 int native_cpu_disable(void) 1687 { 1688 return -ENOSYS; 1689 } 1690 1691 void native_cpu_die(unsigned int cpu) 1692 { 1693 /* We said "no" in __cpu_disable */ 1694 BUG(); 1695 } 1696 1697 void native_play_dead(void) 1698 { 1699 BUG(); 1700 } 1701 1702 #endif 1703