1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com> 5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 51 #include <asm/acpi.h> 52 #include <asm/desc.h> 53 #include <asm/nmi.h> 54 #include <asm/irq.h> 55 #include <asm/idle.h> 56 #include <asm/smp.h> 57 #include <asm/trampoline.h> 58 #include <asm/cpu.h> 59 #include <asm/numa.h> 60 #include <asm/pgtable.h> 61 #include <asm/tlbflush.h> 62 #include <asm/mtrr.h> 63 #include <asm/vmi.h> 64 #include <asm/genapic.h> 65 #include <linux/mc146818rtc.h> 66 67 #include <mach_apic.h> 68 #include <mach_wakecpu.h> 69 #include <smpboot_hooks.h> 70 71 #ifdef CONFIG_X86_32 72 u8 apicid_2_node[MAX_APICID]; 73 static int low_mappings; 74 #endif 75 76 /* State of each CPU */ 77 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 78 79 /* Store all idle threads, this can be reused instead of creating 80 * a new thread. Also avoids complicated thread destroy functionality 81 * for idle threads. 82 */ 83 #ifdef CONFIG_HOTPLUG_CPU 84 /* 85 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 86 * removed after init for !CONFIG_HOTPLUG_CPU. 87 */ 88 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 89 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 90 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 91 #else 92 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 93 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 94 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 95 #endif 96 97 /* Number of siblings per CPU package */ 98 int smp_num_siblings = 1; 99 EXPORT_SYMBOL(smp_num_siblings); 100 101 /* Last level cache ID of each logical CPU */ 102 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 103 104 /* bitmap of online cpus */ 105 cpumask_t cpu_online_map __read_mostly; 106 EXPORT_SYMBOL(cpu_online_map); 107 108 cpumask_t cpu_callin_map; 109 cpumask_t cpu_callout_map; 110 cpumask_t cpu_possible_map; 111 EXPORT_SYMBOL(cpu_possible_map); 112 113 /* representing HT siblings of each logical CPU */ 114 DEFINE_PER_CPU(cpumask_t, cpu_sibling_map); 115 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 116 117 /* representing HT and core siblings of each logical CPU */ 118 DEFINE_PER_CPU(cpumask_t, cpu_core_map); 119 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 120 121 /* Per CPU bogomips and other parameters */ 122 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 123 EXPORT_PER_CPU_SYMBOL(cpu_info); 124 125 static atomic_t init_deasserted; 126 127 128 /* representing cpus for which sibling maps can be computed */ 129 static cpumask_t cpu_sibling_setup_map; 130 131 /* Set if we find a B stepping CPU */ 132 static int __cpuinitdata smp_b_stepping; 133 134 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_32) 135 136 /* which logical CPUs are on which nodes */ 137 cpumask_t node_to_cpumask_map[MAX_NUMNODES] __read_mostly = 138 { [0 ... MAX_NUMNODES-1] = CPU_MASK_NONE }; 139 EXPORT_SYMBOL(node_to_cpumask_map); 140 /* which node each logical CPU is on */ 141 int cpu_to_node_map[NR_CPUS] __read_mostly = { [0 ... NR_CPUS-1] = 0 }; 142 EXPORT_SYMBOL(cpu_to_node_map); 143 144 /* set up a mapping between cpu and node. */ 145 static void map_cpu_to_node(int cpu, int node) 146 { 147 printk(KERN_INFO "Mapping cpu %d to node %d\n", cpu, node); 148 cpu_set(cpu, node_to_cpumask_map[node]); 149 cpu_to_node_map[cpu] = node; 150 } 151 152 /* undo a mapping between cpu and node. */ 153 static void unmap_cpu_to_node(int cpu) 154 { 155 int node; 156 157 printk(KERN_INFO "Unmapping cpu %d from all nodes\n", cpu); 158 for (node = 0; node < MAX_NUMNODES; node++) 159 cpu_clear(cpu, node_to_cpumask_map[node]); 160 cpu_to_node_map[cpu] = 0; 161 } 162 #else /* !(CONFIG_NUMA && CONFIG_X86_32) */ 163 #define map_cpu_to_node(cpu, node) ({}) 164 #define unmap_cpu_to_node(cpu) ({}) 165 #endif 166 167 #ifdef CONFIG_X86_32 168 static int boot_cpu_logical_apicid; 169 170 u8 cpu_2_logical_apicid[NR_CPUS] __read_mostly = 171 { [0 ... NR_CPUS-1] = BAD_APICID }; 172 173 static void map_cpu_to_logical_apicid(void) 174 { 175 int cpu = smp_processor_id(); 176 int apicid = logical_smp_processor_id(); 177 int node = apicid_to_node(apicid); 178 179 if (!node_online(node)) 180 node = first_online_node; 181 182 cpu_2_logical_apicid[cpu] = apicid; 183 map_cpu_to_node(cpu, node); 184 } 185 186 void numa_remove_cpu(int cpu) 187 { 188 cpu_2_logical_apicid[cpu] = BAD_APICID; 189 unmap_cpu_to_node(cpu); 190 } 191 #else 192 #define map_cpu_to_logical_apicid() do {} while (0) 193 #endif 194 195 /* 196 * Report back to the Boot Processor. 197 * Running on AP. 198 */ 199 static void __cpuinit smp_callin(void) 200 { 201 int cpuid, phys_id; 202 unsigned long timeout; 203 204 /* 205 * If waken up by an INIT in an 82489DX configuration 206 * we may get here before an INIT-deassert IPI reaches 207 * our local APIC. We have to wait for the IPI or we'll 208 * lock up on an APIC access. 209 */ 210 wait_for_init_deassert(&init_deasserted); 211 212 /* 213 * (This works even if the APIC is not enabled.) 214 */ 215 phys_id = read_apic_id(); 216 cpuid = smp_processor_id(); 217 if (cpu_isset(cpuid, cpu_callin_map)) { 218 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 219 phys_id, cpuid); 220 } 221 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 222 223 /* 224 * STARTUP IPIs are fragile beasts as they might sometimes 225 * trigger some glue motherboard logic. Complete APIC bus 226 * silence for 1 second, this overestimates the time the 227 * boot CPU is spending to send the up to 2 STARTUP IPIs 228 * by a factor of two. This should be enough. 229 */ 230 231 /* 232 * Waiting 2s total for startup (udelay is not yet working) 233 */ 234 timeout = jiffies + 2*HZ; 235 while (time_before(jiffies, timeout)) { 236 /* 237 * Has the boot CPU finished it's STARTUP sequence? 238 */ 239 if (cpu_isset(cpuid, cpu_callout_map)) 240 break; 241 cpu_relax(); 242 } 243 244 if (!time_before(jiffies, timeout)) { 245 panic("%s: CPU%d started up but did not get a callout!\n", 246 __func__, cpuid); 247 } 248 249 /* 250 * the boot CPU has finished the init stage and is spinning 251 * on callin_map until we finish. We are free to set up this 252 * CPU, first the APIC. (this is probably redundant on most 253 * boards) 254 */ 255 256 pr_debug("CALLIN, before setup_local_APIC().\n"); 257 smp_callin_clear_local_apic(); 258 setup_local_APIC(); 259 end_local_APIC_setup(); 260 map_cpu_to_logical_apicid(); 261 262 notify_cpu_starting(cpuid); 263 /* 264 * Get our bogomips. 265 * 266 * Need to enable IRQs because it can take longer and then 267 * the NMI watchdog might kill us. 268 */ 269 local_irq_enable(); 270 calibrate_delay(); 271 local_irq_disable(); 272 pr_debug("Stack at about %p\n", &cpuid); 273 274 /* 275 * Save our processor parameters 276 */ 277 smp_store_cpu_info(cpuid); 278 279 /* 280 * Allow the master to continue. 281 */ 282 cpu_set(cpuid, cpu_callin_map); 283 } 284 285 static int __cpuinitdata unsafe_smp; 286 287 /* 288 * Activate a secondary processor. 289 */ 290 static void __cpuinit start_secondary(void *unused) 291 { 292 /* 293 * Don't put *anything* before cpu_init(), SMP booting is too 294 * fragile that we want to limit the things done here to the 295 * most necessary things. 296 */ 297 #ifdef CONFIG_VMI 298 vmi_bringup(); 299 #endif 300 cpu_init(); 301 preempt_disable(); 302 smp_callin(); 303 304 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 305 barrier(); 306 /* 307 * Check TSC synchronization with the BP: 308 */ 309 check_tsc_sync_target(); 310 311 if (nmi_watchdog == NMI_IO_APIC) { 312 disable_8259A_irq(0); 313 enable_NMI_through_LVT0(); 314 enable_8259A_irq(0); 315 } 316 317 #ifdef CONFIG_X86_32 318 while (low_mappings) 319 cpu_relax(); 320 __flush_tlb_all(); 321 #endif 322 323 /* This must be done before setting cpu_online_map */ 324 set_cpu_sibling_map(raw_smp_processor_id()); 325 wmb(); 326 327 /* 328 * We need to hold call_lock, so there is no inconsistency 329 * between the time smp_call_function() determines number of 330 * IPI recipients, and the time when the determination is made 331 * for which cpus receive the IPI. Holding this 332 * lock helps us to not include this cpu in a currently in progress 333 * smp_call_function(). 334 * 335 * We need to hold vector_lock so there the set of online cpus 336 * does not change while we are assigning vectors to cpus. Holding 337 * this lock ensures we don't half assign or remove an irq from a cpu. 338 */ 339 ipi_call_lock(); 340 lock_vector_lock(); 341 __setup_vector_irq(smp_processor_id()); 342 cpu_set(smp_processor_id(), cpu_online_map); 343 unlock_vector_lock(); 344 ipi_call_unlock(); 345 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 346 347 /* enable local interrupts */ 348 local_irq_enable(); 349 350 setup_secondary_clock(); 351 352 wmb(); 353 cpu_idle(); 354 } 355 356 static void __cpuinit smp_apply_quirks(struct cpuinfo_x86 *c) 357 { 358 /* 359 * Mask B, Pentium, but not Pentium MMX 360 */ 361 if (c->x86_vendor == X86_VENDOR_INTEL && 362 c->x86 == 5 && 363 c->x86_mask >= 1 && c->x86_mask <= 4 && 364 c->x86_model <= 3) 365 /* 366 * Remember we have B step Pentia with bugs 367 */ 368 smp_b_stepping = 1; 369 370 /* 371 * Certain Athlons might work (for various values of 'work') in SMP 372 * but they are not certified as MP capable. 373 */ 374 if ((c->x86_vendor == X86_VENDOR_AMD) && (c->x86 == 6)) { 375 376 if (num_possible_cpus() == 1) 377 goto valid_k7; 378 379 /* Athlon 660/661 is valid. */ 380 if ((c->x86_model == 6) && ((c->x86_mask == 0) || 381 (c->x86_mask == 1))) 382 goto valid_k7; 383 384 /* Duron 670 is valid */ 385 if ((c->x86_model == 7) && (c->x86_mask == 0)) 386 goto valid_k7; 387 388 /* 389 * Athlon 662, Duron 671, and Athlon >model 7 have capability 390 * bit. It's worth noting that the A5 stepping (662) of some 391 * Athlon XP's have the MP bit set. 392 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for 393 * more. 394 */ 395 if (((c->x86_model == 6) && (c->x86_mask >= 2)) || 396 ((c->x86_model == 7) && (c->x86_mask >= 1)) || 397 (c->x86_model > 7)) 398 if (cpu_has_mp) 399 goto valid_k7; 400 401 /* If we get here, not a certified SMP capable AMD system. */ 402 unsafe_smp = 1; 403 } 404 405 valid_k7: 406 ; 407 } 408 409 static void __cpuinit smp_checks(void) 410 { 411 if (smp_b_stepping) 412 printk(KERN_WARNING "WARNING: SMP operation may be unreliable" 413 "with B stepping processors.\n"); 414 415 /* 416 * Don't taint if we are running SMP kernel on a single non-MP 417 * approved Athlon 418 */ 419 if (unsafe_smp && num_online_cpus() > 1) { 420 printk(KERN_INFO "WARNING: This combination of AMD" 421 "processors is not suitable for SMP.\n"); 422 add_taint(TAINT_UNSAFE_SMP); 423 } 424 } 425 426 /* 427 * The bootstrap kernel entry code has set these up. Save them for 428 * a given CPU 429 */ 430 431 void __cpuinit smp_store_cpu_info(int id) 432 { 433 struct cpuinfo_x86 *c = &cpu_data(id); 434 435 *c = boot_cpu_data; 436 c->cpu_index = id; 437 if (id != 0) 438 identify_secondary_cpu(c); 439 smp_apply_quirks(c); 440 } 441 442 443 void __cpuinit set_cpu_sibling_map(int cpu) 444 { 445 int i; 446 struct cpuinfo_x86 *c = &cpu_data(cpu); 447 448 cpu_set(cpu, cpu_sibling_setup_map); 449 450 if (smp_num_siblings > 1) { 451 for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { 452 if (c->phys_proc_id == cpu_data(i).phys_proc_id && 453 c->cpu_core_id == cpu_data(i).cpu_core_id) { 454 cpu_set(i, per_cpu(cpu_sibling_map, cpu)); 455 cpu_set(cpu, per_cpu(cpu_sibling_map, i)); 456 cpu_set(i, per_cpu(cpu_core_map, cpu)); 457 cpu_set(cpu, per_cpu(cpu_core_map, i)); 458 cpu_set(i, c->llc_shared_map); 459 cpu_set(cpu, cpu_data(i).llc_shared_map); 460 } 461 } 462 } else { 463 cpu_set(cpu, per_cpu(cpu_sibling_map, cpu)); 464 } 465 466 cpu_set(cpu, c->llc_shared_map); 467 468 if (current_cpu_data.x86_max_cores == 1) { 469 per_cpu(cpu_core_map, cpu) = per_cpu(cpu_sibling_map, cpu); 470 c->booted_cores = 1; 471 return; 472 } 473 474 for_each_cpu_mask_nr(i, cpu_sibling_setup_map) { 475 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 476 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 477 cpu_set(i, c->llc_shared_map); 478 cpu_set(cpu, cpu_data(i).llc_shared_map); 479 } 480 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 481 cpu_set(i, per_cpu(cpu_core_map, cpu)); 482 cpu_set(cpu, per_cpu(cpu_core_map, i)); 483 /* 484 * Does this new cpu bringup a new core? 485 */ 486 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) { 487 /* 488 * for each core in package, increment 489 * the booted_cores for this new cpu 490 */ 491 if (first_cpu(per_cpu(cpu_sibling_map, i)) == i) 492 c->booted_cores++; 493 /* 494 * increment the core count for all 495 * the other cpus in this package 496 */ 497 if (i != cpu) 498 cpu_data(i).booted_cores++; 499 } else if (i != cpu && !c->booted_cores) 500 c->booted_cores = cpu_data(i).booted_cores; 501 } 502 } 503 } 504 505 /* maps the cpu to the sched domain representing multi-core */ 506 cpumask_t cpu_coregroup_map(int cpu) 507 { 508 struct cpuinfo_x86 *c = &cpu_data(cpu); 509 /* 510 * For perf, we return last level cache shared map. 511 * And for power savings, we return cpu_core_map 512 */ 513 if (sched_mc_power_savings || sched_smt_power_savings) 514 return per_cpu(cpu_core_map, cpu); 515 else 516 return c->llc_shared_map; 517 } 518 519 static void impress_friends(void) 520 { 521 int cpu; 522 unsigned long bogosum = 0; 523 /* 524 * Allow the user to impress friends. 525 */ 526 pr_debug("Before bogomips.\n"); 527 for_each_possible_cpu(cpu) 528 if (cpu_isset(cpu, cpu_callout_map)) 529 bogosum += cpu_data(cpu).loops_per_jiffy; 530 printk(KERN_INFO 531 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 532 num_online_cpus(), 533 bogosum/(500000/HZ), 534 (bogosum/(5000/HZ))%100); 535 536 pr_debug("Before bogocount - setting activated=1.\n"); 537 } 538 539 static inline void __inquire_remote_apic(int apicid) 540 { 541 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 542 char *names[] = { "ID", "VERSION", "SPIV" }; 543 int timeout; 544 u32 status; 545 546 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 547 548 for (i = 0; i < ARRAY_SIZE(regs); i++) { 549 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 550 551 /* 552 * Wait for idle. 553 */ 554 status = safe_apic_wait_icr_idle(); 555 if (status) 556 printk(KERN_CONT 557 "a previous APIC delivery may have failed\n"); 558 559 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 560 561 timeout = 0; 562 do { 563 udelay(100); 564 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 565 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 566 567 switch (status) { 568 case APIC_ICR_RR_VALID: 569 status = apic_read(APIC_RRR); 570 printk(KERN_CONT "%08x\n", status); 571 break; 572 default: 573 printk(KERN_CONT "failed\n"); 574 } 575 } 576 } 577 578 #ifdef WAKE_SECONDARY_VIA_NMI 579 /* 580 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 581 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 582 * won't ... remember to clear down the APIC, etc later. 583 */ 584 static int __devinit 585 wakeup_secondary_cpu(int logical_apicid, unsigned long start_eip) 586 { 587 unsigned long send_status, accept_status = 0; 588 int maxlvt; 589 590 /* Target chip */ 591 /* Boot on the stack */ 592 /* Kick the second */ 593 apic_icr_write(APIC_DM_NMI | APIC_DEST_LOGICAL, logical_apicid); 594 595 pr_debug("Waiting for send to finish...\n"); 596 send_status = safe_apic_wait_icr_idle(); 597 598 /* 599 * Give the other CPU some time to accept the IPI. 600 */ 601 udelay(200); 602 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 603 maxlvt = lapic_get_maxlvt(); 604 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 605 apic_write(APIC_ESR, 0); 606 accept_status = (apic_read(APIC_ESR) & 0xEF); 607 } 608 pr_debug("NMI sent.\n"); 609 610 if (send_status) 611 printk(KERN_ERR "APIC never delivered???\n"); 612 if (accept_status) 613 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 614 615 return (send_status | accept_status); 616 } 617 #endif /* WAKE_SECONDARY_VIA_NMI */ 618 619 #ifdef WAKE_SECONDARY_VIA_INIT 620 static int __devinit 621 wakeup_secondary_cpu(int phys_apicid, unsigned long start_eip) 622 { 623 unsigned long send_status, accept_status = 0; 624 int maxlvt, num_starts, j; 625 626 if (get_uv_system_type() == UV_NON_UNIQUE_APIC) { 627 send_status = uv_wakeup_secondary(phys_apicid, start_eip); 628 atomic_set(&init_deasserted, 1); 629 return send_status; 630 } 631 632 maxlvt = lapic_get_maxlvt(); 633 634 /* 635 * Be paranoid about clearing APIC errors. 636 */ 637 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 638 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 639 apic_write(APIC_ESR, 0); 640 apic_read(APIC_ESR); 641 } 642 643 pr_debug("Asserting INIT.\n"); 644 645 /* 646 * Turn INIT on target chip 647 */ 648 /* 649 * Send IPI 650 */ 651 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 652 phys_apicid); 653 654 pr_debug("Waiting for send to finish...\n"); 655 send_status = safe_apic_wait_icr_idle(); 656 657 mdelay(10); 658 659 pr_debug("Deasserting INIT.\n"); 660 661 /* Target chip */ 662 /* Send IPI */ 663 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 664 665 pr_debug("Waiting for send to finish...\n"); 666 send_status = safe_apic_wait_icr_idle(); 667 668 mb(); 669 atomic_set(&init_deasserted, 1); 670 671 /* 672 * Should we send STARTUP IPIs ? 673 * 674 * Determine this based on the APIC version. 675 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 676 */ 677 if (APIC_INTEGRATED(apic_version[phys_apicid])) 678 num_starts = 2; 679 else 680 num_starts = 0; 681 682 /* 683 * Paravirt / VMI wants a startup IPI hook here to set up the 684 * target processor state. 685 */ 686 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 687 (unsigned long)stack_start.sp); 688 689 /* 690 * Run STARTUP IPI loop. 691 */ 692 pr_debug("#startup loops: %d.\n", num_starts); 693 694 for (j = 1; j <= num_starts; j++) { 695 pr_debug("Sending STARTUP #%d.\n", j); 696 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 697 apic_write(APIC_ESR, 0); 698 apic_read(APIC_ESR); 699 pr_debug("After apic_write.\n"); 700 701 /* 702 * STARTUP IPI 703 */ 704 705 /* Target chip */ 706 /* Boot on the stack */ 707 /* Kick the second */ 708 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 709 phys_apicid); 710 711 /* 712 * Give the other CPU some time to accept the IPI. 713 */ 714 udelay(300); 715 716 pr_debug("Startup point 1.\n"); 717 718 pr_debug("Waiting for send to finish...\n"); 719 send_status = safe_apic_wait_icr_idle(); 720 721 /* 722 * Give the other CPU some time to accept the IPI. 723 */ 724 udelay(200); 725 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 726 apic_write(APIC_ESR, 0); 727 accept_status = (apic_read(APIC_ESR) & 0xEF); 728 if (send_status || accept_status) 729 break; 730 } 731 pr_debug("After Startup.\n"); 732 733 if (send_status) 734 printk(KERN_ERR "APIC never delivered???\n"); 735 if (accept_status) 736 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 737 738 return (send_status | accept_status); 739 } 740 #endif /* WAKE_SECONDARY_VIA_INIT */ 741 742 struct create_idle { 743 struct work_struct work; 744 struct task_struct *idle; 745 struct completion done; 746 int cpu; 747 }; 748 749 static void __cpuinit do_fork_idle(struct work_struct *work) 750 { 751 struct create_idle *c_idle = 752 container_of(work, struct create_idle, work); 753 754 c_idle->idle = fork_idle(c_idle->cpu); 755 complete(&c_idle->done); 756 } 757 758 #ifdef CONFIG_X86_64 759 760 /* __ref because it's safe to call free_bootmem when after_bootmem == 0. */ 761 static void __ref free_bootmem_pda(struct x8664_pda *oldpda) 762 { 763 if (!after_bootmem) 764 free_bootmem((unsigned long)oldpda, sizeof(*oldpda)); 765 } 766 767 /* 768 * Allocate node local memory for the AP pda. 769 * 770 * Must be called after the _cpu_pda pointer table is initialized. 771 */ 772 int __cpuinit get_local_pda(int cpu) 773 { 774 struct x8664_pda *oldpda, *newpda; 775 unsigned long size = sizeof(struct x8664_pda); 776 int node = cpu_to_node(cpu); 777 778 if (cpu_pda(cpu) && !cpu_pda(cpu)->in_bootmem) 779 return 0; 780 781 oldpda = cpu_pda(cpu); 782 newpda = kmalloc_node(size, GFP_ATOMIC, node); 783 if (!newpda) { 784 printk(KERN_ERR "Could not allocate node local PDA " 785 "for CPU %d on node %d\n", cpu, node); 786 787 if (oldpda) 788 return 0; /* have a usable pda */ 789 else 790 return -1; 791 } 792 793 if (oldpda) { 794 memcpy(newpda, oldpda, size); 795 free_bootmem_pda(oldpda); 796 } 797 798 newpda->in_bootmem = 0; 799 cpu_pda(cpu) = newpda; 800 return 0; 801 } 802 #endif /* CONFIG_X86_64 */ 803 804 static int __cpuinit do_boot_cpu(int apicid, int cpu) 805 /* 806 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 807 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 808 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu. 809 */ 810 { 811 unsigned long boot_error = 0; 812 int timeout; 813 unsigned long start_ip; 814 unsigned short nmi_high = 0, nmi_low = 0; 815 struct create_idle c_idle = { 816 .cpu = cpu, 817 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 818 }; 819 INIT_WORK(&c_idle.work, do_fork_idle); 820 821 #ifdef CONFIG_X86_64 822 /* Allocate node local memory for AP pdas */ 823 if (cpu > 0) { 824 boot_error = get_local_pda(cpu); 825 if (boot_error) 826 goto restore_state; 827 /* if can't get pda memory, can't start cpu */ 828 } 829 #endif 830 831 alternatives_smp_switch(1); 832 833 c_idle.idle = get_idle_for_cpu(cpu); 834 835 /* 836 * We can't use kernel_thread since we must avoid to 837 * reschedule the child. 838 */ 839 if (c_idle.idle) { 840 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 841 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 842 init_idle(c_idle.idle, cpu); 843 goto do_rest; 844 } 845 846 if (!keventd_up() || current_is_keventd()) 847 c_idle.work.func(&c_idle.work); 848 else { 849 schedule_work(&c_idle.work); 850 wait_for_completion(&c_idle.done); 851 } 852 853 if (IS_ERR(c_idle.idle)) { 854 printk("failed fork for CPU %d\n", cpu); 855 return PTR_ERR(c_idle.idle); 856 } 857 858 set_idle_for_cpu(cpu, c_idle.idle); 859 do_rest: 860 #ifdef CONFIG_X86_32 861 per_cpu(current_task, cpu) = c_idle.idle; 862 init_gdt(cpu); 863 /* Stack for startup_32 can be just as for start_secondary onwards */ 864 irq_ctx_init(cpu); 865 #else 866 cpu_pda(cpu)->pcurrent = c_idle.idle; 867 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 868 #endif 869 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 870 initial_code = (unsigned long)start_secondary; 871 stack_start.sp = (void *) c_idle.idle->thread.sp; 872 873 /* start_ip had better be page-aligned! */ 874 start_ip = setup_trampoline(); 875 876 /* So we see what's up */ 877 printk(KERN_INFO "Booting processor %d APIC 0x%x ip 0x%lx\n", 878 cpu, apicid, start_ip); 879 880 /* 881 * This grunge runs the startup process for 882 * the targeted processor. 883 */ 884 885 atomic_set(&init_deasserted, 0); 886 887 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 888 889 pr_debug("Setting warm reset code and vector.\n"); 890 891 store_NMI_vector(&nmi_high, &nmi_low); 892 893 smpboot_setup_warm_reset_vector(start_ip); 894 /* 895 * Be paranoid about clearing APIC errors. 896 */ 897 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 898 apic_write(APIC_ESR, 0); 899 apic_read(APIC_ESR); 900 } 901 } 902 903 /* 904 * Starting actual IPI sequence... 905 */ 906 boot_error = wakeup_secondary_cpu(apicid, start_ip); 907 908 if (!boot_error) { 909 /* 910 * allow APs to start initializing. 911 */ 912 pr_debug("Before Callout %d.\n", cpu); 913 cpu_set(cpu, cpu_callout_map); 914 pr_debug("After Callout %d.\n", cpu); 915 916 /* 917 * Wait 5s total for a response 918 */ 919 for (timeout = 0; timeout < 50000; timeout++) { 920 if (cpu_isset(cpu, cpu_callin_map)) 921 break; /* It has booted */ 922 udelay(100); 923 } 924 925 if (cpu_isset(cpu, cpu_callin_map)) { 926 /* number CPUs logically, starting from 1 (BSP is 0) */ 927 pr_debug("OK.\n"); 928 printk(KERN_INFO "CPU%d: ", cpu); 929 print_cpu_info(&cpu_data(cpu)); 930 pr_debug("CPU has booted.\n"); 931 } else { 932 boot_error = 1; 933 if (*((volatile unsigned char *)trampoline_base) 934 == 0xA5) 935 /* trampoline started but...? */ 936 printk(KERN_ERR "Stuck ??\n"); 937 else 938 /* trampoline code not run */ 939 printk(KERN_ERR "Not responding.\n"); 940 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) 941 inquire_remote_apic(apicid); 942 } 943 } 944 #ifdef CONFIG_X86_64 945 restore_state: 946 #endif 947 if (boot_error) { 948 /* Try to put things back the way they were before ... */ 949 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 950 cpu_clear(cpu, cpu_callout_map); /* was set by do_boot_cpu() */ 951 cpu_clear(cpu, cpu_initialized); /* was set by cpu_init() */ 952 cpu_clear(cpu, cpu_present_map); 953 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 954 } 955 956 /* mark "stuck" area as not stuck */ 957 *((volatile unsigned long *)trampoline_base) = 0; 958 959 /* 960 * Cleanup possible dangling ends... 961 */ 962 smpboot_restore_warm_reset_vector(); 963 964 return boot_error; 965 } 966 967 int __cpuinit native_cpu_up(unsigned int cpu) 968 { 969 int apicid = cpu_present_to_apicid(cpu); 970 unsigned long flags; 971 int err; 972 973 WARN_ON(irqs_disabled()); 974 975 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 976 977 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 978 !physid_isset(apicid, phys_cpu_present_map)) { 979 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 980 return -EINVAL; 981 } 982 983 /* 984 * Already booted CPU? 985 */ 986 if (cpu_isset(cpu, cpu_callin_map)) { 987 pr_debug("do_boot_cpu %d Already started\n", cpu); 988 return -ENOSYS; 989 } 990 991 /* 992 * Save current MTRR state in case it was changed since early boot 993 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 994 */ 995 mtrr_save_state(); 996 997 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 998 999 #ifdef CONFIG_X86_32 1000 /* init low mem mapping */ 1001 clone_pgd_range(swapper_pg_dir, swapper_pg_dir + KERNEL_PGD_BOUNDARY, 1002 min_t(unsigned long, KERNEL_PGD_PTRS, KERNEL_PGD_BOUNDARY)); 1003 flush_tlb_all(); 1004 low_mappings = 1; 1005 1006 err = do_boot_cpu(apicid, cpu); 1007 1008 zap_low_mappings(); 1009 low_mappings = 0; 1010 #else 1011 err = do_boot_cpu(apicid, cpu); 1012 #endif 1013 if (err) { 1014 pr_debug("do_boot_cpu failed %d\n", err); 1015 return -EIO; 1016 } 1017 1018 /* 1019 * Check TSC synchronization with the AP (keep irqs disabled 1020 * while doing so): 1021 */ 1022 local_irq_save(flags); 1023 check_tsc_sync_source(cpu); 1024 local_irq_restore(flags); 1025 1026 while (!cpu_online(cpu)) { 1027 cpu_relax(); 1028 touch_nmi_watchdog(); 1029 } 1030 1031 return 0; 1032 } 1033 1034 /* 1035 * Fall back to non SMP mode after errors. 1036 * 1037 * RED-PEN audit/test this more. I bet there is more state messed up here. 1038 */ 1039 static __init void disable_smp(void) 1040 { 1041 cpu_present_map = cpumask_of_cpu(0); 1042 cpu_possible_map = cpumask_of_cpu(0); 1043 smpboot_clear_io_apic_irqs(); 1044 1045 if (smp_found_config) 1046 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1047 else 1048 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1049 map_cpu_to_logical_apicid(); 1050 cpu_set(0, per_cpu(cpu_sibling_map, 0)); 1051 cpu_set(0, per_cpu(cpu_core_map, 0)); 1052 } 1053 1054 /* 1055 * Various sanity checks. 1056 */ 1057 static int __init smp_sanity_check(unsigned max_cpus) 1058 { 1059 preempt_disable(); 1060 1061 #if defined(CONFIG_X86_PC) && defined(CONFIG_X86_32) 1062 if (def_to_bigsmp && nr_cpu_ids > 8) { 1063 unsigned int cpu; 1064 unsigned nr; 1065 1066 printk(KERN_WARNING 1067 "More than 8 CPUs detected - skipping them.\n" 1068 "Use CONFIG_X86_GENERICARCH and CONFIG_X86_BIGSMP.\n"); 1069 1070 nr = 0; 1071 for_each_present_cpu(cpu) { 1072 if (nr >= 8) 1073 cpu_clear(cpu, cpu_present_map); 1074 nr++; 1075 } 1076 1077 nr = 0; 1078 for_each_possible_cpu(cpu) { 1079 if (nr >= 8) 1080 cpu_clear(cpu, cpu_possible_map); 1081 nr++; 1082 } 1083 1084 nr_cpu_ids = 8; 1085 } 1086 #endif 1087 1088 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1089 printk(KERN_WARNING "weird, boot CPU (#%d) not listed" 1090 "by the BIOS.\n", hard_smp_processor_id()); 1091 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1092 } 1093 1094 /* 1095 * If we couldn't find an SMP configuration at boot time, 1096 * get out of here now! 1097 */ 1098 if (!smp_found_config && !acpi_lapic) { 1099 preempt_enable(); 1100 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 1101 disable_smp(); 1102 if (APIC_init_uniprocessor()) 1103 printk(KERN_NOTICE "Local APIC not detected." 1104 " Using dummy APIC emulation.\n"); 1105 return -1; 1106 } 1107 1108 /* 1109 * Should not be necessary because the MP table should list the boot 1110 * CPU too, but we do it for the sake of robustness anyway. 1111 */ 1112 if (!check_phys_apicid_present(boot_cpu_physical_apicid)) { 1113 printk(KERN_NOTICE 1114 "weird, boot CPU (#%d) not listed by the BIOS.\n", 1115 boot_cpu_physical_apicid); 1116 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1117 } 1118 preempt_enable(); 1119 1120 /* 1121 * If we couldn't find a local APIC, then get out of here now! 1122 */ 1123 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1124 !cpu_has_apic) { 1125 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n", 1126 boot_cpu_physical_apicid); 1127 printk(KERN_ERR "... forcing use of dummy APIC emulation." 1128 "(tell your hw vendor)\n"); 1129 smpboot_clear_io_apic(); 1130 return -1; 1131 } 1132 1133 verify_local_APIC(); 1134 1135 /* 1136 * If SMP should be disabled, then really disable it! 1137 */ 1138 if (!max_cpus) { 1139 printk(KERN_INFO "SMP mode deactivated.\n"); 1140 smpboot_clear_io_apic(); 1141 1142 localise_nmi_watchdog(); 1143 1144 connect_bsp_APIC(); 1145 setup_local_APIC(); 1146 end_local_APIC_setup(); 1147 return -1; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static void __init smp_cpu_index_default(void) 1154 { 1155 int i; 1156 struct cpuinfo_x86 *c; 1157 1158 for_each_possible_cpu(i) { 1159 c = &cpu_data(i); 1160 /* mark all to hotplug */ 1161 c->cpu_index = NR_CPUS; 1162 } 1163 } 1164 1165 /* 1166 * Prepare for SMP bootup. The MP table or ACPI has been read 1167 * earlier. Just do some sanity checking here and enable APIC mode. 1168 */ 1169 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1170 { 1171 preempt_disable(); 1172 smp_cpu_index_default(); 1173 current_cpu_data = boot_cpu_data; 1174 cpu_callin_map = cpumask_of_cpu(0); 1175 mb(); 1176 /* 1177 * Setup boot CPU information 1178 */ 1179 smp_store_cpu_info(0); /* Final full version of the data */ 1180 #ifdef CONFIG_X86_32 1181 boot_cpu_logical_apicid = logical_smp_processor_id(); 1182 #endif 1183 current_thread_info()->cpu = 0; /* needed? */ 1184 set_cpu_sibling_map(0); 1185 1186 #ifdef CONFIG_X86_64 1187 enable_IR_x2apic(); 1188 setup_apic_routing(); 1189 #endif 1190 1191 if (smp_sanity_check(max_cpus) < 0) { 1192 printk(KERN_INFO "SMP disabled\n"); 1193 disable_smp(); 1194 goto out; 1195 } 1196 1197 preempt_disable(); 1198 if (read_apic_id() != boot_cpu_physical_apicid) { 1199 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1200 read_apic_id(), boot_cpu_physical_apicid); 1201 /* Or can we switch back to PIC here? */ 1202 } 1203 preempt_enable(); 1204 1205 connect_bsp_APIC(); 1206 1207 /* 1208 * Switch from PIC to APIC mode. 1209 */ 1210 setup_local_APIC(); 1211 1212 #ifdef CONFIG_X86_64 1213 /* 1214 * Enable IO APIC before setting up error vector 1215 */ 1216 if (!skip_ioapic_setup && nr_ioapics) 1217 enable_IO_APIC(); 1218 #endif 1219 end_local_APIC_setup(); 1220 1221 map_cpu_to_logical_apicid(); 1222 1223 setup_portio_remap(); 1224 1225 smpboot_setup_io_apic(); 1226 /* 1227 * Set up local APIC timer on boot CPU. 1228 */ 1229 1230 printk(KERN_INFO "CPU%d: ", 0); 1231 print_cpu_info(&cpu_data(0)); 1232 setup_boot_clock(); 1233 1234 if (is_uv_system()) 1235 uv_system_init(); 1236 out: 1237 preempt_enable(); 1238 } 1239 /* 1240 * Early setup to make printk work. 1241 */ 1242 void __init native_smp_prepare_boot_cpu(void) 1243 { 1244 int me = smp_processor_id(); 1245 #ifdef CONFIG_X86_32 1246 init_gdt(me); 1247 #endif 1248 switch_to_new_gdt(); 1249 /* already set me in cpu_online_map in boot_cpu_init() */ 1250 cpu_set(me, cpu_callout_map); 1251 per_cpu(cpu_state, me) = CPU_ONLINE; 1252 } 1253 1254 void __init native_smp_cpus_done(unsigned int max_cpus) 1255 { 1256 pr_debug("Boot done.\n"); 1257 1258 impress_friends(); 1259 smp_checks(); 1260 #ifdef CONFIG_X86_IO_APIC 1261 setup_ioapic_dest(); 1262 #endif 1263 check_nmi_watchdog(); 1264 } 1265 1266 /* 1267 * cpu_possible_map should be static, it cannot change as cpu's 1268 * are onlined, or offlined. The reason is per-cpu data-structures 1269 * are allocated by some modules at init time, and dont expect to 1270 * do this dynamically on cpu arrival/departure. 1271 * cpu_present_map on the other hand can change dynamically. 1272 * In case when cpu_hotplug is not compiled, then we resort to current 1273 * behaviour, which is cpu_possible == cpu_present. 1274 * - Ashok Raj 1275 * 1276 * Three ways to find out the number of additional hotplug CPUs: 1277 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1278 * - The user can overwrite it with additional_cpus=NUM 1279 * - Otherwise don't reserve additional CPUs. 1280 * We do this because additional CPUs waste a lot of memory. 1281 * -AK 1282 */ 1283 __init void prefill_possible_map(void) 1284 { 1285 int i, possible; 1286 1287 /* no processor from mptable or madt */ 1288 if (!num_processors) 1289 num_processors = 1; 1290 1291 possible = num_processors + disabled_cpus; 1292 if (possible > NR_CPUS) 1293 possible = NR_CPUS; 1294 1295 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1296 possible, max_t(int, possible - num_processors, 0)); 1297 1298 for (i = 0; i < possible; i++) 1299 cpu_set(i, cpu_possible_map); 1300 1301 nr_cpu_ids = possible; 1302 } 1303 1304 #ifdef CONFIG_HOTPLUG_CPU 1305 1306 static void remove_siblinginfo(int cpu) 1307 { 1308 int sibling; 1309 struct cpuinfo_x86 *c = &cpu_data(cpu); 1310 1311 for_each_cpu_mask_nr(sibling, per_cpu(cpu_core_map, cpu)) { 1312 cpu_clear(cpu, per_cpu(cpu_core_map, sibling)); 1313 /*/ 1314 * last thread sibling in this cpu core going down 1315 */ 1316 if (cpus_weight(per_cpu(cpu_sibling_map, cpu)) == 1) 1317 cpu_data(sibling).booted_cores--; 1318 } 1319 1320 for_each_cpu_mask_nr(sibling, per_cpu(cpu_sibling_map, cpu)) 1321 cpu_clear(cpu, per_cpu(cpu_sibling_map, sibling)); 1322 cpus_clear(per_cpu(cpu_sibling_map, cpu)); 1323 cpus_clear(per_cpu(cpu_core_map, cpu)); 1324 c->phys_proc_id = 0; 1325 c->cpu_core_id = 0; 1326 cpu_clear(cpu, cpu_sibling_setup_map); 1327 } 1328 1329 static void __ref remove_cpu_from_maps(int cpu) 1330 { 1331 cpu_clear(cpu, cpu_online_map); 1332 cpu_clear(cpu, cpu_callout_map); 1333 cpu_clear(cpu, cpu_callin_map); 1334 /* was set by cpu_init() */ 1335 cpu_clear(cpu, cpu_initialized); 1336 numa_remove_cpu(cpu); 1337 } 1338 1339 void cpu_disable_common(void) 1340 { 1341 int cpu = smp_processor_id(); 1342 /* 1343 * HACK: 1344 * Allow any queued timer interrupts to get serviced 1345 * This is only a temporary solution until we cleanup 1346 * fixup_irqs as we do for IA64. 1347 */ 1348 local_irq_enable(); 1349 mdelay(1); 1350 1351 local_irq_disable(); 1352 remove_siblinginfo(cpu); 1353 1354 /* It's now safe to remove this processor from the online map */ 1355 lock_vector_lock(); 1356 remove_cpu_from_maps(cpu); 1357 unlock_vector_lock(); 1358 fixup_irqs(cpu_online_map); 1359 } 1360 1361 int native_cpu_disable(void) 1362 { 1363 int cpu = smp_processor_id(); 1364 1365 /* 1366 * Perhaps use cpufreq to drop frequency, but that could go 1367 * into generic code. 1368 * 1369 * We won't take down the boot processor on i386 due to some 1370 * interrupts only being able to be serviced by the BSP. 1371 * Especially so if we're not using an IOAPIC -zwane 1372 */ 1373 if (cpu == 0) 1374 return -EBUSY; 1375 1376 if (nmi_watchdog == NMI_LOCAL_APIC) 1377 stop_apic_nmi_watchdog(NULL); 1378 clear_local_APIC(); 1379 1380 cpu_disable_common(); 1381 return 0; 1382 } 1383 1384 void native_cpu_die(unsigned int cpu) 1385 { 1386 /* We don't do anything here: idle task is faking death itself. */ 1387 unsigned int i; 1388 1389 for (i = 0; i < 10; i++) { 1390 /* They ack this in play_dead by setting CPU_DEAD */ 1391 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1392 printk(KERN_INFO "CPU %d is now offline\n", cpu); 1393 if (1 == num_online_cpus()) 1394 alternatives_smp_switch(0); 1395 return; 1396 } 1397 msleep(100); 1398 } 1399 printk(KERN_ERR "CPU %u didn't die...\n", cpu); 1400 } 1401 1402 void play_dead_common(void) 1403 { 1404 idle_task_exit(); 1405 reset_lazy_tlbstate(); 1406 irq_ctx_exit(raw_smp_processor_id()); 1407 c1e_remove_cpu(raw_smp_processor_id()); 1408 1409 mb(); 1410 /* Ack it */ 1411 __get_cpu_var(cpu_state) = CPU_DEAD; 1412 1413 /* 1414 * With physical CPU hotplug, we should halt the cpu 1415 */ 1416 local_irq_disable(); 1417 } 1418 1419 void native_play_dead(void) 1420 { 1421 play_dead_common(); 1422 wbinvd_halt(); 1423 } 1424 1425 #else /* ... !CONFIG_HOTPLUG_CPU */ 1426 int native_cpu_disable(void) 1427 { 1428 return -ENOSYS; 1429 } 1430 1431 void native_cpu_die(unsigned int cpu) 1432 { 1433 /* We said "no" in __cpu_disable */ 1434 BUG(); 1435 } 1436 1437 void native_play_dead(void) 1438 { 1439 BUG(); 1440 } 1441 1442 #endif 1443