1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/i387.h> 72 #include <asm/fpu-internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 #include <asm/smpboot_hooks.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 81 /* State of each CPU */ 82 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 83 84 /* Number of siblings per CPU package */ 85 int smp_num_siblings = 1; 86 EXPORT_SYMBOL(smp_num_siblings); 87 88 /* Last level cache ID of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 100 101 /* Per CPU bogomips and other parameters */ 102 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 103 EXPORT_PER_CPU_SYMBOL(cpu_info); 104 105 atomic_t init_deasserted; 106 107 /* 108 * Report back to the Boot Processor during boot time or to the caller processor 109 * during CPU online. 110 */ 111 static void smp_callin(void) 112 { 113 int cpuid, phys_id; 114 115 /* 116 * If waken up by an INIT in an 82489DX configuration 117 * we may get here before an INIT-deassert IPI reaches 118 * our local APIC. We have to wait for the IPI or we'll 119 * lock up on an APIC access. 120 * 121 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. 122 */ 123 cpuid = smp_processor_id(); 124 if (apic->wait_for_init_deassert && cpuid) 125 while (!atomic_read(&init_deasserted)) 126 cpu_relax(); 127 128 /* 129 * (This works even if the APIC is not enabled.) 130 */ 131 phys_id = read_apic_id(); 132 133 /* 134 * the boot CPU has finished the init stage and is spinning 135 * on callin_map until we finish. We are free to set up this 136 * CPU, first the APIC. (this is probably redundant on most 137 * boards) 138 */ 139 setup_local_APIC(); 140 end_local_APIC_setup(); 141 142 /* 143 * Need to setup vector mappings before we enable interrupts. 144 */ 145 setup_vector_irq(smp_processor_id()); 146 147 /* 148 * Save our processor parameters. Note: this information 149 * is needed for clock calibration. 150 */ 151 smp_store_cpu_info(cpuid); 152 153 /* 154 * Get our bogomips. 155 * Update loops_per_jiffy in cpu_data. Previous call to 156 * smp_store_cpu_info() stored a value that is close but not as 157 * accurate as the value just calculated. 158 */ 159 calibrate_delay(); 160 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 161 pr_debug("Stack at about %p\n", &cpuid); 162 163 /* 164 * This must be done before setting cpu_online_mask 165 * or calling notify_cpu_starting. 166 */ 167 set_cpu_sibling_map(raw_smp_processor_id()); 168 wmb(); 169 170 notify_cpu_starting(cpuid); 171 172 /* 173 * Allow the master to continue. 174 */ 175 cpumask_set_cpu(cpuid, cpu_callin_mask); 176 } 177 178 static int cpu0_logical_apicid; 179 static int enable_start_cpu0; 180 /* 181 * Activate a secondary processor. 182 */ 183 static void notrace start_secondary(void *unused) 184 { 185 /* 186 * Don't put *anything* before cpu_init(), SMP booting is too 187 * fragile that we want to limit the things done here to the 188 * most necessary things. 189 */ 190 cpu_init(); 191 x86_cpuinit.early_percpu_clock_init(); 192 preempt_disable(); 193 smp_callin(); 194 195 enable_start_cpu0 = 0; 196 197 #ifdef CONFIG_X86_32 198 /* switch away from the initial page table */ 199 load_cr3(swapper_pg_dir); 200 __flush_tlb_all(); 201 #endif 202 203 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 204 barrier(); 205 /* 206 * Check TSC synchronization with the BP: 207 */ 208 check_tsc_sync_target(); 209 210 /* 211 * Enable the espfix hack for this CPU 212 */ 213 #ifdef CONFIG_X86_ESPFIX64 214 init_espfix_ap(); 215 #endif 216 217 /* 218 * We need to hold vector_lock so there the set of online cpus 219 * does not change while we are assigning vectors to cpus. Holding 220 * this lock ensures we don't half assign or remove an irq from a cpu. 221 */ 222 lock_vector_lock(); 223 set_cpu_online(smp_processor_id(), true); 224 unlock_vector_lock(); 225 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 226 x86_platform.nmi_init(); 227 228 /* enable local interrupts */ 229 local_irq_enable(); 230 231 /* to prevent fake stack check failure in clock setup */ 232 boot_init_stack_canary(); 233 234 x86_cpuinit.setup_percpu_clockev(); 235 236 wmb(); 237 cpu_startup_entry(CPUHP_ONLINE); 238 } 239 240 void __init smp_store_boot_cpu_info(void) 241 { 242 int id = 0; /* CPU 0 */ 243 struct cpuinfo_x86 *c = &cpu_data(id); 244 245 *c = boot_cpu_data; 246 c->cpu_index = id; 247 } 248 249 /* 250 * The bootstrap kernel entry code has set these up. Save them for 251 * a given CPU 252 */ 253 void smp_store_cpu_info(int id) 254 { 255 struct cpuinfo_x86 *c = &cpu_data(id); 256 257 *c = boot_cpu_data; 258 c->cpu_index = id; 259 /* 260 * During boot time, CPU0 has this setup already. Save the info when 261 * bringing up AP or offlined CPU0. 262 */ 263 identify_secondary_cpu(c); 264 } 265 266 static bool 267 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 268 { 269 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 270 271 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 272 } 273 274 static bool 275 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 276 { 277 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 278 279 return !WARN_ONCE(!topology_same_node(c, o), 280 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 281 "[node: %d != %d]. Ignoring dependency.\n", 282 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 283 } 284 285 #define link_mask(_m, c1, c2) \ 286 do { \ 287 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 288 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 289 } while (0) 290 291 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 292 { 293 if (cpu_has_topoext) { 294 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 295 296 if (c->phys_proc_id == o->phys_proc_id && 297 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 298 c->compute_unit_id == o->compute_unit_id) 299 return topology_sane(c, o, "smt"); 300 301 } else if (c->phys_proc_id == o->phys_proc_id && 302 c->cpu_core_id == o->cpu_core_id) { 303 return topology_sane(c, o, "smt"); 304 } 305 306 return false; 307 } 308 309 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 310 { 311 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 312 313 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 314 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 315 return topology_sane(c, o, "llc"); 316 317 return false; 318 } 319 320 /* 321 * Unlike the other levels, we do not enforce keeping a 322 * multicore group inside a NUMA node. If this happens, we will 323 * discard the MC level of the topology later. 324 */ 325 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 326 { 327 if (c->phys_proc_id == o->phys_proc_id) 328 return true; 329 return false; 330 } 331 332 static struct sched_domain_topology_level numa_inside_package_topology[] = { 333 #ifdef CONFIG_SCHED_SMT 334 { cpu_smt_mask, cpu_smt_flags, SD_INIT_NAME(SMT) }, 335 #endif 336 #ifdef CONFIG_SCHED_MC 337 { cpu_coregroup_mask, cpu_core_flags, SD_INIT_NAME(MC) }, 338 #endif 339 { NULL, }, 340 }; 341 /* 342 * set_sched_topology() sets the topology internal to a CPU. The 343 * NUMA topologies are layered on top of it to build the full 344 * system topology. 345 * 346 * If NUMA nodes are observed to occur within a CPU package, this 347 * function should be called. It forces the sched domain code to 348 * only use the SMT level for the CPU portion of the topology. 349 * This essentially falls back to relying on NUMA information 350 * from the SRAT table to describe the entire system topology 351 * (except for hyperthreads). 352 */ 353 static void primarily_use_numa_for_topology(void) 354 { 355 set_sched_topology(numa_inside_package_topology); 356 } 357 358 void set_cpu_sibling_map(int cpu) 359 { 360 bool has_smt = smp_num_siblings > 1; 361 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 362 struct cpuinfo_x86 *c = &cpu_data(cpu); 363 struct cpuinfo_x86 *o; 364 int i; 365 366 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 367 368 if (!has_mp) { 369 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 370 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 371 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 372 c->booted_cores = 1; 373 return; 374 } 375 376 for_each_cpu(i, cpu_sibling_setup_mask) { 377 o = &cpu_data(i); 378 379 if ((i == cpu) || (has_smt && match_smt(c, o))) 380 link_mask(sibling, cpu, i); 381 382 if ((i == cpu) || (has_mp && match_llc(c, o))) 383 link_mask(llc_shared, cpu, i); 384 385 } 386 387 /* 388 * This needs a separate iteration over the cpus because we rely on all 389 * cpu_sibling_mask links to be set-up. 390 */ 391 for_each_cpu(i, cpu_sibling_setup_mask) { 392 o = &cpu_data(i); 393 394 if ((i == cpu) || (has_mp && match_die(c, o))) { 395 link_mask(core, cpu, i); 396 397 /* 398 * Does this new cpu bringup a new core? 399 */ 400 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 401 /* 402 * for each core in package, increment 403 * the booted_cores for this new cpu 404 */ 405 if (cpumask_first(cpu_sibling_mask(i)) == i) 406 c->booted_cores++; 407 /* 408 * increment the core count for all 409 * the other cpus in this package 410 */ 411 if (i != cpu) 412 cpu_data(i).booted_cores++; 413 } else if (i != cpu && !c->booted_cores) 414 c->booted_cores = cpu_data(i).booted_cores; 415 } 416 if (match_die(c, o) && !topology_same_node(c, o)) 417 primarily_use_numa_for_topology(); 418 } 419 } 420 421 /* maps the cpu to the sched domain representing multi-core */ 422 const struct cpumask *cpu_coregroup_mask(int cpu) 423 { 424 return cpu_llc_shared_mask(cpu); 425 } 426 427 static void impress_friends(void) 428 { 429 int cpu; 430 unsigned long bogosum = 0; 431 /* 432 * Allow the user to impress friends. 433 */ 434 pr_debug("Before bogomips\n"); 435 for_each_possible_cpu(cpu) 436 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 437 bogosum += cpu_data(cpu).loops_per_jiffy; 438 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 439 num_online_cpus(), 440 bogosum/(500000/HZ), 441 (bogosum/(5000/HZ))%100); 442 443 pr_debug("Before bogocount - setting activated=1\n"); 444 } 445 446 void __inquire_remote_apic(int apicid) 447 { 448 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 449 const char * const names[] = { "ID", "VERSION", "SPIV" }; 450 int timeout; 451 u32 status; 452 453 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 454 455 for (i = 0; i < ARRAY_SIZE(regs); i++) { 456 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 457 458 /* 459 * Wait for idle. 460 */ 461 status = safe_apic_wait_icr_idle(); 462 if (status) 463 pr_cont("a previous APIC delivery may have failed\n"); 464 465 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 466 467 timeout = 0; 468 do { 469 udelay(100); 470 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 471 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 472 473 switch (status) { 474 case APIC_ICR_RR_VALID: 475 status = apic_read(APIC_RRR); 476 pr_cont("%08x\n", status); 477 break; 478 default: 479 pr_cont("failed\n"); 480 } 481 } 482 } 483 484 /* 485 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 486 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 487 * won't ... remember to clear down the APIC, etc later. 488 */ 489 int 490 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 491 { 492 unsigned long send_status, accept_status = 0; 493 int maxlvt; 494 495 /* Target chip */ 496 /* Boot on the stack */ 497 /* Kick the second */ 498 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 499 500 pr_debug("Waiting for send to finish...\n"); 501 send_status = safe_apic_wait_icr_idle(); 502 503 /* 504 * Give the other CPU some time to accept the IPI. 505 */ 506 udelay(200); 507 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 508 maxlvt = lapic_get_maxlvt(); 509 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 510 apic_write(APIC_ESR, 0); 511 accept_status = (apic_read(APIC_ESR) & 0xEF); 512 } 513 pr_debug("NMI sent\n"); 514 515 if (send_status) 516 pr_err("APIC never delivered???\n"); 517 if (accept_status) 518 pr_err("APIC delivery error (%lx)\n", accept_status); 519 520 return (send_status | accept_status); 521 } 522 523 static int 524 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 525 { 526 unsigned long send_status, accept_status = 0; 527 int maxlvt, num_starts, j; 528 529 maxlvt = lapic_get_maxlvt(); 530 531 /* 532 * Be paranoid about clearing APIC errors. 533 */ 534 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 535 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 536 apic_write(APIC_ESR, 0); 537 apic_read(APIC_ESR); 538 } 539 540 pr_debug("Asserting INIT\n"); 541 542 /* 543 * Turn INIT on target chip 544 */ 545 /* 546 * Send IPI 547 */ 548 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 549 phys_apicid); 550 551 pr_debug("Waiting for send to finish...\n"); 552 send_status = safe_apic_wait_icr_idle(); 553 554 mdelay(10); 555 556 pr_debug("Deasserting INIT\n"); 557 558 /* Target chip */ 559 /* Send IPI */ 560 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 561 562 pr_debug("Waiting for send to finish...\n"); 563 send_status = safe_apic_wait_icr_idle(); 564 565 mb(); 566 atomic_set(&init_deasserted, 1); 567 568 /* 569 * Should we send STARTUP IPIs ? 570 * 571 * Determine this based on the APIC version. 572 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 573 */ 574 if (APIC_INTEGRATED(apic_version[phys_apicid])) 575 num_starts = 2; 576 else 577 num_starts = 0; 578 579 /* 580 * Paravirt / VMI wants a startup IPI hook here to set up the 581 * target processor state. 582 */ 583 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 584 stack_start); 585 586 /* 587 * Run STARTUP IPI loop. 588 */ 589 pr_debug("#startup loops: %d\n", num_starts); 590 591 for (j = 1; j <= num_starts; j++) { 592 pr_debug("Sending STARTUP #%d\n", j); 593 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 594 apic_write(APIC_ESR, 0); 595 apic_read(APIC_ESR); 596 pr_debug("After apic_write\n"); 597 598 /* 599 * STARTUP IPI 600 */ 601 602 /* Target chip */ 603 /* Boot on the stack */ 604 /* Kick the second */ 605 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 606 phys_apicid); 607 608 /* 609 * Give the other CPU some time to accept the IPI. 610 */ 611 udelay(300); 612 613 pr_debug("Startup point 1\n"); 614 615 pr_debug("Waiting for send to finish...\n"); 616 send_status = safe_apic_wait_icr_idle(); 617 618 /* 619 * Give the other CPU some time to accept the IPI. 620 */ 621 udelay(200); 622 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 623 apic_write(APIC_ESR, 0); 624 accept_status = (apic_read(APIC_ESR) & 0xEF); 625 if (send_status || accept_status) 626 break; 627 } 628 pr_debug("After Startup\n"); 629 630 if (send_status) 631 pr_err("APIC never delivered???\n"); 632 if (accept_status) 633 pr_err("APIC delivery error (%lx)\n", accept_status); 634 635 return (send_status | accept_status); 636 } 637 638 void smp_announce(void) 639 { 640 int num_nodes = num_online_nodes(); 641 642 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 643 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 644 } 645 646 /* reduce the number of lines printed when booting a large cpu count system */ 647 static void announce_cpu(int cpu, int apicid) 648 { 649 static int current_node = -1; 650 int node = early_cpu_to_node(cpu); 651 static int width, node_width; 652 653 if (!width) 654 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 655 656 if (!node_width) 657 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 658 659 if (cpu == 1) 660 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 661 662 if (system_state == SYSTEM_BOOTING) { 663 if (node != current_node) { 664 if (current_node > (-1)) 665 pr_cont("\n"); 666 current_node = node; 667 668 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 669 node_width - num_digits(node), " ", node); 670 } 671 672 /* Add padding for the BSP */ 673 if (cpu == 1) 674 pr_cont("%*s", width + 1, " "); 675 676 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 677 678 } else 679 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 680 node, cpu, apicid); 681 } 682 683 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 684 { 685 int cpu; 686 687 cpu = smp_processor_id(); 688 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 689 return NMI_HANDLED; 690 691 return NMI_DONE; 692 } 693 694 /* 695 * Wake up AP by INIT, INIT, STARTUP sequence. 696 * 697 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 698 * boot-strap code which is not a desired behavior for waking up BSP. To 699 * void the boot-strap code, wake up CPU0 by NMI instead. 700 * 701 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 702 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 703 * We'll change this code in the future to wake up hard offlined CPU0 if 704 * real platform and request are available. 705 */ 706 static int 707 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 708 int *cpu0_nmi_registered) 709 { 710 int id; 711 int boot_error; 712 713 preempt_disable(); 714 715 /* 716 * Wake up AP by INIT, INIT, STARTUP sequence. 717 */ 718 if (cpu) { 719 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 720 goto out; 721 } 722 723 /* 724 * Wake up BSP by nmi. 725 * 726 * Register a NMI handler to help wake up CPU0. 727 */ 728 boot_error = register_nmi_handler(NMI_LOCAL, 729 wakeup_cpu0_nmi, 0, "wake_cpu0"); 730 731 if (!boot_error) { 732 enable_start_cpu0 = 1; 733 *cpu0_nmi_registered = 1; 734 if (apic->dest_logical == APIC_DEST_LOGICAL) 735 id = cpu0_logical_apicid; 736 else 737 id = apicid; 738 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 739 } 740 741 out: 742 preempt_enable(); 743 744 return boot_error; 745 } 746 747 /* 748 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 749 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 750 * Returns zero if CPU booted OK, else error code from 751 * ->wakeup_secondary_cpu. 752 */ 753 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 754 { 755 volatile u32 *trampoline_status = 756 (volatile u32 *) __va(real_mode_header->trampoline_status); 757 /* start_ip had better be page-aligned! */ 758 unsigned long start_ip = real_mode_header->trampoline_start; 759 760 unsigned long boot_error = 0; 761 int cpu0_nmi_registered = 0; 762 unsigned long timeout; 763 764 /* Just in case we booted with a single CPU. */ 765 alternatives_enable_smp(); 766 767 idle->thread.sp = (unsigned long) (((struct pt_regs *) 768 (THREAD_SIZE + task_stack_page(idle))) - 1); 769 per_cpu(current_task, cpu) = idle; 770 771 #ifdef CONFIG_X86_32 772 /* Stack for startup_32 can be just as for start_secondary onwards */ 773 irq_ctx_init(cpu); 774 #else 775 clear_tsk_thread_flag(idle, TIF_FORK); 776 initial_gs = per_cpu_offset(cpu); 777 #endif 778 per_cpu(kernel_stack, cpu) = 779 (unsigned long)task_stack_page(idle) - 780 KERNEL_STACK_OFFSET + THREAD_SIZE; 781 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 782 initial_code = (unsigned long)start_secondary; 783 stack_start = idle->thread.sp; 784 785 /* So we see what's up */ 786 announce_cpu(cpu, apicid); 787 788 /* 789 * This grunge runs the startup process for 790 * the targeted processor. 791 */ 792 793 atomic_set(&init_deasserted, 0); 794 795 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 796 797 pr_debug("Setting warm reset code and vector.\n"); 798 799 smpboot_setup_warm_reset_vector(start_ip); 800 /* 801 * Be paranoid about clearing APIC errors. 802 */ 803 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 804 apic_write(APIC_ESR, 0); 805 apic_read(APIC_ESR); 806 } 807 } 808 809 /* 810 * AP might wait on cpu_callout_mask in cpu_init() with 811 * cpu_initialized_mask set if previous attempt to online 812 * it timed-out. Clear cpu_initialized_mask so that after 813 * INIT/SIPI it could start with a clean state. 814 */ 815 cpumask_clear_cpu(cpu, cpu_initialized_mask); 816 smp_mb(); 817 818 /* 819 * Wake up a CPU in difference cases: 820 * - Use the method in the APIC driver if it's defined 821 * Otherwise, 822 * - Use an INIT boot APIC message for APs or NMI for BSP. 823 */ 824 if (apic->wakeup_secondary_cpu) 825 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 826 else 827 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 828 &cpu0_nmi_registered); 829 830 if (!boot_error) { 831 /* 832 * Wait 10s total for a response from AP 833 */ 834 boot_error = -1; 835 timeout = jiffies + 10*HZ; 836 while (time_before(jiffies, timeout)) { 837 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 838 /* 839 * Tell AP to proceed with initialization 840 */ 841 cpumask_set_cpu(cpu, cpu_callout_mask); 842 boot_error = 0; 843 break; 844 } 845 udelay(100); 846 schedule(); 847 } 848 } 849 850 if (!boot_error) { 851 /* 852 * Wait till AP completes initial initialization 853 */ 854 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 855 /* 856 * Allow other tasks to run while we wait for the 857 * AP to come online. This also gives a chance 858 * for the MTRR work(triggered by the AP coming online) 859 * to be completed in the stop machine context. 860 */ 861 udelay(100); 862 schedule(); 863 } 864 } 865 866 /* mark "stuck" area as not stuck */ 867 *trampoline_status = 0; 868 869 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 870 /* 871 * Cleanup possible dangling ends... 872 */ 873 smpboot_restore_warm_reset_vector(); 874 } 875 /* 876 * Clean up the nmi handler. Do this after the callin and callout sync 877 * to avoid impact of possible long unregister time. 878 */ 879 if (cpu0_nmi_registered) 880 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 881 882 return boot_error; 883 } 884 885 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 886 { 887 int apicid = apic->cpu_present_to_apicid(cpu); 888 unsigned long flags; 889 int err; 890 891 WARN_ON(irqs_disabled()); 892 893 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 894 895 if (apicid == BAD_APICID || 896 !physid_isset(apicid, phys_cpu_present_map) || 897 !apic->apic_id_valid(apicid)) { 898 pr_err("%s: bad cpu %d\n", __func__, cpu); 899 return -EINVAL; 900 } 901 902 /* 903 * Already booted CPU? 904 */ 905 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 906 pr_debug("do_boot_cpu %d Already started\n", cpu); 907 return -ENOSYS; 908 } 909 910 /* 911 * Save current MTRR state in case it was changed since early boot 912 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 913 */ 914 mtrr_save_state(); 915 916 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 917 918 /* the FPU context is blank, nobody can own it */ 919 __cpu_disable_lazy_restore(cpu); 920 921 err = do_boot_cpu(apicid, cpu, tidle); 922 if (err) { 923 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 924 return -EIO; 925 } 926 927 /* 928 * Check TSC synchronization with the AP (keep irqs disabled 929 * while doing so): 930 */ 931 local_irq_save(flags); 932 check_tsc_sync_source(cpu); 933 local_irq_restore(flags); 934 935 while (!cpu_online(cpu)) { 936 cpu_relax(); 937 touch_nmi_watchdog(); 938 } 939 940 return 0; 941 } 942 943 /** 944 * arch_disable_smp_support() - disables SMP support for x86 at runtime 945 */ 946 void arch_disable_smp_support(void) 947 { 948 disable_ioapic_support(); 949 } 950 951 /* 952 * Fall back to non SMP mode after errors. 953 * 954 * RED-PEN audit/test this more. I bet there is more state messed up here. 955 */ 956 static __init void disable_smp(void) 957 { 958 init_cpu_present(cpumask_of(0)); 959 init_cpu_possible(cpumask_of(0)); 960 smpboot_clear_io_apic_irqs(); 961 962 if (smp_found_config) 963 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 964 else 965 physid_set_mask_of_physid(0, &phys_cpu_present_map); 966 cpumask_set_cpu(0, cpu_sibling_mask(0)); 967 cpumask_set_cpu(0, cpu_core_mask(0)); 968 } 969 970 /* 971 * Various sanity checks. 972 */ 973 static int __init smp_sanity_check(unsigned max_cpus) 974 { 975 preempt_disable(); 976 977 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 978 if (def_to_bigsmp && nr_cpu_ids > 8) { 979 unsigned int cpu; 980 unsigned nr; 981 982 pr_warn("More than 8 CPUs detected - skipping them\n" 983 "Use CONFIG_X86_BIGSMP\n"); 984 985 nr = 0; 986 for_each_present_cpu(cpu) { 987 if (nr >= 8) 988 set_cpu_present(cpu, false); 989 nr++; 990 } 991 992 nr = 0; 993 for_each_possible_cpu(cpu) { 994 if (nr >= 8) 995 set_cpu_possible(cpu, false); 996 nr++; 997 } 998 999 nr_cpu_ids = 8; 1000 } 1001 #endif 1002 1003 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1004 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1005 hard_smp_processor_id()); 1006 1007 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1008 } 1009 1010 /* 1011 * If we couldn't find an SMP configuration at boot time, 1012 * get out of here now! 1013 */ 1014 if (!smp_found_config && !acpi_lapic) { 1015 preempt_enable(); 1016 pr_notice("SMP motherboard not detected\n"); 1017 disable_smp(); 1018 if (APIC_init_uniprocessor()) 1019 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1020 return -1; 1021 } 1022 1023 /* 1024 * Should not be necessary because the MP table should list the boot 1025 * CPU too, but we do it for the sake of robustness anyway. 1026 */ 1027 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1028 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1029 boot_cpu_physical_apicid); 1030 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1031 } 1032 preempt_enable(); 1033 1034 /* 1035 * If we couldn't find a local APIC, then get out of here now! 1036 */ 1037 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1038 !cpu_has_apic) { 1039 if (!disable_apic) { 1040 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1041 boot_cpu_physical_apicid); 1042 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1043 } 1044 smpboot_clear_io_apic(); 1045 disable_ioapic_support(); 1046 return -1; 1047 } 1048 1049 verify_local_APIC(); 1050 1051 /* 1052 * If SMP should be disabled, then really disable it! 1053 */ 1054 if (!max_cpus) { 1055 pr_info("SMP mode deactivated\n"); 1056 smpboot_clear_io_apic(); 1057 1058 connect_bsp_APIC(); 1059 setup_local_APIC(); 1060 bsp_end_local_APIC_setup(); 1061 return -1; 1062 } 1063 1064 return 0; 1065 } 1066 1067 static void __init smp_cpu_index_default(void) 1068 { 1069 int i; 1070 struct cpuinfo_x86 *c; 1071 1072 for_each_possible_cpu(i) { 1073 c = &cpu_data(i); 1074 /* mark all to hotplug */ 1075 c->cpu_index = nr_cpu_ids; 1076 } 1077 } 1078 1079 /* 1080 * Prepare for SMP bootup. The MP table or ACPI has been read 1081 * earlier. Just do some sanity checking here and enable APIC mode. 1082 */ 1083 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1084 { 1085 unsigned int i; 1086 1087 smp_cpu_index_default(); 1088 1089 /* 1090 * Setup boot CPU information 1091 */ 1092 smp_store_boot_cpu_info(); /* Final full version of the data */ 1093 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1094 mb(); 1095 1096 current_thread_info()->cpu = 0; /* needed? */ 1097 for_each_possible_cpu(i) { 1098 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1099 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1100 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1101 } 1102 set_cpu_sibling_map(0); 1103 1104 if (smp_sanity_check(max_cpus) < 0) { 1105 pr_info("SMP disabled\n"); 1106 disable_smp(); 1107 return; 1108 } 1109 1110 default_setup_apic_routing(); 1111 1112 if (read_apic_id() != boot_cpu_physical_apicid) { 1113 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1114 read_apic_id(), boot_cpu_physical_apicid); 1115 /* Or can we switch back to PIC here? */ 1116 } 1117 1118 connect_bsp_APIC(); 1119 1120 /* 1121 * Switch from PIC to APIC mode. 1122 */ 1123 setup_local_APIC(); 1124 1125 if (x2apic_mode) 1126 cpu0_logical_apicid = apic_read(APIC_LDR); 1127 else 1128 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1129 1130 /* 1131 * Enable IO APIC before setting up error vector 1132 */ 1133 if (!skip_ioapic_setup && nr_ioapics) 1134 enable_IO_APIC(); 1135 1136 bsp_end_local_APIC_setup(); 1137 smpboot_setup_io_apic(); 1138 /* 1139 * Set up local APIC timer on boot CPU. 1140 */ 1141 1142 pr_info("CPU%d: ", 0); 1143 print_cpu_info(&cpu_data(0)); 1144 x86_init.timers.setup_percpu_clockev(); 1145 1146 if (is_uv_system()) 1147 uv_system_init(); 1148 1149 set_mtrr_aps_delayed_init(); 1150 } 1151 1152 void arch_enable_nonboot_cpus_begin(void) 1153 { 1154 set_mtrr_aps_delayed_init(); 1155 } 1156 1157 void arch_enable_nonboot_cpus_end(void) 1158 { 1159 mtrr_aps_init(); 1160 } 1161 1162 /* 1163 * Early setup to make printk work. 1164 */ 1165 void __init native_smp_prepare_boot_cpu(void) 1166 { 1167 int me = smp_processor_id(); 1168 switch_to_new_gdt(me); 1169 /* already set me in cpu_online_mask in boot_cpu_init() */ 1170 cpumask_set_cpu(me, cpu_callout_mask); 1171 per_cpu(cpu_state, me) = CPU_ONLINE; 1172 } 1173 1174 void __init native_smp_cpus_done(unsigned int max_cpus) 1175 { 1176 pr_debug("Boot done\n"); 1177 1178 nmi_selftest(); 1179 impress_friends(); 1180 #ifdef CONFIG_X86_IO_APIC 1181 setup_ioapic_dest(); 1182 #endif 1183 mtrr_aps_init(); 1184 } 1185 1186 static int __initdata setup_possible_cpus = -1; 1187 static int __init _setup_possible_cpus(char *str) 1188 { 1189 get_option(&str, &setup_possible_cpus); 1190 return 0; 1191 } 1192 early_param("possible_cpus", _setup_possible_cpus); 1193 1194 1195 /* 1196 * cpu_possible_mask should be static, it cannot change as cpu's 1197 * are onlined, or offlined. The reason is per-cpu data-structures 1198 * are allocated by some modules at init time, and dont expect to 1199 * do this dynamically on cpu arrival/departure. 1200 * cpu_present_mask on the other hand can change dynamically. 1201 * In case when cpu_hotplug is not compiled, then we resort to current 1202 * behaviour, which is cpu_possible == cpu_present. 1203 * - Ashok Raj 1204 * 1205 * Three ways to find out the number of additional hotplug CPUs: 1206 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1207 * - The user can overwrite it with possible_cpus=NUM 1208 * - Otherwise don't reserve additional CPUs. 1209 * We do this because additional CPUs waste a lot of memory. 1210 * -AK 1211 */ 1212 __init void prefill_possible_map(void) 1213 { 1214 int i, possible; 1215 1216 /* no processor from mptable or madt */ 1217 if (!num_processors) 1218 num_processors = 1; 1219 1220 i = setup_max_cpus ?: 1; 1221 if (setup_possible_cpus == -1) { 1222 possible = num_processors; 1223 #ifdef CONFIG_HOTPLUG_CPU 1224 if (setup_max_cpus) 1225 possible += disabled_cpus; 1226 #else 1227 if (possible > i) 1228 possible = i; 1229 #endif 1230 } else 1231 possible = setup_possible_cpus; 1232 1233 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1234 1235 /* nr_cpu_ids could be reduced via nr_cpus= */ 1236 if (possible > nr_cpu_ids) { 1237 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1238 possible, nr_cpu_ids); 1239 possible = nr_cpu_ids; 1240 } 1241 1242 #ifdef CONFIG_HOTPLUG_CPU 1243 if (!setup_max_cpus) 1244 #endif 1245 if (possible > i) { 1246 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1247 possible, setup_max_cpus); 1248 possible = i; 1249 } 1250 1251 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1252 possible, max_t(int, possible - num_processors, 0)); 1253 1254 for (i = 0; i < possible; i++) 1255 set_cpu_possible(i, true); 1256 for (; i < NR_CPUS; i++) 1257 set_cpu_possible(i, false); 1258 1259 nr_cpu_ids = possible; 1260 } 1261 1262 #ifdef CONFIG_HOTPLUG_CPU 1263 1264 static void remove_siblinginfo(int cpu) 1265 { 1266 int sibling; 1267 struct cpuinfo_x86 *c = &cpu_data(cpu); 1268 1269 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1270 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1271 /*/ 1272 * last thread sibling in this cpu core going down 1273 */ 1274 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1275 cpu_data(sibling).booted_cores--; 1276 } 1277 1278 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1279 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1280 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1281 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1282 cpumask_clear(cpu_llc_shared_mask(cpu)); 1283 cpumask_clear(cpu_sibling_mask(cpu)); 1284 cpumask_clear(cpu_core_mask(cpu)); 1285 c->phys_proc_id = 0; 1286 c->cpu_core_id = 0; 1287 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1288 } 1289 1290 static void __ref remove_cpu_from_maps(int cpu) 1291 { 1292 set_cpu_online(cpu, false); 1293 cpumask_clear_cpu(cpu, cpu_callout_mask); 1294 cpumask_clear_cpu(cpu, cpu_callin_mask); 1295 /* was set by cpu_init() */ 1296 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1297 numa_remove_cpu(cpu); 1298 } 1299 1300 static DEFINE_PER_CPU(struct completion, die_complete); 1301 1302 void cpu_disable_common(void) 1303 { 1304 int cpu = smp_processor_id(); 1305 1306 init_completion(&per_cpu(die_complete, smp_processor_id())); 1307 1308 remove_siblinginfo(cpu); 1309 1310 /* It's now safe to remove this processor from the online map */ 1311 lock_vector_lock(); 1312 remove_cpu_from_maps(cpu); 1313 unlock_vector_lock(); 1314 fixup_irqs(); 1315 } 1316 1317 int native_cpu_disable(void) 1318 { 1319 int ret; 1320 1321 ret = check_irq_vectors_for_cpu_disable(); 1322 if (ret) 1323 return ret; 1324 1325 clear_local_APIC(); 1326 cpu_disable_common(); 1327 1328 return 0; 1329 } 1330 1331 void cpu_die_common(unsigned int cpu) 1332 { 1333 wait_for_completion_timeout(&per_cpu(die_complete, cpu), HZ); 1334 } 1335 1336 void native_cpu_die(unsigned int cpu) 1337 { 1338 /* We don't do anything here: idle task is faking death itself. */ 1339 1340 cpu_die_common(cpu); 1341 1342 /* They ack this in play_dead() by setting CPU_DEAD */ 1343 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1344 if (system_state == SYSTEM_RUNNING) 1345 pr_info("CPU %u is now offline\n", cpu); 1346 } else { 1347 pr_err("CPU %u didn't die...\n", cpu); 1348 } 1349 } 1350 1351 void play_dead_common(void) 1352 { 1353 idle_task_exit(); 1354 reset_lazy_tlbstate(); 1355 amd_e400_remove_cpu(raw_smp_processor_id()); 1356 1357 mb(); 1358 /* Ack it */ 1359 __this_cpu_write(cpu_state, CPU_DEAD); 1360 complete(&per_cpu(die_complete, smp_processor_id())); 1361 1362 /* 1363 * With physical CPU hotplug, we should halt the cpu 1364 */ 1365 local_irq_disable(); 1366 } 1367 1368 static bool wakeup_cpu0(void) 1369 { 1370 if (smp_processor_id() == 0 && enable_start_cpu0) 1371 return true; 1372 1373 return false; 1374 } 1375 1376 /* 1377 * We need to flush the caches before going to sleep, lest we have 1378 * dirty data in our caches when we come back up. 1379 */ 1380 static inline void mwait_play_dead(void) 1381 { 1382 unsigned int eax, ebx, ecx, edx; 1383 unsigned int highest_cstate = 0; 1384 unsigned int highest_subcstate = 0; 1385 void *mwait_ptr; 1386 int i; 1387 1388 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1389 return; 1390 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1391 return; 1392 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1393 return; 1394 1395 eax = CPUID_MWAIT_LEAF; 1396 ecx = 0; 1397 native_cpuid(&eax, &ebx, &ecx, &edx); 1398 1399 /* 1400 * eax will be 0 if EDX enumeration is not valid. 1401 * Initialized below to cstate, sub_cstate value when EDX is valid. 1402 */ 1403 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1404 eax = 0; 1405 } else { 1406 edx >>= MWAIT_SUBSTATE_SIZE; 1407 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1408 if (edx & MWAIT_SUBSTATE_MASK) { 1409 highest_cstate = i; 1410 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1411 } 1412 } 1413 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1414 (highest_subcstate - 1); 1415 } 1416 1417 /* 1418 * This should be a memory location in a cache line which is 1419 * unlikely to be touched by other processors. The actual 1420 * content is immaterial as it is not actually modified in any way. 1421 */ 1422 mwait_ptr = ¤t_thread_info()->flags; 1423 1424 wbinvd(); 1425 1426 while (1) { 1427 /* 1428 * The CLFLUSH is a workaround for erratum AAI65 for 1429 * the Xeon 7400 series. It's not clear it is actually 1430 * needed, but it should be harmless in either case. 1431 * The WBINVD is insufficient due to the spurious-wakeup 1432 * case where we return around the loop. 1433 */ 1434 mb(); 1435 clflush(mwait_ptr); 1436 mb(); 1437 __monitor(mwait_ptr, 0, 0); 1438 mb(); 1439 __mwait(eax, 0); 1440 /* 1441 * If NMI wants to wake up CPU0, start CPU0. 1442 */ 1443 if (wakeup_cpu0()) 1444 start_cpu0(); 1445 } 1446 } 1447 1448 static inline void hlt_play_dead(void) 1449 { 1450 if (__this_cpu_read(cpu_info.x86) >= 4) 1451 wbinvd(); 1452 1453 while (1) { 1454 native_halt(); 1455 /* 1456 * If NMI wants to wake up CPU0, start CPU0. 1457 */ 1458 if (wakeup_cpu0()) 1459 start_cpu0(); 1460 } 1461 } 1462 1463 void native_play_dead(void) 1464 { 1465 play_dead_common(); 1466 tboot_shutdown(TB_SHUTDOWN_WFS); 1467 1468 mwait_play_dead(); /* Only returns on failure */ 1469 if (cpuidle_play_dead()) 1470 hlt_play_dead(); 1471 } 1472 1473 #else /* ... !CONFIG_HOTPLUG_CPU */ 1474 int native_cpu_disable(void) 1475 { 1476 return -ENOSYS; 1477 } 1478 1479 void native_cpu_die(unsigned int cpu) 1480 { 1481 /* We said "no" in __cpu_disable */ 1482 BUG(); 1483 } 1484 1485 void native_play_dead(void) 1486 { 1487 BUG(); 1488 } 1489 1490 #endif 1491