1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/i387.h> 72 #include <asm/fpu-internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 77 #include <asm/smpboot_hooks.h> 78 #include <asm/i8259.h> 79 80 #include <asm/realmode.h> 81 82 /* State of each CPU */ 83 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 84 85 #ifdef CONFIG_HOTPLUG_CPU 86 /* 87 * We need this for trampoline_base protection from concurrent accesses when 88 * off- and onlining cores wildly. 89 */ 90 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 91 92 void cpu_hotplug_driver_lock(void) 93 { 94 mutex_lock(&x86_cpu_hotplug_driver_mutex); 95 } 96 97 void cpu_hotplug_driver_unlock(void) 98 { 99 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 100 } 101 102 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 103 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 104 #endif 105 106 /* Number of siblings per CPU package */ 107 int smp_num_siblings = 1; 108 EXPORT_SYMBOL(smp_num_siblings); 109 110 /* Last level cache ID of each logical CPU */ 111 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 112 113 /* representing HT siblings of each logical CPU */ 114 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 115 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 116 117 /* representing HT and core siblings of each logical CPU */ 118 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 119 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 120 121 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 122 123 /* Per CPU bogomips and other parameters */ 124 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 125 EXPORT_PER_CPU_SYMBOL(cpu_info); 126 127 atomic_t init_deasserted; 128 129 /* 130 * Report back to the Boot Processor during boot time or to the caller processor 131 * during CPU online. 132 */ 133 static void __cpuinit smp_callin(void) 134 { 135 int cpuid, phys_id; 136 unsigned long timeout; 137 138 /* 139 * If waken up by an INIT in an 82489DX configuration 140 * we may get here before an INIT-deassert IPI reaches 141 * our local APIC. We have to wait for the IPI or we'll 142 * lock up on an APIC access. 143 * 144 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. 145 */ 146 cpuid = smp_processor_id(); 147 if (apic->wait_for_init_deassert && cpuid != 0) 148 apic->wait_for_init_deassert(&init_deasserted); 149 150 /* 151 * (This works even if the APIC is not enabled.) 152 */ 153 phys_id = read_apic_id(); 154 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 155 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 156 phys_id, cpuid); 157 } 158 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 159 160 /* 161 * STARTUP IPIs are fragile beasts as they might sometimes 162 * trigger some glue motherboard logic. Complete APIC bus 163 * silence for 1 second, this overestimates the time the 164 * boot CPU is spending to send the up to 2 STARTUP IPIs 165 * by a factor of two. This should be enough. 166 */ 167 168 /* 169 * Waiting 2s total for startup (udelay is not yet working) 170 */ 171 timeout = jiffies + 2*HZ; 172 while (time_before(jiffies, timeout)) { 173 /* 174 * Has the boot CPU finished it's STARTUP sequence? 175 */ 176 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 177 break; 178 cpu_relax(); 179 } 180 181 if (!time_before(jiffies, timeout)) { 182 panic("%s: CPU%d started up but did not get a callout!\n", 183 __func__, cpuid); 184 } 185 186 /* 187 * the boot CPU has finished the init stage and is spinning 188 * on callin_map until we finish. We are free to set up this 189 * CPU, first the APIC. (this is probably redundant on most 190 * boards) 191 */ 192 193 pr_debug("CALLIN, before setup_local_APIC()\n"); 194 if (apic->smp_callin_clear_local_apic) 195 apic->smp_callin_clear_local_apic(); 196 setup_local_APIC(); 197 end_local_APIC_setup(); 198 199 /* 200 * Need to setup vector mappings before we enable interrupts. 201 */ 202 setup_vector_irq(smp_processor_id()); 203 204 /* 205 * Save our processor parameters. Note: this information 206 * is needed for clock calibration. 207 */ 208 smp_store_cpu_info(cpuid); 209 210 /* 211 * Get our bogomips. 212 * Update loops_per_jiffy in cpu_data. Previous call to 213 * smp_store_cpu_info() stored a value that is close but not as 214 * accurate as the value just calculated. 215 */ 216 calibrate_delay(); 217 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 218 pr_debug("Stack at about %p\n", &cpuid); 219 220 /* 221 * This must be done before setting cpu_online_mask 222 * or calling notify_cpu_starting. 223 */ 224 set_cpu_sibling_map(raw_smp_processor_id()); 225 wmb(); 226 227 notify_cpu_starting(cpuid); 228 229 /* 230 * Allow the master to continue. 231 */ 232 cpumask_set_cpu(cpuid, cpu_callin_mask); 233 } 234 235 static int cpu0_logical_apicid; 236 static int enable_start_cpu0; 237 /* 238 * Activate a secondary processor. 239 */ 240 notrace static void __cpuinit start_secondary(void *unused) 241 { 242 /* 243 * Don't put *anything* before cpu_init(), SMP booting is too 244 * fragile that we want to limit the things done here to the 245 * most necessary things. 246 */ 247 cpu_init(); 248 x86_cpuinit.early_percpu_clock_init(); 249 preempt_disable(); 250 smp_callin(); 251 252 enable_start_cpu0 = 0; 253 254 #ifdef CONFIG_X86_32 255 /* switch away from the initial page table */ 256 load_cr3(swapper_pg_dir); 257 __flush_tlb_all(); 258 #endif 259 260 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 261 barrier(); 262 /* 263 * Check TSC synchronization with the BP: 264 */ 265 check_tsc_sync_target(); 266 267 /* 268 * We need to hold vector_lock so there the set of online cpus 269 * does not change while we are assigning vectors to cpus. Holding 270 * this lock ensures we don't half assign or remove an irq from a cpu. 271 */ 272 lock_vector_lock(); 273 set_cpu_online(smp_processor_id(), true); 274 unlock_vector_lock(); 275 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 276 x86_platform.nmi_init(); 277 278 /* enable local interrupts */ 279 local_irq_enable(); 280 281 /* to prevent fake stack check failure in clock setup */ 282 boot_init_stack_canary(); 283 284 x86_cpuinit.setup_percpu_clockev(); 285 286 wmb(); 287 cpu_idle(); 288 } 289 290 void __init smp_store_boot_cpu_info(void) 291 { 292 int id = 0; /* CPU 0 */ 293 struct cpuinfo_x86 *c = &cpu_data(id); 294 295 *c = boot_cpu_data; 296 c->cpu_index = id; 297 } 298 299 /* 300 * The bootstrap kernel entry code has set these up. Save them for 301 * a given CPU 302 */ 303 void __cpuinit smp_store_cpu_info(int id) 304 { 305 struct cpuinfo_x86 *c = &cpu_data(id); 306 307 *c = boot_cpu_data; 308 c->cpu_index = id; 309 /* 310 * During boot time, CPU0 has this setup already. Save the info when 311 * bringing up AP or offlined CPU0. 312 */ 313 identify_secondary_cpu(c); 314 } 315 316 static bool __cpuinit 317 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 318 { 319 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 320 321 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), 322 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 323 "[node: %d != %d]. Ignoring dependency.\n", 324 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 325 } 326 327 #define link_mask(_m, c1, c2) \ 328 do { \ 329 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 330 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 331 } while (0) 332 333 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 334 { 335 if (cpu_has_topoext) { 336 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 337 338 if (c->phys_proc_id == o->phys_proc_id && 339 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 340 c->compute_unit_id == o->compute_unit_id) 341 return topology_sane(c, o, "smt"); 342 343 } else if (c->phys_proc_id == o->phys_proc_id && 344 c->cpu_core_id == o->cpu_core_id) { 345 return topology_sane(c, o, "smt"); 346 } 347 348 return false; 349 } 350 351 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 352 { 353 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 354 355 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 356 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 357 return topology_sane(c, o, "llc"); 358 359 return false; 360 } 361 362 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 363 { 364 if (c->phys_proc_id == o->phys_proc_id) { 365 if (cpu_has(c, X86_FEATURE_AMD_DCM)) 366 return true; 367 368 return topology_sane(c, o, "mc"); 369 } 370 return false; 371 } 372 373 void __cpuinit set_cpu_sibling_map(int cpu) 374 { 375 bool has_mc = boot_cpu_data.x86_max_cores > 1; 376 bool has_smt = smp_num_siblings > 1; 377 struct cpuinfo_x86 *c = &cpu_data(cpu); 378 struct cpuinfo_x86 *o; 379 int i; 380 381 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 382 383 if (!has_smt && !has_mc) { 384 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 385 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 386 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 387 c->booted_cores = 1; 388 return; 389 } 390 391 for_each_cpu(i, cpu_sibling_setup_mask) { 392 o = &cpu_data(i); 393 394 if ((i == cpu) || (has_smt && match_smt(c, o))) 395 link_mask(sibling, cpu, i); 396 397 if ((i == cpu) || (has_mc && match_llc(c, o))) 398 link_mask(llc_shared, cpu, i); 399 400 } 401 402 /* 403 * This needs a separate iteration over the cpus because we rely on all 404 * cpu_sibling_mask links to be set-up. 405 */ 406 for_each_cpu(i, cpu_sibling_setup_mask) { 407 o = &cpu_data(i); 408 409 if ((i == cpu) || (has_mc && match_mc(c, o))) { 410 link_mask(core, cpu, i); 411 412 /* 413 * Does this new cpu bringup a new core? 414 */ 415 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 416 /* 417 * for each core in package, increment 418 * the booted_cores for this new cpu 419 */ 420 if (cpumask_first(cpu_sibling_mask(i)) == i) 421 c->booted_cores++; 422 /* 423 * increment the core count for all 424 * the other cpus in this package 425 */ 426 if (i != cpu) 427 cpu_data(i).booted_cores++; 428 } else if (i != cpu && !c->booted_cores) 429 c->booted_cores = cpu_data(i).booted_cores; 430 } 431 } 432 } 433 434 /* maps the cpu to the sched domain representing multi-core */ 435 const struct cpumask *cpu_coregroup_mask(int cpu) 436 { 437 return cpu_llc_shared_mask(cpu); 438 } 439 440 static void impress_friends(void) 441 { 442 int cpu; 443 unsigned long bogosum = 0; 444 /* 445 * Allow the user to impress friends. 446 */ 447 pr_debug("Before bogomips\n"); 448 for_each_possible_cpu(cpu) 449 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 450 bogosum += cpu_data(cpu).loops_per_jiffy; 451 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 452 num_online_cpus(), 453 bogosum/(500000/HZ), 454 (bogosum/(5000/HZ))%100); 455 456 pr_debug("Before bogocount - setting activated=1\n"); 457 } 458 459 void __inquire_remote_apic(int apicid) 460 { 461 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 462 const char * const names[] = { "ID", "VERSION", "SPIV" }; 463 int timeout; 464 u32 status; 465 466 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 467 468 for (i = 0; i < ARRAY_SIZE(regs); i++) { 469 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 470 471 /* 472 * Wait for idle. 473 */ 474 status = safe_apic_wait_icr_idle(); 475 if (status) 476 pr_cont("a previous APIC delivery may have failed\n"); 477 478 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 479 480 timeout = 0; 481 do { 482 udelay(100); 483 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 484 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 485 486 switch (status) { 487 case APIC_ICR_RR_VALID: 488 status = apic_read(APIC_RRR); 489 pr_cont("%08x\n", status); 490 break; 491 default: 492 pr_cont("failed\n"); 493 } 494 } 495 } 496 497 /* 498 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 499 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 500 * won't ... remember to clear down the APIC, etc later. 501 */ 502 int __cpuinit 503 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 504 { 505 unsigned long send_status, accept_status = 0; 506 int maxlvt; 507 508 /* Target chip */ 509 /* Boot on the stack */ 510 /* Kick the second */ 511 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 512 513 pr_debug("Waiting for send to finish...\n"); 514 send_status = safe_apic_wait_icr_idle(); 515 516 /* 517 * Give the other CPU some time to accept the IPI. 518 */ 519 udelay(200); 520 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 521 maxlvt = lapic_get_maxlvt(); 522 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 523 apic_write(APIC_ESR, 0); 524 accept_status = (apic_read(APIC_ESR) & 0xEF); 525 } 526 pr_debug("NMI sent\n"); 527 528 if (send_status) 529 pr_err("APIC never delivered???\n"); 530 if (accept_status) 531 pr_err("APIC delivery error (%lx)\n", accept_status); 532 533 return (send_status | accept_status); 534 } 535 536 static int __cpuinit 537 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 538 { 539 unsigned long send_status, accept_status = 0; 540 int maxlvt, num_starts, j; 541 542 maxlvt = lapic_get_maxlvt(); 543 544 /* 545 * Be paranoid about clearing APIC errors. 546 */ 547 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 548 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 549 apic_write(APIC_ESR, 0); 550 apic_read(APIC_ESR); 551 } 552 553 pr_debug("Asserting INIT\n"); 554 555 /* 556 * Turn INIT on target chip 557 */ 558 /* 559 * Send IPI 560 */ 561 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 562 phys_apicid); 563 564 pr_debug("Waiting for send to finish...\n"); 565 send_status = safe_apic_wait_icr_idle(); 566 567 mdelay(10); 568 569 pr_debug("Deasserting INIT\n"); 570 571 /* Target chip */ 572 /* Send IPI */ 573 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 574 575 pr_debug("Waiting for send to finish...\n"); 576 send_status = safe_apic_wait_icr_idle(); 577 578 mb(); 579 atomic_set(&init_deasserted, 1); 580 581 /* 582 * Should we send STARTUP IPIs ? 583 * 584 * Determine this based on the APIC version. 585 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 586 */ 587 if (APIC_INTEGRATED(apic_version[phys_apicid])) 588 num_starts = 2; 589 else 590 num_starts = 0; 591 592 /* 593 * Paravirt / VMI wants a startup IPI hook here to set up the 594 * target processor state. 595 */ 596 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 597 stack_start); 598 599 /* 600 * Run STARTUP IPI loop. 601 */ 602 pr_debug("#startup loops: %d\n", num_starts); 603 604 for (j = 1; j <= num_starts; j++) { 605 pr_debug("Sending STARTUP #%d\n", j); 606 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 607 apic_write(APIC_ESR, 0); 608 apic_read(APIC_ESR); 609 pr_debug("After apic_write\n"); 610 611 /* 612 * STARTUP IPI 613 */ 614 615 /* Target chip */ 616 /* Boot on the stack */ 617 /* Kick the second */ 618 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 619 phys_apicid); 620 621 /* 622 * Give the other CPU some time to accept the IPI. 623 */ 624 udelay(300); 625 626 pr_debug("Startup point 1\n"); 627 628 pr_debug("Waiting for send to finish...\n"); 629 send_status = safe_apic_wait_icr_idle(); 630 631 /* 632 * Give the other CPU some time to accept the IPI. 633 */ 634 udelay(200); 635 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 636 apic_write(APIC_ESR, 0); 637 accept_status = (apic_read(APIC_ESR) & 0xEF); 638 if (send_status || accept_status) 639 break; 640 } 641 pr_debug("After Startup\n"); 642 643 if (send_status) 644 pr_err("APIC never delivered???\n"); 645 if (accept_status) 646 pr_err("APIC delivery error (%lx)\n", accept_status); 647 648 return (send_status | accept_status); 649 } 650 651 /* reduce the number of lines printed when booting a large cpu count system */ 652 static void __cpuinit announce_cpu(int cpu, int apicid) 653 { 654 static int current_node = -1; 655 int node = early_cpu_to_node(cpu); 656 657 if (system_state == SYSTEM_BOOTING) { 658 if (node != current_node) { 659 if (current_node > (-1)) 660 pr_cont(" OK\n"); 661 current_node = node; 662 pr_info("Booting Node %3d, Processors ", node); 663 } 664 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : ""); 665 return; 666 } else 667 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 668 node, cpu, apicid); 669 } 670 671 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 672 { 673 int cpu; 674 675 cpu = smp_processor_id(); 676 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 677 return NMI_HANDLED; 678 679 return NMI_DONE; 680 } 681 682 /* 683 * Wake up AP by INIT, INIT, STARTUP sequence. 684 * 685 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 686 * boot-strap code which is not a desired behavior for waking up BSP. To 687 * void the boot-strap code, wake up CPU0 by NMI instead. 688 * 689 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 690 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 691 * We'll change this code in the future to wake up hard offlined CPU0 if 692 * real platform and request are available. 693 */ 694 static int __cpuinit 695 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 696 int *cpu0_nmi_registered) 697 { 698 int id; 699 int boot_error; 700 701 /* 702 * Wake up AP by INIT, INIT, STARTUP sequence. 703 */ 704 if (cpu) 705 return wakeup_secondary_cpu_via_init(apicid, start_ip); 706 707 /* 708 * Wake up BSP by nmi. 709 * 710 * Register a NMI handler to help wake up CPU0. 711 */ 712 boot_error = register_nmi_handler(NMI_LOCAL, 713 wakeup_cpu0_nmi, 0, "wake_cpu0"); 714 715 if (!boot_error) { 716 enable_start_cpu0 = 1; 717 *cpu0_nmi_registered = 1; 718 if (apic->dest_logical == APIC_DEST_LOGICAL) 719 id = cpu0_logical_apicid; 720 else 721 id = apicid; 722 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 723 } 724 725 return boot_error; 726 } 727 728 /* 729 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 730 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 731 * Returns zero if CPU booted OK, else error code from 732 * ->wakeup_secondary_cpu. 733 */ 734 static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 735 { 736 volatile u32 *trampoline_status = 737 (volatile u32 *) __va(real_mode_header->trampoline_status); 738 /* start_ip had better be page-aligned! */ 739 unsigned long start_ip = real_mode_header->trampoline_start; 740 741 unsigned long boot_error = 0; 742 int timeout; 743 int cpu0_nmi_registered = 0; 744 745 /* Just in case we booted with a single CPU. */ 746 alternatives_enable_smp(); 747 748 idle->thread.sp = (unsigned long) (((struct pt_regs *) 749 (THREAD_SIZE + task_stack_page(idle))) - 1); 750 per_cpu(current_task, cpu) = idle; 751 752 #ifdef CONFIG_X86_32 753 /* Stack for startup_32 can be just as for start_secondary onwards */ 754 irq_ctx_init(cpu); 755 #else 756 clear_tsk_thread_flag(idle, TIF_FORK); 757 initial_gs = per_cpu_offset(cpu); 758 per_cpu(kernel_stack, cpu) = 759 (unsigned long)task_stack_page(idle) - 760 KERNEL_STACK_OFFSET + THREAD_SIZE; 761 #endif 762 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 763 initial_code = (unsigned long)start_secondary; 764 stack_start = idle->thread.sp; 765 766 /* So we see what's up */ 767 announce_cpu(cpu, apicid); 768 769 /* 770 * This grunge runs the startup process for 771 * the targeted processor. 772 */ 773 774 atomic_set(&init_deasserted, 0); 775 776 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 777 778 pr_debug("Setting warm reset code and vector.\n"); 779 780 smpboot_setup_warm_reset_vector(start_ip); 781 /* 782 * Be paranoid about clearing APIC errors. 783 */ 784 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 785 apic_write(APIC_ESR, 0); 786 apic_read(APIC_ESR); 787 } 788 } 789 790 /* 791 * Wake up a CPU in difference cases: 792 * - Use the method in the APIC driver if it's defined 793 * Otherwise, 794 * - Use an INIT boot APIC message for APs or NMI for BSP. 795 */ 796 if (apic->wakeup_secondary_cpu) 797 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 798 else 799 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 800 &cpu0_nmi_registered); 801 802 if (!boot_error) { 803 /* 804 * allow APs to start initializing. 805 */ 806 pr_debug("Before Callout %d\n", cpu); 807 cpumask_set_cpu(cpu, cpu_callout_mask); 808 pr_debug("After Callout %d\n", cpu); 809 810 /* 811 * Wait 5s total for a response 812 */ 813 for (timeout = 0; timeout < 50000; timeout++) { 814 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 815 break; /* It has booted */ 816 udelay(100); 817 /* 818 * Allow other tasks to run while we wait for the 819 * AP to come online. This also gives a chance 820 * for the MTRR work(triggered by the AP coming online) 821 * to be completed in the stop machine context. 822 */ 823 schedule(); 824 } 825 826 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 827 print_cpu_msr(&cpu_data(cpu)); 828 pr_debug("CPU%d: has booted.\n", cpu); 829 } else { 830 boot_error = 1; 831 if (*trampoline_status == 0xA5A5A5A5) 832 /* trampoline started but...? */ 833 pr_err("CPU%d: Stuck ??\n", cpu); 834 else 835 /* trampoline code not run */ 836 pr_err("CPU%d: Not responding\n", cpu); 837 if (apic->inquire_remote_apic) 838 apic->inquire_remote_apic(apicid); 839 } 840 } 841 842 if (boot_error) { 843 /* Try to put things back the way they were before ... */ 844 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 845 846 /* was set by do_boot_cpu() */ 847 cpumask_clear_cpu(cpu, cpu_callout_mask); 848 849 /* was set by cpu_init() */ 850 cpumask_clear_cpu(cpu, cpu_initialized_mask); 851 852 set_cpu_present(cpu, false); 853 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 854 } 855 856 /* mark "stuck" area as not stuck */ 857 *trampoline_status = 0; 858 859 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 860 /* 861 * Cleanup possible dangling ends... 862 */ 863 smpboot_restore_warm_reset_vector(); 864 } 865 /* 866 * Clean up the nmi handler. Do this after the callin and callout sync 867 * to avoid impact of possible long unregister time. 868 */ 869 if (cpu0_nmi_registered) 870 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 871 872 return boot_error; 873 } 874 875 int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) 876 { 877 int apicid = apic->cpu_present_to_apicid(cpu); 878 unsigned long flags; 879 int err; 880 881 WARN_ON(irqs_disabled()); 882 883 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 884 885 if (apicid == BAD_APICID || 886 !physid_isset(apicid, phys_cpu_present_map) || 887 !apic->apic_id_valid(apicid)) { 888 pr_err("%s: bad cpu %d\n", __func__, cpu); 889 return -EINVAL; 890 } 891 892 /* 893 * Already booted CPU? 894 */ 895 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 896 pr_debug("do_boot_cpu %d Already started\n", cpu); 897 return -ENOSYS; 898 } 899 900 /* 901 * Save current MTRR state in case it was changed since early boot 902 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 903 */ 904 mtrr_save_state(); 905 906 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 907 908 /* the FPU context is blank, nobody can own it */ 909 __cpu_disable_lazy_restore(cpu); 910 911 err = do_boot_cpu(apicid, cpu, tidle); 912 if (err) { 913 pr_debug("do_boot_cpu failed %d\n", err); 914 return -EIO; 915 } 916 917 /* 918 * Check TSC synchronization with the AP (keep irqs disabled 919 * while doing so): 920 */ 921 local_irq_save(flags); 922 check_tsc_sync_source(cpu); 923 local_irq_restore(flags); 924 925 while (!cpu_online(cpu)) { 926 cpu_relax(); 927 touch_nmi_watchdog(); 928 } 929 930 return 0; 931 } 932 933 /** 934 * arch_disable_smp_support() - disables SMP support for x86 at runtime 935 */ 936 void arch_disable_smp_support(void) 937 { 938 disable_ioapic_support(); 939 } 940 941 /* 942 * Fall back to non SMP mode after errors. 943 * 944 * RED-PEN audit/test this more. I bet there is more state messed up here. 945 */ 946 static __init void disable_smp(void) 947 { 948 init_cpu_present(cpumask_of(0)); 949 init_cpu_possible(cpumask_of(0)); 950 smpboot_clear_io_apic_irqs(); 951 952 if (smp_found_config) 953 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 954 else 955 physid_set_mask_of_physid(0, &phys_cpu_present_map); 956 cpumask_set_cpu(0, cpu_sibling_mask(0)); 957 cpumask_set_cpu(0, cpu_core_mask(0)); 958 } 959 960 /* 961 * Various sanity checks. 962 */ 963 static int __init smp_sanity_check(unsigned max_cpus) 964 { 965 preempt_disable(); 966 967 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 968 if (def_to_bigsmp && nr_cpu_ids > 8) { 969 unsigned int cpu; 970 unsigned nr; 971 972 pr_warn("More than 8 CPUs detected - skipping them\n" 973 "Use CONFIG_X86_BIGSMP\n"); 974 975 nr = 0; 976 for_each_present_cpu(cpu) { 977 if (nr >= 8) 978 set_cpu_present(cpu, false); 979 nr++; 980 } 981 982 nr = 0; 983 for_each_possible_cpu(cpu) { 984 if (nr >= 8) 985 set_cpu_possible(cpu, false); 986 nr++; 987 } 988 989 nr_cpu_ids = 8; 990 } 991 #endif 992 993 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 994 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 995 hard_smp_processor_id()); 996 997 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 998 } 999 1000 /* 1001 * If we couldn't find an SMP configuration at boot time, 1002 * get out of here now! 1003 */ 1004 if (!smp_found_config && !acpi_lapic) { 1005 preempt_enable(); 1006 pr_notice("SMP motherboard not detected\n"); 1007 disable_smp(); 1008 if (APIC_init_uniprocessor()) 1009 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1010 return -1; 1011 } 1012 1013 /* 1014 * Should not be necessary because the MP table should list the boot 1015 * CPU too, but we do it for the sake of robustness anyway. 1016 */ 1017 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1018 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1019 boot_cpu_physical_apicid); 1020 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1021 } 1022 preempt_enable(); 1023 1024 /* 1025 * If we couldn't find a local APIC, then get out of here now! 1026 */ 1027 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1028 !cpu_has_apic) { 1029 if (!disable_apic) { 1030 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1031 boot_cpu_physical_apicid); 1032 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1033 } 1034 smpboot_clear_io_apic(); 1035 disable_ioapic_support(); 1036 return -1; 1037 } 1038 1039 verify_local_APIC(); 1040 1041 /* 1042 * If SMP should be disabled, then really disable it! 1043 */ 1044 if (!max_cpus) { 1045 pr_info("SMP mode deactivated\n"); 1046 smpboot_clear_io_apic(); 1047 1048 connect_bsp_APIC(); 1049 setup_local_APIC(); 1050 bsp_end_local_APIC_setup(); 1051 return -1; 1052 } 1053 1054 return 0; 1055 } 1056 1057 static void __init smp_cpu_index_default(void) 1058 { 1059 int i; 1060 struct cpuinfo_x86 *c; 1061 1062 for_each_possible_cpu(i) { 1063 c = &cpu_data(i); 1064 /* mark all to hotplug */ 1065 c->cpu_index = nr_cpu_ids; 1066 } 1067 } 1068 1069 /* 1070 * Prepare for SMP bootup. The MP table or ACPI has been read 1071 * earlier. Just do some sanity checking here and enable APIC mode. 1072 */ 1073 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1074 { 1075 unsigned int i; 1076 1077 preempt_disable(); 1078 smp_cpu_index_default(); 1079 1080 /* 1081 * Setup boot CPU information 1082 */ 1083 smp_store_boot_cpu_info(); /* Final full version of the data */ 1084 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1085 mb(); 1086 1087 current_thread_info()->cpu = 0; /* needed? */ 1088 for_each_possible_cpu(i) { 1089 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1090 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1091 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1092 } 1093 set_cpu_sibling_map(0); 1094 1095 1096 if (smp_sanity_check(max_cpus) < 0) { 1097 pr_info("SMP disabled\n"); 1098 disable_smp(); 1099 goto out; 1100 } 1101 1102 default_setup_apic_routing(); 1103 1104 preempt_disable(); 1105 if (read_apic_id() != boot_cpu_physical_apicid) { 1106 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1107 read_apic_id(), boot_cpu_physical_apicid); 1108 /* Or can we switch back to PIC here? */ 1109 } 1110 preempt_enable(); 1111 1112 connect_bsp_APIC(); 1113 1114 /* 1115 * Switch from PIC to APIC mode. 1116 */ 1117 setup_local_APIC(); 1118 1119 if (x2apic_mode) 1120 cpu0_logical_apicid = apic_read(APIC_LDR); 1121 else 1122 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1123 1124 /* 1125 * Enable IO APIC before setting up error vector 1126 */ 1127 if (!skip_ioapic_setup && nr_ioapics) 1128 enable_IO_APIC(); 1129 1130 bsp_end_local_APIC_setup(); 1131 1132 if (apic->setup_portio_remap) 1133 apic->setup_portio_remap(); 1134 1135 smpboot_setup_io_apic(); 1136 /* 1137 * Set up local APIC timer on boot CPU. 1138 */ 1139 1140 pr_info("CPU%d: ", 0); 1141 print_cpu_info(&cpu_data(0)); 1142 x86_init.timers.setup_percpu_clockev(); 1143 1144 if (is_uv_system()) 1145 uv_system_init(); 1146 1147 set_mtrr_aps_delayed_init(); 1148 out: 1149 preempt_enable(); 1150 } 1151 1152 void arch_enable_nonboot_cpus_begin(void) 1153 { 1154 set_mtrr_aps_delayed_init(); 1155 } 1156 1157 void arch_enable_nonboot_cpus_end(void) 1158 { 1159 mtrr_aps_init(); 1160 } 1161 1162 /* 1163 * Early setup to make printk work. 1164 */ 1165 void __init native_smp_prepare_boot_cpu(void) 1166 { 1167 int me = smp_processor_id(); 1168 switch_to_new_gdt(me); 1169 /* already set me in cpu_online_mask in boot_cpu_init() */ 1170 cpumask_set_cpu(me, cpu_callout_mask); 1171 per_cpu(cpu_state, me) = CPU_ONLINE; 1172 } 1173 1174 void __init native_smp_cpus_done(unsigned int max_cpus) 1175 { 1176 pr_debug("Boot done\n"); 1177 1178 nmi_selftest(); 1179 impress_friends(); 1180 #ifdef CONFIG_X86_IO_APIC 1181 setup_ioapic_dest(); 1182 #endif 1183 mtrr_aps_init(); 1184 } 1185 1186 static int __initdata setup_possible_cpus = -1; 1187 static int __init _setup_possible_cpus(char *str) 1188 { 1189 get_option(&str, &setup_possible_cpus); 1190 return 0; 1191 } 1192 early_param("possible_cpus", _setup_possible_cpus); 1193 1194 1195 /* 1196 * cpu_possible_mask should be static, it cannot change as cpu's 1197 * are onlined, or offlined. The reason is per-cpu data-structures 1198 * are allocated by some modules at init time, and dont expect to 1199 * do this dynamically on cpu arrival/departure. 1200 * cpu_present_mask on the other hand can change dynamically. 1201 * In case when cpu_hotplug is not compiled, then we resort to current 1202 * behaviour, which is cpu_possible == cpu_present. 1203 * - Ashok Raj 1204 * 1205 * Three ways to find out the number of additional hotplug CPUs: 1206 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1207 * - The user can overwrite it with possible_cpus=NUM 1208 * - Otherwise don't reserve additional CPUs. 1209 * We do this because additional CPUs waste a lot of memory. 1210 * -AK 1211 */ 1212 __init void prefill_possible_map(void) 1213 { 1214 int i, possible; 1215 1216 /* no processor from mptable or madt */ 1217 if (!num_processors) 1218 num_processors = 1; 1219 1220 i = setup_max_cpus ?: 1; 1221 if (setup_possible_cpus == -1) { 1222 possible = num_processors; 1223 #ifdef CONFIG_HOTPLUG_CPU 1224 if (setup_max_cpus) 1225 possible += disabled_cpus; 1226 #else 1227 if (possible > i) 1228 possible = i; 1229 #endif 1230 } else 1231 possible = setup_possible_cpus; 1232 1233 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1234 1235 /* nr_cpu_ids could be reduced via nr_cpus= */ 1236 if (possible > nr_cpu_ids) { 1237 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1238 possible, nr_cpu_ids); 1239 possible = nr_cpu_ids; 1240 } 1241 1242 #ifdef CONFIG_HOTPLUG_CPU 1243 if (!setup_max_cpus) 1244 #endif 1245 if (possible > i) { 1246 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1247 possible, setup_max_cpus); 1248 possible = i; 1249 } 1250 1251 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1252 possible, max_t(int, possible - num_processors, 0)); 1253 1254 for (i = 0; i < possible; i++) 1255 set_cpu_possible(i, true); 1256 for (; i < NR_CPUS; i++) 1257 set_cpu_possible(i, false); 1258 1259 nr_cpu_ids = possible; 1260 } 1261 1262 #ifdef CONFIG_HOTPLUG_CPU 1263 1264 static void remove_siblinginfo(int cpu) 1265 { 1266 int sibling; 1267 struct cpuinfo_x86 *c = &cpu_data(cpu); 1268 1269 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1270 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1271 /*/ 1272 * last thread sibling in this cpu core going down 1273 */ 1274 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1275 cpu_data(sibling).booted_cores--; 1276 } 1277 1278 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1279 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1280 cpumask_clear(cpu_sibling_mask(cpu)); 1281 cpumask_clear(cpu_core_mask(cpu)); 1282 c->phys_proc_id = 0; 1283 c->cpu_core_id = 0; 1284 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1285 } 1286 1287 static void __ref remove_cpu_from_maps(int cpu) 1288 { 1289 set_cpu_online(cpu, false); 1290 cpumask_clear_cpu(cpu, cpu_callout_mask); 1291 cpumask_clear_cpu(cpu, cpu_callin_mask); 1292 /* was set by cpu_init() */ 1293 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1294 numa_remove_cpu(cpu); 1295 } 1296 1297 void cpu_disable_common(void) 1298 { 1299 int cpu = smp_processor_id(); 1300 1301 remove_siblinginfo(cpu); 1302 1303 /* It's now safe to remove this processor from the online map */ 1304 lock_vector_lock(); 1305 remove_cpu_from_maps(cpu); 1306 unlock_vector_lock(); 1307 fixup_irqs(); 1308 } 1309 1310 int native_cpu_disable(void) 1311 { 1312 clear_local_APIC(); 1313 1314 cpu_disable_common(); 1315 return 0; 1316 } 1317 1318 void native_cpu_die(unsigned int cpu) 1319 { 1320 /* We don't do anything here: idle task is faking death itself. */ 1321 unsigned int i; 1322 1323 for (i = 0; i < 10; i++) { 1324 /* They ack this in play_dead by setting CPU_DEAD */ 1325 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1326 if (system_state == SYSTEM_RUNNING) 1327 pr_info("CPU %u is now offline\n", cpu); 1328 return; 1329 } 1330 msleep(100); 1331 } 1332 pr_err("CPU %u didn't die...\n", cpu); 1333 } 1334 1335 void play_dead_common(void) 1336 { 1337 idle_task_exit(); 1338 reset_lazy_tlbstate(); 1339 amd_e400_remove_cpu(raw_smp_processor_id()); 1340 1341 mb(); 1342 /* Ack it */ 1343 __this_cpu_write(cpu_state, CPU_DEAD); 1344 1345 /* 1346 * With physical CPU hotplug, we should halt the cpu 1347 */ 1348 local_irq_disable(); 1349 } 1350 1351 static bool wakeup_cpu0(void) 1352 { 1353 if (smp_processor_id() == 0 && enable_start_cpu0) 1354 return true; 1355 1356 return false; 1357 } 1358 1359 /* 1360 * We need to flush the caches before going to sleep, lest we have 1361 * dirty data in our caches when we come back up. 1362 */ 1363 static inline void mwait_play_dead(void) 1364 { 1365 unsigned int eax, ebx, ecx, edx; 1366 unsigned int highest_cstate = 0; 1367 unsigned int highest_subcstate = 0; 1368 int i; 1369 void *mwait_ptr; 1370 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1371 1372 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1373 return; 1374 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1375 return; 1376 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1377 return; 1378 1379 eax = CPUID_MWAIT_LEAF; 1380 ecx = 0; 1381 native_cpuid(&eax, &ebx, &ecx, &edx); 1382 1383 /* 1384 * eax will be 0 if EDX enumeration is not valid. 1385 * Initialized below to cstate, sub_cstate value when EDX is valid. 1386 */ 1387 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1388 eax = 0; 1389 } else { 1390 edx >>= MWAIT_SUBSTATE_SIZE; 1391 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1392 if (edx & MWAIT_SUBSTATE_MASK) { 1393 highest_cstate = i; 1394 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1395 } 1396 } 1397 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1398 (highest_subcstate - 1); 1399 } 1400 1401 /* 1402 * This should be a memory location in a cache line which is 1403 * unlikely to be touched by other processors. The actual 1404 * content is immaterial as it is not actually modified in any way. 1405 */ 1406 mwait_ptr = ¤t_thread_info()->flags; 1407 1408 wbinvd(); 1409 1410 while (1) { 1411 /* 1412 * The CLFLUSH is a workaround for erratum AAI65 for 1413 * the Xeon 7400 series. It's not clear it is actually 1414 * needed, but it should be harmless in either case. 1415 * The WBINVD is insufficient due to the spurious-wakeup 1416 * case where we return around the loop. 1417 */ 1418 clflush(mwait_ptr); 1419 __monitor(mwait_ptr, 0, 0); 1420 mb(); 1421 __mwait(eax, 0); 1422 /* 1423 * If NMI wants to wake up CPU0, start CPU0. 1424 */ 1425 if (wakeup_cpu0()) 1426 start_cpu0(); 1427 } 1428 } 1429 1430 static inline void hlt_play_dead(void) 1431 { 1432 if (__this_cpu_read(cpu_info.x86) >= 4) 1433 wbinvd(); 1434 1435 while (1) { 1436 native_halt(); 1437 /* 1438 * If NMI wants to wake up CPU0, start CPU0. 1439 */ 1440 if (wakeup_cpu0()) 1441 start_cpu0(); 1442 } 1443 } 1444 1445 void native_play_dead(void) 1446 { 1447 play_dead_common(); 1448 tboot_shutdown(TB_SHUTDOWN_WFS); 1449 1450 mwait_play_dead(); /* Only returns on failure */ 1451 if (cpuidle_play_dead()) 1452 hlt_play_dead(); 1453 } 1454 1455 #else /* ... !CONFIG_HOTPLUG_CPU */ 1456 int native_cpu_disable(void) 1457 { 1458 return -ENOSYS; 1459 } 1460 1461 void native_cpu_die(unsigned int cpu) 1462 { 1463 /* We said "no" in __cpu_disable */ 1464 BUG(); 1465 } 1466 1467 void native_play_dead(void) 1468 { 1469 BUG(); 1470 } 1471 1472 #endif 1473