1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/i387.h> 72 #include <asm/fpu-internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 #include <asm/smpboot_hooks.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 81 /* State of each CPU */ 82 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 83 84 /* Number of siblings per CPU package */ 85 int smp_num_siblings = 1; 86 EXPORT_SYMBOL(smp_num_siblings); 87 88 /* Last level cache ID of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 100 101 /* Per CPU bogomips and other parameters */ 102 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 103 EXPORT_PER_CPU_SYMBOL(cpu_info); 104 105 atomic_t init_deasserted; 106 107 /* 108 * Report back to the Boot Processor during boot time or to the caller processor 109 * during CPU online. 110 */ 111 static void smp_callin(void) 112 { 113 int cpuid, phys_id; 114 unsigned long timeout; 115 116 /* 117 * If waken up by an INIT in an 82489DX configuration 118 * we may get here before an INIT-deassert IPI reaches 119 * our local APIC. We have to wait for the IPI or we'll 120 * lock up on an APIC access. 121 * 122 * Since CPU0 is not wakened up by INIT, it doesn't wait for the IPI. 123 */ 124 cpuid = smp_processor_id(); 125 if (apic->wait_for_init_deassert && cpuid) 126 while (!atomic_read(&init_deasserted)) 127 cpu_relax(); 128 129 /* 130 * (This works even if the APIC is not enabled.) 131 */ 132 phys_id = read_apic_id(); 133 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 134 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 135 phys_id, cpuid); 136 } 137 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 138 139 /* 140 * STARTUP IPIs are fragile beasts as they might sometimes 141 * trigger some glue motherboard logic. Complete APIC bus 142 * silence for 1 second, this overestimates the time the 143 * boot CPU is spending to send the up to 2 STARTUP IPIs 144 * by a factor of two. This should be enough. 145 */ 146 147 /* 148 * Waiting 2s total for startup (udelay is not yet working) 149 */ 150 timeout = jiffies + 2*HZ; 151 while (time_before(jiffies, timeout)) { 152 /* 153 * Has the boot CPU finished it's STARTUP sequence? 154 */ 155 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 156 break; 157 cpu_relax(); 158 } 159 160 if (!time_before(jiffies, timeout)) { 161 panic("%s: CPU%d started up but did not get a callout!\n", 162 __func__, cpuid); 163 } 164 165 /* 166 * the boot CPU has finished the init stage and is spinning 167 * on callin_map until we finish. We are free to set up this 168 * CPU, first the APIC. (this is probably redundant on most 169 * boards) 170 */ 171 172 pr_debug("CALLIN, before setup_local_APIC()\n"); 173 if (apic->smp_callin_clear_local_apic) 174 apic->smp_callin_clear_local_apic(); 175 setup_local_APIC(); 176 end_local_APIC_setup(); 177 178 /* 179 * Need to setup vector mappings before we enable interrupts. 180 */ 181 setup_vector_irq(smp_processor_id()); 182 183 /* 184 * Save our processor parameters. Note: this information 185 * is needed for clock calibration. 186 */ 187 smp_store_cpu_info(cpuid); 188 189 /* 190 * Get our bogomips. 191 * Update loops_per_jiffy in cpu_data. Previous call to 192 * smp_store_cpu_info() stored a value that is close but not as 193 * accurate as the value just calculated. 194 */ 195 calibrate_delay(); 196 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 197 pr_debug("Stack at about %p\n", &cpuid); 198 199 /* 200 * This must be done before setting cpu_online_mask 201 * or calling notify_cpu_starting. 202 */ 203 set_cpu_sibling_map(raw_smp_processor_id()); 204 wmb(); 205 206 notify_cpu_starting(cpuid); 207 208 /* 209 * Allow the master to continue. 210 */ 211 cpumask_set_cpu(cpuid, cpu_callin_mask); 212 } 213 214 static int cpu0_logical_apicid; 215 static int enable_start_cpu0; 216 /* 217 * Activate a secondary processor. 218 */ 219 static void notrace start_secondary(void *unused) 220 { 221 /* 222 * Don't put *anything* before cpu_init(), SMP booting is too 223 * fragile that we want to limit the things done here to the 224 * most necessary things. 225 */ 226 cpu_init(); 227 x86_cpuinit.early_percpu_clock_init(); 228 preempt_disable(); 229 smp_callin(); 230 231 enable_start_cpu0 = 0; 232 233 #ifdef CONFIG_X86_32 234 /* switch away from the initial page table */ 235 load_cr3(swapper_pg_dir); 236 __flush_tlb_all(); 237 #endif 238 239 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 240 barrier(); 241 /* 242 * Check TSC synchronization with the BP: 243 */ 244 check_tsc_sync_target(); 245 246 /* 247 * We need to hold vector_lock so there the set of online cpus 248 * does not change while we are assigning vectors to cpus. Holding 249 * this lock ensures we don't half assign or remove an irq from a cpu. 250 */ 251 lock_vector_lock(); 252 set_cpu_online(smp_processor_id(), true); 253 unlock_vector_lock(); 254 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 255 x86_platform.nmi_init(); 256 257 /* enable local interrupts */ 258 local_irq_enable(); 259 260 /* to prevent fake stack check failure in clock setup */ 261 boot_init_stack_canary(); 262 263 x86_cpuinit.setup_percpu_clockev(); 264 265 wmb(); 266 cpu_startup_entry(CPUHP_ONLINE); 267 } 268 269 void __init smp_store_boot_cpu_info(void) 270 { 271 int id = 0; /* CPU 0 */ 272 struct cpuinfo_x86 *c = &cpu_data(id); 273 274 *c = boot_cpu_data; 275 c->cpu_index = id; 276 } 277 278 /* 279 * The bootstrap kernel entry code has set these up. Save them for 280 * a given CPU 281 */ 282 void smp_store_cpu_info(int id) 283 { 284 struct cpuinfo_x86 *c = &cpu_data(id); 285 286 *c = boot_cpu_data; 287 c->cpu_index = id; 288 /* 289 * During boot time, CPU0 has this setup already. Save the info when 290 * bringing up AP or offlined CPU0. 291 */ 292 identify_secondary_cpu(c); 293 } 294 295 static bool 296 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 297 { 298 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 299 300 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), 301 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 302 "[node: %d != %d]. Ignoring dependency.\n", 303 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 304 } 305 306 #define link_mask(_m, c1, c2) \ 307 do { \ 308 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 309 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 310 } while (0) 311 312 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 313 { 314 if (cpu_has_topoext) { 315 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 316 317 if (c->phys_proc_id == o->phys_proc_id && 318 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 319 c->compute_unit_id == o->compute_unit_id) 320 return topology_sane(c, o, "smt"); 321 322 } else if (c->phys_proc_id == o->phys_proc_id && 323 c->cpu_core_id == o->cpu_core_id) { 324 return topology_sane(c, o, "smt"); 325 } 326 327 return false; 328 } 329 330 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 331 { 332 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 333 334 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 335 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 336 return topology_sane(c, o, "llc"); 337 338 return false; 339 } 340 341 static bool match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 342 { 343 if (c->phys_proc_id == o->phys_proc_id) { 344 if (cpu_has(c, X86_FEATURE_AMD_DCM)) 345 return true; 346 347 return topology_sane(c, o, "mc"); 348 } 349 return false; 350 } 351 352 void set_cpu_sibling_map(int cpu) 353 { 354 bool has_smt = smp_num_siblings > 1; 355 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 356 struct cpuinfo_x86 *c = &cpu_data(cpu); 357 struct cpuinfo_x86 *o; 358 int i; 359 360 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 361 362 if (!has_mp) { 363 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 364 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 365 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 366 c->booted_cores = 1; 367 return; 368 } 369 370 for_each_cpu(i, cpu_sibling_setup_mask) { 371 o = &cpu_data(i); 372 373 if ((i == cpu) || (has_smt && match_smt(c, o))) 374 link_mask(sibling, cpu, i); 375 376 if ((i == cpu) || (has_mp && match_llc(c, o))) 377 link_mask(llc_shared, cpu, i); 378 379 } 380 381 /* 382 * This needs a separate iteration over the cpus because we rely on all 383 * cpu_sibling_mask links to be set-up. 384 */ 385 for_each_cpu(i, cpu_sibling_setup_mask) { 386 o = &cpu_data(i); 387 388 if ((i == cpu) || (has_mp && match_mc(c, o))) { 389 link_mask(core, cpu, i); 390 391 /* 392 * Does this new cpu bringup a new core? 393 */ 394 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 395 /* 396 * for each core in package, increment 397 * the booted_cores for this new cpu 398 */ 399 if (cpumask_first(cpu_sibling_mask(i)) == i) 400 c->booted_cores++; 401 /* 402 * increment the core count for all 403 * the other cpus in this package 404 */ 405 if (i != cpu) 406 cpu_data(i).booted_cores++; 407 } else if (i != cpu && !c->booted_cores) 408 c->booted_cores = cpu_data(i).booted_cores; 409 } 410 } 411 } 412 413 /* maps the cpu to the sched domain representing multi-core */ 414 const struct cpumask *cpu_coregroup_mask(int cpu) 415 { 416 return cpu_llc_shared_mask(cpu); 417 } 418 419 static void impress_friends(void) 420 { 421 int cpu; 422 unsigned long bogosum = 0; 423 /* 424 * Allow the user to impress friends. 425 */ 426 pr_debug("Before bogomips\n"); 427 for_each_possible_cpu(cpu) 428 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 429 bogosum += cpu_data(cpu).loops_per_jiffy; 430 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 431 num_online_cpus(), 432 bogosum/(500000/HZ), 433 (bogosum/(5000/HZ))%100); 434 435 pr_debug("Before bogocount - setting activated=1\n"); 436 } 437 438 void __inquire_remote_apic(int apicid) 439 { 440 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 441 const char * const names[] = { "ID", "VERSION", "SPIV" }; 442 int timeout; 443 u32 status; 444 445 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 446 447 for (i = 0; i < ARRAY_SIZE(regs); i++) { 448 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 449 450 /* 451 * Wait for idle. 452 */ 453 status = safe_apic_wait_icr_idle(); 454 if (status) 455 pr_cont("a previous APIC delivery may have failed\n"); 456 457 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 458 459 timeout = 0; 460 do { 461 udelay(100); 462 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 463 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 464 465 switch (status) { 466 case APIC_ICR_RR_VALID: 467 status = apic_read(APIC_RRR); 468 pr_cont("%08x\n", status); 469 break; 470 default: 471 pr_cont("failed\n"); 472 } 473 } 474 } 475 476 /* 477 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 478 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 479 * won't ... remember to clear down the APIC, etc later. 480 */ 481 int 482 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 483 { 484 unsigned long send_status, accept_status = 0; 485 int maxlvt; 486 487 /* Target chip */ 488 /* Boot on the stack */ 489 /* Kick the second */ 490 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 491 492 pr_debug("Waiting for send to finish...\n"); 493 send_status = safe_apic_wait_icr_idle(); 494 495 /* 496 * Give the other CPU some time to accept the IPI. 497 */ 498 udelay(200); 499 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 500 maxlvt = lapic_get_maxlvt(); 501 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 502 apic_write(APIC_ESR, 0); 503 accept_status = (apic_read(APIC_ESR) & 0xEF); 504 } 505 pr_debug("NMI sent\n"); 506 507 if (send_status) 508 pr_err("APIC never delivered???\n"); 509 if (accept_status) 510 pr_err("APIC delivery error (%lx)\n", accept_status); 511 512 return (send_status | accept_status); 513 } 514 515 static int 516 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 517 { 518 unsigned long send_status, accept_status = 0; 519 int maxlvt, num_starts, j; 520 521 maxlvt = lapic_get_maxlvt(); 522 523 /* 524 * Be paranoid about clearing APIC errors. 525 */ 526 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 527 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 528 apic_write(APIC_ESR, 0); 529 apic_read(APIC_ESR); 530 } 531 532 pr_debug("Asserting INIT\n"); 533 534 /* 535 * Turn INIT on target chip 536 */ 537 /* 538 * Send IPI 539 */ 540 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 541 phys_apicid); 542 543 pr_debug("Waiting for send to finish...\n"); 544 send_status = safe_apic_wait_icr_idle(); 545 546 mdelay(10); 547 548 pr_debug("Deasserting INIT\n"); 549 550 /* Target chip */ 551 /* Send IPI */ 552 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 553 554 pr_debug("Waiting for send to finish...\n"); 555 send_status = safe_apic_wait_icr_idle(); 556 557 mb(); 558 atomic_set(&init_deasserted, 1); 559 560 /* 561 * Should we send STARTUP IPIs ? 562 * 563 * Determine this based on the APIC version. 564 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 565 */ 566 if (APIC_INTEGRATED(apic_version[phys_apicid])) 567 num_starts = 2; 568 else 569 num_starts = 0; 570 571 /* 572 * Paravirt / VMI wants a startup IPI hook here to set up the 573 * target processor state. 574 */ 575 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 576 stack_start); 577 578 /* 579 * Run STARTUP IPI loop. 580 */ 581 pr_debug("#startup loops: %d\n", num_starts); 582 583 for (j = 1; j <= num_starts; j++) { 584 pr_debug("Sending STARTUP #%d\n", j); 585 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 586 apic_write(APIC_ESR, 0); 587 apic_read(APIC_ESR); 588 pr_debug("After apic_write\n"); 589 590 /* 591 * STARTUP IPI 592 */ 593 594 /* Target chip */ 595 /* Boot on the stack */ 596 /* Kick the second */ 597 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 598 phys_apicid); 599 600 /* 601 * Give the other CPU some time to accept the IPI. 602 */ 603 udelay(300); 604 605 pr_debug("Startup point 1\n"); 606 607 pr_debug("Waiting for send to finish...\n"); 608 send_status = safe_apic_wait_icr_idle(); 609 610 /* 611 * Give the other CPU some time to accept the IPI. 612 */ 613 udelay(200); 614 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 615 apic_write(APIC_ESR, 0); 616 accept_status = (apic_read(APIC_ESR) & 0xEF); 617 if (send_status || accept_status) 618 break; 619 } 620 pr_debug("After Startup\n"); 621 622 if (send_status) 623 pr_err("APIC never delivered???\n"); 624 if (accept_status) 625 pr_err("APIC delivery error (%lx)\n", accept_status); 626 627 return (send_status | accept_status); 628 } 629 630 void smp_announce(void) 631 { 632 int num_nodes = num_online_nodes(); 633 634 printk(KERN_INFO "x86: Booted up %d node%s, %d CPUs\n", 635 num_nodes, (num_nodes > 1 ? "s" : ""), num_online_cpus()); 636 } 637 638 /* reduce the number of lines printed when booting a large cpu count system */ 639 static void announce_cpu(int cpu, int apicid) 640 { 641 static int current_node = -1; 642 int node = early_cpu_to_node(cpu); 643 static int width, node_width; 644 645 if (!width) 646 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 647 648 if (!node_width) 649 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 650 651 if (cpu == 1) 652 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 653 654 if (system_state == SYSTEM_BOOTING) { 655 if (node != current_node) { 656 if (current_node > (-1)) 657 pr_cont("\n"); 658 current_node = node; 659 660 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 661 node_width - num_digits(node), " ", node); 662 } 663 664 /* Add padding for the BSP */ 665 if (cpu == 1) 666 pr_cont("%*s", width + 1, " "); 667 668 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 669 670 } else 671 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 672 node, cpu, apicid); 673 } 674 675 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 676 { 677 int cpu; 678 679 cpu = smp_processor_id(); 680 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 681 return NMI_HANDLED; 682 683 return NMI_DONE; 684 } 685 686 /* 687 * Wake up AP by INIT, INIT, STARTUP sequence. 688 * 689 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 690 * boot-strap code which is not a desired behavior for waking up BSP. To 691 * void the boot-strap code, wake up CPU0 by NMI instead. 692 * 693 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 694 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 695 * We'll change this code in the future to wake up hard offlined CPU0 if 696 * real platform and request are available. 697 */ 698 static int 699 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 700 int *cpu0_nmi_registered) 701 { 702 int id; 703 int boot_error; 704 705 preempt_disable(); 706 707 /* 708 * Wake up AP by INIT, INIT, STARTUP sequence. 709 */ 710 if (cpu) { 711 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 712 goto out; 713 } 714 715 /* 716 * Wake up BSP by nmi. 717 * 718 * Register a NMI handler to help wake up CPU0. 719 */ 720 boot_error = register_nmi_handler(NMI_LOCAL, 721 wakeup_cpu0_nmi, 0, "wake_cpu0"); 722 723 if (!boot_error) { 724 enable_start_cpu0 = 1; 725 *cpu0_nmi_registered = 1; 726 if (apic->dest_logical == APIC_DEST_LOGICAL) 727 id = cpu0_logical_apicid; 728 else 729 id = apicid; 730 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 731 } 732 733 out: 734 preempt_enable(); 735 736 return boot_error; 737 } 738 739 /* 740 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 741 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 742 * Returns zero if CPU booted OK, else error code from 743 * ->wakeup_secondary_cpu. 744 */ 745 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 746 { 747 volatile u32 *trampoline_status = 748 (volatile u32 *) __va(real_mode_header->trampoline_status); 749 /* start_ip had better be page-aligned! */ 750 unsigned long start_ip = real_mode_header->trampoline_start; 751 752 unsigned long boot_error = 0; 753 int timeout; 754 int cpu0_nmi_registered = 0; 755 756 /* Just in case we booted with a single CPU. */ 757 alternatives_enable_smp(); 758 759 idle->thread.sp = (unsigned long) (((struct pt_regs *) 760 (THREAD_SIZE + task_stack_page(idle))) - 1); 761 per_cpu(current_task, cpu) = idle; 762 763 #ifdef CONFIG_X86_32 764 /* Stack for startup_32 can be just as for start_secondary onwards */ 765 irq_ctx_init(cpu); 766 #else 767 clear_tsk_thread_flag(idle, TIF_FORK); 768 initial_gs = per_cpu_offset(cpu); 769 #endif 770 per_cpu(kernel_stack, cpu) = 771 (unsigned long)task_stack_page(idle) - 772 KERNEL_STACK_OFFSET + THREAD_SIZE; 773 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 774 initial_code = (unsigned long)start_secondary; 775 stack_start = idle->thread.sp; 776 777 /* So we see what's up */ 778 announce_cpu(cpu, apicid); 779 780 /* 781 * This grunge runs the startup process for 782 * the targeted processor. 783 */ 784 785 atomic_set(&init_deasserted, 0); 786 787 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 788 789 pr_debug("Setting warm reset code and vector.\n"); 790 791 smpboot_setup_warm_reset_vector(start_ip); 792 /* 793 * Be paranoid about clearing APIC errors. 794 */ 795 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 796 apic_write(APIC_ESR, 0); 797 apic_read(APIC_ESR); 798 } 799 } 800 801 /* 802 * Wake up a CPU in difference cases: 803 * - Use the method in the APIC driver if it's defined 804 * Otherwise, 805 * - Use an INIT boot APIC message for APs or NMI for BSP. 806 */ 807 if (apic->wakeup_secondary_cpu) 808 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 809 else 810 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 811 &cpu0_nmi_registered); 812 813 if (!boot_error) { 814 /* 815 * allow APs to start initializing. 816 */ 817 pr_debug("Before Callout %d\n", cpu); 818 cpumask_set_cpu(cpu, cpu_callout_mask); 819 pr_debug("After Callout %d\n", cpu); 820 821 /* 822 * Wait 5s total for a response 823 */ 824 for (timeout = 0; timeout < 50000; timeout++) { 825 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 826 break; /* It has booted */ 827 udelay(100); 828 /* 829 * Allow other tasks to run while we wait for the 830 * AP to come online. This also gives a chance 831 * for the MTRR work(triggered by the AP coming online) 832 * to be completed in the stop machine context. 833 */ 834 schedule(); 835 } 836 837 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 838 print_cpu_msr(&cpu_data(cpu)); 839 pr_debug("CPU%d: has booted.\n", cpu); 840 } else { 841 boot_error = 1; 842 if (*trampoline_status == 0xA5A5A5A5) 843 /* trampoline started but...? */ 844 pr_err("CPU%d: Stuck ??\n", cpu); 845 else 846 /* trampoline code not run */ 847 pr_err("CPU%d: Not responding\n", cpu); 848 if (apic->inquire_remote_apic) 849 apic->inquire_remote_apic(apicid); 850 } 851 } 852 853 if (boot_error) { 854 /* Try to put things back the way they were before ... */ 855 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 856 857 /* was set by do_boot_cpu() */ 858 cpumask_clear_cpu(cpu, cpu_callout_mask); 859 860 /* was set by cpu_init() */ 861 cpumask_clear_cpu(cpu, cpu_initialized_mask); 862 863 set_cpu_present(cpu, false); 864 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 865 } 866 867 /* mark "stuck" area as not stuck */ 868 *trampoline_status = 0; 869 870 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 871 /* 872 * Cleanup possible dangling ends... 873 */ 874 smpboot_restore_warm_reset_vector(); 875 } 876 /* 877 * Clean up the nmi handler. Do this after the callin and callout sync 878 * to avoid impact of possible long unregister time. 879 */ 880 if (cpu0_nmi_registered) 881 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 882 883 return boot_error; 884 } 885 886 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 887 { 888 int apicid = apic->cpu_present_to_apicid(cpu); 889 unsigned long flags; 890 int err; 891 892 WARN_ON(irqs_disabled()); 893 894 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 895 896 if (apicid == BAD_APICID || 897 !physid_isset(apicid, phys_cpu_present_map) || 898 !apic->apic_id_valid(apicid)) { 899 pr_err("%s: bad cpu %d\n", __func__, cpu); 900 return -EINVAL; 901 } 902 903 /* 904 * Already booted CPU? 905 */ 906 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 907 pr_debug("do_boot_cpu %d Already started\n", cpu); 908 return -ENOSYS; 909 } 910 911 /* 912 * Save current MTRR state in case it was changed since early boot 913 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 914 */ 915 mtrr_save_state(); 916 917 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 918 919 /* the FPU context is blank, nobody can own it */ 920 __cpu_disable_lazy_restore(cpu); 921 922 err = do_boot_cpu(apicid, cpu, tidle); 923 if (err) { 924 pr_debug("do_boot_cpu failed %d\n", err); 925 return -EIO; 926 } 927 928 /* 929 * Check TSC synchronization with the AP (keep irqs disabled 930 * while doing so): 931 */ 932 local_irq_save(flags); 933 check_tsc_sync_source(cpu); 934 local_irq_restore(flags); 935 936 while (!cpu_online(cpu)) { 937 cpu_relax(); 938 touch_nmi_watchdog(); 939 } 940 941 return 0; 942 } 943 944 /** 945 * arch_disable_smp_support() - disables SMP support for x86 at runtime 946 */ 947 void arch_disable_smp_support(void) 948 { 949 disable_ioapic_support(); 950 } 951 952 /* 953 * Fall back to non SMP mode after errors. 954 * 955 * RED-PEN audit/test this more. I bet there is more state messed up here. 956 */ 957 static __init void disable_smp(void) 958 { 959 init_cpu_present(cpumask_of(0)); 960 init_cpu_possible(cpumask_of(0)); 961 smpboot_clear_io_apic_irqs(); 962 963 if (smp_found_config) 964 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 965 else 966 physid_set_mask_of_physid(0, &phys_cpu_present_map); 967 cpumask_set_cpu(0, cpu_sibling_mask(0)); 968 cpumask_set_cpu(0, cpu_core_mask(0)); 969 } 970 971 /* 972 * Various sanity checks. 973 */ 974 static int __init smp_sanity_check(unsigned max_cpus) 975 { 976 preempt_disable(); 977 978 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 979 if (def_to_bigsmp && nr_cpu_ids > 8) { 980 unsigned int cpu; 981 unsigned nr; 982 983 pr_warn("More than 8 CPUs detected - skipping them\n" 984 "Use CONFIG_X86_BIGSMP\n"); 985 986 nr = 0; 987 for_each_present_cpu(cpu) { 988 if (nr >= 8) 989 set_cpu_present(cpu, false); 990 nr++; 991 } 992 993 nr = 0; 994 for_each_possible_cpu(cpu) { 995 if (nr >= 8) 996 set_cpu_possible(cpu, false); 997 nr++; 998 } 999 1000 nr_cpu_ids = 8; 1001 } 1002 #endif 1003 1004 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1005 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1006 hard_smp_processor_id()); 1007 1008 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1009 } 1010 1011 /* 1012 * If we couldn't find an SMP configuration at boot time, 1013 * get out of here now! 1014 */ 1015 if (!smp_found_config && !acpi_lapic) { 1016 preempt_enable(); 1017 pr_notice("SMP motherboard not detected\n"); 1018 disable_smp(); 1019 if (APIC_init_uniprocessor()) 1020 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1021 return -1; 1022 } 1023 1024 /* 1025 * Should not be necessary because the MP table should list the boot 1026 * CPU too, but we do it for the sake of robustness anyway. 1027 */ 1028 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1029 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1030 boot_cpu_physical_apicid); 1031 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1032 } 1033 preempt_enable(); 1034 1035 /* 1036 * If we couldn't find a local APIC, then get out of here now! 1037 */ 1038 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 1039 !cpu_has_apic) { 1040 if (!disable_apic) { 1041 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1042 boot_cpu_physical_apicid); 1043 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1044 } 1045 smpboot_clear_io_apic(); 1046 disable_ioapic_support(); 1047 return -1; 1048 } 1049 1050 verify_local_APIC(); 1051 1052 /* 1053 * If SMP should be disabled, then really disable it! 1054 */ 1055 if (!max_cpus) { 1056 pr_info("SMP mode deactivated\n"); 1057 smpboot_clear_io_apic(); 1058 1059 connect_bsp_APIC(); 1060 setup_local_APIC(); 1061 bsp_end_local_APIC_setup(); 1062 return -1; 1063 } 1064 1065 return 0; 1066 } 1067 1068 static void __init smp_cpu_index_default(void) 1069 { 1070 int i; 1071 struct cpuinfo_x86 *c; 1072 1073 for_each_possible_cpu(i) { 1074 c = &cpu_data(i); 1075 /* mark all to hotplug */ 1076 c->cpu_index = nr_cpu_ids; 1077 } 1078 } 1079 1080 /* 1081 * Prepare for SMP bootup. The MP table or ACPI has been read 1082 * earlier. Just do some sanity checking here and enable APIC mode. 1083 */ 1084 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1085 { 1086 unsigned int i; 1087 1088 preempt_disable(); 1089 smp_cpu_index_default(); 1090 1091 /* 1092 * Setup boot CPU information 1093 */ 1094 smp_store_boot_cpu_info(); /* Final full version of the data */ 1095 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1096 mb(); 1097 1098 current_thread_info()->cpu = 0; /* needed? */ 1099 for_each_possible_cpu(i) { 1100 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1101 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1102 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1103 } 1104 set_cpu_sibling_map(0); 1105 1106 1107 if (smp_sanity_check(max_cpus) < 0) { 1108 pr_info("SMP disabled\n"); 1109 disable_smp(); 1110 goto out; 1111 } 1112 1113 default_setup_apic_routing(); 1114 1115 preempt_disable(); 1116 if (read_apic_id() != boot_cpu_physical_apicid) { 1117 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1118 read_apic_id(), boot_cpu_physical_apicid); 1119 /* Or can we switch back to PIC here? */ 1120 } 1121 preempt_enable(); 1122 1123 connect_bsp_APIC(); 1124 1125 /* 1126 * Switch from PIC to APIC mode. 1127 */ 1128 setup_local_APIC(); 1129 1130 if (x2apic_mode) 1131 cpu0_logical_apicid = apic_read(APIC_LDR); 1132 else 1133 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1134 1135 /* 1136 * Enable IO APIC before setting up error vector 1137 */ 1138 if (!skip_ioapic_setup && nr_ioapics) 1139 enable_IO_APIC(); 1140 1141 bsp_end_local_APIC_setup(); 1142 1143 if (apic->setup_portio_remap) 1144 apic->setup_portio_remap(); 1145 1146 smpboot_setup_io_apic(); 1147 /* 1148 * Set up local APIC timer on boot CPU. 1149 */ 1150 1151 pr_info("CPU%d: ", 0); 1152 print_cpu_info(&cpu_data(0)); 1153 x86_init.timers.setup_percpu_clockev(); 1154 1155 if (is_uv_system()) 1156 uv_system_init(); 1157 1158 set_mtrr_aps_delayed_init(); 1159 out: 1160 preempt_enable(); 1161 } 1162 1163 void arch_enable_nonboot_cpus_begin(void) 1164 { 1165 set_mtrr_aps_delayed_init(); 1166 } 1167 1168 void arch_enable_nonboot_cpus_end(void) 1169 { 1170 mtrr_aps_init(); 1171 } 1172 1173 /* 1174 * Early setup to make printk work. 1175 */ 1176 void __init native_smp_prepare_boot_cpu(void) 1177 { 1178 int me = smp_processor_id(); 1179 switch_to_new_gdt(me); 1180 /* already set me in cpu_online_mask in boot_cpu_init() */ 1181 cpumask_set_cpu(me, cpu_callout_mask); 1182 per_cpu(cpu_state, me) = CPU_ONLINE; 1183 } 1184 1185 void __init native_smp_cpus_done(unsigned int max_cpus) 1186 { 1187 pr_debug("Boot done\n"); 1188 1189 nmi_selftest(); 1190 impress_friends(); 1191 #ifdef CONFIG_X86_IO_APIC 1192 setup_ioapic_dest(); 1193 #endif 1194 mtrr_aps_init(); 1195 } 1196 1197 static int __initdata setup_possible_cpus = -1; 1198 static int __init _setup_possible_cpus(char *str) 1199 { 1200 get_option(&str, &setup_possible_cpus); 1201 return 0; 1202 } 1203 early_param("possible_cpus", _setup_possible_cpus); 1204 1205 1206 /* 1207 * cpu_possible_mask should be static, it cannot change as cpu's 1208 * are onlined, or offlined. The reason is per-cpu data-structures 1209 * are allocated by some modules at init time, and dont expect to 1210 * do this dynamically on cpu arrival/departure. 1211 * cpu_present_mask on the other hand can change dynamically. 1212 * In case when cpu_hotplug is not compiled, then we resort to current 1213 * behaviour, which is cpu_possible == cpu_present. 1214 * - Ashok Raj 1215 * 1216 * Three ways to find out the number of additional hotplug CPUs: 1217 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1218 * - The user can overwrite it with possible_cpus=NUM 1219 * - Otherwise don't reserve additional CPUs. 1220 * We do this because additional CPUs waste a lot of memory. 1221 * -AK 1222 */ 1223 __init void prefill_possible_map(void) 1224 { 1225 int i, possible; 1226 1227 /* no processor from mptable or madt */ 1228 if (!num_processors) 1229 num_processors = 1; 1230 1231 i = setup_max_cpus ?: 1; 1232 if (setup_possible_cpus == -1) { 1233 possible = num_processors; 1234 #ifdef CONFIG_HOTPLUG_CPU 1235 if (setup_max_cpus) 1236 possible += disabled_cpus; 1237 #else 1238 if (possible > i) 1239 possible = i; 1240 #endif 1241 } else 1242 possible = setup_possible_cpus; 1243 1244 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1245 1246 /* nr_cpu_ids could be reduced via nr_cpus= */ 1247 if (possible > nr_cpu_ids) { 1248 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1249 possible, nr_cpu_ids); 1250 possible = nr_cpu_ids; 1251 } 1252 1253 #ifdef CONFIG_HOTPLUG_CPU 1254 if (!setup_max_cpus) 1255 #endif 1256 if (possible > i) { 1257 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1258 possible, setup_max_cpus); 1259 possible = i; 1260 } 1261 1262 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1263 possible, max_t(int, possible - num_processors, 0)); 1264 1265 for (i = 0; i < possible; i++) 1266 set_cpu_possible(i, true); 1267 for (; i < NR_CPUS; i++) 1268 set_cpu_possible(i, false); 1269 1270 nr_cpu_ids = possible; 1271 } 1272 1273 #ifdef CONFIG_HOTPLUG_CPU 1274 1275 static void remove_siblinginfo(int cpu) 1276 { 1277 int sibling; 1278 struct cpuinfo_x86 *c = &cpu_data(cpu); 1279 1280 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1281 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1282 /*/ 1283 * last thread sibling in this cpu core going down 1284 */ 1285 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1286 cpu_data(sibling).booted_cores--; 1287 } 1288 1289 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1290 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1291 cpumask_clear(cpu_sibling_mask(cpu)); 1292 cpumask_clear(cpu_core_mask(cpu)); 1293 c->phys_proc_id = 0; 1294 c->cpu_core_id = 0; 1295 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1296 } 1297 1298 static void __ref remove_cpu_from_maps(int cpu) 1299 { 1300 set_cpu_online(cpu, false); 1301 cpumask_clear_cpu(cpu, cpu_callout_mask); 1302 cpumask_clear_cpu(cpu, cpu_callin_mask); 1303 /* was set by cpu_init() */ 1304 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1305 numa_remove_cpu(cpu); 1306 } 1307 1308 void cpu_disable_common(void) 1309 { 1310 int cpu = smp_processor_id(); 1311 1312 remove_siblinginfo(cpu); 1313 1314 /* It's now safe to remove this processor from the online map */ 1315 lock_vector_lock(); 1316 remove_cpu_from_maps(cpu); 1317 unlock_vector_lock(); 1318 fixup_irqs(); 1319 } 1320 1321 int native_cpu_disable(void) 1322 { 1323 int ret; 1324 1325 ret = check_irq_vectors_for_cpu_disable(); 1326 if (ret) 1327 return ret; 1328 1329 clear_local_APIC(); 1330 1331 cpu_disable_common(); 1332 return 0; 1333 } 1334 1335 void native_cpu_die(unsigned int cpu) 1336 { 1337 /* We don't do anything here: idle task is faking death itself. */ 1338 unsigned int i; 1339 1340 for (i = 0; i < 10; i++) { 1341 /* They ack this in play_dead by setting CPU_DEAD */ 1342 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1343 if (system_state == SYSTEM_RUNNING) 1344 pr_info("CPU %u is now offline\n", cpu); 1345 return; 1346 } 1347 msleep(100); 1348 } 1349 pr_err("CPU %u didn't die...\n", cpu); 1350 } 1351 1352 void play_dead_common(void) 1353 { 1354 idle_task_exit(); 1355 reset_lazy_tlbstate(); 1356 amd_e400_remove_cpu(raw_smp_processor_id()); 1357 1358 mb(); 1359 /* Ack it */ 1360 __this_cpu_write(cpu_state, CPU_DEAD); 1361 1362 /* 1363 * With physical CPU hotplug, we should halt the cpu 1364 */ 1365 local_irq_disable(); 1366 } 1367 1368 static bool wakeup_cpu0(void) 1369 { 1370 if (smp_processor_id() == 0 && enable_start_cpu0) 1371 return true; 1372 1373 return false; 1374 } 1375 1376 /* 1377 * We need to flush the caches before going to sleep, lest we have 1378 * dirty data in our caches when we come back up. 1379 */ 1380 static inline void mwait_play_dead(void) 1381 { 1382 unsigned int eax, ebx, ecx, edx; 1383 unsigned int highest_cstate = 0; 1384 unsigned int highest_subcstate = 0; 1385 void *mwait_ptr; 1386 int i; 1387 1388 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1389 return; 1390 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1391 return; 1392 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1393 return; 1394 1395 eax = CPUID_MWAIT_LEAF; 1396 ecx = 0; 1397 native_cpuid(&eax, &ebx, &ecx, &edx); 1398 1399 /* 1400 * eax will be 0 if EDX enumeration is not valid. 1401 * Initialized below to cstate, sub_cstate value when EDX is valid. 1402 */ 1403 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1404 eax = 0; 1405 } else { 1406 edx >>= MWAIT_SUBSTATE_SIZE; 1407 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1408 if (edx & MWAIT_SUBSTATE_MASK) { 1409 highest_cstate = i; 1410 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1411 } 1412 } 1413 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1414 (highest_subcstate - 1); 1415 } 1416 1417 /* 1418 * This should be a memory location in a cache line which is 1419 * unlikely to be touched by other processors. The actual 1420 * content is immaterial as it is not actually modified in any way. 1421 */ 1422 mwait_ptr = ¤t_thread_info()->flags; 1423 1424 wbinvd(); 1425 1426 while (1) { 1427 /* 1428 * The CLFLUSH is a workaround for erratum AAI65 for 1429 * the Xeon 7400 series. It's not clear it is actually 1430 * needed, but it should be harmless in either case. 1431 * The WBINVD is insufficient due to the spurious-wakeup 1432 * case where we return around the loop. 1433 */ 1434 mb(); 1435 clflush(mwait_ptr); 1436 mb(); 1437 __monitor(mwait_ptr, 0, 0); 1438 mb(); 1439 __mwait(eax, 0); 1440 /* 1441 * If NMI wants to wake up CPU0, start CPU0. 1442 */ 1443 if (wakeup_cpu0()) 1444 start_cpu0(); 1445 } 1446 } 1447 1448 static inline void hlt_play_dead(void) 1449 { 1450 if (__this_cpu_read(cpu_info.x86) >= 4) 1451 wbinvd(); 1452 1453 while (1) { 1454 native_halt(); 1455 /* 1456 * If NMI wants to wake up CPU0, start CPU0. 1457 */ 1458 if (wakeup_cpu0()) 1459 start_cpu0(); 1460 } 1461 } 1462 1463 void native_play_dead(void) 1464 { 1465 play_dead_common(); 1466 tboot_shutdown(TB_SHUTDOWN_WFS); 1467 1468 mwait_play_dead(); /* Only returns on failure */ 1469 if (cpuidle_play_dead()) 1470 hlt_play_dead(); 1471 } 1472 1473 #else /* ... !CONFIG_HOTPLUG_CPU */ 1474 int native_cpu_disable(void) 1475 { 1476 return -ENOSYS; 1477 } 1478 1479 void native_cpu_die(unsigned int cpu) 1480 { 1481 /* We said "no" in __cpu_disable */ 1482 BUG(); 1483 } 1484 1485 void native_play_dead(void) 1486 { 1487 BUG(); 1488 } 1489 1490 #endif 1491