1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/module.h> 45 #include <linux/sched.h> 46 #include <linux/percpu.h> 47 #include <linux/bootmem.h> 48 #include <linux/err.h> 49 #include <linux/nmi.h> 50 #include <linux/tboot.h> 51 #include <linux/stackprotector.h> 52 #include <linux/gfp.h> 53 54 #include <asm/acpi.h> 55 #include <asm/desc.h> 56 #include <asm/nmi.h> 57 #include <asm/irq.h> 58 #include <asm/idle.h> 59 #include <asm/trampoline.h> 60 #include <asm/cpu.h> 61 #include <asm/numa.h> 62 #include <asm/pgtable.h> 63 #include <asm/tlbflush.h> 64 #include <asm/mtrr.h> 65 #include <asm/mwait.h> 66 #include <asm/apic.h> 67 #include <asm/io_apic.h> 68 #include <asm/setup.h> 69 #include <asm/uv/uv.h> 70 #include <linux/mc146818rtc.h> 71 72 #include <asm/smpboot_hooks.h> 73 #include <asm/i8259.h> 74 75 /* State of each CPU */ 76 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 77 78 /* Store all idle threads, this can be reused instead of creating 79 * a new thread. Also avoids complicated thread destroy functionality 80 * for idle threads. 81 */ 82 #ifdef CONFIG_HOTPLUG_CPU 83 /* 84 * Needed only for CONFIG_HOTPLUG_CPU because __cpuinitdata is 85 * removed after init for !CONFIG_HOTPLUG_CPU. 86 */ 87 static DEFINE_PER_CPU(struct task_struct *, idle_thread_array); 88 #define get_idle_for_cpu(x) (per_cpu(idle_thread_array, x)) 89 #define set_idle_for_cpu(x, p) (per_cpu(idle_thread_array, x) = (p)) 90 91 /* 92 * We need this for trampoline_base protection from concurrent accesses when 93 * off- and onlining cores wildly. 94 */ 95 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 96 97 void cpu_hotplug_driver_lock(void) 98 { 99 mutex_lock(&x86_cpu_hotplug_driver_mutex); 100 } 101 102 void cpu_hotplug_driver_unlock(void) 103 { 104 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 105 } 106 107 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 108 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 109 #else 110 static struct task_struct *idle_thread_array[NR_CPUS] __cpuinitdata ; 111 #define get_idle_for_cpu(x) (idle_thread_array[(x)]) 112 #define set_idle_for_cpu(x, p) (idle_thread_array[(x)] = (p)) 113 #endif 114 115 /* Number of siblings per CPU package */ 116 int smp_num_siblings = 1; 117 EXPORT_SYMBOL(smp_num_siblings); 118 119 /* Last level cache ID of each logical CPU */ 120 DEFINE_PER_CPU(u16, cpu_llc_id) = BAD_APICID; 121 122 /* representing HT siblings of each logical CPU */ 123 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map); 124 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 125 126 /* representing HT and core siblings of each logical CPU */ 127 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map); 128 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 129 130 DEFINE_PER_CPU(cpumask_var_t, cpu_llc_shared_map); 131 132 /* Per CPU bogomips and other parameters */ 133 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 134 EXPORT_PER_CPU_SYMBOL(cpu_info); 135 136 atomic_t init_deasserted; 137 138 /* 139 * Report back to the Boot Processor. 140 * Running on AP. 141 */ 142 static void __cpuinit smp_callin(void) 143 { 144 int cpuid, phys_id; 145 unsigned long timeout; 146 147 /* 148 * If waken up by an INIT in an 82489DX configuration 149 * we may get here before an INIT-deassert IPI reaches 150 * our local APIC. We have to wait for the IPI or we'll 151 * lock up on an APIC access. 152 */ 153 if (apic->wait_for_init_deassert) 154 apic->wait_for_init_deassert(&init_deasserted); 155 156 /* 157 * (This works even if the APIC is not enabled.) 158 */ 159 phys_id = read_apic_id(); 160 cpuid = smp_processor_id(); 161 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 162 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 163 phys_id, cpuid); 164 } 165 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 166 167 /* 168 * STARTUP IPIs are fragile beasts as they might sometimes 169 * trigger some glue motherboard logic. Complete APIC bus 170 * silence for 1 second, this overestimates the time the 171 * boot CPU is spending to send the up to 2 STARTUP IPIs 172 * by a factor of two. This should be enough. 173 */ 174 175 /* 176 * Waiting 2s total for startup (udelay is not yet working) 177 */ 178 timeout = jiffies + 2*HZ; 179 while (time_before(jiffies, timeout)) { 180 /* 181 * Has the boot CPU finished it's STARTUP sequence? 182 */ 183 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 184 break; 185 cpu_relax(); 186 } 187 188 if (!time_before(jiffies, timeout)) { 189 panic("%s: CPU%d started up but did not get a callout!\n", 190 __func__, cpuid); 191 } 192 193 /* 194 * the boot CPU has finished the init stage and is spinning 195 * on callin_map until we finish. We are free to set up this 196 * CPU, first the APIC. (this is probably redundant on most 197 * boards) 198 */ 199 200 pr_debug("CALLIN, before setup_local_APIC().\n"); 201 if (apic->smp_callin_clear_local_apic) 202 apic->smp_callin_clear_local_apic(); 203 setup_local_APIC(); 204 end_local_APIC_setup(); 205 206 /* 207 * Need to setup vector mappings before we enable interrupts. 208 */ 209 setup_vector_irq(smp_processor_id()); 210 211 /* 212 * Save our processor parameters. Note: this information 213 * is needed for clock calibration. 214 */ 215 smp_store_cpu_info(cpuid); 216 217 /* 218 * Get our bogomips. 219 * Update loops_per_jiffy in cpu_data. Previous call to 220 * smp_store_cpu_info() stored a value that is close but not as 221 * accurate as the value just calculated. 222 * 223 * Need to enable IRQs because it can take longer and then 224 * the NMI watchdog might kill us. 225 */ 226 local_irq_enable(); 227 calibrate_delay(); 228 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 229 local_irq_disable(); 230 pr_debug("Stack at about %p\n", &cpuid); 231 232 /* 233 * This must be done before setting cpu_online_mask 234 * or calling notify_cpu_starting. 235 */ 236 set_cpu_sibling_map(raw_smp_processor_id()); 237 wmb(); 238 239 notify_cpu_starting(cpuid); 240 241 /* 242 * Allow the master to continue. 243 */ 244 cpumask_set_cpu(cpuid, cpu_callin_mask); 245 } 246 247 /* 248 * Activate a secondary processor. 249 */ 250 notrace static void __cpuinit start_secondary(void *unused) 251 { 252 /* 253 * Don't put *anything* before cpu_init(), SMP booting is too 254 * fragile that we want to limit the things done here to the 255 * most necessary things. 256 */ 257 cpu_init(); 258 preempt_disable(); 259 smp_callin(); 260 261 #ifdef CONFIG_X86_32 262 /* switch away from the initial page table */ 263 load_cr3(swapper_pg_dir); 264 __flush_tlb_all(); 265 #endif 266 267 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 268 barrier(); 269 /* 270 * Check TSC synchronization with the BP: 271 */ 272 check_tsc_sync_target(); 273 274 /* 275 * We need to hold call_lock, so there is no inconsistency 276 * between the time smp_call_function() determines number of 277 * IPI recipients, and the time when the determination is made 278 * for which cpus receive the IPI. Holding this 279 * lock helps us to not include this cpu in a currently in progress 280 * smp_call_function(). 281 * 282 * We need to hold vector_lock so there the set of online cpus 283 * does not change while we are assigning vectors to cpus. Holding 284 * this lock ensures we don't half assign or remove an irq from a cpu. 285 */ 286 ipi_call_lock(); 287 lock_vector_lock(); 288 set_cpu_online(smp_processor_id(), true); 289 unlock_vector_lock(); 290 ipi_call_unlock(); 291 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 292 x86_platform.nmi_init(); 293 294 /* 295 * Wait until the cpu which brought this one up marked it 296 * online before enabling interrupts. If we don't do that then 297 * we can end up waking up the softirq thread before this cpu 298 * reached the active state, which makes the scheduler unhappy 299 * and schedule the softirq thread on the wrong cpu. This is 300 * only observable with forced threaded interrupts, but in 301 * theory it could also happen w/o them. It's just way harder 302 * to achieve. 303 */ 304 while (!cpumask_test_cpu(smp_processor_id(), cpu_active_mask)) 305 cpu_relax(); 306 307 /* enable local interrupts */ 308 local_irq_enable(); 309 310 /* to prevent fake stack check failure in clock setup */ 311 boot_init_stack_canary(); 312 313 x86_cpuinit.setup_percpu_clockev(); 314 315 wmb(); 316 cpu_idle(); 317 } 318 319 /* 320 * The bootstrap kernel entry code has set these up. Save them for 321 * a given CPU 322 */ 323 324 void __cpuinit smp_store_cpu_info(int id) 325 { 326 struct cpuinfo_x86 *c = &cpu_data(id); 327 328 *c = boot_cpu_data; 329 c->cpu_index = id; 330 if (id != 0) 331 identify_secondary_cpu(c); 332 } 333 334 static void __cpuinit link_thread_siblings(int cpu1, int cpu2) 335 { 336 cpumask_set_cpu(cpu1, cpu_sibling_mask(cpu2)); 337 cpumask_set_cpu(cpu2, cpu_sibling_mask(cpu1)); 338 cpumask_set_cpu(cpu1, cpu_core_mask(cpu2)); 339 cpumask_set_cpu(cpu2, cpu_core_mask(cpu1)); 340 cpumask_set_cpu(cpu1, cpu_llc_shared_mask(cpu2)); 341 cpumask_set_cpu(cpu2, cpu_llc_shared_mask(cpu1)); 342 } 343 344 345 void __cpuinit set_cpu_sibling_map(int cpu) 346 { 347 int i; 348 struct cpuinfo_x86 *c = &cpu_data(cpu); 349 350 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 351 352 if (smp_num_siblings > 1) { 353 for_each_cpu(i, cpu_sibling_setup_mask) { 354 struct cpuinfo_x86 *o = &cpu_data(i); 355 356 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 357 if (c->phys_proc_id == o->phys_proc_id && 358 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i) && 359 c->compute_unit_id == o->compute_unit_id) 360 link_thread_siblings(cpu, i); 361 } else if (c->phys_proc_id == o->phys_proc_id && 362 c->cpu_core_id == o->cpu_core_id) { 363 link_thread_siblings(cpu, i); 364 } 365 } 366 } else { 367 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 368 } 369 370 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 371 372 if (__this_cpu_read(cpu_info.x86_max_cores) == 1) { 373 cpumask_copy(cpu_core_mask(cpu), cpu_sibling_mask(cpu)); 374 c->booted_cores = 1; 375 return; 376 } 377 378 for_each_cpu(i, cpu_sibling_setup_mask) { 379 if (per_cpu(cpu_llc_id, cpu) != BAD_APICID && 380 per_cpu(cpu_llc_id, cpu) == per_cpu(cpu_llc_id, i)) { 381 cpumask_set_cpu(i, cpu_llc_shared_mask(cpu)); 382 cpumask_set_cpu(cpu, cpu_llc_shared_mask(i)); 383 } 384 if (c->phys_proc_id == cpu_data(i).phys_proc_id) { 385 cpumask_set_cpu(i, cpu_core_mask(cpu)); 386 cpumask_set_cpu(cpu, cpu_core_mask(i)); 387 /* 388 * Does this new cpu bringup a new core? 389 */ 390 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 391 /* 392 * for each core in package, increment 393 * the booted_cores for this new cpu 394 */ 395 if (cpumask_first(cpu_sibling_mask(i)) == i) 396 c->booted_cores++; 397 /* 398 * increment the core count for all 399 * the other cpus in this package 400 */ 401 if (i != cpu) 402 cpu_data(i).booted_cores++; 403 } else if (i != cpu && !c->booted_cores) 404 c->booted_cores = cpu_data(i).booted_cores; 405 } 406 } 407 } 408 409 /* maps the cpu to the sched domain representing multi-core */ 410 const struct cpumask *cpu_coregroup_mask(int cpu) 411 { 412 struct cpuinfo_x86 *c = &cpu_data(cpu); 413 /* 414 * For perf, we return last level cache shared map. 415 * And for power savings, we return cpu_core_map 416 */ 417 if ((sched_mc_power_savings || sched_smt_power_savings) && 418 !(cpu_has(c, X86_FEATURE_AMD_DCM))) 419 return cpu_core_mask(cpu); 420 else 421 return cpu_llc_shared_mask(cpu); 422 } 423 424 static void impress_friends(void) 425 { 426 int cpu; 427 unsigned long bogosum = 0; 428 /* 429 * Allow the user to impress friends. 430 */ 431 pr_debug("Before bogomips.\n"); 432 for_each_possible_cpu(cpu) 433 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 434 bogosum += cpu_data(cpu).loops_per_jiffy; 435 printk(KERN_INFO 436 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n", 437 num_online_cpus(), 438 bogosum/(500000/HZ), 439 (bogosum/(5000/HZ))%100); 440 441 pr_debug("Before bogocount - setting activated=1.\n"); 442 } 443 444 void __inquire_remote_apic(int apicid) 445 { 446 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 447 const char * const names[] = { "ID", "VERSION", "SPIV" }; 448 int timeout; 449 u32 status; 450 451 printk(KERN_INFO "Inquiring remote APIC 0x%x...\n", apicid); 452 453 for (i = 0; i < ARRAY_SIZE(regs); i++) { 454 printk(KERN_INFO "... APIC 0x%x %s: ", apicid, names[i]); 455 456 /* 457 * Wait for idle. 458 */ 459 status = safe_apic_wait_icr_idle(); 460 if (status) 461 printk(KERN_CONT 462 "a previous APIC delivery may have failed\n"); 463 464 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 465 466 timeout = 0; 467 do { 468 udelay(100); 469 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 470 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 471 472 switch (status) { 473 case APIC_ICR_RR_VALID: 474 status = apic_read(APIC_RRR); 475 printk(KERN_CONT "%08x\n", status); 476 break; 477 default: 478 printk(KERN_CONT "failed\n"); 479 } 480 } 481 } 482 483 /* 484 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 485 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 486 * won't ... remember to clear down the APIC, etc later. 487 */ 488 int __cpuinit 489 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 490 { 491 unsigned long send_status, accept_status = 0; 492 int maxlvt; 493 494 /* Target chip */ 495 /* Boot on the stack */ 496 /* Kick the second */ 497 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 498 499 pr_debug("Waiting for send to finish...\n"); 500 send_status = safe_apic_wait_icr_idle(); 501 502 /* 503 * Give the other CPU some time to accept the IPI. 504 */ 505 udelay(200); 506 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 507 maxlvt = lapic_get_maxlvt(); 508 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 509 apic_write(APIC_ESR, 0); 510 accept_status = (apic_read(APIC_ESR) & 0xEF); 511 } 512 pr_debug("NMI sent.\n"); 513 514 if (send_status) 515 printk(KERN_ERR "APIC never delivered???\n"); 516 if (accept_status) 517 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 518 519 return (send_status | accept_status); 520 } 521 522 static int __cpuinit 523 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 524 { 525 unsigned long send_status, accept_status = 0; 526 int maxlvt, num_starts, j; 527 528 maxlvt = lapic_get_maxlvt(); 529 530 /* 531 * Be paranoid about clearing APIC errors. 532 */ 533 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 534 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 535 apic_write(APIC_ESR, 0); 536 apic_read(APIC_ESR); 537 } 538 539 pr_debug("Asserting INIT.\n"); 540 541 /* 542 * Turn INIT on target chip 543 */ 544 /* 545 * Send IPI 546 */ 547 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 548 phys_apicid); 549 550 pr_debug("Waiting for send to finish...\n"); 551 send_status = safe_apic_wait_icr_idle(); 552 553 mdelay(10); 554 555 pr_debug("Deasserting INIT.\n"); 556 557 /* Target chip */ 558 /* Send IPI */ 559 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 560 561 pr_debug("Waiting for send to finish...\n"); 562 send_status = safe_apic_wait_icr_idle(); 563 564 mb(); 565 atomic_set(&init_deasserted, 1); 566 567 /* 568 * Should we send STARTUP IPIs ? 569 * 570 * Determine this based on the APIC version. 571 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 572 */ 573 if (APIC_INTEGRATED(apic_version[phys_apicid])) 574 num_starts = 2; 575 else 576 num_starts = 0; 577 578 /* 579 * Paravirt / VMI wants a startup IPI hook here to set up the 580 * target processor state. 581 */ 582 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 583 stack_start); 584 585 /* 586 * Run STARTUP IPI loop. 587 */ 588 pr_debug("#startup loops: %d.\n", num_starts); 589 590 for (j = 1; j <= num_starts; j++) { 591 pr_debug("Sending STARTUP #%d.\n", j); 592 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 593 apic_write(APIC_ESR, 0); 594 apic_read(APIC_ESR); 595 pr_debug("After apic_write.\n"); 596 597 /* 598 * STARTUP IPI 599 */ 600 601 /* Target chip */ 602 /* Boot on the stack */ 603 /* Kick the second */ 604 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 605 phys_apicid); 606 607 /* 608 * Give the other CPU some time to accept the IPI. 609 */ 610 udelay(300); 611 612 pr_debug("Startup point 1.\n"); 613 614 pr_debug("Waiting for send to finish...\n"); 615 send_status = safe_apic_wait_icr_idle(); 616 617 /* 618 * Give the other CPU some time to accept the IPI. 619 */ 620 udelay(200); 621 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 622 apic_write(APIC_ESR, 0); 623 accept_status = (apic_read(APIC_ESR) & 0xEF); 624 if (send_status || accept_status) 625 break; 626 } 627 pr_debug("After Startup.\n"); 628 629 if (send_status) 630 printk(KERN_ERR "APIC never delivered???\n"); 631 if (accept_status) 632 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status); 633 634 return (send_status | accept_status); 635 } 636 637 struct create_idle { 638 struct work_struct work; 639 struct task_struct *idle; 640 struct completion done; 641 int cpu; 642 }; 643 644 static void __cpuinit do_fork_idle(struct work_struct *work) 645 { 646 struct create_idle *c_idle = 647 container_of(work, struct create_idle, work); 648 649 c_idle->idle = fork_idle(c_idle->cpu); 650 complete(&c_idle->done); 651 } 652 653 /* reduce the number of lines printed when booting a large cpu count system */ 654 static void __cpuinit announce_cpu(int cpu, int apicid) 655 { 656 static int current_node = -1; 657 int node = early_cpu_to_node(cpu); 658 659 if (system_state == SYSTEM_BOOTING) { 660 if (node != current_node) { 661 if (current_node > (-1)) 662 pr_cont(" Ok.\n"); 663 current_node = node; 664 pr_info("Booting Node %3d, Processors ", node); 665 } 666 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " Ok.\n" : ""); 667 return; 668 } else 669 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 670 node, cpu, apicid); 671 } 672 673 /* 674 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 675 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 676 * Returns zero if CPU booted OK, else error code from 677 * ->wakeup_secondary_cpu. 678 */ 679 static int __cpuinit do_boot_cpu(int apicid, int cpu) 680 { 681 unsigned long boot_error = 0; 682 unsigned long start_ip; 683 int timeout; 684 struct create_idle c_idle = { 685 .cpu = cpu, 686 .done = COMPLETION_INITIALIZER_ONSTACK(c_idle.done), 687 }; 688 689 INIT_WORK_ONSTACK(&c_idle.work, do_fork_idle); 690 691 alternatives_smp_switch(1); 692 693 c_idle.idle = get_idle_for_cpu(cpu); 694 695 /* 696 * We can't use kernel_thread since we must avoid to 697 * reschedule the child. 698 */ 699 if (c_idle.idle) { 700 c_idle.idle->thread.sp = (unsigned long) (((struct pt_regs *) 701 (THREAD_SIZE + task_stack_page(c_idle.idle))) - 1); 702 init_idle(c_idle.idle, cpu); 703 goto do_rest; 704 } 705 706 schedule_work(&c_idle.work); 707 wait_for_completion(&c_idle.done); 708 709 if (IS_ERR(c_idle.idle)) { 710 printk("failed fork for CPU %d\n", cpu); 711 destroy_work_on_stack(&c_idle.work); 712 return PTR_ERR(c_idle.idle); 713 } 714 715 set_idle_for_cpu(cpu, c_idle.idle); 716 do_rest: 717 per_cpu(current_task, cpu) = c_idle.idle; 718 #ifdef CONFIG_X86_32 719 /* Stack for startup_32 can be just as for start_secondary onwards */ 720 irq_ctx_init(cpu); 721 #else 722 clear_tsk_thread_flag(c_idle.idle, TIF_FORK); 723 initial_gs = per_cpu_offset(cpu); 724 per_cpu(kernel_stack, cpu) = 725 (unsigned long)task_stack_page(c_idle.idle) - 726 KERNEL_STACK_OFFSET + THREAD_SIZE; 727 #endif 728 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 729 initial_code = (unsigned long)start_secondary; 730 stack_start = c_idle.idle->thread.sp; 731 732 /* start_ip had better be page-aligned! */ 733 start_ip = trampoline_address(); 734 735 /* So we see what's up */ 736 announce_cpu(cpu, apicid); 737 738 /* 739 * This grunge runs the startup process for 740 * the targeted processor. 741 */ 742 743 printk(KERN_DEBUG "smpboot cpu %d: start_ip = %lx\n", cpu, start_ip); 744 745 atomic_set(&init_deasserted, 0); 746 747 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 748 749 pr_debug("Setting warm reset code and vector.\n"); 750 751 smpboot_setup_warm_reset_vector(start_ip); 752 /* 753 * Be paranoid about clearing APIC errors. 754 */ 755 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 756 apic_write(APIC_ESR, 0); 757 apic_read(APIC_ESR); 758 } 759 } 760 761 /* 762 * Kick the secondary CPU. Use the method in the APIC driver 763 * if it's defined - or use an INIT boot APIC message otherwise: 764 */ 765 if (apic->wakeup_secondary_cpu) 766 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 767 else 768 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 769 770 if (!boot_error) { 771 /* 772 * allow APs to start initializing. 773 */ 774 pr_debug("Before Callout %d.\n", cpu); 775 cpumask_set_cpu(cpu, cpu_callout_mask); 776 pr_debug("After Callout %d.\n", cpu); 777 778 /* 779 * Wait 5s total for a response 780 */ 781 for (timeout = 0; timeout < 50000; timeout++) { 782 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 783 break; /* It has booted */ 784 udelay(100); 785 /* 786 * Allow other tasks to run while we wait for the 787 * AP to come online. This also gives a chance 788 * for the MTRR work(triggered by the AP coming online) 789 * to be completed in the stop machine context. 790 */ 791 schedule(); 792 } 793 794 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 795 pr_debug("CPU%d: has booted.\n", cpu); 796 else { 797 boot_error = 1; 798 if (*(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) 799 == 0xA5A5A5A5) 800 /* trampoline started but...? */ 801 pr_err("CPU%d: Stuck ??\n", cpu); 802 else 803 /* trampoline code not run */ 804 pr_err("CPU%d: Not responding.\n", cpu); 805 if (apic->inquire_remote_apic) 806 apic->inquire_remote_apic(apicid); 807 } 808 } 809 810 if (boot_error) { 811 /* Try to put things back the way they were before ... */ 812 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 813 814 /* was set by do_boot_cpu() */ 815 cpumask_clear_cpu(cpu, cpu_callout_mask); 816 817 /* was set by cpu_init() */ 818 cpumask_clear_cpu(cpu, cpu_initialized_mask); 819 820 set_cpu_present(cpu, false); 821 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 822 } 823 824 /* mark "stuck" area as not stuck */ 825 *(volatile u32 *)TRAMPOLINE_SYM(trampoline_status) = 0; 826 827 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 828 /* 829 * Cleanup possible dangling ends... 830 */ 831 smpboot_restore_warm_reset_vector(); 832 } 833 834 destroy_work_on_stack(&c_idle.work); 835 return boot_error; 836 } 837 838 int __cpuinit native_cpu_up(unsigned int cpu) 839 { 840 int apicid = apic->cpu_present_to_apicid(cpu); 841 unsigned long flags; 842 int err; 843 844 WARN_ON(irqs_disabled()); 845 846 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 847 848 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 849 !physid_isset(apicid, phys_cpu_present_map) || 850 (!x2apic_mode && apicid >= 255)) { 851 printk(KERN_ERR "%s: bad cpu %d\n", __func__, cpu); 852 return -EINVAL; 853 } 854 855 /* 856 * Already booted CPU? 857 */ 858 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 859 pr_debug("do_boot_cpu %d Already started\n", cpu); 860 return -ENOSYS; 861 } 862 863 /* 864 * Save current MTRR state in case it was changed since early boot 865 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 866 */ 867 mtrr_save_state(); 868 869 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 870 871 err = do_boot_cpu(apicid, cpu); 872 if (err) { 873 pr_debug("do_boot_cpu failed %d\n", err); 874 return -EIO; 875 } 876 877 /* 878 * Check TSC synchronization with the AP (keep irqs disabled 879 * while doing so): 880 */ 881 local_irq_save(flags); 882 check_tsc_sync_source(cpu); 883 local_irq_restore(flags); 884 885 while (!cpu_online(cpu)) { 886 cpu_relax(); 887 touch_nmi_watchdog(); 888 } 889 890 return 0; 891 } 892 893 /** 894 * arch_disable_smp_support() - disables SMP support for x86 at runtime 895 */ 896 void arch_disable_smp_support(void) 897 { 898 disable_ioapic_support(); 899 } 900 901 /* 902 * Fall back to non SMP mode after errors. 903 * 904 * RED-PEN audit/test this more. I bet there is more state messed up here. 905 */ 906 static __init void disable_smp(void) 907 { 908 init_cpu_present(cpumask_of(0)); 909 init_cpu_possible(cpumask_of(0)); 910 smpboot_clear_io_apic_irqs(); 911 912 if (smp_found_config) 913 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 914 else 915 physid_set_mask_of_physid(0, &phys_cpu_present_map); 916 cpumask_set_cpu(0, cpu_sibling_mask(0)); 917 cpumask_set_cpu(0, cpu_core_mask(0)); 918 } 919 920 /* 921 * Various sanity checks. 922 */ 923 static int __init smp_sanity_check(unsigned max_cpus) 924 { 925 preempt_disable(); 926 927 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 928 if (def_to_bigsmp && nr_cpu_ids > 8) { 929 unsigned int cpu; 930 unsigned nr; 931 932 printk(KERN_WARNING 933 "More than 8 CPUs detected - skipping them.\n" 934 "Use CONFIG_X86_BIGSMP.\n"); 935 936 nr = 0; 937 for_each_present_cpu(cpu) { 938 if (nr >= 8) 939 set_cpu_present(cpu, false); 940 nr++; 941 } 942 943 nr = 0; 944 for_each_possible_cpu(cpu) { 945 if (nr >= 8) 946 set_cpu_possible(cpu, false); 947 nr++; 948 } 949 950 nr_cpu_ids = 8; 951 } 952 #endif 953 954 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 955 printk(KERN_WARNING 956 "weird, boot CPU (#%d) not listed by the BIOS.\n", 957 hard_smp_processor_id()); 958 959 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 960 } 961 962 /* 963 * If we couldn't find an SMP configuration at boot time, 964 * get out of here now! 965 */ 966 if (!smp_found_config && !acpi_lapic) { 967 preempt_enable(); 968 printk(KERN_NOTICE "SMP motherboard not detected.\n"); 969 disable_smp(); 970 if (APIC_init_uniprocessor()) 971 printk(KERN_NOTICE "Local APIC not detected." 972 " Using dummy APIC emulation.\n"); 973 return -1; 974 } 975 976 /* 977 * Should not be necessary because the MP table should list the boot 978 * CPU too, but we do it for the sake of robustness anyway. 979 */ 980 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 981 printk(KERN_NOTICE 982 "weird, boot CPU (#%d) not listed by the BIOS.\n", 983 boot_cpu_physical_apicid); 984 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 985 } 986 preempt_enable(); 987 988 /* 989 * If we couldn't find a local APIC, then get out of here now! 990 */ 991 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 992 !cpu_has_apic) { 993 if (!disable_apic) { 994 pr_err("BIOS bug, local APIC #%d not detected!...\n", 995 boot_cpu_physical_apicid); 996 pr_err("... forcing use of dummy APIC emulation." 997 "(tell your hw vendor)\n"); 998 } 999 smpboot_clear_io_apic(); 1000 disable_ioapic_support(); 1001 return -1; 1002 } 1003 1004 verify_local_APIC(); 1005 1006 /* 1007 * If SMP should be disabled, then really disable it! 1008 */ 1009 if (!max_cpus) { 1010 printk(KERN_INFO "SMP mode deactivated.\n"); 1011 smpboot_clear_io_apic(); 1012 1013 connect_bsp_APIC(); 1014 setup_local_APIC(); 1015 bsp_end_local_APIC_setup(); 1016 return -1; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static void __init smp_cpu_index_default(void) 1023 { 1024 int i; 1025 struct cpuinfo_x86 *c; 1026 1027 for_each_possible_cpu(i) { 1028 c = &cpu_data(i); 1029 /* mark all to hotplug */ 1030 c->cpu_index = nr_cpu_ids; 1031 } 1032 } 1033 1034 /* 1035 * Prepare for SMP bootup. The MP table or ACPI has been read 1036 * earlier. Just do some sanity checking here and enable APIC mode. 1037 */ 1038 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1039 { 1040 unsigned int i; 1041 1042 preempt_disable(); 1043 smp_cpu_index_default(); 1044 1045 /* 1046 * Setup boot CPU information 1047 */ 1048 smp_store_cpu_info(0); /* Final full version of the data */ 1049 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1050 mb(); 1051 1052 current_thread_info()->cpu = 0; /* needed? */ 1053 for_each_possible_cpu(i) { 1054 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1055 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1056 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1057 } 1058 set_cpu_sibling_map(0); 1059 1060 1061 if (smp_sanity_check(max_cpus) < 0) { 1062 printk(KERN_INFO "SMP disabled\n"); 1063 disable_smp(); 1064 goto out; 1065 } 1066 1067 default_setup_apic_routing(); 1068 1069 preempt_disable(); 1070 if (read_apic_id() != boot_cpu_physical_apicid) { 1071 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1072 read_apic_id(), boot_cpu_physical_apicid); 1073 /* Or can we switch back to PIC here? */ 1074 } 1075 preempt_enable(); 1076 1077 connect_bsp_APIC(); 1078 1079 /* 1080 * Switch from PIC to APIC mode. 1081 */ 1082 setup_local_APIC(); 1083 1084 /* 1085 * Enable IO APIC before setting up error vector 1086 */ 1087 if (!skip_ioapic_setup && nr_ioapics) 1088 enable_IO_APIC(); 1089 1090 bsp_end_local_APIC_setup(); 1091 1092 if (apic->setup_portio_remap) 1093 apic->setup_portio_remap(); 1094 1095 smpboot_setup_io_apic(); 1096 /* 1097 * Set up local APIC timer on boot CPU. 1098 */ 1099 1100 printk(KERN_INFO "CPU%d: ", 0); 1101 print_cpu_info(&cpu_data(0)); 1102 x86_init.timers.setup_percpu_clockev(); 1103 1104 if (is_uv_system()) 1105 uv_system_init(); 1106 1107 set_mtrr_aps_delayed_init(); 1108 out: 1109 preempt_enable(); 1110 } 1111 1112 void arch_disable_nonboot_cpus_begin(void) 1113 { 1114 /* 1115 * Avoid the smp alternatives switch during the disable_nonboot_cpus(). 1116 * In the suspend path, we will be back in the SMP mode shortly anyways. 1117 */ 1118 skip_smp_alternatives = true; 1119 } 1120 1121 void arch_disable_nonboot_cpus_end(void) 1122 { 1123 skip_smp_alternatives = false; 1124 } 1125 1126 void arch_enable_nonboot_cpus_begin(void) 1127 { 1128 set_mtrr_aps_delayed_init(); 1129 } 1130 1131 void arch_enable_nonboot_cpus_end(void) 1132 { 1133 mtrr_aps_init(); 1134 } 1135 1136 /* 1137 * Early setup to make printk work. 1138 */ 1139 void __init native_smp_prepare_boot_cpu(void) 1140 { 1141 int me = smp_processor_id(); 1142 switch_to_new_gdt(me); 1143 /* already set me in cpu_online_mask in boot_cpu_init() */ 1144 cpumask_set_cpu(me, cpu_callout_mask); 1145 per_cpu(cpu_state, me) = CPU_ONLINE; 1146 } 1147 1148 void __init native_smp_cpus_done(unsigned int max_cpus) 1149 { 1150 pr_debug("Boot done.\n"); 1151 1152 nmi_selftest(); 1153 impress_friends(); 1154 #ifdef CONFIG_X86_IO_APIC 1155 setup_ioapic_dest(); 1156 #endif 1157 mtrr_aps_init(); 1158 } 1159 1160 static int __initdata setup_possible_cpus = -1; 1161 static int __init _setup_possible_cpus(char *str) 1162 { 1163 get_option(&str, &setup_possible_cpus); 1164 return 0; 1165 } 1166 early_param("possible_cpus", _setup_possible_cpus); 1167 1168 1169 /* 1170 * cpu_possible_mask should be static, it cannot change as cpu's 1171 * are onlined, or offlined. The reason is per-cpu data-structures 1172 * are allocated by some modules at init time, and dont expect to 1173 * do this dynamically on cpu arrival/departure. 1174 * cpu_present_mask on the other hand can change dynamically. 1175 * In case when cpu_hotplug is not compiled, then we resort to current 1176 * behaviour, which is cpu_possible == cpu_present. 1177 * - Ashok Raj 1178 * 1179 * Three ways to find out the number of additional hotplug CPUs: 1180 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1181 * - The user can overwrite it with possible_cpus=NUM 1182 * - Otherwise don't reserve additional CPUs. 1183 * We do this because additional CPUs waste a lot of memory. 1184 * -AK 1185 */ 1186 __init void prefill_possible_map(void) 1187 { 1188 int i, possible; 1189 1190 /* no processor from mptable or madt */ 1191 if (!num_processors) 1192 num_processors = 1; 1193 1194 i = setup_max_cpus ?: 1; 1195 if (setup_possible_cpus == -1) { 1196 possible = num_processors; 1197 #ifdef CONFIG_HOTPLUG_CPU 1198 if (setup_max_cpus) 1199 possible += disabled_cpus; 1200 #else 1201 if (possible > i) 1202 possible = i; 1203 #endif 1204 } else 1205 possible = setup_possible_cpus; 1206 1207 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1208 1209 /* nr_cpu_ids could be reduced via nr_cpus= */ 1210 if (possible > nr_cpu_ids) { 1211 printk(KERN_WARNING 1212 "%d Processors exceeds NR_CPUS limit of %d\n", 1213 possible, nr_cpu_ids); 1214 possible = nr_cpu_ids; 1215 } 1216 1217 #ifdef CONFIG_HOTPLUG_CPU 1218 if (!setup_max_cpus) 1219 #endif 1220 if (possible > i) { 1221 printk(KERN_WARNING 1222 "%d Processors exceeds max_cpus limit of %u\n", 1223 possible, setup_max_cpus); 1224 possible = i; 1225 } 1226 1227 printk(KERN_INFO "SMP: Allowing %d CPUs, %d hotplug CPUs\n", 1228 possible, max_t(int, possible - num_processors, 0)); 1229 1230 for (i = 0; i < possible; i++) 1231 set_cpu_possible(i, true); 1232 for (; i < NR_CPUS; i++) 1233 set_cpu_possible(i, false); 1234 1235 nr_cpu_ids = possible; 1236 } 1237 1238 #ifdef CONFIG_HOTPLUG_CPU 1239 1240 static void remove_siblinginfo(int cpu) 1241 { 1242 int sibling; 1243 struct cpuinfo_x86 *c = &cpu_data(cpu); 1244 1245 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1246 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1247 /*/ 1248 * last thread sibling in this cpu core going down 1249 */ 1250 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1251 cpu_data(sibling).booted_cores--; 1252 } 1253 1254 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1255 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1256 cpumask_clear(cpu_sibling_mask(cpu)); 1257 cpumask_clear(cpu_core_mask(cpu)); 1258 c->phys_proc_id = 0; 1259 c->cpu_core_id = 0; 1260 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1261 } 1262 1263 static void __ref remove_cpu_from_maps(int cpu) 1264 { 1265 set_cpu_online(cpu, false); 1266 cpumask_clear_cpu(cpu, cpu_callout_mask); 1267 cpumask_clear_cpu(cpu, cpu_callin_mask); 1268 /* was set by cpu_init() */ 1269 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1270 numa_remove_cpu(cpu); 1271 } 1272 1273 void cpu_disable_common(void) 1274 { 1275 int cpu = smp_processor_id(); 1276 1277 remove_siblinginfo(cpu); 1278 1279 /* It's now safe to remove this processor from the online map */ 1280 lock_vector_lock(); 1281 remove_cpu_from_maps(cpu); 1282 unlock_vector_lock(); 1283 fixup_irqs(); 1284 } 1285 1286 int native_cpu_disable(void) 1287 { 1288 int cpu = smp_processor_id(); 1289 1290 /* 1291 * Perhaps use cpufreq to drop frequency, but that could go 1292 * into generic code. 1293 * 1294 * We won't take down the boot processor on i386 due to some 1295 * interrupts only being able to be serviced by the BSP. 1296 * Especially so if we're not using an IOAPIC -zwane 1297 */ 1298 if (cpu == 0) 1299 return -EBUSY; 1300 1301 clear_local_APIC(); 1302 1303 cpu_disable_common(); 1304 return 0; 1305 } 1306 1307 void native_cpu_die(unsigned int cpu) 1308 { 1309 /* We don't do anything here: idle task is faking death itself. */ 1310 unsigned int i; 1311 1312 for (i = 0; i < 10; i++) { 1313 /* They ack this in play_dead by setting CPU_DEAD */ 1314 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1315 if (system_state == SYSTEM_RUNNING) 1316 pr_info("CPU %u is now offline\n", cpu); 1317 1318 if (1 == num_online_cpus()) 1319 alternatives_smp_switch(0); 1320 return; 1321 } 1322 msleep(100); 1323 } 1324 pr_err("CPU %u didn't die...\n", cpu); 1325 } 1326 1327 void play_dead_common(void) 1328 { 1329 idle_task_exit(); 1330 reset_lazy_tlbstate(); 1331 amd_e400_remove_cpu(raw_smp_processor_id()); 1332 1333 mb(); 1334 /* Ack it */ 1335 __this_cpu_write(cpu_state, CPU_DEAD); 1336 1337 /* 1338 * With physical CPU hotplug, we should halt the cpu 1339 */ 1340 local_irq_disable(); 1341 } 1342 1343 /* 1344 * We need to flush the caches before going to sleep, lest we have 1345 * dirty data in our caches when we come back up. 1346 */ 1347 static inline void mwait_play_dead(void) 1348 { 1349 unsigned int eax, ebx, ecx, edx; 1350 unsigned int highest_cstate = 0; 1351 unsigned int highest_subcstate = 0; 1352 int i; 1353 void *mwait_ptr; 1354 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1355 1356 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1357 return; 1358 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1359 return; 1360 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1361 return; 1362 1363 eax = CPUID_MWAIT_LEAF; 1364 ecx = 0; 1365 native_cpuid(&eax, &ebx, &ecx, &edx); 1366 1367 /* 1368 * eax will be 0 if EDX enumeration is not valid. 1369 * Initialized below to cstate, sub_cstate value when EDX is valid. 1370 */ 1371 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1372 eax = 0; 1373 } else { 1374 edx >>= MWAIT_SUBSTATE_SIZE; 1375 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1376 if (edx & MWAIT_SUBSTATE_MASK) { 1377 highest_cstate = i; 1378 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1379 } 1380 } 1381 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1382 (highest_subcstate - 1); 1383 } 1384 1385 /* 1386 * This should be a memory location in a cache line which is 1387 * unlikely to be touched by other processors. The actual 1388 * content is immaterial as it is not actually modified in any way. 1389 */ 1390 mwait_ptr = ¤t_thread_info()->flags; 1391 1392 wbinvd(); 1393 1394 while (1) { 1395 /* 1396 * The CLFLUSH is a workaround for erratum AAI65 for 1397 * the Xeon 7400 series. It's not clear it is actually 1398 * needed, but it should be harmless in either case. 1399 * The WBINVD is insufficient due to the spurious-wakeup 1400 * case where we return around the loop. 1401 */ 1402 clflush(mwait_ptr); 1403 __monitor(mwait_ptr, 0, 0); 1404 mb(); 1405 __mwait(eax, 0); 1406 } 1407 } 1408 1409 static inline void hlt_play_dead(void) 1410 { 1411 if (__this_cpu_read(cpu_info.x86) >= 4) 1412 wbinvd(); 1413 1414 while (1) { 1415 native_halt(); 1416 } 1417 } 1418 1419 void native_play_dead(void) 1420 { 1421 play_dead_common(); 1422 tboot_shutdown(TB_SHUTDOWN_WFS); 1423 1424 mwait_play_dead(); /* Only returns on failure */ 1425 hlt_play_dead(); 1426 } 1427 1428 #else /* ... !CONFIG_HOTPLUG_CPU */ 1429 int native_cpu_disable(void) 1430 { 1431 return -ENOSYS; 1432 } 1433 1434 void native_cpu_die(unsigned int cpu) 1435 { 1436 /* We said "no" in __cpu_disable */ 1437 BUG(); 1438 } 1439 1440 void native_play_dead(void) 1441 { 1442 BUG(); 1443 } 1444 1445 #endif 1446