1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/export.h> 47 #include <linux/sched.h> 48 #include <linux/sched/topology.h> 49 #include <linux/sched/hotplug.h> 50 #include <linux/sched/task_stack.h> 51 #include <linux/percpu.h> 52 #include <linux/bootmem.h> 53 #include <linux/err.h> 54 #include <linux/nmi.h> 55 #include <linux/tboot.h> 56 #include <linux/stackprotector.h> 57 #include <linux/gfp.h> 58 #include <linux/cpuidle.h> 59 60 #include <asm/acpi.h> 61 #include <asm/desc.h> 62 #include <asm/nmi.h> 63 #include <asm/irq.h> 64 #include <asm/realmode.h> 65 #include <asm/cpu.h> 66 #include <asm/numa.h> 67 #include <asm/pgtable.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/internal.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/realmode.h> 79 #include <asm/misc.h> 80 81 /* Number of siblings per CPU package */ 82 int smp_num_siblings = 1; 83 EXPORT_SYMBOL(smp_num_siblings); 84 85 /* Last level cache ID of each logical CPU */ 86 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 87 88 /* representing HT siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 91 92 /* representing HT and core siblings of each logical CPU */ 93 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 94 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 95 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 97 98 /* Per CPU bogomips and other parameters */ 99 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 100 EXPORT_PER_CPU_SYMBOL(cpu_info); 101 102 /* Logical package management. We might want to allocate that dynamically */ 103 static int *physical_to_logical_pkg __read_mostly; 104 static unsigned long *physical_package_map __read_mostly;; 105 static unsigned int max_physical_pkg_id __read_mostly; 106 unsigned int __max_logical_packages __read_mostly; 107 EXPORT_SYMBOL(__max_logical_packages); 108 static unsigned int logical_packages __read_mostly; 109 110 /* Maximum number of SMT threads on any online core */ 111 int __max_smt_threads __read_mostly; 112 113 /* Flag to indicate if a complete sched domain rebuild is required */ 114 bool x86_topology_update; 115 116 int arch_update_cpu_topology(void) 117 { 118 int retval = x86_topology_update; 119 120 x86_topology_update = false; 121 return retval; 122 } 123 124 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 125 { 126 unsigned long flags; 127 128 spin_lock_irqsave(&rtc_lock, flags); 129 CMOS_WRITE(0xa, 0xf); 130 spin_unlock_irqrestore(&rtc_lock, flags); 131 local_flush_tlb(); 132 pr_debug("1.\n"); 133 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 134 start_eip >> 4; 135 pr_debug("2.\n"); 136 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 137 start_eip & 0xf; 138 pr_debug("3.\n"); 139 } 140 141 static inline void smpboot_restore_warm_reset_vector(void) 142 { 143 unsigned long flags; 144 145 /* 146 * Install writable page 0 entry to set BIOS data area. 147 */ 148 local_flush_tlb(); 149 150 /* 151 * Paranoid: Set warm reset code and vector here back 152 * to default values. 153 */ 154 spin_lock_irqsave(&rtc_lock, flags); 155 CMOS_WRITE(0, 0xf); 156 spin_unlock_irqrestore(&rtc_lock, flags); 157 158 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 159 } 160 161 /* 162 * Report back to the Boot Processor during boot time or to the caller processor 163 * during CPU online. 164 */ 165 static void smp_callin(void) 166 { 167 int cpuid, phys_id; 168 169 /* 170 * If waken up by an INIT in an 82489DX configuration 171 * cpu_callout_mask guarantees we don't get here before 172 * an INIT_deassert IPI reaches our local APIC, so it is 173 * now safe to touch our local APIC. 174 */ 175 cpuid = smp_processor_id(); 176 177 /* 178 * (This works even if the APIC is not enabled.) 179 */ 180 phys_id = read_apic_id(); 181 182 /* 183 * the boot CPU has finished the init stage and is spinning 184 * on callin_map until we finish. We are free to set up this 185 * CPU, first the APIC. (this is probably redundant on most 186 * boards) 187 */ 188 apic_ap_setup(); 189 190 /* 191 * Save our processor parameters. Note: this information 192 * is needed for clock calibration. 193 */ 194 smp_store_cpu_info(cpuid); 195 196 /* 197 * Get our bogomips. 198 * Update loops_per_jiffy in cpu_data. Previous call to 199 * smp_store_cpu_info() stored a value that is close but not as 200 * accurate as the value just calculated. 201 */ 202 calibrate_delay(); 203 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 204 pr_debug("Stack at about %p\n", &cpuid); 205 206 /* 207 * This must be done before setting cpu_online_mask 208 * or calling notify_cpu_starting. 209 */ 210 set_cpu_sibling_map(raw_smp_processor_id()); 211 wmb(); 212 213 notify_cpu_starting(cpuid); 214 215 /* 216 * Allow the master to continue. 217 */ 218 cpumask_set_cpu(cpuid, cpu_callin_mask); 219 } 220 221 static int cpu0_logical_apicid; 222 static int enable_start_cpu0; 223 /* 224 * Activate a secondary processor. 225 */ 226 static void notrace start_secondary(void *unused) 227 { 228 /* 229 * Don't put *anything* except direct CPU state initialization 230 * before cpu_init(), SMP booting is too fragile that we want to 231 * limit the things done here to the most necessary things. 232 */ 233 if (boot_cpu_has(X86_FEATURE_PCID)) 234 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 235 236 #ifdef CONFIG_X86_32 237 /* switch away from the initial page table */ 238 load_cr3(swapper_pg_dir); 239 __flush_tlb_all(); 240 #endif 241 242 cpu_init(); 243 x86_cpuinit.early_percpu_clock_init(); 244 preempt_disable(); 245 smp_callin(); 246 247 enable_start_cpu0 = 0; 248 249 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 250 barrier(); 251 /* 252 * Check TSC synchronization with the BP: 253 */ 254 check_tsc_sync_target(); 255 256 /* 257 * Lock vector_lock and initialize the vectors on this cpu 258 * before setting the cpu online. We must set it online with 259 * vector_lock held to prevent a concurrent setup/teardown 260 * from seeing a half valid vector space. 261 */ 262 lock_vector_lock(); 263 setup_vector_irq(smp_processor_id()); 264 set_cpu_online(smp_processor_id(), true); 265 unlock_vector_lock(); 266 cpu_set_state_online(smp_processor_id()); 267 x86_platform.nmi_init(); 268 269 /* enable local interrupts */ 270 local_irq_enable(); 271 272 /* to prevent fake stack check failure in clock setup */ 273 boot_init_stack_canary(); 274 275 x86_cpuinit.setup_percpu_clockev(); 276 277 wmb(); 278 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 279 } 280 281 /** 282 * topology_update_package_map - Update the physical to logical package map 283 * @pkg: The physical package id as retrieved via CPUID 284 * @cpu: The cpu for which this is updated 285 */ 286 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 287 { 288 unsigned int new; 289 290 /* Called from early boot ? */ 291 if (!physical_package_map) 292 return 0; 293 294 if (pkg >= max_physical_pkg_id) 295 return -EINVAL; 296 297 /* Set the logical package id */ 298 if (test_and_set_bit(pkg, physical_package_map)) 299 goto found; 300 301 if (logical_packages >= __max_logical_packages) { 302 pr_warn("Package %u of CPU %u exceeds BIOS package data %u.\n", 303 logical_packages, cpu, __max_logical_packages); 304 return -ENOSPC; 305 } 306 307 new = logical_packages++; 308 if (new != pkg) { 309 pr_info("CPU %u Converting physical %u to logical package %u\n", 310 cpu, pkg, new); 311 } 312 physical_to_logical_pkg[pkg] = new; 313 314 found: 315 cpu_data(cpu).logical_proc_id = physical_to_logical_pkg[pkg]; 316 return 0; 317 } 318 319 /** 320 * topology_phys_to_logical_pkg - Map a physical package id to a logical 321 * 322 * Returns logical package id or -1 if not found 323 */ 324 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 325 { 326 if (phys_pkg >= max_physical_pkg_id) 327 return -1; 328 return physical_to_logical_pkg[phys_pkg]; 329 } 330 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 331 332 static void __init smp_init_package_map(struct cpuinfo_x86 *c, unsigned int cpu) 333 { 334 unsigned int ncpus; 335 size_t size; 336 337 /* 338 * Today neither Intel nor AMD support heterogenous systems. That 339 * might change in the future.... 340 * 341 * While ideally we'd want '* smp_num_siblings' in the below @ncpus 342 * computation, this won't actually work since some Intel BIOSes 343 * report inconsistent HT data when they disable HT. 344 * 345 * In particular, they reduce the APIC-IDs to only include the cores, 346 * but leave the CPUID topology to say there are (2) siblings. 347 * This means we don't know how many threads there will be until 348 * after the APIC enumeration. 349 * 350 * By not including this we'll sometimes over-estimate the number of 351 * logical packages by the amount of !present siblings, but this is 352 * still better than MAX_LOCAL_APIC. 353 * 354 * We use total_cpus not nr_cpu_ids because nr_cpu_ids can be limited 355 * on the command line leading to a similar issue as the HT disable 356 * problem because the hyperthreads are usually enumerated after the 357 * primary cores. 358 */ 359 ncpus = boot_cpu_data.x86_max_cores; 360 if (!ncpus) { 361 pr_warn("x86_max_cores == zero !?!?"); 362 ncpus = 1; 363 } 364 365 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 366 logical_packages = 0; 367 368 /* 369 * Possibly larger than what we need as the number of apic ids per 370 * package can be smaller than the actual used apic ids. 371 */ 372 max_physical_pkg_id = DIV_ROUND_UP(MAX_LOCAL_APIC, ncpus); 373 size = max_physical_pkg_id * sizeof(unsigned int); 374 physical_to_logical_pkg = kmalloc(size, GFP_KERNEL); 375 memset(physical_to_logical_pkg, 0xff, size); 376 size = BITS_TO_LONGS(max_physical_pkg_id) * sizeof(unsigned long); 377 physical_package_map = kzalloc(size, GFP_KERNEL); 378 379 pr_info("Max logical packages: %u\n", __max_logical_packages); 380 381 topology_update_package_map(c->phys_proc_id, cpu); 382 } 383 384 void __init smp_store_boot_cpu_info(void) 385 { 386 int id = 0; /* CPU 0 */ 387 struct cpuinfo_x86 *c = &cpu_data(id); 388 389 *c = boot_cpu_data; 390 c->cpu_index = id; 391 smp_init_package_map(c, id); 392 } 393 394 /* 395 * The bootstrap kernel entry code has set these up. Save them for 396 * a given CPU 397 */ 398 void smp_store_cpu_info(int id) 399 { 400 struct cpuinfo_x86 *c = &cpu_data(id); 401 402 *c = boot_cpu_data; 403 c->cpu_index = id; 404 /* 405 * During boot time, CPU0 has this setup already. Save the info when 406 * bringing up AP or offlined CPU0. 407 */ 408 identify_secondary_cpu(c); 409 } 410 411 static bool 412 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 413 { 414 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 415 416 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 417 } 418 419 static bool 420 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 421 { 422 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 423 424 return !WARN_ONCE(!topology_same_node(c, o), 425 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 426 "[node: %d != %d]. Ignoring dependency.\n", 427 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 428 } 429 430 #define link_mask(mfunc, c1, c2) \ 431 do { \ 432 cpumask_set_cpu((c1), mfunc(c2)); \ 433 cpumask_set_cpu((c2), mfunc(c1)); \ 434 } while (0) 435 436 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 437 { 438 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 439 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 440 441 if (c->phys_proc_id == o->phys_proc_id && 442 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 443 if (c->cpu_core_id == o->cpu_core_id) 444 return topology_sane(c, o, "smt"); 445 446 if ((c->cu_id != 0xff) && 447 (o->cu_id != 0xff) && 448 (c->cu_id == o->cu_id)) 449 return topology_sane(c, o, "smt"); 450 } 451 452 } else if (c->phys_proc_id == o->phys_proc_id && 453 c->cpu_core_id == o->cpu_core_id) { 454 return topology_sane(c, o, "smt"); 455 } 456 457 return false; 458 } 459 460 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 461 { 462 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 463 464 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 465 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 466 return topology_sane(c, o, "llc"); 467 468 return false; 469 } 470 471 /* 472 * Unlike the other levels, we do not enforce keeping a 473 * multicore group inside a NUMA node. If this happens, we will 474 * discard the MC level of the topology later. 475 */ 476 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 477 { 478 if (c->phys_proc_id == o->phys_proc_id) 479 return true; 480 return false; 481 } 482 483 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 484 static inline int x86_sched_itmt_flags(void) 485 { 486 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 487 } 488 489 #ifdef CONFIG_SCHED_MC 490 static int x86_core_flags(void) 491 { 492 return cpu_core_flags() | x86_sched_itmt_flags(); 493 } 494 #endif 495 #ifdef CONFIG_SCHED_SMT 496 static int x86_smt_flags(void) 497 { 498 return cpu_smt_flags() | x86_sched_itmt_flags(); 499 } 500 #endif 501 #endif 502 503 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 504 #ifdef CONFIG_SCHED_SMT 505 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 506 #endif 507 #ifdef CONFIG_SCHED_MC 508 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 509 #endif 510 { NULL, }, 511 }; 512 513 static struct sched_domain_topology_level x86_topology[] = { 514 #ifdef CONFIG_SCHED_SMT 515 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 516 #endif 517 #ifdef CONFIG_SCHED_MC 518 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 519 #endif 520 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 521 { NULL, }, 522 }; 523 524 /* 525 * Set if a package/die has multiple NUMA nodes inside. 526 * AMD Magny-Cours and Intel Cluster-on-Die have this. 527 */ 528 static bool x86_has_numa_in_package; 529 530 void set_cpu_sibling_map(int cpu) 531 { 532 bool has_smt = smp_num_siblings > 1; 533 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 534 struct cpuinfo_x86 *c = &cpu_data(cpu); 535 struct cpuinfo_x86 *o; 536 int i, threads; 537 538 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 539 540 if (!has_mp) { 541 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 542 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 543 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 544 c->booted_cores = 1; 545 return; 546 } 547 548 for_each_cpu(i, cpu_sibling_setup_mask) { 549 o = &cpu_data(i); 550 551 if ((i == cpu) || (has_smt && match_smt(c, o))) 552 link_mask(topology_sibling_cpumask, cpu, i); 553 554 if ((i == cpu) || (has_mp && match_llc(c, o))) 555 link_mask(cpu_llc_shared_mask, cpu, i); 556 557 } 558 559 /* 560 * This needs a separate iteration over the cpus because we rely on all 561 * topology_sibling_cpumask links to be set-up. 562 */ 563 for_each_cpu(i, cpu_sibling_setup_mask) { 564 o = &cpu_data(i); 565 566 if ((i == cpu) || (has_mp && match_die(c, o))) { 567 link_mask(topology_core_cpumask, cpu, i); 568 569 /* 570 * Does this new cpu bringup a new core? 571 */ 572 if (cpumask_weight( 573 topology_sibling_cpumask(cpu)) == 1) { 574 /* 575 * for each core in package, increment 576 * the booted_cores for this new cpu 577 */ 578 if (cpumask_first( 579 topology_sibling_cpumask(i)) == i) 580 c->booted_cores++; 581 /* 582 * increment the core count for all 583 * the other cpus in this package 584 */ 585 if (i != cpu) 586 cpu_data(i).booted_cores++; 587 } else if (i != cpu && !c->booted_cores) 588 c->booted_cores = cpu_data(i).booted_cores; 589 } 590 if (match_die(c, o) && !topology_same_node(c, o)) 591 x86_has_numa_in_package = true; 592 } 593 594 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 595 if (threads > __max_smt_threads) 596 __max_smt_threads = threads; 597 } 598 599 /* maps the cpu to the sched domain representing multi-core */ 600 const struct cpumask *cpu_coregroup_mask(int cpu) 601 { 602 return cpu_llc_shared_mask(cpu); 603 } 604 605 static void impress_friends(void) 606 { 607 int cpu; 608 unsigned long bogosum = 0; 609 /* 610 * Allow the user to impress friends. 611 */ 612 pr_debug("Before bogomips\n"); 613 for_each_possible_cpu(cpu) 614 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 615 bogosum += cpu_data(cpu).loops_per_jiffy; 616 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 617 num_online_cpus(), 618 bogosum/(500000/HZ), 619 (bogosum/(5000/HZ))%100); 620 621 pr_debug("Before bogocount - setting activated=1\n"); 622 } 623 624 void __inquire_remote_apic(int apicid) 625 { 626 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 627 const char * const names[] = { "ID", "VERSION", "SPIV" }; 628 int timeout; 629 u32 status; 630 631 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 632 633 for (i = 0; i < ARRAY_SIZE(regs); i++) { 634 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 635 636 /* 637 * Wait for idle. 638 */ 639 status = safe_apic_wait_icr_idle(); 640 if (status) 641 pr_cont("a previous APIC delivery may have failed\n"); 642 643 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 644 645 timeout = 0; 646 do { 647 udelay(100); 648 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 649 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 650 651 switch (status) { 652 case APIC_ICR_RR_VALID: 653 status = apic_read(APIC_RRR); 654 pr_cont("%08x\n", status); 655 break; 656 default: 657 pr_cont("failed\n"); 658 } 659 } 660 } 661 662 /* 663 * The Multiprocessor Specification 1.4 (1997) example code suggests 664 * that there should be a 10ms delay between the BSP asserting INIT 665 * and de-asserting INIT, when starting a remote processor. 666 * But that slows boot and resume on modern processors, which include 667 * many cores and don't require that delay. 668 * 669 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 670 * Modern processor families are quirked to remove the delay entirely. 671 */ 672 #define UDELAY_10MS_DEFAULT 10000 673 674 static unsigned int init_udelay = UINT_MAX; 675 676 static int __init cpu_init_udelay(char *str) 677 { 678 get_option(&str, &init_udelay); 679 680 return 0; 681 } 682 early_param("cpu_init_udelay", cpu_init_udelay); 683 684 static void __init smp_quirk_init_udelay(void) 685 { 686 /* if cmdline changed it from default, leave it alone */ 687 if (init_udelay != UINT_MAX) 688 return; 689 690 /* if modern processor, use no delay */ 691 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 692 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 693 init_udelay = 0; 694 return; 695 } 696 /* else, use legacy delay */ 697 init_udelay = UDELAY_10MS_DEFAULT; 698 } 699 700 /* 701 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 702 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 703 * won't ... remember to clear down the APIC, etc later. 704 */ 705 int 706 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 707 { 708 unsigned long send_status, accept_status = 0; 709 int maxlvt; 710 711 /* Target chip */ 712 /* Boot on the stack */ 713 /* Kick the second */ 714 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 715 716 pr_debug("Waiting for send to finish...\n"); 717 send_status = safe_apic_wait_icr_idle(); 718 719 /* 720 * Give the other CPU some time to accept the IPI. 721 */ 722 udelay(200); 723 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 724 maxlvt = lapic_get_maxlvt(); 725 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 726 apic_write(APIC_ESR, 0); 727 accept_status = (apic_read(APIC_ESR) & 0xEF); 728 } 729 pr_debug("NMI sent\n"); 730 731 if (send_status) 732 pr_err("APIC never delivered???\n"); 733 if (accept_status) 734 pr_err("APIC delivery error (%lx)\n", accept_status); 735 736 return (send_status | accept_status); 737 } 738 739 static int 740 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 741 { 742 unsigned long send_status = 0, accept_status = 0; 743 int maxlvt, num_starts, j; 744 745 maxlvt = lapic_get_maxlvt(); 746 747 /* 748 * Be paranoid about clearing APIC errors. 749 */ 750 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 751 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 752 apic_write(APIC_ESR, 0); 753 apic_read(APIC_ESR); 754 } 755 756 pr_debug("Asserting INIT\n"); 757 758 /* 759 * Turn INIT on target chip 760 */ 761 /* 762 * Send IPI 763 */ 764 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 765 phys_apicid); 766 767 pr_debug("Waiting for send to finish...\n"); 768 send_status = safe_apic_wait_icr_idle(); 769 770 udelay(init_udelay); 771 772 pr_debug("Deasserting INIT\n"); 773 774 /* Target chip */ 775 /* Send IPI */ 776 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 777 778 pr_debug("Waiting for send to finish...\n"); 779 send_status = safe_apic_wait_icr_idle(); 780 781 mb(); 782 783 /* 784 * Should we send STARTUP IPIs ? 785 * 786 * Determine this based on the APIC version. 787 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 788 */ 789 if (APIC_INTEGRATED(boot_cpu_apic_version)) 790 num_starts = 2; 791 else 792 num_starts = 0; 793 794 /* 795 * Run STARTUP IPI loop. 796 */ 797 pr_debug("#startup loops: %d\n", num_starts); 798 799 for (j = 1; j <= num_starts; j++) { 800 pr_debug("Sending STARTUP #%d\n", j); 801 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 802 apic_write(APIC_ESR, 0); 803 apic_read(APIC_ESR); 804 pr_debug("After apic_write\n"); 805 806 /* 807 * STARTUP IPI 808 */ 809 810 /* Target chip */ 811 /* Boot on the stack */ 812 /* Kick the second */ 813 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 814 phys_apicid); 815 816 /* 817 * Give the other CPU some time to accept the IPI. 818 */ 819 if (init_udelay == 0) 820 udelay(10); 821 else 822 udelay(300); 823 824 pr_debug("Startup point 1\n"); 825 826 pr_debug("Waiting for send to finish...\n"); 827 send_status = safe_apic_wait_icr_idle(); 828 829 /* 830 * Give the other CPU some time to accept the IPI. 831 */ 832 if (init_udelay == 0) 833 udelay(10); 834 else 835 udelay(200); 836 837 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 838 apic_write(APIC_ESR, 0); 839 accept_status = (apic_read(APIC_ESR) & 0xEF); 840 if (send_status || accept_status) 841 break; 842 } 843 pr_debug("After Startup\n"); 844 845 if (send_status) 846 pr_err("APIC never delivered???\n"); 847 if (accept_status) 848 pr_err("APIC delivery error (%lx)\n", accept_status); 849 850 return (send_status | accept_status); 851 } 852 853 /* reduce the number of lines printed when booting a large cpu count system */ 854 static void announce_cpu(int cpu, int apicid) 855 { 856 static int current_node = -1; 857 int node = early_cpu_to_node(cpu); 858 static int width, node_width; 859 860 if (!width) 861 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 862 863 if (!node_width) 864 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 865 866 if (cpu == 1) 867 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 868 869 if (system_state < SYSTEM_RUNNING) { 870 if (node != current_node) { 871 if (current_node > (-1)) 872 pr_cont("\n"); 873 current_node = node; 874 875 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 876 node_width - num_digits(node), " ", node); 877 } 878 879 /* Add padding for the BSP */ 880 if (cpu == 1) 881 pr_cont("%*s", width + 1, " "); 882 883 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 884 885 } else 886 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 887 node, cpu, apicid); 888 } 889 890 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 891 { 892 int cpu; 893 894 cpu = smp_processor_id(); 895 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 896 return NMI_HANDLED; 897 898 return NMI_DONE; 899 } 900 901 /* 902 * Wake up AP by INIT, INIT, STARTUP sequence. 903 * 904 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 905 * boot-strap code which is not a desired behavior for waking up BSP. To 906 * void the boot-strap code, wake up CPU0 by NMI instead. 907 * 908 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 909 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 910 * We'll change this code in the future to wake up hard offlined CPU0 if 911 * real platform and request are available. 912 */ 913 static int 914 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 915 int *cpu0_nmi_registered) 916 { 917 int id; 918 int boot_error; 919 920 preempt_disable(); 921 922 /* 923 * Wake up AP by INIT, INIT, STARTUP sequence. 924 */ 925 if (cpu) { 926 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 927 goto out; 928 } 929 930 /* 931 * Wake up BSP by nmi. 932 * 933 * Register a NMI handler to help wake up CPU0. 934 */ 935 boot_error = register_nmi_handler(NMI_LOCAL, 936 wakeup_cpu0_nmi, 0, "wake_cpu0"); 937 938 if (!boot_error) { 939 enable_start_cpu0 = 1; 940 *cpu0_nmi_registered = 1; 941 if (apic->dest_logical == APIC_DEST_LOGICAL) 942 id = cpu0_logical_apicid; 943 else 944 id = apicid; 945 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 946 } 947 948 out: 949 preempt_enable(); 950 951 return boot_error; 952 } 953 954 void common_cpu_up(unsigned int cpu, struct task_struct *idle) 955 { 956 /* Just in case we booted with a single CPU. */ 957 alternatives_enable_smp(); 958 959 per_cpu(current_task, cpu) = idle; 960 961 #ifdef CONFIG_X86_32 962 /* Stack for startup_32 can be just as for start_secondary onwards */ 963 irq_ctx_init(cpu); 964 per_cpu(cpu_current_top_of_stack, cpu) = 965 (unsigned long)task_stack_page(idle) + THREAD_SIZE; 966 #else 967 initial_gs = per_cpu_offset(cpu); 968 #endif 969 } 970 971 /* 972 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 973 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 974 * Returns zero if CPU booted OK, else error code from 975 * ->wakeup_secondary_cpu. 976 */ 977 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 978 int *cpu0_nmi_registered) 979 { 980 volatile u32 *trampoline_status = 981 (volatile u32 *) __va(real_mode_header->trampoline_status); 982 /* start_ip had better be page-aligned! */ 983 unsigned long start_ip = real_mode_header->trampoline_start; 984 985 unsigned long boot_error = 0; 986 unsigned long timeout; 987 988 idle->thread.sp = (unsigned long)task_pt_regs(idle); 989 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 990 initial_code = (unsigned long)start_secondary; 991 initial_stack = idle->thread.sp; 992 993 /* 994 * Enable the espfix hack for this CPU 995 */ 996 #ifdef CONFIG_X86_ESPFIX64 997 init_espfix_ap(cpu); 998 #endif 999 1000 /* So we see what's up */ 1001 announce_cpu(cpu, apicid); 1002 1003 /* 1004 * This grunge runs the startup process for 1005 * the targeted processor. 1006 */ 1007 1008 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1009 1010 pr_debug("Setting warm reset code and vector.\n"); 1011 1012 smpboot_setup_warm_reset_vector(start_ip); 1013 /* 1014 * Be paranoid about clearing APIC errors. 1015 */ 1016 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1017 apic_write(APIC_ESR, 0); 1018 apic_read(APIC_ESR); 1019 } 1020 } 1021 1022 /* 1023 * AP might wait on cpu_callout_mask in cpu_init() with 1024 * cpu_initialized_mask set if previous attempt to online 1025 * it timed-out. Clear cpu_initialized_mask so that after 1026 * INIT/SIPI it could start with a clean state. 1027 */ 1028 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1029 smp_mb(); 1030 1031 /* 1032 * Wake up a CPU in difference cases: 1033 * - Use the method in the APIC driver if it's defined 1034 * Otherwise, 1035 * - Use an INIT boot APIC message for APs or NMI for BSP. 1036 */ 1037 if (apic->wakeup_secondary_cpu) 1038 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1039 else 1040 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1041 cpu0_nmi_registered); 1042 1043 if (!boot_error) { 1044 /* 1045 * Wait 10s total for first sign of life from AP 1046 */ 1047 boot_error = -1; 1048 timeout = jiffies + 10*HZ; 1049 while (time_before(jiffies, timeout)) { 1050 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1051 /* 1052 * Tell AP to proceed with initialization 1053 */ 1054 cpumask_set_cpu(cpu, cpu_callout_mask); 1055 boot_error = 0; 1056 break; 1057 } 1058 schedule(); 1059 } 1060 } 1061 1062 if (!boot_error) { 1063 /* 1064 * Wait till AP completes initial initialization 1065 */ 1066 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1067 /* 1068 * Allow other tasks to run while we wait for the 1069 * AP to come online. This also gives a chance 1070 * for the MTRR work(triggered by the AP coming online) 1071 * to be completed in the stop machine context. 1072 */ 1073 schedule(); 1074 } 1075 } 1076 1077 /* mark "stuck" area as not stuck */ 1078 *trampoline_status = 0; 1079 1080 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 1081 /* 1082 * Cleanup possible dangling ends... 1083 */ 1084 smpboot_restore_warm_reset_vector(); 1085 } 1086 1087 return boot_error; 1088 } 1089 1090 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1091 { 1092 int apicid = apic->cpu_present_to_apicid(cpu); 1093 int cpu0_nmi_registered = 0; 1094 unsigned long flags; 1095 int err, ret = 0; 1096 1097 WARN_ON(irqs_disabled()); 1098 1099 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1100 1101 if (apicid == BAD_APICID || 1102 !physid_isset(apicid, phys_cpu_present_map) || 1103 !apic->apic_id_valid(apicid)) { 1104 pr_err("%s: bad cpu %d\n", __func__, cpu); 1105 return -EINVAL; 1106 } 1107 1108 /* 1109 * Already booted CPU? 1110 */ 1111 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1112 pr_debug("do_boot_cpu %d Already started\n", cpu); 1113 return -ENOSYS; 1114 } 1115 1116 /* 1117 * Save current MTRR state in case it was changed since early boot 1118 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1119 */ 1120 mtrr_save_state(); 1121 1122 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1123 err = cpu_check_up_prepare(cpu); 1124 if (err && err != -EBUSY) 1125 return err; 1126 1127 /* the FPU context is blank, nobody can own it */ 1128 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1129 1130 common_cpu_up(cpu, tidle); 1131 1132 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1133 if (err) { 1134 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1135 ret = -EIO; 1136 goto unreg_nmi; 1137 } 1138 1139 /* 1140 * Check TSC synchronization with the AP (keep irqs disabled 1141 * while doing so): 1142 */ 1143 local_irq_save(flags); 1144 check_tsc_sync_source(cpu); 1145 local_irq_restore(flags); 1146 1147 while (!cpu_online(cpu)) { 1148 cpu_relax(); 1149 touch_nmi_watchdog(); 1150 } 1151 1152 unreg_nmi: 1153 /* 1154 * Clean up the nmi handler. Do this after the callin and callout sync 1155 * to avoid impact of possible long unregister time. 1156 */ 1157 if (cpu0_nmi_registered) 1158 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1159 1160 return ret; 1161 } 1162 1163 /** 1164 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1165 */ 1166 void arch_disable_smp_support(void) 1167 { 1168 disable_ioapic_support(); 1169 } 1170 1171 /* 1172 * Fall back to non SMP mode after errors. 1173 * 1174 * RED-PEN audit/test this more. I bet there is more state messed up here. 1175 */ 1176 static __init void disable_smp(void) 1177 { 1178 pr_info("SMP disabled\n"); 1179 1180 disable_ioapic_support(); 1181 1182 init_cpu_present(cpumask_of(0)); 1183 init_cpu_possible(cpumask_of(0)); 1184 1185 if (smp_found_config) 1186 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1187 else 1188 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1189 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1190 cpumask_set_cpu(0, topology_core_cpumask(0)); 1191 } 1192 1193 enum { 1194 SMP_OK, 1195 SMP_NO_CONFIG, 1196 SMP_NO_APIC, 1197 SMP_FORCE_UP, 1198 }; 1199 1200 /* 1201 * Various sanity checks. 1202 */ 1203 static int __init smp_sanity_check(unsigned max_cpus) 1204 { 1205 preempt_disable(); 1206 1207 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1208 if (def_to_bigsmp && nr_cpu_ids > 8) { 1209 unsigned int cpu; 1210 unsigned nr; 1211 1212 pr_warn("More than 8 CPUs detected - skipping them\n" 1213 "Use CONFIG_X86_BIGSMP\n"); 1214 1215 nr = 0; 1216 for_each_present_cpu(cpu) { 1217 if (nr >= 8) 1218 set_cpu_present(cpu, false); 1219 nr++; 1220 } 1221 1222 nr = 0; 1223 for_each_possible_cpu(cpu) { 1224 if (nr >= 8) 1225 set_cpu_possible(cpu, false); 1226 nr++; 1227 } 1228 1229 nr_cpu_ids = 8; 1230 } 1231 #endif 1232 1233 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1234 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1235 hard_smp_processor_id()); 1236 1237 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1238 } 1239 1240 /* 1241 * If we couldn't find an SMP configuration at boot time, 1242 * get out of here now! 1243 */ 1244 if (!smp_found_config && !acpi_lapic) { 1245 preempt_enable(); 1246 pr_notice("SMP motherboard not detected\n"); 1247 return SMP_NO_CONFIG; 1248 } 1249 1250 /* 1251 * Should not be necessary because the MP table should list the boot 1252 * CPU too, but we do it for the sake of robustness anyway. 1253 */ 1254 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1255 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1256 boot_cpu_physical_apicid); 1257 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1258 } 1259 preempt_enable(); 1260 1261 /* 1262 * If we couldn't find a local APIC, then get out of here now! 1263 */ 1264 if (APIC_INTEGRATED(boot_cpu_apic_version) && 1265 !boot_cpu_has(X86_FEATURE_APIC)) { 1266 if (!disable_apic) { 1267 pr_err("BIOS bug, local APIC #%d not detected!...\n", 1268 boot_cpu_physical_apicid); 1269 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 1270 } 1271 return SMP_NO_APIC; 1272 } 1273 1274 /* 1275 * If SMP should be disabled, then really disable it! 1276 */ 1277 if (!max_cpus) { 1278 pr_info("SMP mode deactivated\n"); 1279 return SMP_FORCE_UP; 1280 } 1281 1282 return SMP_OK; 1283 } 1284 1285 static void __init smp_cpu_index_default(void) 1286 { 1287 int i; 1288 struct cpuinfo_x86 *c; 1289 1290 for_each_possible_cpu(i) { 1291 c = &cpu_data(i); 1292 /* mark all to hotplug */ 1293 c->cpu_index = nr_cpu_ids; 1294 } 1295 } 1296 1297 /* 1298 * Prepare for SMP bootup. The MP table or ACPI has been read 1299 * earlier. Just do some sanity checking here and enable APIC mode. 1300 */ 1301 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1302 { 1303 unsigned int i; 1304 1305 smp_cpu_index_default(); 1306 1307 /* 1308 * Setup boot CPU information 1309 */ 1310 smp_store_boot_cpu_info(); /* Final full version of the data */ 1311 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1312 mb(); 1313 1314 for_each_possible_cpu(i) { 1315 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1316 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1317 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1318 } 1319 1320 /* 1321 * Set 'default' x86 topology, this matches default_topology() in that 1322 * it has NUMA nodes as a topology level. See also 1323 * native_smp_cpus_done(). 1324 * 1325 * Must be done before set_cpus_sibling_map() is ran. 1326 */ 1327 set_sched_topology(x86_topology); 1328 1329 set_cpu_sibling_map(0); 1330 1331 switch (smp_sanity_check(max_cpus)) { 1332 case SMP_NO_CONFIG: 1333 disable_smp(); 1334 if (APIC_init_uniprocessor()) 1335 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 1336 return; 1337 case SMP_NO_APIC: 1338 disable_smp(); 1339 return; 1340 case SMP_FORCE_UP: 1341 disable_smp(); 1342 apic_bsp_setup(false); 1343 return; 1344 case SMP_OK: 1345 break; 1346 } 1347 1348 if (read_apic_id() != boot_cpu_physical_apicid) { 1349 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1350 read_apic_id(), boot_cpu_physical_apicid); 1351 /* Or can we switch back to PIC here? */ 1352 } 1353 1354 default_setup_apic_routing(); 1355 cpu0_logical_apicid = apic_bsp_setup(false); 1356 1357 pr_info("CPU0: "); 1358 print_cpu_info(&cpu_data(0)); 1359 1360 uv_system_init(); 1361 1362 set_mtrr_aps_delayed_init(); 1363 1364 smp_quirk_init_udelay(); 1365 } 1366 1367 void arch_enable_nonboot_cpus_begin(void) 1368 { 1369 set_mtrr_aps_delayed_init(); 1370 } 1371 1372 void arch_enable_nonboot_cpus_end(void) 1373 { 1374 mtrr_aps_init(); 1375 } 1376 1377 /* 1378 * Early setup to make printk work. 1379 */ 1380 void __init native_smp_prepare_boot_cpu(void) 1381 { 1382 int me = smp_processor_id(); 1383 switch_to_new_gdt(me); 1384 /* already set me in cpu_online_mask in boot_cpu_init() */ 1385 cpumask_set_cpu(me, cpu_callout_mask); 1386 cpu_set_state_online(me); 1387 } 1388 1389 void __init native_smp_cpus_done(unsigned int max_cpus) 1390 { 1391 pr_debug("Boot done\n"); 1392 1393 if (x86_has_numa_in_package) 1394 set_sched_topology(x86_numa_in_package_topology); 1395 1396 nmi_selftest(); 1397 impress_friends(); 1398 setup_ioapic_dest(); 1399 mtrr_aps_init(); 1400 } 1401 1402 static int __initdata setup_possible_cpus = -1; 1403 static int __init _setup_possible_cpus(char *str) 1404 { 1405 get_option(&str, &setup_possible_cpus); 1406 return 0; 1407 } 1408 early_param("possible_cpus", _setup_possible_cpus); 1409 1410 1411 /* 1412 * cpu_possible_mask should be static, it cannot change as cpu's 1413 * are onlined, or offlined. The reason is per-cpu data-structures 1414 * are allocated by some modules at init time, and dont expect to 1415 * do this dynamically on cpu arrival/departure. 1416 * cpu_present_mask on the other hand can change dynamically. 1417 * In case when cpu_hotplug is not compiled, then we resort to current 1418 * behaviour, which is cpu_possible == cpu_present. 1419 * - Ashok Raj 1420 * 1421 * Three ways to find out the number of additional hotplug CPUs: 1422 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1423 * - The user can overwrite it with possible_cpus=NUM 1424 * - Otherwise don't reserve additional CPUs. 1425 * We do this because additional CPUs waste a lot of memory. 1426 * -AK 1427 */ 1428 __init void prefill_possible_map(void) 1429 { 1430 int i, possible; 1431 1432 /* No boot processor was found in mptable or ACPI MADT */ 1433 if (!num_processors) { 1434 if (boot_cpu_has(X86_FEATURE_APIC)) { 1435 int apicid = boot_cpu_physical_apicid; 1436 int cpu = hard_smp_processor_id(); 1437 1438 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1439 1440 /* Make sure boot cpu is enumerated */ 1441 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1442 apic->apic_id_valid(apicid)) 1443 generic_processor_info(apicid, boot_cpu_apic_version); 1444 } 1445 1446 if (!num_processors) 1447 num_processors = 1; 1448 } 1449 1450 i = setup_max_cpus ?: 1; 1451 if (setup_possible_cpus == -1) { 1452 possible = num_processors; 1453 #ifdef CONFIG_HOTPLUG_CPU 1454 if (setup_max_cpus) 1455 possible += disabled_cpus; 1456 #else 1457 if (possible > i) 1458 possible = i; 1459 #endif 1460 } else 1461 possible = setup_possible_cpus; 1462 1463 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1464 1465 /* nr_cpu_ids could be reduced via nr_cpus= */ 1466 if (possible > nr_cpu_ids) { 1467 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1468 possible, nr_cpu_ids); 1469 possible = nr_cpu_ids; 1470 } 1471 1472 #ifdef CONFIG_HOTPLUG_CPU 1473 if (!setup_max_cpus) 1474 #endif 1475 if (possible > i) { 1476 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1477 possible, setup_max_cpus); 1478 possible = i; 1479 } 1480 1481 nr_cpu_ids = possible; 1482 1483 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1484 possible, max_t(int, possible - num_processors, 0)); 1485 1486 reset_cpu_possible_mask(); 1487 1488 for (i = 0; i < possible; i++) 1489 set_cpu_possible(i, true); 1490 } 1491 1492 #ifdef CONFIG_HOTPLUG_CPU 1493 1494 /* Recompute SMT state for all CPUs on offline */ 1495 static void recompute_smt_state(void) 1496 { 1497 int max_threads, cpu; 1498 1499 max_threads = 0; 1500 for_each_online_cpu (cpu) { 1501 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1502 1503 if (threads > max_threads) 1504 max_threads = threads; 1505 } 1506 __max_smt_threads = max_threads; 1507 } 1508 1509 static void remove_siblinginfo(int cpu) 1510 { 1511 int sibling; 1512 struct cpuinfo_x86 *c = &cpu_data(cpu); 1513 1514 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1515 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1516 /*/ 1517 * last thread sibling in this cpu core going down 1518 */ 1519 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1520 cpu_data(sibling).booted_cores--; 1521 } 1522 1523 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1524 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1525 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1526 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1527 cpumask_clear(cpu_llc_shared_mask(cpu)); 1528 cpumask_clear(topology_sibling_cpumask(cpu)); 1529 cpumask_clear(topology_core_cpumask(cpu)); 1530 c->phys_proc_id = 0; 1531 c->cpu_core_id = 0; 1532 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1533 recompute_smt_state(); 1534 } 1535 1536 static void remove_cpu_from_maps(int cpu) 1537 { 1538 set_cpu_online(cpu, false); 1539 cpumask_clear_cpu(cpu, cpu_callout_mask); 1540 cpumask_clear_cpu(cpu, cpu_callin_mask); 1541 /* was set by cpu_init() */ 1542 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1543 numa_remove_cpu(cpu); 1544 } 1545 1546 void cpu_disable_common(void) 1547 { 1548 int cpu = smp_processor_id(); 1549 1550 remove_siblinginfo(cpu); 1551 1552 /* It's now safe to remove this processor from the online map */ 1553 lock_vector_lock(); 1554 remove_cpu_from_maps(cpu); 1555 unlock_vector_lock(); 1556 fixup_irqs(); 1557 } 1558 1559 int native_cpu_disable(void) 1560 { 1561 int ret; 1562 1563 ret = check_irq_vectors_for_cpu_disable(); 1564 if (ret) 1565 return ret; 1566 1567 clear_local_APIC(); 1568 cpu_disable_common(); 1569 1570 return 0; 1571 } 1572 1573 int common_cpu_die(unsigned int cpu) 1574 { 1575 int ret = 0; 1576 1577 /* We don't do anything here: idle task is faking death itself. */ 1578 1579 /* They ack this in play_dead() by setting CPU_DEAD */ 1580 if (cpu_wait_death(cpu, 5)) { 1581 if (system_state == SYSTEM_RUNNING) 1582 pr_info("CPU %u is now offline\n", cpu); 1583 } else { 1584 pr_err("CPU %u didn't die...\n", cpu); 1585 ret = -1; 1586 } 1587 1588 return ret; 1589 } 1590 1591 void native_cpu_die(unsigned int cpu) 1592 { 1593 common_cpu_die(cpu); 1594 } 1595 1596 void play_dead_common(void) 1597 { 1598 idle_task_exit(); 1599 1600 /* Ack it */ 1601 (void)cpu_report_death(); 1602 1603 /* 1604 * With physical CPU hotplug, we should halt the cpu 1605 */ 1606 local_irq_disable(); 1607 } 1608 1609 static bool wakeup_cpu0(void) 1610 { 1611 if (smp_processor_id() == 0 && enable_start_cpu0) 1612 return true; 1613 1614 return false; 1615 } 1616 1617 /* 1618 * We need to flush the caches before going to sleep, lest we have 1619 * dirty data in our caches when we come back up. 1620 */ 1621 static inline void mwait_play_dead(void) 1622 { 1623 unsigned int eax, ebx, ecx, edx; 1624 unsigned int highest_cstate = 0; 1625 unsigned int highest_subcstate = 0; 1626 void *mwait_ptr; 1627 int i; 1628 1629 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1630 return; 1631 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1632 return; 1633 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1634 return; 1635 1636 eax = CPUID_MWAIT_LEAF; 1637 ecx = 0; 1638 native_cpuid(&eax, &ebx, &ecx, &edx); 1639 1640 /* 1641 * eax will be 0 if EDX enumeration is not valid. 1642 * Initialized below to cstate, sub_cstate value when EDX is valid. 1643 */ 1644 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1645 eax = 0; 1646 } else { 1647 edx >>= MWAIT_SUBSTATE_SIZE; 1648 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1649 if (edx & MWAIT_SUBSTATE_MASK) { 1650 highest_cstate = i; 1651 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1652 } 1653 } 1654 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1655 (highest_subcstate - 1); 1656 } 1657 1658 /* 1659 * This should be a memory location in a cache line which is 1660 * unlikely to be touched by other processors. The actual 1661 * content is immaterial as it is not actually modified in any way. 1662 */ 1663 mwait_ptr = ¤t_thread_info()->flags; 1664 1665 wbinvd(); 1666 1667 while (1) { 1668 /* 1669 * The CLFLUSH is a workaround for erratum AAI65 for 1670 * the Xeon 7400 series. It's not clear it is actually 1671 * needed, but it should be harmless in either case. 1672 * The WBINVD is insufficient due to the spurious-wakeup 1673 * case where we return around the loop. 1674 */ 1675 mb(); 1676 clflush(mwait_ptr); 1677 mb(); 1678 __monitor(mwait_ptr, 0, 0); 1679 mb(); 1680 __mwait(eax, 0); 1681 /* 1682 * If NMI wants to wake up CPU0, start CPU0. 1683 */ 1684 if (wakeup_cpu0()) 1685 start_cpu0(); 1686 } 1687 } 1688 1689 void hlt_play_dead(void) 1690 { 1691 if (__this_cpu_read(cpu_info.x86) >= 4) 1692 wbinvd(); 1693 1694 while (1) { 1695 native_halt(); 1696 /* 1697 * If NMI wants to wake up CPU0, start CPU0. 1698 */ 1699 if (wakeup_cpu0()) 1700 start_cpu0(); 1701 } 1702 } 1703 1704 void native_play_dead(void) 1705 { 1706 play_dead_common(); 1707 tboot_shutdown(TB_SHUTDOWN_WFS); 1708 1709 mwait_play_dead(); /* Only returns on failure */ 1710 if (cpuidle_play_dead()) 1711 hlt_play_dead(); 1712 } 1713 1714 #else /* ... !CONFIG_HOTPLUG_CPU */ 1715 int native_cpu_disable(void) 1716 { 1717 return -ENOSYS; 1718 } 1719 1720 void native_cpu_die(unsigned int cpu) 1721 { 1722 /* We said "no" in __cpu_disable */ 1723 BUG(); 1724 } 1725 1726 void native_play_dead(void) 1727 { 1728 BUG(); 1729 } 1730 1731 #endif 1732