1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/stackprotector.h> 55 #include <linux/gfp.h> 56 #include <linux/cpuidle.h> 57 #include <linux/numa.h> 58 59 #include <asm/acpi.h> 60 #include <asm/desc.h> 61 #include <asm/nmi.h> 62 #include <asm/irq.h> 63 #include <asm/realmode.h> 64 #include <asm/cpu.h> 65 #include <asm/numa.h> 66 #include <asm/pgtable.h> 67 #include <asm/tlbflush.h> 68 #include <asm/mtrr.h> 69 #include <asm/mwait.h> 70 #include <asm/apic.h> 71 #include <asm/io_apic.h> 72 #include <asm/fpu/internal.h> 73 #include <asm/setup.h> 74 #include <asm/uv/uv.h> 75 #include <linux/mc146818rtc.h> 76 #include <asm/i8259.h> 77 #include <asm/misc.h> 78 #include <asm/qspinlock.h> 79 #include <asm/intel-family.h> 80 #include <asm/cpu_device_id.h> 81 #include <asm/spec-ctrl.h> 82 #include <asm/hw_irq.h> 83 84 /* representing HT siblings of each logical CPU */ 85 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 86 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 87 88 /* representing HT and core siblings of each logical CPU */ 89 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 90 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 91 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 93 94 /* Per CPU bogomips and other parameters */ 95 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 96 EXPORT_PER_CPU_SYMBOL(cpu_info); 97 98 /* Logical package management. We might want to allocate that dynamically */ 99 unsigned int __max_logical_packages __read_mostly; 100 EXPORT_SYMBOL(__max_logical_packages); 101 static unsigned int logical_packages __read_mostly; 102 103 /* Maximum number of SMT threads on any online core */ 104 int __read_mostly __max_smt_threads = 1; 105 106 /* Flag to indicate if a complete sched domain rebuild is required */ 107 bool x86_topology_update; 108 109 int arch_update_cpu_topology(void) 110 { 111 int retval = x86_topology_update; 112 113 x86_topology_update = false; 114 return retval; 115 } 116 117 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 118 { 119 unsigned long flags; 120 121 spin_lock_irqsave(&rtc_lock, flags); 122 CMOS_WRITE(0xa, 0xf); 123 spin_unlock_irqrestore(&rtc_lock, flags); 124 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 125 start_eip >> 4; 126 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 127 start_eip & 0xf; 128 } 129 130 static inline void smpboot_restore_warm_reset_vector(void) 131 { 132 unsigned long flags; 133 134 /* 135 * Paranoid: Set warm reset code and vector here back 136 * to default values. 137 */ 138 spin_lock_irqsave(&rtc_lock, flags); 139 CMOS_WRITE(0, 0xf); 140 spin_unlock_irqrestore(&rtc_lock, flags); 141 142 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 143 } 144 145 /* 146 * Report back to the Boot Processor during boot time or to the caller processor 147 * during CPU online. 148 */ 149 static void smp_callin(void) 150 { 151 int cpuid; 152 153 /* 154 * If waken up by an INIT in an 82489DX configuration 155 * cpu_callout_mask guarantees we don't get here before 156 * an INIT_deassert IPI reaches our local APIC, so it is 157 * now safe to touch our local APIC. 158 */ 159 cpuid = smp_processor_id(); 160 161 /* 162 * the boot CPU has finished the init stage and is spinning 163 * on callin_map until we finish. We are free to set up this 164 * CPU, first the APIC. (this is probably redundant on most 165 * boards) 166 */ 167 apic_ap_setup(); 168 169 /* 170 * Save our processor parameters. Note: this information 171 * is needed for clock calibration. 172 */ 173 smp_store_cpu_info(cpuid); 174 175 /* 176 * The topology information must be up to date before 177 * calibrate_delay() and notify_cpu_starting(). 178 */ 179 set_cpu_sibling_map(raw_smp_processor_id()); 180 181 /* 182 * Get our bogomips. 183 * Update loops_per_jiffy in cpu_data. Previous call to 184 * smp_store_cpu_info() stored a value that is close but not as 185 * accurate as the value just calculated. 186 */ 187 calibrate_delay(); 188 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 189 pr_debug("Stack at about %p\n", &cpuid); 190 191 wmb(); 192 193 notify_cpu_starting(cpuid); 194 195 /* 196 * Allow the master to continue. 197 */ 198 cpumask_set_cpu(cpuid, cpu_callin_mask); 199 } 200 201 static int cpu0_logical_apicid; 202 static int enable_start_cpu0; 203 /* 204 * Activate a secondary processor. 205 */ 206 static void notrace start_secondary(void *unused) 207 { 208 /* 209 * Don't put *anything* except direct CPU state initialization 210 * before cpu_init(), SMP booting is too fragile that we want to 211 * limit the things done here to the most necessary things. 212 */ 213 if (boot_cpu_has(X86_FEATURE_PCID)) 214 __write_cr4(__read_cr4() | X86_CR4_PCIDE); 215 216 #ifdef CONFIG_X86_32 217 /* switch away from the initial page table */ 218 load_cr3(swapper_pg_dir); 219 /* 220 * Initialize the CR4 shadow before doing anything that could 221 * try to read it. 222 */ 223 cr4_init_shadow(); 224 __flush_tlb_all(); 225 #endif 226 load_current_idt(); 227 cpu_init(); 228 x86_cpuinit.early_percpu_clock_init(); 229 preempt_disable(); 230 smp_callin(); 231 232 enable_start_cpu0 = 0; 233 234 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 235 barrier(); 236 /* 237 * Check TSC synchronization with the boot CPU: 238 */ 239 check_tsc_sync_target(); 240 241 speculative_store_bypass_ht_init(); 242 243 /* 244 * Lock vector_lock, set CPU online and bring the vector 245 * allocator online. Online must be set with vector_lock held 246 * to prevent a concurrent irq setup/teardown from seeing a 247 * half valid vector space. 248 */ 249 lock_vector_lock(); 250 set_cpu_online(smp_processor_id(), true); 251 lapic_online(); 252 unlock_vector_lock(); 253 cpu_set_state_online(smp_processor_id()); 254 x86_platform.nmi_init(); 255 256 /* enable local interrupts */ 257 local_irq_enable(); 258 259 /* to prevent fake stack check failure in clock setup */ 260 boot_init_stack_canary(); 261 262 x86_cpuinit.setup_percpu_clockev(); 263 264 wmb(); 265 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 266 } 267 268 /** 269 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 270 * @cpu: CPU to check 271 */ 272 bool topology_is_primary_thread(unsigned int cpu) 273 { 274 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 275 } 276 277 /** 278 * topology_smt_supported - Check whether SMT is supported by the CPUs 279 */ 280 bool topology_smt_supported(void) 281 { 282 return smp_num_siblings > 1; 283 } 284 285 /** 286 * topology_phys_to_logical_pkg - Map a physical package id to a logical 287 * 288 * Returns logical package id or -1 if not found 289 */ 290 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 291 { 292 int cpu; 293 294 for_each_possible_cpu(cpu) { 295 struct cpuinfo_x86 *c = &cpu_data(cpu); 296 297 if (c->initialized && c->phys_proc_id == phys_pkg) 298 return c->logical_proc_id; 299 } 300 return -1; 301 } 302 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 303 304 /** 305 * topology_update_package_map - Update the physical to logical package map 306 * @pkg: The physical package id as retrieved via CPUID 307 * @cpu: The cpu for which this is updated 308 */ 309 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 310 { 311 int new; 312 313 /* Already available somewhere? */ 314 new = topology_phys_to_logical_pkg(pkg); 315 if (new >= 0) 316 goto found; 317 318 new = logical_packages++; 319 if (new != pkg) { 320 pr_info("CPU %u Converting physical %u to logical package %u\n", 321 cpu, pkg, new); 322 } 323 found: 324 cpu_data(cpu).logical_proc_id = new; 325 return 0; 326 } 327 328 void __init smp_store_boot_cpu_info(void) 329 { 330 int id = 0; /* CPU 0 */ 331 struct cpuinfo_x86 *c = &cpu_data(id); 332 333 *c = boot_cpu_data; 334 c->cpu_index = id; 335 topology_update_package_map(c->phys_proc_id, id); 336 c->initialized = true; 337 } 338 339 /* 340 * The bootstrap kernel entry code has set these up. Save them for 341 * a given CPU 342 */ 343 void smp_store_cpu_info(int id) 344 { 345 struct cpuinfo_x86 *c = &cpu_data(id); 346 347 /* Copy boot_cpu_data only on the first bringup */ 348 if (!c->initialized) 349 *c = boot_cpu_data; 350 c->cpu_index = id; 351 /* 352 * During boot time, CPU0 has this setup already. Save the info when 353 * bringing up AP or offlined CPU0. 354 */ 355 identify_secondary_cpu(c); 356 c->initialized = true; 357 } 358 359 static bool 360 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 361 { 362 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 363 364 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 365 } 366 367 static bool 368 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 369 { 370 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 371 372 return !WARN_ONCE(!topology_same_node(c, o), 373 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 374 "[node: %d != %d]. Ignoring dependency.\n", 375 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 376 } 377 378 #define link_mask(mfunc, c1, c2) \ 379 do { \ 380 cpumask_set_cpu((c1), mfunc(c2)); \ 381 cpumask_set_cpu((c2), mfunc(c1)); \ 382 } while (0) 383 384 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 385 { 386 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 387 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 388 389 if (c->phys_proc_id == o->phys_proc_id && 390 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 391 if (c->cpu_core_id == o->cpu_core_id) 392 return topology_sane(c, o, "smt"); 393 394 if ((c->cu_id != 0xff) && 395 (o->cu_id != 0xff) && 396 (c->cu_id == o->cu_id)) 397 return topology_sane(c, o, "smt"); 398 } 399 400 } else if (c->phys_proc_id == o->phys_proc_id && 401 c->cpu_core_id == o->cpu_core_id) { 402 return topology_sane(c, o, "smt"); 403 } 404 405 return false; 406 } 407 408 /* 409 * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. 410 * 411 * These are Intel CPUs that enumerate an LLC that is shared by 412 * multiple NUMA nodes. The LLC on these systems is shared for 413 * off-package data access but private to the NUMA node (half 414 * of the package) for on-package access. 415 * 416 * CPUID (the source of the information about the LLC) can only 417 * enumerate the cache as being shared *or* unshared, but not 418 * this particular configuration. The CPU in this case enumerates 419 * the cache to be shared across the entire package (spanning both 420 * NUMA nodes). 421 */ 422 423 static const struct x86_cpu_id snc_cpu[] = { 424 { X86_VENDOR_INTEL, 6, INTEL_FAM6_SKYLAKE_X }, 425 {} 426 }; 427 428 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 429 { 430 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 431 432 /* Do not match if we do not have a valid APICID for cpu: */ 433 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 434 return false; 435 436 /* Do not match if LLC id does not match: */ 437 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 438 return false; 439 440 /* 441 * Allow the SNC topology without warning. Return of false 442 * means 'c' does not share the LLC of 'o'. This will be 443 * reflected to userspace. 444 */ 445 if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) 446 return false; 447 448 return topology_sane(c, o, "llc"); 449 } 450 451 /* 452 * Unlike the other levels, we do not enforce keeping a 453 * multicore group inside a NUMA node. If this happens, we will 454 * discard the MC level of the topology later. 455 */ 456 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 457 { 458 if (c->phys_proc_id == o->phys_proc_id) 459 return true; 460 return false; 461 } 462 463 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) 464 static inline int x86_sched_itmt_flags(void) 465 { 466 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 467 } 468 469 #ifdef CONFIG_SCHED_MC 470 static int x86_core_flags(void) 471 { 472 return cpu_core_flags() | x86_sched_itmt_flags(); 473 } 474 #endif 475 #ifdef CONFIG_SCHED_SMT 476 static int x86_smt_flags(void) 477 { 478 return cpu_smt_flags() | x86_sched_itmt_flags(); 479 } 480 #endif 481 #endif 482 483 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 484 #ifdef CONFIG_SCHED_SMT 485 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 486 #endif 487 #ifdef CONFIG_SCHED_MC 488 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 489 #endif 490 { NULL, }, 491 }; 492 493 static struct sched_domain_topology_level x86_topology[] = { 494 #ifdef CONFIG_SCHED_SMT 495 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 496 #endif 497 #ifdef CONFIG_SCHED_MC 498 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 499 #endif 500 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 501 { NULL, }, 502 }; 503 504 /* 505 * Set if a package/die has multiple NUMA nodes inside. 506 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 507 * Sub-NUMA Clustering have this. 508 */ 509 static bool x86_has_numa_in_package; 510 511 void set_cpu_sibling_map(int cpu) 512 { 513 bool has_smt = smp_num_siblings > 1; 514 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 515 struct cpuinfo_x86 *c = &cpu_data(cpu); 516 struct cpuinfo_x86 *o; 517 int i, threads; 518 519 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 520 521 if (!has_mp) { 522 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 523 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 524 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 525 c->booted_cores = 1; 526 return; 527 } 528 529 for_each_cpu(i, cpu_sibling_setup_mask) { 530 o = &cpu_data(i); 531 532 if ((i == cpu) || (has_smt && match_smt(c, o))) 533 link_mask(topology_sibling_cpumask, cpu, i); 534 535 if ((i == cpu) || (has_mp && match_llc(c, o))) 536 link_mask(cpu_llc_shared_mask, cpu, i); 537 538 } 539 540 /* 541 * This needs a separate iteration over the cpus because we rely on all 542 * topology_sibling_cpumask links to be set-up. 543 */ 544 for_each_cpu(i, cpu_sibling_setup_mask) { 545 o = &cpu_data(i); 546 547 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 548 link_mask(topology_core_cpumask, cpu, i); 549 550 /* 551 * Does this new cpu bringup a new core? 552 */ 553 if (cpumask_weight( 554 topology_sibling_cpumask(cpu)) == 1) { 555 /* 556 * for each core in package, increment 557 * the booted_cores for this new cpu 558 */ 559 if (cpumask_first( 560 topology_sibling_cpumask(i)) == i) 561 c->booted_cores++; 562 /* 563 * increment the core count for all 564 * the other cpus in this package 565 */ 566 if (i != cpu) 567 cpu_data(i).booted_cores++; 568 } else if (i != cpu && !c->booted_cores) 569 c->booted_cores = cpu_data(i).booted_cores; 570 } 571 if (match_pkg(c, o) && !topology_same_node(c, o)) 572 x86_has_numa_in_package = true; 573 } 574 575 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 576 if (threads > __max_smt_threads) 577 __max_smt_threads = threads; 578 } 579 580 /* maps the cpu to the sched domain representing multi-core */ 581 const struct cpumask *cpu_coregroup_mask(int cpu) 582 { 583 return cpu_llc_shared_mask(cpu); 584 } 585 586 static void impress_friends(void) 587 { 588 int cpu; 589 unsigned long bogosum = 0; 590 /* 591 * Allow the user to impress friends. 592 */ 593 pr_debug("Before bogomips\n"); 594 for_each_possible_cpu(cpu) 595 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 596 bogosum += cpu_data(cpu).loops_per_jiffy; 597 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 598 num_online_cpus(), 599 bogosum/(500000/HZ), 600 (bogosum/(5000/HZ))%100); 601 602 pr_debug("Before bogocount - setting activated=1\n"); 603 } 604 605 void __inquire_remote_apic(int apicid) 606 { 607 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 608 const char * const names[] = { "ID", "VERSION", "SPIV" }; 609 int timeout; 610 u32 status; 611 612 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 613 614 for (i = 0; i < ARRAY_SIZE(regs); i++) { 615 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 616 617 /* 618 * Wait for idle. 619 */ 620 status = safe_apic_wait_icr_idle(); 621 if (status) 622 pr_cont("a previous APIC delivery may have failed\n"); 623 624 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 625 626 timeout = 0; 627 do { 628 udelay(100); 629 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 630 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 631 632 switch (status) { 633 case APIC_ICR_RR_VALID: 634 status = apic_read(APIC_RRR); 635 pr_cont("%08x\n", status); 636 break; 637 default: 638 pr_cont("failed\n"); 639 } 640 } 641 } 642 643 /* 644 * The Multiprocessor Specification 1.4 (1997) example code suggests 645 * that there should be a 10ms delay between the BSP asserting INIT 646 * and de-asserting INIT, when starting a remote processor. 647 * But that slows boot and resume on modern processors, which include 648 * many cores and don't require that delay. 649 * 650 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 651 * Modern processor families are quirked to remove the delay entirely. 652 */ 653 #define UDELAY_10MS_DEFAULT 10000 654 655 static unsigned int init_udelay = UINT_MAX; 656 657 static int __init cpu_init_udelay(char *str) 658 { 659 get_option(&str, &init_udelay); 660 661 return 0; 662 } 663 early_param("cpu_init_udelay", cpu_init_udelay); 664 665 static void __init smp_quirk_init_udelay(void) 666 { 667 /* if cmdline changed it from default, leave it alone */ 668 if (init_udelay != UINT_MAX) 669 return; 670 671 /* if modern processor, use no delay */ 672 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 673 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 674 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 675 init_udelay = 0; 676 return; 677 } 678 /* else, use legacy delay */ 679 init_udelay = UDELAY_10MS_DEFAULT; 680 } 681 682 /* 683 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 684 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 685 * won't ... remember to clear down the APIC, etc later. 686 */ 687 int 688 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 689 { 690 unsigned long send_status, accept_status = 0; 691 int maxlvt; 692 693 /* Target chip */ 694 /* Boot on the stack */ 695 /* Kick the second */ 696 apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); 697 698 pr_debug("Waiting for send to finish...\n"); 699 send_status = safe_apic_wait_icr_idle(); 700 701 /* 702 * Give the other CPU some time to accept the IPI. 703 */ 704 udelay(200); 705 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 706 maxlvt = lapic_get_maxlvt(); 707 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 708 apic_write(APIC_ESR, 0); 709 accept_status = (apic_read(APIC_ESR) & 0xEF); 710 } 711 pr_debug("NMI sent\n"); 712 713 if (send_status) 714 pr_err("APIC never delivered???\n"); 715 if (accept_status) 716 pr_err("APIC delivery error (%lx)\n", accept_status); 717 718 return (send_status | accept_status); 719 } 720 721 static int 722 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 723 { 724 unsigned long send_status = 0, accept_status = 0; 725 int maxlvt, num_starts, j; 726 727 maxlvt = lapic_get_maxlvt(); 728 729 /* 730 * Be paranoid about clearing APIC errors. 731 */ 732 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 733 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 734 apic_write(APIC_ESR, 0); 735 apic_read(APIC_ESR); 736 } 737 738 pr_debug("Asserting INIT\n"); 739 740 /* 741 * Turn INIT on target chip 742 */ 743 /* 744 * Send IPI 745 */ 746 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 747 phys_apicid); 748 749 pr_debug("Waiting for send to finish...\n"); 750 send_status = safe_apic_wait_icr_idle(); 751 752 udelay(init_udelay); 753 754 pr_debug("Deasserting INIT\n"); 755 756 /* Target chip */ 757 /* Send IPI */ 758 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 759 760 pr_debug("Waiting for send to finish...\n"); 761 send_status = safe_apic_wait_icr_idle(); 762 763 mb(); 764 765 /* 766 * Should we send STARTUP IPIs ? 767 * 768 * Determine this based on the APIC version. 769 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 770 */ 771 if (APIC_INTEGRATED(boot_cpu_apic_version)) 772 num_starts = 2; 773 else 774 num_starts = 0; 775 776 /* 777 * Run STARTUP IPI loop. 778 */ 779 pr_debug("#startup loops: %d\n", num_starts); 780 781 for (j = 1; j <= num_starts; j++) { 782 pr_debug("Sending STARTUP #%d\n", j); 783 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 784 apic_write(APIC_ESR, 0); 785 apic_read(APIC_ESR); 786 pr_debug("After apic_write\n"); 787 788 /* 789 * STARTUP IPI 790 */ 791 792 /* Target chip */ 793 /* Boot on the stack */ 794 /* Kick the second */ 795 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 796 phys_apicid); 797 798 /* 799 * Give the other CPU some time to accept the IPI. 800 */ 801 if (init_udelay == 0) 802 udelay(10); 803 else 804 udelay(300); 805 806 pr_debug("Startup point 1\n"); 807 808 pr_debug("Waiting for send to finish...\n"); 809 send_status = safe_apic_wait_icr_idle(); 810 811 /* 812 * Give the other CPU some time to accept the IPI. 813 */ 814 if (init_udelay == 0) 815 udelay(10); 816 else 817 udelay(200); 818 819 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 820 apic_write(APIC_ESR, 0); 821 accept_status = (apic_read(APIC_ESR) & 0xEF); 822 if (send_status || accept_status) 823 break; 824 } 825 pr_debug("After Startup\n"); 826 827 if (send_status) 828 pr_err("APIC never delivered???\n"); 829 if (accept_status) 830 pr_err("APIC delivery error (%lx)\n", accept_status); 831 832 return (send_status | accept_status); 833 } 834 835 /* reduce the number of lines printed when booting a large cpu count system */ 836 static void announce_cpu(int cpu, int apicid) 837 { 838 static int current_node = NUMA_NO_NODE; 839 int node = early_cpu_to_node(cpu); 840 static int width, node_width; 841 842 if (!width) 843 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 844 845 if (!node_width) 846 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 847 848 if (cpu == 1) 849 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 850 851 if (system_state < SYSTEM_RUNNING) { 852 if (node != current_node) { 853 if (current_node > (-1)) 854 pr_cont("\n"); 855 current_node = node; 856 857 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 858 node_width - num_digits(node), " ", node); 859 } 860 861 /* Add padding for the BSP */ 862 if (cpu == 1) 863 pr_cont("%*s", width + 1, " "); 864 865 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 866 867 } else 868 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 869 node, cpu, apicid); 870 } 871 872 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 873 { 874 int cpu; 875 876 cpu = smp_processor_id(); 877 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 878 return NMI_HANDLED; 879 880 return NMI_DONE; 881 } 882 883 /* 884 * Wake up AP by INIT, INIT, STARTUP sequence. 885 * 886 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 887 * boot-strap code which is not a desired behavior for waking up BSP. To 888 * void the boot-strap code, wake up CPU0 by NMI instead. 889 * 890 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 891 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 892 * We'll change this code in the future to wake up hard offlined CPU0 if 893 * real platform and request are available. 894 */ 895 static int 896 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 897 int *cpu0_nmi_registered) 898 { 899 int id; 900 int boot_error; 901 902 preempt_disable(); 903 904 /* 905 * Wake up AP by INIT, INIT, STARTUP sequence. 906 */ 907 if (cpu) { 908 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 909 goto out; 910 } 911 912 /* 913 * Wake up BSP by nmi. 914 * 915 * Register a NMI handler to help wake up CPU0. 916 */ 917 boot_error = register_nmi_handler(NMI_LOCAL, 918 wakeup_cpu0_nmi, 0, "wake_cpu0"); 919 920 if (!boot_error) { 921 enable_start_cpu0 = 1; 922 *cpu0_nmi_registered = 1; 923 if (apic->dest_logical == APIC_DEST_LOGICAL) 924 id = cpu0_logical_apicid; 925 else 926 id = apicid; 927 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 928 } 929 930 out: 931 preempt_enable(); 932 933 return boot_error; 934 } 935 936 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 937 { 938 int ret; 939 940 /* Just in case we booted with a single CPU. */ 941 alternatives_enable_smp(); 942 943 per_cpu(current_task, cpu) = idle; 944 945 /* Initialize the interrupt stack(s) */ 946 ret = irq_init_percpu_irqstack(cpu); 947 if (ret) 948 return ret; 949 950 #ifdef CONFIG_X86_32 951 /* Stack for startup_32 can be just as for start_secondary onwards */ 952 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 953 #else 954 initial_gs = per_cpu_offset(cpu); 955 #endif 956 return 0; 957 } 958 959 /* 960 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 961 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 962 * Returns zero if CPU booted OK, else error code from 963 * ->wakeup_secondary_cpu. 964 */ 965 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 966 int *cpu0_nmi_registered) 967 { 968 volatile u32 *trampoline_status = 969 (volatile u32 *) __va(real_mode_header->trampoline_status); 970 /* start_ip had better be page-aligned! */ 971 unsigned long start_ip = real_mode_header->trampoline_start; 972 973 unsigned long boot_error = 0; 974 unsigned long timeout; 975 976 idle->thread.sp = (unsigned long)task_pt_regs(idle); 977 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 978 initial_code = (unsigned long)start_secondary; 979 initial_stack = idle->thread.sp; 980 981 /* Enable the espfix hack for this CPU */ 982 init_espfix_ap(cpu); 983 984 /* So we see what's up */ 985 announce_cpu(cpu, apicid); 986 987 /* 988 * This grunge runs the startup process for 989 * the targeted processor. 990 */ 991 992 if (x86_platform.legacy.warm_reset) { 993 994 pr_debug("Setting warm reset code and vector.\n"); 995 996 smpboot_setup_warm_reset_vector(start_ip); 997 /* 998 * Be paranoid about clearing APIC errors. 999 */ 1000 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1001 apic_write(APIC_ESR, 0); 1002 apic_read(APIC_ESR); 1003 } 1004 } 1005 1006 /* 1007 * AP might wait on cpu_callout_mask in cpu_init() with 1008 * cpu_initialized_mask set if previous attempt to online 1009 * it timed-out. Clear cpu_initialized_mask so that after 1010 * INIT/SIPI it could start with a clean state. 1011 */ 1012 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1013 smp_mb(); 1014 1015 /* 1016 * Wake up a CPU in difference cases: 1017 * - Use the method in the APIC driver if it's defined 1018 * Otherwise, 1019 * - Use an INIT boot APIC message for APs or NMI for BSP. 1020 */ 1021 if (apic->wakeup_secondary_cpu) 1022 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1023 else 1024 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1025 cpu0_nmi_registered); 1026 1027 if (!boot_error) { 1028 /* 1029 * Wait 10s total for first sign of life from AP 1030 */ 1031 boot_error = -1; 1032 timeout = jiffies + 10*HZ; 1033 while (time_before(jiffies, timeout)) { 1034 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1035 /* 1036 * Tell AP to proceed with initialization 1037 */ 1038 cpumask_set_cpu(cpu, cpu_callout_mask); 1039 boot_error = 0; 1040 break; 1041 } 1042 schedule(); 1043 } 1044 } 1045 1046 if (!boot_error) { 1047 /* 1048 * Wait till AP completes initial initialization 1049 */ 1050 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1051 /* 1052 * Allow other tasks to run while we wait for the 1053 * AP to come online. This also gives a chance 1054 * for the MTRR work(triggered by the AP coming online) 1055 * to be completed in the stop machine context. 1056 */ 1057 schedule(); 1058 } 1059 } 1060 1061 /* mark "stuck" area as not stuck */ 1062 *trampoline_status = 0; 1063 1064 if (x86_platform.legacy.warm_reset) { 1065 /* 1066 * Cleanup possible dangling ends... 1067 */ 1068 smpboot_restore_warm_reset_vector(); 1069 } 1070 1071 return boot_error; 1072 } 1073 1074 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1075 { 1076 int apicid = apic->cpu_present_to_apicid(cpu); 1077 int cpu0_nmi_registered = 0; 1078 unsigned long flags; 1079 int err, ret = 0; 1080 1081 lockdep_assert_irqs_enabled(); 1082 1083 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1084 1085 if (apicid == BAD_APICID || 1086 !physid_isset(apicid, phys_cpu_present_map) || 1087 !apic->apic_id_valid(apicid)) { 1088 pr_err("%s: bad cpu %d\n", __func__, cpu); 1089 return -EINVAL; 1090 } 1091 1092 /* 1093 * Already booted CPU? 1094 */ 1095 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1096 pr_debug("do_boot_cpu %d Already started\n", cpu); 1097 return -ENOSYS; 1098 } 1099 1100 /* 1101 * Save current MTRR state in case it was changed since early boot 1102 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1103 */ 1104 mtrr_save_state(); 1105 1106 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1107 err = cpu_check_up_prepare(cpu); 1108 if (err && err != -EBUSY) 1109 return err; 1110 1111 /* the FPU context is blank, nobody can own it */ 1112 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1113 1114 err = common_cpu_up(cpu, tidle); 1115 if (err) 1116 return err; 1117 1118 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1119 if (err) { 1120 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1121 ret = -EIO; 1122 goto unreg_nmi; 1123 } 1124 1125 /* 1126 * Check TSC synchronization with the AP (keep irqs disabled 1127 * while doing so): 1128 */ 1129 local_irq_save(flags); 1130 check_tsc_sync_source(cpu); 1131 local_irq_restore(flags); 1132 1133 while (!cpu_online(cpu)) { 1134 cpu_relax(); 1135 touch_nmi_watchdog(); 1136 } 1137 1138 unreg_nmi: 1139 /* 1140 * Clean up the nmi handler. Do this after the callin and callout sync 1141 * to avoid impact of possible long unregister time. 1142 */ 1143 if (cpu0_nmi_registered) 1144 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1145 1146 return ret; 1147 } 1148 1149 /** 1150 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1151 */ 1152 void arch_disable_smp_support(void) 1153 { 1154 disable_ioapic_support(); 1155 } 1156 1157 /* 1158 * Fall back to non SMP mode after errors. 1159 * 1160 * RED-PEN audit/test this more. I bet there is more state messed up here. 1161 */ 1162 static __init void disable_smp(void) 1163 { 1164 pr_info("SMP disabled\n"); 1165 1166 disable_ioapic_support(); 1167 1168 init_cpu_present(cpumask_of(0)); 1169 init_cpu_possible(cpumask_of(0)); 1170 1171 if (smp_found_config) 1172 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1173 else 1174 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1175 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1176 cpumask_set_cpu(0, topology_core_cpumask(0)); 1177 } 1178 1179 /* 1180 * Various sanity checks. 1181 */ 1182 static void __init smp_sanity_check(void) 1183 { 1184 preempt_disable(); 1185 1186 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1187 if (def_to_bigsmp && nr_cpu_ids > 8) { 1188 unsigned int cpu; 1189 unsigned nr; 1190 1191 pr_warn("More than 8 CPUs detected - skipping them\n" 1192 "Use CONFIG_X86_BIGSMP\n"); 1193 1194 nr = 0; 1195 for_each_present_cpu(cpu) { 1196 if (nr >= 8) 1197 set_cpu_present(cpu, false); 1198 nr++; 1199 } 1200 1201 nr = 0; 1202 for_each_possible_cpu(cpu) { 1203 if (nr >= 8) 1204 set_cpu_possible(cpu, false); 1205 nr++; 1206 } 1207 1208 nr_cpu_ids = 8; 1209 } 1210 #endif 1211 1212 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1213 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1214 hard_smp_processor_id()); 1215 1216 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1217 } 1218 1219 /* 1220 * Should not be necessary because the MP table should list the boot 1221 * CPU too, but we do it for the sake of robustness anyway. 1222 */ 1223 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1224 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1225 boot_cpu_physical_apicid); 1226 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1227 } 1228 preempt_enable(); 1229 } 1230 1231 static void __init smp_cpu_index_default(void) 1232 { 1233 int i; 1234 struct cpuinfo_x86 *c; 1235 1236 for_each_possible_cpu(i) { 1237 c = &cpu_data(i); 1238 /* mark all to hotplug */ 1239 c->cpu_index = nr_cpu_ids; 1240 } 1241 } 1242 1243 static void __init smp_get_logical_apicid(void) 1244 { 1245 if (x2apic_mode) 1246 cpu0_logical_apicid = apic_read(APIC_LDR); 1247 else 1248 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1249 } 1250 1251 /* 1252 * Prepare for SMP bootup. 1253 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1254 * for common interface support. 1255 */ 1256 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1257 { 1258 unsigned int i; 1259 1260 smp_cpu_index_default(); 1261 1262 /* 1263 * Setup boot CPU information 1264 */ 1265 smp_store_boot_cpu_info(); /* Final full version of the data */ 1266 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1267 mb(); 1268 1269 for_each_possible_cpu(i) { 1270 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1271 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1272 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1273 } 1274 1275 /* 1276 * Set 'default' x86 topology, this matches default_topology() in that 1277 * it has NUMA nodes as a topology level. See also 1278 * native_smp_cpus_done(). 1279 * 1280 * Must be done before set_cpus_sibling_map() is ran. 1281 */ 1282 set_sched_topology(x86_topology); 1283 1284 set_cpu_sibling_map(0); 1285 1286 smp_sanity_check(); 1287 1288 switch (apic_intr_mode) { 1289 case APIC_PIC: 1290 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1291 disable_smp(); 1292 return; 1293 case APIC_SYMMETRIC_IO_NO_ROUTING: 1294 disable_smp(); 1295 /* Setup local timer */ 1296 x86_init.timers.setup_percpu_clockev(); 1297 return; 1298 case APIC_VIRTUAL_WIRE: 1299 case APIC_SYMMETRIC_IO: 1300 break; 1301 } 1302 1303 /* Setup local timer */ 1304 x86_init.timers.setup_percpu_clockev(); 1305 1306 smp_get_logical_apicid(); 1307 1308 pr_info("CPU0: "); 1309 print_cpu_info(&cpu_data(0)); 1310 1311 native_pv_lock_init(); 1312 1313 uv_system_init(); 1314 1315 set_mtrr_aps_delayed_init(); 1316 1317 smp_quirk_init_udelay(); 1318 1319 speculative_store_bypass_ht_init(); 1320 } 1321 1322 void arch_enable_nonboot_cpus_begin(void) 1323 { 1324 set_mtrr_aps_delayed_init(); 1325 } 1326 1327 void arch_enable_nonboot_cpus_end(void) 1328 { 1329 mtrr_aps_init(); 1330 } 1331 1332 /* 1333 * Early setup to make printk work. 1334 */ 1335 void __init native_smp_prepare_boot_cpu(void) 1336 { 1337 int me = smp_processor_id(); 1338 switch_to_new_gdt(me); 1339 /* already set me in cpu_online_mask in boot_cpu_init() */ 1340 cpumask_set_cpu(me, cpu_callout_mask); 1341 cpu_set_state_online(me); 1342 } 1343 1344 void __init calculate_max_logical_packages(void) 1345 { 1346 int ncpus; 1347 1348 /* 1349 * Today neither Intel nor AMD support heterogenous systems so 1350 * extrapolate the boot cpu's data to all packages. 1351 */ 1352 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1353 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1354 pr_info("Max logical packages: %u\n", __max_logical_packages); 1355 } 1356 1357 void __init native_smp_cpus_done(unsigned int max_cpus) 1358 { 1359 pr_debug("Boot done\n"); 1360 1361 calculate_max_logical_packages(); 1362 1363 if (x86_has_numa_in_package) 1364 set_sched_topology(x86_numa_in_package_topology); 1365 1366 nmi_selftest(); 1367 impress_friends(); 1368 mtrr_aps_init(); 1369 } 1370 1371 static int __initdata setup_possible_cpus = -1; 1372 static int __init _setup_possible_cpus(char *str) 1373 { 1374 get_option(&str, &setup_possible_cpus); 1375 return 0; 1376 } 1377 early_param("possible_cpus", _setup_possible_cpus); 1378 1379 1380 /* 1381 * cpu_possible_mask should be static, it cannot change as cpu's 1382 * are onlined, or offlined. The reason is per-cpu data-structures 1383 * are allocated by some modules at init time, and dont expect to 1384 * do this dynamically on cpu arrival/departure. 1385 * cpu_present_mask on the other hand can change dynamically. 1386 * In case when cpu_hotplug is not compiled, then we resort to current 1387 * behaviour, which is cpu_possible == cpu_present. 1388 * - Ashok Raj 1389 * 1390 * Three ways to find out the number of additional hotplug CPUs: 1391 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1392 * - The user can overwrite it with possible_cpus=NUM 1393 * - Otherwise don't reserve additional CPUs. 1394 * We do this because additional CPUs waste a lot of memory. 1395 * -AK 1396 */ 1397 __init void prefill_possible_map(void) 1398 { 1399 int i, possible; 1400 1401 /* No boot processor was found in mptable or ACPI MADT */ 1402 if (!num_processors) { 1403 if (boot_cpu_has(X86_FEATURE_APIC)) { 1404 int apicid = boot_cpu_physical_apicid; 1405 int cpu = hard_smp_processor_id(); 1406 1407 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1408 1409 /* Make sure boot cpu is enumerated */ 1410 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1411 apic->apic_id_valid(apicid)) 1412 generic_processor_info(apicid, boot_cpu_apic_version); 1413 } 1414 1415 if (!num_processors) 1416 num_processors = 1; 1417 } 1418 1419 i = setup_max_cpus ?: 1; 1420 if (setup_possible_cpus == -1) { 1421 possible = num_processors; 1422 #ifdef CONFIG_HOTPLUG_CPU 1423 if (setup_max_cpus) 1424 possible += disabled_cpus; 1425 #else 1426 if (possible > i) 1427 possible = i; 1428 #endif 1429 } else 1430 possible = setup_possible_cpus; 1431 1432 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1433 1434 /* nr_cpu_ids could be reduced via nr_cpus= */ 1435 if (possible > nr_cpu_ids) { 1436 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1437 possible, nr_cpu_ids); 1438 possible = nr_cpu_ids; 1439 } 1440 1441 #ifdef CONFIG_HOTPLUG_CPU 1442 if (!setup_max_cpus) 1443 #endif 1444 if (possible > i) { 1445 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1446 possible, setup_max_cpus); 1447 possible = i; 1448 } 1449 1450 nr_cpu_ids = possible; 1451 1452 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1453 possible, max_t(int, possible - num_processors, 0)); 1454 1455 reset_cpu_possible_mask(); 1456 1457 for (i = 0; i < possible; i++) 1458 set_cpu_possible(i, true); 1459 } 1460 1461 #ifdef CONFIG_HOTPLUG_CPU 1462 1463 /* Recompute SMT state for all CPUs on offline */ 1464 static void recompute_smt_state(void) 1465 { 1466 int max_threads, cpu; 1467 1468 max_threads = 0; 1469 for_each_online_cpu (cpu) { 1470 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1471 1472 if (threads > max_threads) 1473 max_threads = threads; 1474 } 1475 __max_smt_threads = max_threads; 1476 } 1477 1478 static void remove_siblinginfo(int cpu) 1479 { 1480 int sibling; 1481 struct cpuinfo_x86 *c = &cpu_data(cpu); 1482 1483 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1484 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1485 /*/ 1486 * last thread sibling in this cpu core going down 1487 */ 1488 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1489 cpu_data(sibling).booted_cores--; 1490 } 1491 1492 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) 1493 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1494 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1495 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1496 cpumask_clear(cpu_llc_shared_mask(cpu)); 1497 cpumask_clear(topology_sibling_cpumask(cpu)); 1498 cpumask_clear(topology_core_cpumask(cpu)); 1499 c->cpu_core_id = 0; 1500 c->booted_cores = 0; 1501 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1502 recompute_smt_state(); 1503 } 1504 1505 static void remove_cpu_from_maps(int cpu) 1506 { 1507 set_cpu_online(cpu, false); 1508 cpumask_clear_cpu(cpu, cpu_callout_mask); 1509 cpumask_clear_cpu(cpu, cpu_callin_mask); 1510 /* was set by cpu_init() */ 1511 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1512 numa_remove_cpu(cpu); 1513 } 1514 1515 void cpu_disable_common(void) 1516 { 1517 int cpu = smp_processor_id(); 1518 1519 remove_siblinginfo(cpu); 1520 1521 /* It's now safe to remove this processor from the online map */ 1522 lock_vector_lock(); 1523 remove_cpu_from_maps(cpu); 1524 unlock_vector_lock(); 1525 fixup_irqs(); 1526 lapic_offline(); 1527 } 1528 1529 int native_cpu_disable(void) 1530 { 1531 int ret; 1532 1533 ret = lapic_can_unplug_cpu(); 1534 if (ret) 1535 return ret; 1536 1537 clear_local_APIC(); 1538 cpu_disable_common(); 1539 1540 return 0; 1541 } 1542 1543 int common_cpu_die(unsigned int cpu) 1544 { 1545 int ret = 0; 1546 1547 /* We don't do anything here: idle task is faking death itself. */ 1548 1549 /* They ack this in play_dead() by setting CPU_DEAD */ 1550 if (cpu_wait_death(cpu, 5)) { 1551 if (system_state == SYSTEM_RUNNING) 1552 pr_info("CPU %u is now offline\n", cpu); 1553 } else { 1554 pr_err("CPU %u didn't die...\n", cpu); 1555 ret = -1; 1556 } 1557 1558 return ret; 1559 } 1560 1561 void native_cpu_die(unsigned int cpu) 1562 { 1563 common_cpu_die(cpu); 1564 } 1565 1566 void play_dead_common(void) 1567 { 1568 idle_task_exit(); 1569 1570 /* Ack it */ 1571 (void)cpu_report_death(); 1572 1573 /* 1574 * With physical CPU hotplug, we should halt the cpu 1575 */ 1576 local_irq_disable(); 1577 } 1578 1579 static bool wakeup_cpu0(void) 1580 { 1581 if (smp_processor_id() == 0 && enable_start_cpu0) 1582 return true; 1583 1584 return false; 1585 } 1586 1587 /* 1588 * We need to flush the caches before going to sleep, lest we have 1589 * dirty data in our caches when we come back up. 1590 */ 1591 static inline void mwait_play_dead(void) 1592 { 1593 unsigned int eax, ebx, ecx, edx; 1594 unsigned int highest_cstate = 0; 1595 unsigned int highest_subcstate = 0; 1596 void *mwait_ptr; 1597 int i; 1598 1599 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1600 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1601 return; 1602 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1603 return; 1604 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1605 return; 1606 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1607 return; 1608 1609 eax = CPUID_MWAIT_LEAF; 1610 ecx = 0; 1611 native_cpuid(&eax, &ebx, &ecx, &edx); 1612 1613 /* 1614 * eax will be 0 if EDX enumeration is not valid. 1615 * Initialized below to cstate, sub_cstate value when EDX is valid. 1616 */ 1617 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1618 eax = 0; 1619 } else { 1620 edx >>= MWAIT_SUBSTATE_SIZE; 1621 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1622 if (edx & MWAIT_SUBSTATE_MASK) { 1623 highest_cstate = i; 1624 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1625 } 1626 } 1627 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1628 (highest_subcstate - 1); 1629 } 1630 1631 /* 1632 * This should be a memory location in a cache line which is 1633 * unlikely to be touched by other processors. The actual 1634 * content is immaterial as it is not actually modified in any way. 1635 */ 1636 mwait_ptr = ¤t_thread_info()->flags; 1637 1638 wbinvd(); 1639 1640 while (1) { 1641 /* 1642 * The CLFLUSH is a workaround for erratum AAI65 for 1643 * the Xeon 7400 series. It's not clear it is actually 1644 * needed, but it should be harmless in either case. 1645 * The WBINVD is insufficient due to the spurious-wakeup 1646 * case where we return around the loop. 1647 */ 1648 mb(); 1649 clflush(mwait_ptr); 1650 mb(); 1651 __monitor(mwait_ptr, 0, 0); 1652 mb(); 1653 __mwait(eax, 0); 1654 /* 1655 * If NMI wants to wake up CPU0, start CPU0. 1656 */ 1657 if (wakeup_cpu0()) 1658 start_cpu0(); 1659 } 1660 } 1661 1662 void hlt_play_dead(void) 1663 { 1664 if (__this_cpu_read(cpu_info.x86) >= 4) 1665 wbinvd(); 1666 1667 while (1) { 1668 native_halt(); 1669 /* 1670 * If NMI wants to wake up CPU0, start CPU0. 1671 */ 1672 if (wakeup_cpu0()) 1673 start_cpu0(); 1674 } 1675 } 1676 1677 void native_play_dead(void) 1678 { 1679 play_dead_common(); 1680 tboot_shutdown(TB_SHUTDOWN_WFS); 1681 1682 mwait_play_dead(); /* Only returns on failure */ 1683 if (cpuidle_play_dead()) 1684 hlt_play_dead(); 1685 } 1686 1687 #else /* ... !CONFIG_HOTPLUG_CPU */ 1688 int native_cpu_disable(void) 1689 { 1690 return -ENOSYS; 1691 } 1692 1693 void native_cpu_die(unsigned int cpu) 1694 { 1695 /* We said "no" in __cpu_disable */ 1696 BUG(); 1697 } 1698 1699 void native_play_dead(void) 1700 { 1701 BUG(); 1702 } 1703 1704 #endif 1705