1 /* 2 * x86 SMP booting functions 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * Copyright 2001 Andi Kleen, SuSE Labs. 7 * 8 * Much of the core SMP work is based on previous work by Thomas Radke, to 9 * whom a great many thanks are extended. 10 * 11 * Thanks to Intel for making available several different Pentium, 12 * Pentium Pro and Pentium-II/Xeon MP machines. 13 * Original development of Linux SMP code supported by Caldera. 14 * 15 * This code is released under the GNU General Public License version 2 or 16 * later. 17 * 18 * Fixes 19 * Felix Koop : NR_CPUS used properly 20 * Jose Renau : Handle single CPU case. 21 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 22 * Greg Wright : Fix for kernel stacks panic. 23 * Erich Boleyn : MP v1.4 and additional changes. 24 * Matthias Sattler : Changes for 2.1 kernel map. 25 * Michel Lespinasse : Changes for 2.1 kernel map. 26 * Michael Chastain : Change trampoline.S to gnu as. 27 * Alan Cox : Dumb bug: 'B' step PPro's are fine 28 * Ingo Molnar : Added APIC timers, based on code 29 * from Jose Renau 30 * Ingo Molnar : various cleanups and rewrites 31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 33 * Andi Kleen : Changed for SMP boot into long mode. 34 * Martin J. Bligh : Added support for multi-quad systems 35 * Dave Jones : Report invalid combinations of Athlon CPUs. 36 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 37 * Andi Kleen : Converted to new state machine. 38 * Ashok Raj : CPU hotplug support 39 * Glauber Costa : i386 and x86_64 integration 40 */ 41 42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 43 44 #include <linux/init.h> 45 #include <linux/smp.h> 46 #include <linux/module.h> 47 #include <linux/sched.h> 48 #include <linux/percpu.h> 49 #include <linux/bootmem.h> 50 #include <linux/err.h> 51 #include <linux/nmi.h> 52 #include <linux/tboot.h> 53 #include <linux/stackprotector.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 57 #include <asm/acpi.h> 58 #include <asm/desc.h> 59 #include <asm/nmi.h> 60 #include <asm/irq.h> 61 #include <asm/idle.h> 62 #include <asm/realmode.h> 63 #include <asm/cpu.h> 64 #include <asm/numa.h> 65 #include <asm/pgtable.h> 66 #include <asm/tlbflush.h> 67 #include <asm/mtrr.h> 68 #include <asm/mwait.h> 69 #include <asm/apic.h> 70 #include <asm/io_apic.h> 71 #include <asm/setup.h> 72 #include <asm/uv/uv.h> 73 #include <linux/mc146818rtc.h> 74 75 #include <asm/smpboot_hooks.h> 76 #include <asm/i8259.h> 77 78 #include <asm/realmode.h> 79 80 /* State of each CPU */ 81 DEFINE_PER_CPU(int, cpu_state) = { 0 }; 82 83 #ifdef CONFIG_HOTPLUG_CPU 84 /* 85 * We need this for trampoline_base protection from concurrent accesses when 86 * off- and onlining cores wildly. 87 */ 88 static DEFINE_MUTEX(x86_cpu_hotplug_driver_mutex); 89 90 void cpu_hotplug_driver_lock(void) 91 { 92 mutex_lock(&x86_cpu_hotplug_driver_mutex); 93 } 94 95 void cpu_hotplug_driver_unlock(void) 96 { 97 mutex_unlock(&x86_cpu_hotplug_driver_mutex); 98 } 99 100 ssize_t arch_cpu_probe(const char *buf, size_t count) { return -1; } 101 ssize_t arch_cpu_release(const char *buf, size_t count) { return -1; } 102 #endif 103 104 /* Number of siblings per CPU package */ 105 int smp_num_siblings = 1; 106 EXPORT_SYMBOL(smp_num_siblings); 107 108 /* Last level cache ID of each logical CPU */ 109 DEFINE_PER_CPU_READ_MOSTLY(u16, cpu_llc_id) = BAD_APICID; 110 111 /* representing HT siblings of each logical CPU */ 112 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 113 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 114 115 /* representing HT and core siblings of each logical CPU */ 116 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 117 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 118 119 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 120 121 /* Per CPU bogomips and other parameters */ 122 DEFINE_PER_CPU_SHARED_ALIGNED(struct cpuinfo_x86, cpu_info); 123 EXPORT_PER_CPU_SYMBOL(cpu_info); 124 125 atomic_t init_deasserted; 126 127 /* 128 * Report back to the Boot Processor. 129 * Running on AP. 130 */ 131 static void __cpuinit smp_callin(void) 132 { 133 int cpuid, phys_id; 134 unsigned long timeout; 135 136 /* 137 * If waken up by an INIT in an 82489DX configuration 138 * we may get here before an INIT-deassert IPI reaches 139 * our local APIC. We have to wait for the IPI or we'll 140 * lock up on an APIC access. 141 */ 142 if (apic->wait_for_init_deassert) 143 apic->wait_for_init_deassert(&init_deasserted); 144 145 /* 146 * (This works even if the APIC is not enabled.) 147 */ 148 phys_id = read_apic_id(); 149 cpuid = smp_processor_id(); 150 if (cpumask_test_cpu(cpuid, cpu_callin_mask)) { 151 panic("%s: phys CPU#%d, CPU#%d already present??\n", __func__, 152 phys_id, cpuid); 153 } 154 pr_debug("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id); 155 156 /* 157 * STARTUP IPIs are fragile beasts as they might sometimes 158 * trigger some glue motherboard logic. Complete APIC bus 159 * silence for 1 second, this overestimates the time the 160 * boot CPU is spending to send the up to 2 STARTUP IPIs 161 * by a factor of two. This should be enough. 162 */ 163 164 /* 165 * Waiting 2s total for startup (udelay is not yet working) 166 */ 167 timeout = jiffies + 2*HZ; 168 while (time_before(jiffies, timeout)) { 169 /* 170 * Has the boot CPU finished it's STARTUP sequence? 171 */ 172 if (cpumask_test_cpu(cpuid, cpu_callout_mask)) 173 break; 174 cpu_relax(); 175 } 176 177 if (!time_before(jiffies, timeout)) { 178 panic("%s: CPU%d started up but did not get a callout!\n", 179 __func__, cpuid); 180 } 181 182 /* 183 * the boot CPU has finished the init stage and is spinning 184 * on callin_map until we finish. We are free to set up this 185 * CPU, first the APIC. (this is probably redundant on most 186 * boards) 187 */ 188 189 pr_debug("CALLIN, before setup_local_APIC()\n"); 190 if (apic->smp_callin_clear_local_apic) 191 apic->smp_callin_clear_local_apic(); 192 setup_local_APIC(); 193 end_local_APIC_setup(); 194 195 /* 196 * Need to setup vector mappings before we enable interrupts. 197 */ 198 setup_vector_irq(smp_processor_id()); 199 200 /* 201 * Save our processor parameters. Note: this information 202 * is needed for clock calibration. 203 */ 204 smp_store_cpu_info(cpuid); 205 206 /* 207 * Get our bogomips. 208 * Update loops_per_jiffy in cpu_data. Previous call to 209 * smp_store_cpu_info() stored a value that is close but not as 210 * accurate as the value just calculated. 211 */ 212 calibrate_delay(); 213 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 214 pr_debug("Stack at about %p\n", &cpuid); 215 216 /* 217 * This must be done before setting cpu_online_mask 218 * or calling notify_cpu_starting. 219 */ 220 set_cpu_sibling_map(raw_smp_processor_id()); 221 wmb(); 222 223 notify_cpu_starting(cpuid); 224 225 /* 226 * Allow the master to continue. 227 */ 228 cpumask_set_cpu(cpuid, cpu_callin_mask); 229 } 230 231 /* 232 * Activate a secondary processor. 233 */ 234 notrace static void __cpuinit start_secondary(void *unused) 235 { 236 /* 237 * Don't put *anything* before cpu_init(), SMP booting is too 238 * fragile that we want to limit the things done here to the 239 * most necessary things. 240 */ 241 cpu_init(); 242 x86_cpuinit.early_percpu_clock_init(); 243 preempt_disable(); 244 smp_callin(); 245 246 #ifdef CONFIG_X86_32 247 /* switch away from the initial page table */ 248 load_cr3(swapper_pg_dir); 249 __flush_tlb_all(); 250 #endif 251 252 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 253 barrier(); 254 /* 255 * Check TSC synchronization with the BP: 256 */ 257 check_tsc_sync_target(); 258 259 /* 260 * We need to hold vector_lock so there the set of online cpus 261 * does not change while we are assigning vectors to cpus. Holding 262 * this lock ensures we don't half assign or remove an irq from a cpu. 263 */ 264 lock_vector_lock(); 265 set_cpu_online(smp_processor_id(), true); 266 unlock_vector_lock(); 267 per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE; 268 x86_platform.nmi_init(); 269 270 /* enable local interrupts */ 271 local_irq_enable(); 272 273 /* to prevent fake stack check failure in clock setup */ 274 boot_init_stack_canary(); 275 276 x86_cpuinit.setup_percpu_clockev(); 277 278 wmb(); 279 cpu_idle(); 280 } 281 282 /* 283 * The bootstrap kernel entry code has set these up. Save them for 284 * a given CPU 285 */ 286 287 void __cpuinit smp_store_cpu_info(int id) 288 { 289 struct cpuinfo_x86 *c = &cpu_data(id); 290 291 *c = boot_cpu_data; 292 c->cpu_index = id; 293 if (id != 0) 294 identify_secondary_cpu(c); 295 } 296 297 static bool __cpuinit 298 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 299 { 300 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 301 302 return !WARN_ONCE(cpu_to_node(cpu1) != cpu_to_node(cpu2), 303 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 304 "[node: %d != %d]. Ignoring dependency.\n", 305 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 306 } 307 308 #define link_mask(_m, c1, c2) \ 309 do { \ 310 cpumask_set_cpu((c1), cpu_##_m##_mask(c2)); \ 311 cpumask_set_cpu((c2), cpu_##_m##_mask(c1)); \ 312 } while (0) 313 314 static bool __cpuinit match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 315 { 316 if (cpu_has(c, X86_FEATURE_TOPOEXT)) { 317 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 318 319 if (c->phys_proc_id == o->phys_proc_id && 320 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2) && 321 c->compute_unit_id == o->compute_unit_id) 322 return topology_sane(c, o, "smt"); 323 324 } else if (c->phys_proc_id == o->phys_proc_id && 325 c->cpu_core_id == o->cpu_core_id) { 326 return topology_sane(c, o, "smt"); 327 } 328 329 return false; 330 } 331 332 static bool __cpuinit match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 333 { 334 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 335 336 if (per_cpu(cpu_llc_id, cpu1) != BAD_APICID && 337 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) 338 return topology_sane(c, o, "llc"); 339 340 return false; 341 } 342 343 static bool __cpuinit match_mc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 344 { 345 if (c->phys_proc_id == o->phys_proc_id) { 346 if (cpu_has(c, X86_FEATURE_AMD_DCM)) 347 return true; 348 349 return topology_sane(c, o, "mc"); 350 } 351 return false; 352 } 353 354 void __cpuinit set_cpu_sibling_map(int cpu) 355 { 356 bool has_mc = boot_cpu_data.x86_max_cores > 1; 357 bool has_smt = smp_num_siblings > 1; 358 struct cpuinfo_x86 *c = &cpu_data(cpu); 359 struct cpuinfo_x86 *o; 360 int i; 361 362 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 363 364 if (!has_smt && !has_mc) { 365 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu)); 366 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 367 cpumask_set_cpu(cpu, cpu_core_mask(cpu)); 368 c->booted_cores = 1; 369 return; 370 } 371 372 for_each_cpu(i, cpu_sibling_setup_mask) { 373 o = &cpu_data(i); 374 375 if ((i == cpu) || (has_smt && match_smt(c, o))) 376 link_mask(sibling, cpu, i); 377 378 if ((i == cpu) || (has_mc && match_llc(c, o))) 379 link_mask(llc_shared, cpu, i); 380 381 } 382 383 /* 384 * This needs a separate iteration over the cpus because we rely on all 385 * cpu_sibling_mask links to be set-up. 386 */ 387 for_each_cpu(i, cpu_sibling_setup_mask) { 388 o = &cpu_data(i); 389 390 if ((i == cpu) || (has_mc && match_mc(c, o))) { 391 link_mask(core, cpu, i); 392 393 /* 394 * Does this new cpu bringup a new core? 395 */ 396 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) { 397 /* 398 * for each core in package, increment 399 * the booted_cores for this new cpu 400 */ 401 if (cpumask_first(cpu_sibling_mask(i)) == i) 402 c->booted_cores++; 403 /* 404 * increment the core count for all 405 * the other cpus in this package 406 */ 407 if (i != cpu) 408 cpu_data(i).booted_cores++; 409 } else if (i != cpu && !c->booted_cores) 410 c->booted_cores = cpu_data(i).booted_cores; 411 } 412 } 413 } 414 415 /* maps the cpu to the sched domain representing multi-core */ 416 const struct cpumask *cpu_coregroup_mask(int cpu) 417 { 418 return cpu_llc_shared_mask(cpu); 419 } 420 421 static void impress_friends(void) 422 { 423 int cpu; 424 unsigned long bogosum = 0; 425 /* 426 * Allow the user to impress friends. 427 */ 428 pr_debug("Before bogomips\n"); 429 for_each_possible_cpu(cpu) 430 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 431 bogosum += cpu_data(cpu).loops_per_jiffy; 432 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 433 num_online_cpus(), 434 bogosum/(500000/HZ), 435 (bogosum/(5000/HZ))%100); 436 437 pr_debug("Before bogocount - setting activated=1\n"); 438 } 439 440 void __inquire_remote_apic(int apicid) 441 { 442 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 443 const char * const names[] = { "ID", "VERSION", "SPIV" }; 444 int timeout; 445 u32 status; 446 447 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 448 449 for (i = 0; i < ARRAY_SIZE(regs); i++) { 450 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 451 452 /* 453 * Wait for idle. 454 */ 455 status = safe_apic_wait_icr_idle(); 456 if (status) 457 pr_cont("a previous APIC delivery may have failed\n"); 458 459 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 460 461 timeout = 0; 462 do { 463 udelay(100); 464 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 465 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 466 467 switch (status) { 468 case APIC_ICR_RR_VALID: 469 status = apic_read(APIC_RRR); 470 pr_cont("%08x\n", status); 471 break; 472 default: 473 pr_cont("failed\n"); 474 } 475 } 476 } 477 478 /* 479 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 480 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 481 * won't ... remember to clear down the APIC, etc later. 482 */ 483 int __cpuinit 484 wakeup_secondary_cpu_via_nmi(int logical_apicid, unsigned long start_eip) 485 { 486 unsigned long send_status, accept_status = 0; 487 int maxlvt; 488 489 /* Target chip */ 490 /* Boot on the stack */ 491 /* Kick the second */ 492 apic_icr_write(APIC_DM_NMI | apic->dest_logical, logical_apicid); 493 494 pr_debug("Waiting for send to finish...\n"); 495 send_status = safe_apic_wait_icr_idle(); 496 497 /* 498 * Give the other CPU some time to accept the IPI. 499 */ 500 udelay(200); 501 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 502 maxlvt = lapic_get_maxlvt(); 503 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 504 apic_write(APIC_ESR, 0); 505 accept_status = (apic_read(APIC_ESR) & 0xEF); 506 } 507 pr_debug("NMI sent\n"); 508 509 if (send_status) 510 pr_err("APIC never delivered???\n"); 511 if (accept_status) 512 pr_err("APIC delivery error (%lx)\n", accept_status); 513 514 return (send_status | accept_status); 515 } 516 517 static int __cpuinit 518 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 519 { 520 unsigned long send_status, accept_status = 0; 521 int maxlvt, num_starts, j; 522 523 maxlvt = lapic_get_maxlvt(); 524 525 /* 526 * Be paranoid about clearing APIC errors. 527 */ 528 if (APIC_INTEGRATED(apic_version[phys_apicid])) { 529 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 530 apic_write(APIC_ESR, 0); 531 apic_read(APIC_ESR); 532 } 533 534 pr_debug("Asserting INIT\n"); 535 536 /* 537 * Turn INIT on target chip 538 */ 539 /* 540 * Send IPI 541 */ 542 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 543 phys_apicid); 544 545 pr_debug("Waiting for send to finish...\n"); 546 send_status = safe_apic_wait_icr_idle(); 547 548 mdelay(10); 549 550 pr_debug("Deasserting INIT\n"); 551 552 /* Target chip */ 553 /* Send IPI */ 554 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 555 556 pr_debug("Waiting for send to finish...\n"); 557 send_status = safe_apic_wait_icr_idle(); 558 559 mb(); 560 atomic_set(&init_deasserted, 1); 561 562 /* 563 * Should we send STARTUP IPIs ? 564 * 565 * Determine this based on the APIC version. 566 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 567 */ 568 if (APIC_INTEGRATED(apic_version[phys_apicid])) 569 num_starts = 2; 570 else 571 num_starts = 0; 572 573 /* 574 * Paravirt / VMI wants a startup IPI hook here to set up the 575 * target processor state. 576 */ 577 startup_ipi_hook(phys_apicid, (unsigned long) start_secondary, 578 stack_start); 579 580 /* 581 * Run STARTUP IPI loop. 582 */ 583 pr_debug("#startup loops: %d\n", num_starts); 584 585 for (j = 1; j <= num_starts; j++) { 586 pr_debug("Sending STARTUP #%d\n", j); 587 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 588 apic_write(APIC_ESR, 0); 589 apic_read(APIC_ESR); 590 pr_debug("After apic_write\n"); 591 592 /* 593 * STARTUP IPI 594 */ 595 596 /* Target chip */ 597 /* Boot on the stack */ 598 /* Kick the second */ 599 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 600 phys_apicid); 601 602 /* 603 * Give the other CPU some time to accept the IPI. 604 */ 605 udelay(300); 606 607 pr_debug("Startup point 1\n"); 608 609 pr_debug("Waiting for send to finish...\n"); 610 send_status = safe_apic_wait_icr_idle(); 611 612 /* 613 * Give the other CPU some time to accept the IPI. 614 */ 615 udelay(200); 616 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 617 apic_write(APIC_ESR, 0); 618 accept_status = (apic_read(APIC_ESR) & 0xEF); 619 if (send_status || accept_status) 620 break; 621 } 622 pr_debug("After Startup\n"); 623 624 if (send_status) 625 pr_err("APIC never delivered???\n"); 626 if (accept_status) 627 pr_err("APIC delivery error (%lx)\n", accept_status); 628 629 return (send_status | accept_status); 630 } 631 632 /* reduce the number of lines printed when booting a large cpu count system */ 633 static void __cpuinit announce_cpu(int cpu, int apicid) 634 { 635 static int current_node = -1; 636 int node = early_cpu_to_node(cpu); 637 638 if (system_state == SYSTEM_BOOTING) { 639 if (node != current_node) { 640 if (current_node > (-1)) 641 pr_cont(" OK\n"); 642 current_node = node; 643 pr_info("Booting Node %3d, Processors ", node); 644 } 645 pr_cont(" #%d%s", cpu, cpu == (nr_cpu_ids - 1) ? " OK\n" : ""); 646 return; 647 } else 648 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 649 node, cpu, apicid); 650 } 651 652 /* 653 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 654 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 655 * Returns zero if CPU booted OK, else error code from 656 * ->wakeup_secondary_cpu. 657 */ 658 static int __cpuinit do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 659 { 660 volatile u32 *trampoline_status = 661 (volatile u32 *) __va(real_mode_header->trampoline_status); 662 /* start_ip had better be page-aligned! */ 663 unsigned long start_ip = real_mode_header->trampoline_start; 664 665 unsigned long boot_error = 0; 666 int timeout; 667 668 /* Just in case we booted with a single CPU. */ 669 alternatives_enable_smp(); 670 671 idle->thread.sp = (unsigned long) (((struct pt_regs *) 672 (THREAD_SIZE + task_stack_page(idle))) - 1); 673 per_cpu(current_task, cpu) = idle; 674 675 #ifdef CONFIG_X86_32 676 /* Stack for startup_32 can be just as for start_secondary onwards */ 677 irq_ctx_init(cpu); 678 #else 679 clear_tsk_thread_flag(idle, TIF_FORK); 680 initial_gs = per_cpu_offset(cpu); 681 per_cpu(kernel_stack, cpu) = 682 (unsigned long)task_stack_page(idle) - 683 KERNEL_STACK_OFFSET + THREAD_SIZE; 684 #endif 685 early_gdt_descr.address = (unsigned long)get_cpu_gdt_table(cpu); 686 initial_code = (unsigned long)start_secondary; 687 stack_start = idle->thread.sp; 688 689 /* So we see what's up */ 690 announce_cpu(cpu, apicid); 691 692 /* 693 * This grunge runs the startup process for 694 * the targeted processor. 695 */ 696 697 atomic_set(&init_deasserted, 0); 698 699 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 700 701 pr_debug("Setting warm reset code and vector.\n"); 702 703 smpboot_setup_warm_reset_vector(start_ip); 704 /* 705 * Be paranoid about clearing APIC errors. 706 */ 707 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid])) { 708 apic_write(APIC_ESR, 0); 709 apic_read(APIC_ESR); 710 } 711 } 712 713 /* 714 * Kick the secondary CPU. Use the method in the APIC driver 715 * if it's defined - or use an INIT boot APIC message otherwise: 716 */ 717 if (apic->wakeup_secondary_cpu) 718 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 719 else 720 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 721 722 if (!boot_error) { 723 /* 724 * allow APs to start initializing. 725 */ 726 pr_debug("Before Callout %d\n", cpu); 727 cpumask_set_cpu(cpu, cpu_callout_mask); 728 pr_debug("After Callout %d\n", cpu); 729 730 /* 731 * Wait 5s total for a response 732 */ 733 for (timeout = 0; timeout < 50000; timeout++) { 734 if (cpumask_test_cpu(cpu, cpu_callin_mask)) 735 break; /* It has booted */ 736 udelay(100); 737 /* 738 * Allow other tasks to run while we wait for the 739 * AP to come online. This also gives a chance 740 * for the MTRR work(triggered by the AP coming online) 741 * to be completed in the stop machine context. 742 */ 743 schedule(); 744 } 745 746 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 747 print_cpu_msr(&cpu_data(cpu)); 748 pr_debug("CPU%d: has booted.\n", cpu); 749 } else { 750 boot_error = 1; 751 if (*trampoline_status == 0xA5A5A5A5) 752 /* trampoline started but...? */ 753 pr_err("CPU%d: Stuck ??\n", cpu); 754 else 755 /* trampoline code not run */ 756 pr_err("CPU%d: Not responding\n", cpu); 757 if (apic->inquire_remote_apic) 758 apic->inquire_remote_apic(apicid); 759 } 760 } 761 762 if (boot_error) { 763 /* Try to put things back the way they were before ... */ 764 numa_remove_cpu(cpu); /* was set by numa_add_cpu */ 765 766 /* was set by do_boot_cpu() */ 767 cpumask_clear_cpu(cpu, cpu_callout_mask); 768 769 /* was set by cpu_init() */ 770 cpumask_clear_cpu(cpu, cpu_initialized_mask); 771 772 set_cpu_present(cpu, false); 773 per_cpu(x86_cpu_to_apicid, cpu) = BAD_APICID; 774 } 775 776 /* mark "stuck" area as not stuck */ 777 *trampoline_status = 0; 778 779 if (get_uv_system_type() != UV_NON_UNIQUE_APIC) { 780 /* 781 * Cleanup possible dangling ends... 782 */ 783 smpboot_restore_warm_reset_vector(); 784 } 785 return boot_error; 786 } 787 788 int __cpuinit native_cpu_up(unsigned int cpu, struct task_struct *tidle) 789 { 790 int apicid = apic->cpu_present_to_apicid(cpu); 791 unsigned long flags; 792 int err; 793 794 WARN_ON(irqs_disabled()); 795 796 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 797 798 if (apicid == BAD_APICID || apicid == boot_cpu_physical_apicid || 799 !physid_isset(apicid, phys_cpu_present_map) || 800 !apic->apic_id_valid(apicid)) { 801 pr_err("%s: bad cpu %d\n", __func__, cpu); 802 return -EINVAL; 803 } 804 805 /* 806 * Already booted CPU? 807 */ 808 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 809 pr_debug("do_boot_cpu %d Already started\n", cpu); 810 return -ENOSYS; 811 } 812 813 /* 814 * Save current MTRR state in case it was changed since early boot 815 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 816 */ 817 mtrr_save_state(); 818 819 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE; 820 821 err = do_boot_cpu(apicid, cpu, tidle); 822 if (err) { 823 pr_debug("do_boot_cpu failed %d\n", err); 824 return -EIO; 825 } 826 827 /* 828 * Check TSC synchronization with the AP (keep irqs disabled 829 * while doing so): 830 */ 831 local_irq_save(flags); 832 check_tsc_sync_source(cpu); 833 local_irq_restore(flags); 834 835 while (!cpu_online(cpu)) { 836 cpu_relax(); 837 touch_nmi_watchdog(); 838 } 839 840 return 0; 841 } 842 843 /** 844 * arch_disable_smp_support() - disables SMP support for x86 at runtime 845 */ 846 void arch_disable_smp_support(void) 847 { 848 disable_ioapic_support(); 849 } 850 851 /* 852 * Fall back to non SMP mode after errors. 853 * 854 * RED-PEN audit/test this more. I bet there is more state messed up here. 855 */ 856 static __init void disable_smp(void) 857 { 858 init_cpu_present(cpumask_of(0)); 859 init_cpu_possible(cpumask_of(0)); 860 smpboot_clear_io_apic_irqs(); 861 862 if (smp_found_config) 863 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 864 else 865 physid_set_mask_of_physid(0, &phys_cpu_present_map); 866 cpumask_set_cpu(0, cpu_sibling_mask(0)); 867 cpumask_set_cpu(0, cpu_core_mask(0)); 868 } 869 870 /* 871 * Various sanity checks. 872 */ 873 static int __init smp_sanity_check(unsigned max_cpus) 874 { 875 preempt_disable(); 876 877 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 878 if (def_to_bigsmp && nr_cpu_ids > 8) { 879 unsigned int cpu; 880 unsigned nr; 881 882 pr_warn("More than 8 CPUs detected - skipping them\n" 883 "Use CONFIG_X86_BIGSMP\n"); 884 885 nr = 0; 886 for_each_present_cpu(cpu) { 887 if (nr >= 8) 888 set_cpu_present(cpu, false); 889 nr++; 890 } 891 892 nr = 0; 893 for_each_possible_cpu(cpu) { 894 if (nr >= 8) 895 set_cpu_possible(cpu, false); 896 nr++; 897 } 898 899 nr_cpu_ids = 8; 900 } 901 #endif 902 903 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 904 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 905 hard_smp_processor_id()); 906 907 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 908 } 909 910 /* 911 * If we couldn't find an SMP configuration at boot time, 912 * get out of here now! 913 */ 914 if (!smp_found_config && !acpi_lapic) { 915 preempt_enable(); 916 pr_notice("SMP motherboard not detected\n"); 917 disable_smp(); 918 if (APIC_init_uniprocessor()) 919 pr_notice("Local APIC not detected. Using dummy APIC emulation.\n"); 920 return -1; 921 } 922 923 /* 924 * Should not be necessary because the MP table should list the boot 925 * CPU too, but we do it for the sake of robustness anyway. 926 */ 927 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 928 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 929 boot_cpu_physical_apicid); 930 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 931 } 932 preempt_enable(); 933 934 /* 935 * If we couldn't find a local APIC, then get out of here now! 936 */ 937 if (APIC_INTEGRATED(apic_version[boot_cpu_physical_apicid]) && 938 !cpu_has_apic) { 939 if (!disable_apic) { 940 pr_err("BIOS bug, local APIC #%d not detected!...\n", 941 boot_cpu_physical_apicid); 942 pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n"); 943 } 944 smpboot_clear_io_apic(); 945 disable_ioapic_support(); 946 return -1; 947 } 948 949 verify_local_APIC(); 950 951 /* 952 * If SMP should be disabled, then really disable it! 953 */ 954 if (!max_cpus) { 955 pr_info("SMP mode deactivated\n"); 956 smpboot_clear_io_apic(); 957 958 connect_bsp_APIC(); 959 setup_local_APIC(); 960 bsp_end_local_APIC_setup(); 961 return -1; 962 } 963 964 return 0; 965 } 966 967 static void __init smp_cpu_index_default(void) 968 { 969 int i; 970 struct cpuinfo_x86 *c; 971 972 for_each_possible_cpu(i) { 973 c = &cpu_data(i); 974 /* mark all to hotplug */ 975 c->cpu_index = nr_cpu_ids; 976 } 977 } 978 979 /* 980 * Prepare for SMP bootup. The MP table or ACPI has been read 981 * earlier. Just do some sanity checking here and enable APIC mode. 982 */ 983 void __init native_smp_prepare_cpus(unsigned int max_cpus) 984 { 985 unsigned int i; 986 987 preempt_disable(); 988 smp_cpu_index_default(); 989 990 /* 991 * Setup boot CPU information 992 */ 993 smp_store_cpu_info(0); /* Final full version of the data */ 994 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 995 mb(); 996 997 current_thread_info()->cpu = 0; /* needed? */ 998 for_each_possible_cpu(i) { 999 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1000 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1001 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1002 } 1003 set_cpu_sibling_map(0); 1004 1005 1006 if (smp_sanity_check(max_cpus) < 0) { 1007 pr_info("SMP disabled\n"); 1008 disable_smp(); 1009 goto out; 1010 } 1011 1012 default_setup_apic_routing(); 1013 1014 preempt_disable(); 1015 if (read_apic_id() != boot_cpu_physical_apicid) { 1016 panic("Boot APIC ID in local APIC unexpected (%d vs %d)", 1017 read_apic_id(), boot_cpu_physical_apicid); 1018 /* Or can we switch back to PIC here? */ 1019 } 1020 preempt_enable(); 1021 1022 connect_bsp_APIC(); 1023 1024 /* 1025 * Switch from PIC to APIC mode. 1026 */ 1027 setup_local_APIC(); 1028 1029 /* 1030 * Enable IO APIC before setting up error vector 1031 */ 1032 if (!skip_ioapic_setup && nr_ioapics) 1033 enable_IO_APIC(); 1034 1035 bsp_end_local_APIC_setup(); 1036 1037 if (apic->setup_portio_remap) 1038 apic->setup_portio_remap(); 1039 1040 smpboot_setup_io_apic(); 1041 /* 1042 * Set up local APIC timer on boot CPU. 1043 */ 1044 1045 pr_info("CPU%d: ", 0); 1046 print_cpu_info(&cpu_data(0)); 1047 x86_init.timers.setup_percpu_clockev(); 1048 1049 if (is_uv_system()) 1050 uv_system_init(); 1051 1052 set_mtrr_aps_delayed_init(); 1053 out: 1054 preempt_enable(); 1055 } 1056 1057 void arch_enable_nonboot_cpus_begin(void) 1058 { 1059 set_mtrr_aps_delayed_init(); 1060 } 1061 1062 void arch_enable_nonboot_cpus_end(void) 1063 { 1064 mtrr_aps_init(); 1065 } 1066 1067 /* 1068 * Early setup to make printk work. 1069 */ 1070 void __init native_smp_prepare_boot_cpu(void) 1071 { 1072 int me = smp_processor_id(); 1073 switch_to_new_gdt(me); 1074 /* already set me in cpu_online_mask in boot_cpu_init() */ 1075 cpumask_set_cpu(me, cpu_callout_mask); 1076 per_cpu(cpu_state, me) = CPU_ONLINE; 1077 } 1078 1079 void __init native_smp_cpus_done(unsigned int max_cpus) 1080 { 1081 pr_debug("Boot done\n"); 1082 1083 nmi_selftest(); 1084 impress_friends(); 1085 #ifdef CONFIG_X86_IO_APIC 1086 setup_ioapic_dest(); 1087 #endif 1088 mtrr_aps_init(); 1089 } 1090 1091 static int __initdata setup_possible_cpus = -1; 1092 static int __init _setup_possible_cpus(char *str) 1093 { 1094 get_option(&str, &setup_possible_cpus); 1095 return 0; 1096 } 1097 early_param("possible_cpus", _setup_possible_cpus); 1098 1099 1100 /* 1101 * cpu_possible_mask should be static, it cannot change as cpu's 1102 * are onlined, or offlined. The reason is per-cpu data-structures 1103 * are allocated by some modules at init time, and dont expect to 1104 * do this dynamically on cpu arrival/departure. 1105 * cpu_present_mask on the other hand can change dynamically. 1106 * In case when cpu_hotplug is not compiled, then we resort to current 1107 * behaviour, which is cpu_possible == cpu_present. 1108 * - Ashok Raj 1109 * 1110 * Three ways to find out the number of additional hotplug CPUs: 1111 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1112 * - The user can overwrite it with possible_cpus=NUM 1113 * - Otherwise don't reserve additional CPUs. 1114 * We do this because additional CPUs waste a lot of memory. 1115 * -AK 1116 */ 1117 __init void prefill_possible_map(void) 1118 { 1119 int i, possible; 1120 1121 /* no processor from mptable or madt */ 1122 if (!num_processors) 1123 num_processors = 1; 1124 1125 i = setup_max_cpus ?: 1; 1126 if (setup_possible_cpus == -1) { 1127 possible = num_processors; 1128 #ifdef CONFIG_HOTPLUG_CPU 1129 if (setup_max_cpus) 1130 possible += disabled_cpus; 1131 #else 1132 if (possible > i) 1133 possible = i; 1134 #endif 1135 } else 1136 possible = setup_possible_cpus; 1137 1138 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1139 1140 /* nr_cpu_ids could be reduced via nr_cpus= */ 1141 if (possible > nr_cpu_ids) { 1142 pr_warn("%d Processors exceeds NR_CPUS limit of %d\n", 1143 possible, nr_cpu_ids); 1144 possible = nr_cpu_ids; 1145 } 1146 1147 #ifdef CONFIG_HOTPLUG_CPU 1148 if (!setup_max_cpus) 1149 #endif 1150 if (possible > i) { 1151 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1152 possible, setup_max_cpus); 1153 possible = i; 1154 } 1155 1156 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1157 possible, max_t(int, possible - num_processors, 0)); 1158 1159 for (i = 0; i < possible; i++) 1160 set_cpu_possible(i, true); 1161 for (; i < NR_CPUS; i++) 1162 set_cpu_possible(i, false); 1163 1164 nr_cpu_ids = possible; 1165 } 1166 1167 #ifdef CONFIG_HOTPLUG_CPU 1168 1169 static void remove_siblinginfo(int cpu) 1170 { 1171 int sibling; 1172 struct cpuinfo_x86 *c = &cpu_data(cpu); 1173 1174 for_each_cpu(sibling, cpu_core_mask(cpu)) { 1175 cpumask_clear_cpu(cpu, cpu_core_mask(sibling)); 1176 /*/ 1177 * last thread sibling in this cpu core going down 1178 */ 1179 if (cpumask_weight(cpu_sibling_mask(cpu)) == 1) 1180 cpu_data(sibling).booted_cores--; 1181 } 1182 1183 for_each_cpu(sibling, cpu_sibling_mask(cpu)) 1184 cpumask_clear_cpu(cpu, cpu_sibling_mask(sibling)); 1185 cpumask_clear(cpu_sibling_mask(cpu)); 1186 cpumask_clear(cpu_core_mask(cpu)); 1187 c->phys_proc_id = 0; 1188 c->cpu_core_id = 0; 1189 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1190 } 1191 1192 static void __ref remove_cpu_from_maps(int cpu) 1193 { 1194 set_cpu_online(cpu, false); 1195 cpumask_clear_cpu(cpu, cpu_callout_mask); 1196 cpumask_clear_cpu(cpu, cpu_callin_mask); 1197 /* was set by cpu_init() */ 1198 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1199 numa_remove_cpu(cpu); 1200 } 1201 1202 void cpu_disable_common(void) 1203 { 1204 int cpu = smp_processor_id(); 1205 1206 remove_siblinginfo(cpu); 1207 1208 /* It's now safe to remove this processor from the online map */ 1209 lock_vector_lock(); 1210 remove_cpu_from_maps(cpu); 1211 unlock_vector_lock(); 1212 fixup_irqs(); 1213 } 1214 1215 int native_cpu_disable(void) 1216 { 1217 int cpu = smp_processor_id(); 1218 1219 /* 1220 * Perhaps use cpufreq to drop frequency, but that could go 1221 * into generic code. 1222 * 1223 * We won't take down the boot processor on i386 due to some 1224 * interrupts only being able to be serviced by the BSP. 1225 * Especially so if we're not using an IOAPIC -zwane 1226 */ 1227 if (cpu == 0) 1228 return -EBUSY; 1229 1230 clear_local_APIC(); 1231 1232 cpu_disable_common(); 1233 return 0; 1234 } 1235 1236 void native_cpu_die(unsigned int cpu) 1237 { 1238 /* We don't do anything here: idle task is faking death itself. */ 1239 unsigned int i; 1240 1241 for (i = 0; i < 10; i++) { 1242 /* They ack this in play_dead by setting CPU_DEAD */ 1243 if (per_cpu(cpu_state, cpu) == CPU_DEAD) { 1244 if (system_state == SYSTEM_RUNNING) 1245 pr_info("CPU %u is now offline\n", cpu); 1246 return; 1247 } 1248 msleep(100); 1249 } 1250 pr_err("CPU %u didn't die...\n", cpu); 1251 } 1252 1253 void play_dead_common(void) 1254 { 1255 idle_task_exit(); 1256 reset_lazy_tlbstate(); 1257 amd_e400_remove_cpu(raw_smp_processor_id()); 1258 1259 mb(); 1260 /* Ack it */ 1261 __this_cpu_write(cpu_state, CPU_DEAD); 1262 1263 /* 1264 * With physical CPU hotplug, we should halt the cpu 1265 */ 1266 local_irq_disable(); 1267 } 1268 1269 /* 1270 * We need to flush the caches before going to sleep, lest we have 1271 * dirty data in our caches when we come back up. 1272 */ 1273 static inline void mwait_play_dead(void) 1274 { 1275 unsigned int eax, ebx, ecx, edx; 1276 unsigned int highest_cstate = 0; 1277 unsigned int highest_subcstate = 0; 1278 int i; 1279 void *mwait_ptr; 1280 struct cpuinfo_x86 *c = __this_cpu_ptr(&cpu_info); 1281 1282 if (!(this_cpu_has(X86_FEATURE_MWAIT) && mwait_usable(c))) 1283 return; 1284 if (!this_cpu_has(X86_FEATURE_CLFLSH)) 1285 return; 1286 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1287 return; 1288 1289 eax = CPUID_MWAIT_LEAF; 1290 ecx = 0; 1291 native_cpuid(&eax, &ebx, &ecx, &edx); 1292 1293 /* 1294 * eax will be 0 if EDX enumeration is not valid. 1295 * Initialized below to cstate, sub_cstate value when EDX is valid. 1296 */ 1297 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1298 eax = 0; 1299 } else { 1300 edx >>= MWAIT_SUBSTATE_SIZE; 1301 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1302 if (edx & MWAIT_SUBSTATE_MASK) { 1303 highest_cstate = i; 1304 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1305 } 1306 } 1307 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1308 (highest_subcstate - 1); 1309 } 1310 1311 /* 1312 * This should be a memory location in a cache line which is 1313 * unlikely to be touched by other processors. The actual 1314 * content is immaterial as it is not actually modified in any way. 1315 */ 1316 mwait_ptr = ¤t_thread_info()->flags; 1317 1318 wbinvd(); 1319 1320 while (1) { 1321 /* 1322 * The CLFLUSH is a workaround for erratum AAI65 for 1323 * the Xeon 7400 series. It's not clear it is actually 1324 * needed, but it should be harmless in either case. 1325 * The WBINVD is insufficient due to the spurious-wakeup 1326 * case where we return around the loop. 1327 */ 1328 clflush(mwait_ptr); 1329 __monitor(mwait_ptr, 0, 0); 1330 mb(); 1331 __mwait(eax, 0); 1332 } 1333 } 1334 1335 static inline void hlt_play_dead(void) 1336 { 1337 if (__this_cpu_read(cpu_info.x86) >= 4) 1338 wbinvd(); 1339 1340 while (1) { 1341 native_halt(); 1342 } 1343 } 1344 1345 void native_play_dead(void) 1346 { 1347 play_dead_common(); 1348 tboot_shutdown(TB_SHUTDOWN_WFS); 1349 1350 mwait_play_dead(); /* Only returns on failure */ 1351 if (cpuidle_play_dead()) 1352 hlt_play_dead(); 1353 } 1354 1355 #else /* ... !CONFIG_HOTPLUG_CPU */ 1356 int native_cpu_disable(void) 1357 { 1358 return -ENOSYS; 1359 } 1360 1361 void native_cpu_die(unsigned int cpu) 1362 { 1363 /* We said "no" in __cpu_disable */ 1364 BUG(); 1365 } 1366 1367 void native_play_dead(void) 1368 { 1369 BUG(); 1370 } 1371 1372 #endif 1373