1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/numa.h> 57 #include <linux/pgtable.h> 58 #include <linux/overflow.h> 59 #include <linux/syscore_ops.h> 60 61 #include <asm/acpi.h> 62 #include <asm/desc.h> 63 #include <asm/nmi.h> 64 #include <asm/irq.h> 65 #include <asm/realmode.h> 66 #include <asm/cpu.h> 67 #include <asm/numa.h> 68 #include <asm/tlbflush.h> 69 #include <asm/mtrr.h> 70 #include <asm/mwait.h> 71 #include <asm/apic.h> 72 #include <asm/io_apic.h> 73 #include <asm/fpu/api.h> 74 #include <asm/setup.h> 75 #include <asm/uv/uv.h> 76 #include <linux/mc146818rtc.h> 77 #include <asm/i8259.h> 78 #include <asm/misc.h> 79 #include <asm/qspinlock.h> 80 #include <asm/intel-family.h> 81 #include <asm/cpu_device_id.h> 82 #include <asm/spec-ctrl.h> 83 #include <asm/hw_irq.h> 84 #include <asm/stackprotector.h> 85 86 #ifdef CONFIG_ACPI_CPPC_LIB 87 #include <acpi/cppc_acpi.h> 88 #endif 89 90 /* representing HT siblings of each logical CPU */ 91 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 92 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 93 94 /* representing HT and core siblings of each logical CPU */ 95 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 96 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 97 98 /* representing HT, core, and die siblings of each logical CPU */ 99 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 100 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 101 102 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); 103 104 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_l2c_shared_map); 105 106 /* Per CPU bogomips and other parameters */ 107 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 108 EXPORT_PER_CPU_SYMBOL(cpu_info); 109 110 /* Logical package management. We might want to allocate that dynamically */ 111 unsigned int __max_logical_packages __read_mostly; 112 EXPORT_SYMBOL(__max_logical_packages); 113 static unsigned int logical_packages __read_mostly; 114 static unsigned int logical_die __read_mostly; 115 116 /* Maximum number of SMT threads on any online core */ 117 int __read_mostly __max_smt_threads = 1; 118 119 /* Flag to indicate if a complete sched domain rebuild is required */ 120 bool x86_topology_update; 121 122 int arch_update_cpu_topology(void) 123 { 124 int retval = x86_topology_update; 125 126 x86_topology_update = false; 127 return retval; 128 } 129 130 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 131 { 132 unsigned long flags; 133 134 spin_lock_irqsave(&rtc_lock, flags); 135 CMOS_WRITE(0xa, 0xf); 136 spin_unlock_irqrestore(&rtc_lock, flags); 137 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = 138 start_eip >> 4; 139 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 140 start_eip & 0xf; 141 } 142 143 static inline void smpboot_restore_warm_reset_vector(void) 144 { 145 unsigned long flags; 146 147 /* 148 * Paranoid: Set warm reset code and vector here back 149 * to default values. 150 */ 151 spin_lock_irqsave(&rtc_lock, flags); 152 CMOS_WRITE(0, 0xf); 153 spin_unlock_irqrestore(&rtc_lock, flags); 154 155 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 156 } 157 158 static void init_freq_invariance(bool secondary, bool cppc_ready); 159 160 /* 161 * Report back to the Boot Processor during boot time or to the caller processor 162 * during CPU online. 163 */ 164 static void smp_callin(void) 165 { 166 int cpuid; 167 168 /* 169 * If waken up by an INIT in an 82489DX configuration 170 * cpu_callout_mask guarantees we don't get here before 171 * an INIT_deassert IPI reaches our local APIC, so it is 172 * now safe to touch our local APIC. 173 */ 174 cpuid = smp_processor_id(); 175 176 /* 177 * the boot CPU has finished the init stage and is spinning 178 * on callin_map until we finish. We are free to set up this 179 * CPU, first the APIC. (this is probably redundant on most 180 * boards) 181 */ 182 apic_ap_setup(); 183 184 /* 185 * Save our processor parameters. Note: this information 186 * is needed for clock calibration. 187 */ 188 smp_store_cpu_info(cpuid); 189 190 /* 191 * The topology information must be up to date before 192 * calibrate_delay() and notify_cpu_starting(). 193 */ 194 set_cpu_sibling_map(raw_smp_processor_id()); 195 196 init_freq_invariance(true, false); 197 198 /* 199 * Get our bogomips. 200 * Update loops_per_jiffy in cpu_data. Previous call to 201 * smp_store_cpu_info() stored a value that is close but not as 202 * accurate as the value just calculated. 203 */ 204 calibrate_delay(); 205 cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; 206 pr_debug("Stack at about %p\n", &cpuid); 207 208 wmb(); 209 210 notify_cpu_starting(cpuid); 211 212 /* 213 * Allow the master to continue. 214 */ 215 cpumask_set_cpu(cpuid, cpu_callin_mask); 216 } 217 218 static int cpu0_logical_apicid; 219 static int enable_start_cpu0; 220 /* 221 * Activate a secondary processor. 222 */ 223 static void notrace start_secondary(void *unused) 224 { 225 /* 226 * Don't put *anything* except direct CPU state initialization 227 * before cpu_init(), SMP booting is too fragile that we want to 228 * limit the things done here to the most necessary things. 229 */ 230 cr4_init(); 231 232 #ifdef CONFIG_X86_32 233 /* switch away from the initial page table */ 234 load_cr3(swapper_pg_dir); 235 __flush_tlb_all(); 236 #endif 237 cpu_init_secondary(); 238 rcu_cpu_starting(raw_smp_processor_id()); 239 x86_cpuinit.early_percpu_clock_init(); 240 smp_callin(); 241 242 enable_start_cpu0 = 0; 243 244 /* otherwise gcc will move up smp_processor_id before the cpu_init */ 245 barrier(); 246 /* 247 * Check TSC synchronization with the boot CPU: 248 */ 249 check_tsc_sync_target(); 250 251 speculative_store_bypass_ht_init(); 252 253 /* 254 * Lock vector_lock, set CPU online and bring the vector 255 * allocator online. Online must be set with vector_lock held 256 * to prevent a concurrent irq setup/teardown from seeing a 257 * half valid vector space. 258 */ 259 lock_vector_lock(); 260 set_cpu_online(smp_processor_id(), true); 261 lapic_online(); 262 unlock_vector_lock(); 263 cpu_set_state_online(smp_processor_id()); 264 x86_platform.nmi_init(); 265 266 /* enable local interrupts */ 267 local_irq_enable(); 268 269 x86_cpuinit.setup_percpu_clockev(); 270 271 wmb(); 272 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 273 } 274 275 /** 276 * topology_is_primary_thread - Check whether CPU is the primary SMT thread 277 * @cpu: CPU to check 278 */ 279 bool topology_is_primary_thread(unsigned int cpu) 280 { 281 return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); 282 } 283 284 /** 285 * topology_smt_supported - Check whether SMT is supported by the CPUs 286 */ 287 bool topology_smt_supported(void) 288 { 289 return smp_num_siblings > 1; 290 } 291 292 /** 293 * topology_phys_to_logical_pkg - Map a physical package id to a logical 294 * 295 * Returns logical package id or -1 if not found 296 */ 297 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 298 { 299 int cpu; 300 301 for_each_possible_cpu(cpu) { 302 struct cpuinfo_x86 *c = &cpu_data(cpu); 303 304 if (c->initialized && c->phys_proc_id == phys_pkg) 305 return c->logical_proc_id; 306 } 307 return -1; 308 } 309 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 310 /** 311 * topology_phys_to_logical_die - Map a physical die id to logical 312 * 313 * Returns logical die id or -1 if not found 314 */ 315 int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 316 { 317 int cpu; 318 int proc_id = cpu_data(cur_cpu).phys_proc_id; 319 320 for_each_possible_cpu(cpu) { 321 struct cpuinfo_x86 *c = &cpu_data(cpu); 322 323 if (c->initialized && c->cpu_die_id == die_id && 324 c->phys_proc_id == proc_id) 325 return c->logical_die_id; 326 } 327 return -1; 328 } 329 EXPORT_SYMBOL(topology_phys_to_logical_die); 330 331 /** 332 * topology_update_package_map - Update the physical to logical package map 333 * @pkg: The physical package id as retrieved via CPUID 334 * @cpu: The cpu for which this is updated 335 */ 336 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 337 { 338 int new; 339 340 /* Already available somewhere? */ 341 new = topology_phys_to_logical_pkg(pkg); 342 if (new >= 0) 343 goto found; 344 345 new = logical_packages++; 346 if (new != pkg) { 347 pr_info("CPU %u Converting physical %u to logical package %u\n", 348 cpu, pkg, new); 349 } 350 found: 351 cpu_data(cpu).logical_proc_id = new; 352 return 0; 353 } 354 /** 355 * topology_update_die_map - Update the physical to logical die map 356 * @die: The die id as retrieved via CPUID 357 * @cpu: The cpu for which this is updated 358 */ 359 int topology_update_die_map(unsigned int die, unsigned int cpu) 360 { 361 int new; 362 363 /* Already available somewhere? */ 364 new = topology_phys_to_logical_die(die, cpu); 365 if (new >= 0) 366 goto found; 367 368 new = logical_die++; 369 if (new != die) { 370 pr_info("CPU %u Converting physical %u to logical die %u\n", 371 cpu, die, new); 372 } 373 found: 374 cpu_data(cpu).logical_die_id = new; 375 return 0; 376 } 377 378 void __init smp_store_boot_cpu_info(void) 379 { 380 int id = 0; /* CPU 0 */ 381 struct cpuinfo_x86 *c = &cpu_data(id); 382 383 *c = boot_cpu_data; 384 c->cpu_index = id; 385 topology_update_package_map(c->phys_proc_id, id); 386 topology_update_die_map(c->cpu_die_id, id); 387 c->initialized = true; 388 } 389 390 /* 391 * The bootstrap kernel entry code has set these up. Save them for 392 * a given CPU 393 */ 394 void smp_store_cpu_info(int id) 395 { 396 struct cpuinfo_x86 *c = &cpu_data(id); 397 398 /* Copy boot_cpu_data only on the first bringup */ 399 if (!c->initialized) 400 *c = boot_cpu_data; 401 c->cpu_index = id; 402 /* 403 * During boot time, CPU0 has this setup already. Save the info when 404 * bringing up AP or offlined CPU0. 405 */ 406 identify_secondary_cpu(c); 407 c->initialized = true; 408 } 409 410 static bool 411 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 412 { 413 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 414 415 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 416 } 417 418 static bool 419 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 420 { 421 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 422 423 return !WARN_ONCE(!topology_same_node(c, o), 424 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 425 "[node: %d != %d]. Ignoring dependency.\n", 426 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 427 } 428 429 #define link_mask(mfunc, c1, c2) \ 430 do { \ 431 cpumask_set_cpu((c1), mfunc(c2)); \ 432 cpumask_set_cpu((c2), mfunc(c1)); \ 433 } while (0) 434 435 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 436 { 437 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 438 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 439 440 if (c->phys_proc_id == o->phys_proc_id && 441 c->cpu_die_id == o->cpu_die_id && 442 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 443 if (c->cpu_core_id == o->cpu_core_id) 444 return topology_sane(c, o, "smt"); 445 446 if ((c->cu_id != 0xff) && 447 (o->cu_id != 0xff) && 448 (c->cu_id == o->cu_id)) 449 return topology_sane(c, o, "smt"); 450 } 451 452 } else if (c->phys_proc_id == o->phys_proc_id && 453 c->cpu_die_id == o->cpu_die_id && 454 c->cpu_core_id == o->cpu_core_id) { 455 return topology_sane(c, o, "smt"); 456 } 457 458 return false; 459 } 460 461 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 462 { 463 if (c->phys_proc_id == o->phys_proc_id && 464 c->cpu_die_id == o->cpu_die_id) 465 return true; 466 return false; 467 } 468 469 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 470 { 471 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 472 473 /* If the arch didn't set up l2c_id, fall back to SMT */ 474 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 475 return match_smt(c, o); 476 477 /* Do not match if L2 cache id does not match: */ 478 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 479 return false; 480 481 return topology_sane(c, o, "l2c"); 482 } 483 484 /* 485 * Unlike the other levels, we do not enforce keeping a 486 * multicore group inside a NUMA node. If this happens, we will 487 * discard the MC level of the topology later. 488 */ 489 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 490 { 491 if (c->phys_proc_id == o->phys_proc_id) 492 return true; 493 return false; 494 } 495 496 /* 497 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 498 * 499 * Any Intel CPU that has multiple nodes per package and does not 500 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 501 * 502 * When in SNC mode, these CPUs enumerate an LLC that is shared 503 * by multiple NUMA nodes. The LLC is shared for off-package data 504 * access but private to the NUMA node (half of the package) for 505 * on-package access. CPUID (the source of the information about 506 * the LLC) can only enumerate the cache as shared or unshared, 507 * but not this particular configuration. 508 */ 509 510 static const struct x86_cpu_id intel_cod_cpu[] = { 511 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 512 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 513 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 514 {} 515 }; 516 517 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 518 { 519 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 520 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 521 bool intel_snc = id && id->driver_data; 522 523 /* Do not match if we do not have a valid APICID for cpu: */ 524 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 525 return false; 526 527 /* Do not match if LLC id does not match: */ 528 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 529 return false; 530 531 /* 532 * Allow the SNC topology without warning. Return of false 533 * means 'c' does not share the LLC of 'o'. This will be 534 * reflected to userspace. 535 */ 536 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 537 return false; 538 539 return topology_sane(c, o, "llc"); 540 } 541 542 543 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 544 static inline int x86_sched_itmt_flags(void) 545 { 546 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 547 } 548 549 #ifdef CONFIG_SCHED_MC 550 static int x86_core_flags(void) 551 { 552 return cpu_core_flags() | x86_sched_itmt_flags(); 553 } 554 #endif 555 #ifdef CONFIG_SCHED_SMT 556 static int x86_smt_flags(void) 557 { 558 return cpu_smt_flags() | x86_sched_itmt_flags(); 559 } 560 #endif 561 #ifdef CONFIG_SCHED_CLUSTER 562 static int x86_cluster_flags(void) 563 { 564 return cpu_cluster_flags() | x86_sched_itmt_flags(); 565 } 566 #endif 567 #endif 568 569 static struct sched_domain_topology_level x86_numa_in_package_topology[] = { 570 #ifdef CONFIG_SCHED_SMT 571 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 572 #endif 573 #ifdef CONFIG_SCHED_CLUSTER 574 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 575 #endif 576 #ifdef CONFIG_SCHED_MC 577 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 578 #endif 579 { NULL, }, 580 }; 581 582 static struct sched_domain_topology_level x86_topology[] = { 583 #ifdef CONFIG_SCHED_SMT 584 { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, 585 #endif 586 #ifdef CONFIG_SCHED_CLUSTER 587 { cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) }, 588 #endif 589 #ifdef CONFIG_SCHED_MC 590 { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, 591 #endif 592 { cpu_cpu_mask, SD_INIT_NAME(DIE) }, 593 { NULL, }, 594 }; 595 596 /* 597 * Set if a package/die has multiple NUMA nodes inside. 598 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 599 * Sub-NUMA Clustering have this. 600 */ 601 static bool x86_has_numa_in_package; 602 603 void set_cpu_sibling_map(int cpu) 604 { 605 bool has_smt = smp_num_siblings > 1; 606 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 607 struct cpuinfo_x86 *c = &cpu_data(cpu); 608 struct cpuinfo_x86 *o; 609 int i, threads; 610 611 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 612 613 if (!has_mp) { 614 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 615 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 616 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 617 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 618 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 619 c->booted_cores = 1; 620 return; 621 } 622 623 for_each_cpu(i, cpu_sibling_setup_mask) { 624 o = &cpu_data(i); 625 626 if (match_pkg(c, o) && !topology_same_node(c, o)) 627 x86_has_numa_in_package = true; 628 629 if ((i == cpu) || (has_smt && match_smt(c, o))) 630 link_mask(topology_sibling_cpumask, cpu, i); 631 632 if ((i == cpu) || (has_mp && match_llc(c, o))) 633 link_mask(cpu_llc_shared_mask, cpu, i); 634 635 if ((i == cpu) || (has_mp && match_l2c(c, o))) 636 link_mask(cpu_l2c_shared_mask, cpu, i); 637 638 if ((i == cpu) || (has_mp && match_die(c, o))) 639 link_mask(topology_die_cpumask, cpu, i); 640 } 641 642 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 643 if (threads > __max_smt_threads) 644 __max_smt_threads = threads; 645 646 for_each_cpu(i, topology_sibling_cpumask(cpu)) 647 cpu_data(i).smt_active = threads > 1; 648 649 /* 650 * This needs a separate iteration over the cpus because we rely on all 651 * topology_sibling_cpumask links to be set-up. 652 */ 653 for_each_cpu(i, cpu_sibling_setup_mask) { 654 o = &cpu_data(i); 655 656 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 657 link_mask(topology_core_cpumask, cpu, i); 658 659 /* 660 * Does this new cpu bringup a new core? 661 */ 662 if (threads == 1) { 663 /* 664 * for each core in package, increment 665 * the booted_cores for this new cpu 666 */ 667 if (cpumask_first( 668 topology_sibling_cpumask(i)) == i) 669 c->booted_cores++; 670 /* 671 * increment the core count for all 672 * the other cpus in this package 673 */ 674 if (i != cpu) 675 cpu_data(i).booted_cores++; 676 } else if (i != cpu && !c->booted_cores) 677 c->booted_cores = cpu_data(i).booted_cores; 678 } 679 } 680 } 681 682 /* maps the cpu to the sched domain representing multi-core */ 683 const struct cpumask *cpu_coregroup_mask(int cpu) 684 { 685 return cpu_llc_shared_mask(cpu); 686 } 687 688 const struct cpumask *cpu_clustergroup_mask(int cpu) 689 { 690 return cpu_l2c_shared_mask(cpu); 691 } 692 693 static void impress_friends(void) 694 { 695 int cpu; 696 unsigned long bogosum = 0; 697 /* 698 * Allow the user to impress friends. 699 */ 700 pr_debug("Before bogomips\n"); 701 for_each_possible_cpu(cpu) 702 if (cpumask_test_cpu(cpu, cpu_callout_mask)) 703 bogosum += cpu_data(cpu).loops_per_jiffy; 704 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 705 num_online_cpus(), 706 bogosum/(500000/HZ), 707 (bogosum/(5000/HZ))%100); 708 709 pr_debug("Before bogocount - setting activated=1\n"); 710 } 711 712 void __inquire_remote_apic(int apicid) 713 { 714 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; 715 const char * const names[] = { "ID", "VERSION", "SPIV" }; 716 int timeout; 717 u32 status; 718 719 pr_info("Inquiring remote APIC 0x%x...\n", apicid); 720 721 for (i = 0; i < ARRAY_SIZE(regs); i++) { 722 pr_info("... APIC 0x%x %s: ", apicid, names[i]); 723 724 /* 725 * Wait for idle. 726 */ 727 status = safe_apic_wait_icr_idle(); 728 if (status) 729 pr_cont("a previous APIC delivery may have failed\n"); 730 731 apic_icr_write(APIC_DM_REMRD | regs[i], apicid); 732 733 timeout = 0; 734 do { 735 udelay(100); 736 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; 737 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); 738 739 switch (status) { 740 case APIC_ICR_RR_VALID: 741 status = apic_read(APIC_RRR); 742 pr_cont("%08x\n", status); 743 break; 744 default: 745 pr_cont("failed\n"); 746 } 747 } 748 } 749 750 /* 751 * The Multiprocessor Specification 1.4 (1997) example code suggests 752 * that there should be a 10ms delay between the BSP asserting INIT 753 * and de-asserting INIT, when starting a remote processor. 754 * But that slows boot and resume on modern processors, which include 755 * many cores and don't require that delay. 756 * 757 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 758 * Modern processor families are quirked to remove the delay entirely. 759 */ 760 #define UDELAY_10MS_DEFAULT 10000 761 762 static unsigned int init_udelay = UINT_MAX; 763 764 static int __init cpu_init_udelay(char *str) 765 { 766 get_option(&str, &init_udelay); 767 768 return 0; 769 } 770 early_param("cpu_init_udelay", cpu_init_udelay); 771 772 static void __init smp_quirk_init_udelay(void) 773 { 774 /* if cmdline changed it from default, leave it alone */ 775 if (init_udelay != UINT_MAX) 776 return; 777 778 /* if modern processor, use no delay */ 779 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 780 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 781 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 782 init_udelay = 0; 783 return; 784 } 785 /* else, use legacy delay */ 786 init_udelay = UDELAY_10MS_DEFAULT; 787 } 788 789 /* 790 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal 791 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this 792 * won't ... remember to clear down the APIC, etc later. 793 */ 794 int 795 wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) 796 { 797 u32 dm = apic->dest_mode_logical ? APIC_DEST_LOGICAL : APIC_DEST_PHYSICAL; 798 unsigned long send_status, accept_status = 0; 799 int maxlvt; 800 801 /* Target chip */ 802 /* Boot on the stack */ 803 /* Kick the second */ 804 apic_icr_write(APIC_DM_NMI | dm, apicid); 805 806 pr_debug("Waiting for send to finish...\n"); 807 send_status = safe_apic_wait_icr_idle(); 808 809 /* 810 * Give the other CPU some time to accept the IPI. 811 */ 812 udelay(200); 813 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 814 maxlvt = lapic_get_maxlvt(); 815 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 816 apic_write(APIC_ESR, 0); 817 accept_status = (apic_read(APIC_ESR) & 0xEF); 818 } 819 pr_debug("NMI sent\n"); 820 821 if (send_status) 822 pr_err("APIC never delivered???\n"); 823 if (accept_status) 824 pr_err("APIC delivery error (%lx)\n", accept_status); 825 826 return (send_status | accept_status); 827 } 828 829 static int 830 wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 831 { 832 unsigned long send_status = 0, accept_status = 0; 833 int maxlvt, num_starts, j; 834 835 maxlvt = lapic_get_maxlvt(); 836 837 /* 838 * Be paranoid about clearing APIC errors. 839 */ 840 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 841 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 842 apic_write(APIC_ESR, 0); 843 apic_read(APIC_ESR); 844 } 845 846 pr_debug("Asserting INIT\n"); 847 848 /* 849 * Turn INIT on target chip 850 */ 851 /* 852 * Send IPI 853 */ 854 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, 855 phys_apicid); 856 857 pr_debug("Waiting for send to finish...\n"); 858 send_status = safe_apic_wait_icr_idle(); 859 860 udelay(init_udelay); 861 862 pr_debug("Deasserting INIT\n"); 863 864 /* Target chip */ 865 /* Send IPI */ 866 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 867 868 pr_debug("Waiting for send to finish...\n"); 869 send_status = safe_apic_wait_icr_idle(); 870 871 mb(); 872 873 /* 874 * Should we send STARTUP IPIs ? 875 * 876 * Determine this based on the APIC version. 877 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 878 */ 879 if (APIC_INTEGRATED(boot_cpu_apic_version)) 880 num_starts = 2; 881 else 882 num_starts = 0; 883 884 /* 885 * Run STARTUP IPI loop. 886 */ 887 pr_debug("#startup loops: %d\n", num_starts); 888 889 for (j = 1; j <= num_starts; j++) { 890 pr_debug("Sending STARTUP #%d\n", j); 891 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 892 apic_write(APIC_ESR, 0); 893 apic_read(APIC_ESR); 894 pr_debug("After apic_write\n"); 895 896 /* 897 * STARTUP IPI 898 */ 899 900 /* Target chip */ 901 /* Boot on the stack */ 902 /* Kick the second */ 903 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 904 phys_apicid); 905 906 /* 907 * Give the other CPU some time to accept the IPI. 908 */ 909 if (init_udelay == 0) 910 udelay(10); 911 else 912 udelay(300); 913 914 pr_debug("Startup point 1\n"); 915 916 pr_debug("Waiting for send to finish...\n"); 917 send_status = safe_apic_wait_icr_idle(); 918 919 /* 920 * Give the other CPU some time to accept the IPI. 921 */ 922 if (init_udelay == 0) 923 udelay(10); 924 else 925 udelay(200); 926 927 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 928 apic_write(APIC_ESR, 0); 929 accept_status = (apic_read(APIC_ESR) & 0xEF); 930 if (send_status || accept_status) 931 break; 932 } 933 pr_debug("After Startup\n"); 934 935 if (send_status) 936 pr_err("APIC never delivered???\n"); 937 if (accept_status) 938 pr_err("APIC delivery error (%lx)\n", accept_status); 939 940 return (send_status | accept_status); 941 } 942 943 /* reduce the number of lines printed when booting a large cpu count system */ 944 static void announce_cpu(int cpu, int apicid) 945 { 946 static int current_node = NUMA_NO_NODE; 947 int node = early_cpu_to_node(cpu); 948 static int width, node_width; 949 950 if (!width) 951 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 952 953 if (!node_width) 954 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 955 956 if (cpu == 1) 957 printk(KERN_INFO "x86: Booting SMP configuration:\n"); 958 959 if (system_state < SYSTEM_RUNNING) { 960 if (node != current_node) { 961 if (current_node > (-1)) 962 pr_cont("\n"); 963 current_node = node; 964 965 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 966 node_width - num_digits(node), " ", node); 967 } 968 969 /* Add padding for the BSP */ 970 if (cpu == 1) 971 pr_cont("%*s", width + 1, " "); 972 973 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 974 975 } else 976 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 977 node, cpu, apicid); 978 } 979 980 static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) 981 { 982 int cpu; 983 984 cpu = smp_processor_id(); 985 if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) 986 return NMI_HANDLED; 987 988 return NMI_DONE; 989 } 990 991 /* 992 * Wake up AP by INIT, INIT, STARTUP sequence. 993 * 994 * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS 995 * boot-strap code which is not a desired behavior for waking up BSP. To 996 * void the boot-strap code, wake up CPU0 by NMI instead. 997 * 998 * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined 999 * (i.e. physically hot removed and then hot added), NMI won't wake it up. 1000 * We'll change this code in the future to wake up hard offlined CPU0 if 1001 * real platform and request are available. 1002 */ 1003 static int 1004 wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, 1005 int *cpu0_nmi_registered) 1006 { 1007 int id; 1008 int boot_error; 1009 1010 preempt_disable(); 1011 1012 /* 1013 * Wake up AP by INIT, INIT, STARTUP sequence. 1014 */ 1015 if (cpu) { 1016 boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); 1017 goto out; 1018 } 1019 1020 /* 1021 * Wake up BSP by nmi. 1022 * 1023 * Register a NMI handler to help wake up CPU0. 1024 */ 1025 boot_error = register_nmi_handler(NMI_LOCAL, 1026 wakeup_cpu0_nmi, 0, "wake_cpu0"); 1027 1028 if (!boot_error) { 1029 enable_start_cpu0 = 1; 1030 *cpu0_nmi_registered = 1; 1031 id = apic->dest_mode_logical ? cpu0_logical_apicid : apicid; 1032 boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); 1033 } 1034 1035 out: 1036 preempt_enable(); 1037 1038 return boot_error; 1039 } 1040 1041 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 1042 { 1043 int ret; 1044 1045 /* Just in case we booted with a single CPU. */ 1046 alternatives_enable_smp(); 1047 1048 per_cpu(current_task, cpu) = idle; 1049 cpu_init_stack_canary(cpu, idle); 1050 1051 /* Initialize the interrupt stack(s) */ 1052 ret = irq_init_percpu_irqstack(cpu); 1053 if (ret) 1054 return ret; 1055 1056 #ifdef CONFIG_X86_32 1057 /* Stack for startup_32 can be just as for start_secondary onwards */ 1058 per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); 1059 #else 1060 initial_gs = per_cpu_offset(cpu); 1061 #endif 1062 return 0; 1063 } 1064 1065 /* 1066 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 1067 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 1068 * Returns zero if CPU booted OK, else error code from 1069 * ->wakeup_secondary_cpu. 1070 */ 1071 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, 1072 int *cpu0_nmi_registered) 1073 { 1074 /* start_ip had better be page-aligned! */ 1075 unsigned long start_ip = real_mode_header->trampoline_start; 1076 1077 unsigned long boot_error = 0; 1078 unsigned long timeout; 1079 1080 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1081 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1082 initial_code = (unsigned long)start_secondary; 1083 initial_stack = idle->thread.sp; 1084 1085 /* Enable the espfix hack for this CPU */ 1086 init_espfix_ap(cpu); 1087 1088 /* So we see what's up */ 1089 announce_cpu(cpu, apicid); 1090 1091 /* 1092 * This grunge runs the startup process for 1093 * the targeted processor. 1094 */ 1095 1096 if (x86_platform.legacy.warm_reset) { 1097 1098 pr_debug("Setting warm reset code and vector.\n"); 1099 1100 smpboot_setup_warm_reset_vector(start_ip); 1101 /* 1102 * Be paranoid about clearing APIC errors. 1103 */ 1104 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1105 apic_write(APIC_ESR, 0); 1106 apic_read(APIC_ESR); 1107 } 1108 } 1109 1110 /* 1111 * AP might wait on cpu_callout_mask in cpu_init() with 1112 * cpu_initialized_mask set if previous attempt to online 1113 * it timed-out. Clear cpu_initialized_mask so that after 1114 * INIT/SIPI it could start with a clean state. 1115 */ 1116 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1117 smp_mb(); 1118 1119 /* 1120 * Wake up a CPU in difference cases: 1121 * - Use the method in the APIC driver if it's defined 1122 * Otherwise, 1123 * - Use an INIT boot APIC message for APs or NMI for BSP. 1124 */ 1125 if (apic->wakeup_secondary_cpu) 1126 boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); 1127 else 1128 boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, 1129 cpu0_nmi_registered); 1130 1131 if (!boot_error) { 1132 /* 1133 * Wait 10s total for first sign of life from AP 1134 */ 1135 boot_error = -1; 1136 timeout = jiffies + 10*HZ; 1137 while (time_before(jiffies, timeout)) { 1138 if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { 1139 /* 1140 * Tell AP to proceed with initialization 1141 */ 1142 cpumask_set_cpu(cpu, cpu_callout_mask); 1143 boot_error = 0; 1144 break; 1145 } 1146 schedule(); 1147 } 1148 } 1149 1150 if (!boot_error) { 1151 /* 1152 * Wait till AP completes initial initialization 1153 */ 1154 while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { 1155 /* 1156 * Allow other tasks to run while we wait for the 1157 * AP to come online. This also gives a chance 1158 * for the MTRR work(triggered by the AP coming online) 1159 * to be completed in the stop machine context. 1160 */ 1161 schedule(); 1162 } 1163 } 1164 1165 if (x86_platform.legacy.warm_reset) { 1166 /* 1167 * Cleanup possible dangling ends... 1168 */ 1169 smpboot_restore_warm_reset_vector(); 1170 } 1171 1172 return boot_error; 1173 } 1174 1175 int native_cpu_up(unsigned int cpu, struct task_struct *tidle) 1176 { 1177 int apicid = apic->cpu_present_to_apicid(cpu); 1178 int cpu0_nmi_registered = 0; 1179 unsigned long flags; 1180 int err, ret = 0; 1181 1182 lockdep_assert_irqs_enabled(); 1183 1184 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1185 1186 if (apicid == BAD_APICID || 1187 !physid_isset(apicid, phys_cpu_present_map) || 1188 !apic->apic_id_valid(apicid)) { 1189 pr_err("%s: bad cpu %d\n", __func__, cpu); 1190 return -EINVAL; 1191 } 1192 1193 /* 1194 * Already booted CPU? 1195 */ 1196 if (cpumask_test_cpu(cpu, cpu_callin_mask)) { 1197 pr_debug("do_boot_cpu %d Already started\n", cpu); 1198 return -ENOSYS; 1199 } 1200 1201 /* 1202 * Save current MTRR state in case it was changed since early boot 1203 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1204 */ 1205 mtrr_save_state(); 1206 1207 /* x86 CPUs take themselves offline, so delayed offline is OK. */ 1208 err = cpu_check_up_prepare(cpu); 1209 if (err && err != -EBUSY) 1210 return err; 1211 1212 /* the FPU context is blank, nobody can own it */ 1213 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1214 1215 err = common_cpu_up(cpu, tidle); 1216 if (err) 1217 return err; 1218 1219 err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); 1220 if (err) { 1221 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1222 ret = -EIO; 1223 goto unreg_nmi; 1224 } 1225 1226 /* 1227 * Check TSC synchronization with the AP (keep irqs disabled 1228 * while doing so): 1229 */ 1230 local_irq_save(flags); 1231 check_tsc_sync_source(cpu); 1232 local_irq_restore(flags); 1233 1234 while (!cpu_online(cpu)) { 1235 cpu_relax(); 1236 touch_nmi_watchdog(); 1237 } 1238 1239 unreg_nmi: 1240 /* 1241 * Clean up the nmi handler. Do this after the callin and callout sync 1242 * to avoid impact of possible long unregister time. 1243 */ 1244 if (cpu0_nmi_registered) 1245 unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); 1246 1247 return ret; 1248 } 1249 1250 /** 1251 * arch_disable_smp_support() - disables SMP support for x86 at runtime 1252 */ 1253 void arch_disable_smp_support(void) 1254 { 1255 disable_ioapic_support(); 1256 } 1257 1258 /* 1259 * Fall back to non SMP mode after errors. 1260 * 1261 * RED-PEN audit/test this more. I bet there is more state messed up here. 1262 */ 1263 static __init void disable_smp(void) 1264 { 1265 pr_info("SMP disabled\n"); 1266 1267 disable_ioapic_support(); 1268 1269 init_cpu_present(cpumask_of(0)); 1270 init_cpu_possible(cpumask_of(0)); 1271 1272 if (smp_found_config) 1273 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1274 else 1275 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1276 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1277 cpumask_set_cpu(0, topology_core_cpumask(0)); 1278 cpumask_set_cpu(0, topology_die_cpumask(0)); 1279 } 1280 1281 /* 1282 * Various sanity checks. 1283 */ 1284 static void __init smp_sanity_check(void) 1285 { 1286 preempt_disable(); 1287 1288 #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) 1289 if (def_to_bigsmp && nr_cpu_ids > 8) { 1290 unsigned int cpu; 1291 unsigned nr; 1292 1293 pr_warn("More than 8 CPUs detected - skipping them\n" 1294 "Use CONFIG_X86_BIGSMP\n"); 1295 1296 nr = 0; 1297 for_each_present_cpu(cpu) { 1298 if (nr >= 8) 1299 set_cpu_present(cpu, false); 1300 nr++; 1301 } 1302 1303 nr = 0; 1304 for_each_possible_cpu(cpu) { 1305 if (nr >= 8) 1306 set_cpu_possible(cpu, false); 1307 nr++; 1308 } 1309 1310 nr_cpu_ids = 8; 1311 } 1312 #endif 1313 1314 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { 1315 pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", 1316 hard_smp_processor_id()); 1317 1318 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1319 } 1320 1321 /* 1322 * Should not be necessary because the MP table should list the boot 1323 * CPU too, but we do it for the sake of robustness anyway. 1324 */ 1325 if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { 1326 pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", 1327 boot_cpu_physical_apicid); 1328 physid_set(hard_smp_processor_id(), phys_cpu_present_map); 1329 } 1330 preempt_enable(); 1331 } 1332 1333 static void __init smp_cpu_index_default(void) 1334 { 1335 int i; 1336 struct cpuinfo_x86 *c; 1337 1338 for_each_possible_cpu(i) { 1339 c = &cpu_data(i); 1340 /* mark all to hotplug */ 1341 c->cpu_index = nr_cpu_ids; 1342 } 1343 } 1344 1345 static void __init smp_get_logical_apicid(void) 1346 { 1347 if (x2apic_mode) 1348 cpu0_logical_apicid = apic_read(APIC_LDR); 1349 else 1350 cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); 1351 } 1352 1353 void __init smp_prepare_cpus_common(void) 1354 { 1355 unsigned int i; 1356 1357 smp_cpu_index_default(); 1358 1359 /* 1360 * Setup boot CPU information 1361 */ 1362 smp_store_boot_cpu_info(); /* Final full version of the data */ 1363 cpumask_copy(cpu_callin_mask, cpumask_of(0)); 1364 mb(); 1365 1366 for_each_possible_cpu(i) { 1367 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1368 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1369 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1370 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1371 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1372 } 1373 1374 /* 1375 * Set 'default' x86 topology, this matches default_topology() in that 1376 * it has NUMA nodes as a topology level. See also 1377 * native_smp_cpus_done(). 1378 * 1379 * Must be done before set_cpus_sibling_map() is ran. 1380 */ 1381 set_sched_topology(x86_topology); 1382 1383 set_cpu_sibling_map(0); 1384 } 1385 1386 /* 1387 * Prepare for SMP bootup. 1388 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1389 * for common interface support. 1390 */ 1391 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1392 { 1393 smp_prepare_cpus_common(); 1394 1395 init_freq_invariance(false, false); 1396 smp_sanity_check(); 1397 1398 switch (apic_intr_mode) { 1399 case APIC_PIC: 1400 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1401 disable_smp(); 1402 return; 1403 case APIC_SYMMETRIC_IO_NO_ROUTING: 1404 disable_smp(); 1405 /* Setup local timer */ 1406 x86_init.timers.setup_percpu_clockev(); 1407 return; 1408 case APIC_VIRTUAL_WIRE: 1409 case APIC_SYMMETRIC_IO: 1410 break; 1411 } 1412 1413 /* Setup local timer */ 1414 x86_init.timers.setup_percpu_clockev(); 1415 1416 smp_get_logical_apicid(); 1417 1418 pr_info("CPU0: "); 1419 print_cpu_info(&cpu_data(0)); 1420 1421 uv_system_init(); 1422 1423 set_mtrr_aps_delayed_init(); 1424 1425 smp_quirk_init_udelay(); 1426 1427 speculative_store_bypass_ht_init(); 1428 } 1429 1430 void arch_thaw_secondary_cpus_begin(void) 1431 { 1432 set_mtrr_aps_delayed_init(); 1433 } 1434 1435 void arch_thaw_secondary_cpus_end(void) 1436 { 1437 mtrr_aps_init(); 1438 } 1439 1440 /* 1441 * Early setup to make printk work. 1442 */ 1443 void __init native_smp_prepare_boot_cpu(void) 1444 { 1445 int me = smp_processor_id(); 1446 switch_to_new_gdt(me); 1447 /* already set me in cpu_online_mask in boot_cpu_init() */ 1448 cpumask_set_cpu(me, cpu_callout_mask); 1449 cpu_set_state_online(me); 1450 native_pv_lock_init(); 1451 } 1452 1453 void __init calculate_max_logical_packages(void) 1454 { 1455 int ncpus; 1456 1457 /* 1458 * Today neither Intel nor AMD support heterogeneous systems so 1459 * extrapolate the boot cpu's data to all packages. 1460 */ 1461 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1462 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1463 pr_info("Max logical packages: %u\n", __max_logical_packages); 1464 } 1465 1466 void __init native_smp_cpus_done(unsigned int max_cpus) 1467 { 1468 pr_debug("Boot done\n"); 1469 1470 calculate_max_logical_packages(); 1471 1472 if (x86_has_numa_in_package) 1473 set_sched_topology(x86_numa_in_package_topology); 1474 1475 nmi_selftest(); 1476 impress_friends(); 1477 mtrr_aps_init(); 1478 } 1479 1480 static int __initdata setup_possible_cpus = -1; 1481 static int __init _setup_possible_cpus(char *str) 1482 { 1483 get_option(&str, &setup_possible_cpus); 1484 return 0; 1485 } 1486 early_param("possible_cpus", _setup_possible_cpus); 1487 1488 1489 /* 1490 * cpu_possible_mask should be static, it cannot change as cpu's 1491 * are onlined, or offlined. The reason is per-cpu data-structures 1492 * are allocated by some modules at init time, and don't expect to 1493 * do this dynamically on cpu arrival/departure. 1494 * cpu_present_mask on the other hand can change dynamically. 1495 * In case when cpu_hotplug is not compiled, then we resort to current 1496 * behaviour, which is cpu_possible == cpu_present. 1497 * - Ashok Raj 1498 * 1499 * Three ways to find out the number of additional hotplug CPUs: 1500 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1501 * - The user can overwrite it with possible_cpus=NUM 1502 * - Otherwise don't reserve additional CPUs. 1503 * We do this because additional CPUs waste a lot of memory. 1504 * -AK 1505 */ 1506 __init void prefill_possible_map(void) 1507 { 1508 int i, possible; 1509 1510 /* No boot processor was found in mptable or ACPI MADT */ 1511 if (!num_processors) { 1512 if (boot_cpu_has(X86_FEATURE_APIC)) { 1513 int apicid = boot_cpu_physical_apicid; 1514 int cpu = hard_smp_processor_id(); 1515 1516 pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); 1517 1518 /* Make sure boot cpu is enumerated */ 1519 if (apic->cpu_present_to_apicid(0) == BAD_APICID && 1520 apic->apic_id_valid(apicid)) 1521 generic_processor_info(apicid, boot_cpu_apic_version); 1522 } 1523 1524 if (!num_processors) 1525 num_processors = 1; 1526 } 1527 1528 i = setup_max_cpus ?: 1; 1529 if (setup_possible_cpus == -1) { 1530 possible = num_processors; 1531 #ifdef CONFIG_HOTPLUG_CPU 1532 if (setup_max_cpus) 1533 possible += disabled_cpus; 1534 #else 1535 if (possible > i) 1536 possible = i; 1537 #endif 1538 } else 1539 possible = setup_possible_cpus; 1540 1541 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1542 1543 /* nr_cpu_ids could be reduced via nr_cpus= */ 1544 if (possible > nr_cpu_ids) { 1545 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1546 possible, nr_cpu_ids); 1547 possible = nr_cpu_ids; 1548 } 1549 1550 #ifdef CONFIG_HOTPLUG_CPU 1551 if (!setup_max_cpus) 1552 #endif 1553 if (possible > i) { 1554 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1555 possible, setup_max_cpus); 1556 possible = i; 1557 } 1558 1559 nr_cpu_ids = possible; 1560 1561 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1562 possible, max_t(int, possible - num_processors, 0)); 1563 1564 reset_cpu_possible_mask(); 1565 1566 for (i = 0; i < possible; i++) 1567 set_cpu_possible(i, true); 1568 } 1569 1570 #ifdef CONFIG_HOTPLUG_CPU 1571 1572 /* Recompute SMT state for all CPUs on offline */ 1573 static void recompute_smt_state(void) 1574 { 1575 int max_threads, cpu; 1576 1577 max_threads = 0; 1578 for_each_online_cpu (cpu) { 1579 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1580 1581 if (threads > max_threads) 1582 max_threads = threads; 1583 } 1584 __max_smt_threads = max_threads; 1585 } 1586 1587 static void remove_siblinginfo(int cpu) 1588 { 1589 int sibling; 1590 struct cpuinfo_x86 *c = &cpu_data(cpu); 1591 1592 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1593 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1594 /*/ 1595 * last thread sibling in this cpu core going down 1596 */ 1597 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1598 cpu_data(sibling).booted_cores--; 1599 } 1600 1601 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1602 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1603 1604 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1605 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1606 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1607 cpu_data(sibling).smt_active = false; 1608 } 1609 1610 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1611 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1612 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1613 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1614 cpumask_clear(cpu_llc_shared_mask(cpu)); 1615 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1616 cpumask_clear(topology_sibling_cpumask(cpu)); 1617 cpumask_clear(topology_core_cpumask(cpu)); 1618 cpumask_clear(topology_die_cpumask(cpu)); 1619 c->cpu_core_id = 0; 1620 c->booted_cores = 0; 1621 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1622 recompute_smt_state(); 1623 } 1624 1625 static void remove_cpu_from_maps(int cpu) 1626 { 1627 set_cpu_online(cpu, false); 1628 cpumask_clear_cpu(cpu, cpu_callout_mask); 1629 cpumask_clear_cpu(cpu, cpu_callin_mask); 1630 /* was set by cpu_init() */ 1631 cpumask_clear_cpu(cpu, cpu_initialized_mask); 1632 numa_remove_cpu(cpu); 1633 } 1634 1635 void cpu_disable_common(void) 1636 { 1637 int cpu = smp_processor_id(); 1638 1639 remove_siblinginfo(cpu); 1640 1641 /* It's now safe to remove this processor from the online map */ 1642 lock_vector_lock(); 1643 remove_cpu_from_maps(cpu); 1644 unlock_vector_lock(); 1645 fixup_irqs(); 1646 lapic_offline(); 1647 } 1648 1649 int native_cpu_disable(void) 1650 { 1651 int ret; 1652 1653 ret = lapic_can_unplug_cpu(); 1654 if (ret) 1655 return ret; 1656 1657 cpu_disable_common(); 1658 1659 /* 1660 * Disable the local APIC. Otherwise IPI broadcasts will reach 1661 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1662 * messages. 1663 * 1664 * Disabling the APIC must happen after cpu_disable_common() 1665 * which invokes fixup_irqs(). 1666 * 1667 * Disabling the APIC preserves already set bits in IRR, but 1668 * an interrupt arriving after disabling the local APIC does not 1669 * set the corresponding IRR bit. 1670 * 1671 * fixup_irqs() scans IRR for set bits so it can raise a not 1672 * yet handled interrupt on the new destination CPU via an IPI 1673 * but obviously it can't do so for IRR bits which are not set. 1674 * IOW, interrupts arriving after disabling the local APIC will 1675 * be lost. 1676 */ 1677 apic_soft_disable(); 1678 1679 return 0; 1680 } 1681 1682 int common_cpu_die(unsigned int cpu) 1683 { 1684 int ret = 0; 1685 1686 /* We don't do anything here: idle task is faking death itself. */ 1687 1688 /* They ack this in play_dead() by setting CPU_DEAD */ 1689 if (cpu_wait_death(cpu, 5)) { 1690 if (system_state == SYSTEM_RUNNING) 1691 pr_info("CPU %u is now offline\n", cpu); 1692 } else { 1693 pr_err("CPU %u didn't die...\n", cpu); 1694 ret = -1; 1695 } 1696 1697 return ret; 1698 } 1699 1700 void native_cpu_die(unsigned int cpu) 1701 { 1702 common_cpu_die(cpu); 1703 } 1704 1705 void play_dead_common(void) 1706 { 1707 idle_task_exit(); 1708 1709 /* Ack it */ 1710 (void)cpu_report_death(); 1711 1712 /* 1713 * With physical CPU hotplug, we should halt the cpu 1714 */ 1715 local_irq_disable(); 1716 } 1717 1718 /** 1719 * cond_wakeup_cpu0 - Wake up CPU0 if needed. 1720 * 1721 * If NMI wants to wake up CPU0, start CPU0. 1722 */ 1723 void cond_wakeup_cpu0(void) 1724 { 1725 if (smp_processor_id() == 0 && enable_start_cpu0) 1726 start_cpu0(); 1727 } 1728 EXPORT_SYMBOL_GPL(cond_wakeup_cpu0); 1729 1730 /* 1731 * We need to flush the caches before going to sleep, lest we have 1732 * dirty data in our caches when we come back up. 1733 */ 1734 static inline void mwait_play_dead(void) 1735 { 1736 unsigned int eax, ebx, ecx, edx; 1737 unsigned int highest_cstate = 0; 1738 unsigned int highest_subcstate = 0; 1739 void *mwait_ptr; 1740 int i; 1741 1742 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1743 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1744 return; 1745 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1746 return; 1747 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1748 return; 1749 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1750 return; 1751 1752 eax = CPUID_MWAIT_LEAF; 1753 ecx = 0; 1754 native_cpuid(&eax, &ebx, &ecx, &edx); 1755 1756 /* 1757 * eax will be 0 if EDX enumeration is not valid. 1758 * Initialized below to cstate, sub_cstate value when EDX is valid. 1759 */ 1760 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1761 eax = 0; 1762 } else { 1763 edx >>= MWAIT_SUBSTATE_SIZE; 1764 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1765 if (edx & MWAIT_SUBSTATE_MASK) { 1766 highest_cstate = i; 1767 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1768 } 1769 } 1770 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1771 (highest_subcstate - 1); 1772 } 1773 1774 /* 1775 * This should be a memory location in a cache line which is 1776 * unlikely to be touched by other processors. The actual 1777 * content is immaterial as it is not actually modified in any way. 1778 */ 1779 mwait_ptr = ¤t_thread_info()->flags; 1780 1781 wbinvd(); 1782 1783 while (1) { 1784 /* 1785 * The CLFLUSH is a workaround for erratum AAI65 for 1786 * the Xeon 7400 series. It's not clear it is actually 1787 * needed, but it should be harmless in either case. 1788 * The WBINVD is insufficient due to the spurious-wakeup 1789 * case where we return around the loop. 1790 */ 1791 mb(); 1792 clflush(mwait_ptr); 1793 mb(); 1794 __monitor(mwait_ptr, 0, 0); 1795 mb(); 1796 __mwait(eax, 0); 1797 1798 cond_wakeup_cpu0(); 1799 } 1800 } 1801 1802 void hlt_play_dead(void) 1803 { 1804 if (__this_cpu_read(cpu_info.x86) >= 4) 1805 wbinvd(); 1806 1807 while (1) { 1808 native_halt(); 1809 1810 cond_wakeup_cpu0(); 1811 } 1812 } 1813 1814 void native_play_dead(void) 1815 { 1816 play_dead_common(); 1817 tboot_shutdown(TB_SHUTDOWN_WFS); 1818 1819 mwait_play_dead(); /* Only returns on failure */ 1820 if (cpuidle_play_dead()) 1821 hlt_play_dead(); 1822 } 1823 1824 #else /* ... !CONFIG_HOTPLUG_CPU */ 1825 int native_cpu_disable(void) 1826 { 1827 return -ENOSYS; 1828 } 1829 1830 void native_cpu_die(unsigned int cpu) 1831 { 1832 /* We said "no" in __cpu_disable */ 1833 BUG(); 1834 } 1835 1836 void native_play_dead(void) 1837 { 1838 BUG(); 1839 } 1840 1841 #endif 1842 1843 #ifdef CONFIG_X86_64 1844 /* 1845 * APERF/MPERF frequency ratio computation. 1846 * 1847 * The scheduler wants to do frequency invariant accounting and needs a <1 1848 * ratio to account for the 'current' frequency, corresponding to 1849 * freq_curr / freq_max. 1850 * 1851 * Since the frequency freq_curr on x86 is controlled by micro-controller and 1852 * our P-state setting is little more than a request/hint, we need to observe 1853 * the effective frequency 'BusyMHz', i.e. the average frequency over a time 1854 * interval after discarding idle time. This is given by: 1855 * 1856 * BusyMHz = delta_APERF / delta_MPERF * freq_base 1857 * 1858 * where freq_base is the max non-turbo P-state. 1859 * 1860 * The freq_max term has to be set to a somewhat arbitrary value, because we 1861 * can't know which turbo states will be available at a given point in time: 1862 * it all depends on the thermal headroom of the entire package. We set it to 1863 * the turbo level with 4 cores active. 1864 * 1865 * Benchmarks show that's a good compromise between the 1C turbo ratio 1866 * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, 1867 * which would ignore the entire turbo range (a conspicuous part, making 1868 * freq_curr/freq_max always maxed out). 1869 * 1870 * An exception to the heuristic above is the Atom uarch, where we choose the 1871 * highest turbo level for freq_max since Atom's are generally oriented towards 1872 * power efficiency. 1873 * 1874 * Setting freq_max to anything less than the 1C turbo ratio makes the ratio 1875 * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. 1876 */ 1877 1878 DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); 1879 1880 static DEFINE_PER_CPU(u64, arch_prev_aperf); 1881 static DEFINE_PER_CPU(u64, arch_prev_mperf); 1882 static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; 1883 static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; 1884 1885 void arch_set_max_freq_ratio(bool turbo_disabled) 1886 { 1887 arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : 1888 arch_turbo_freq_ratio; 1889 } 1890 EXPORT_SYMBOL_GPL(arch_set_max_freq_ratio); 1891 1892 static bool turbo_disabled(void) 1893 { 1894 u64 misc_en; 1895 int err; 1896 1897 err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); 1898 if (err) 1899 return false; 1900 1901 return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); 1902 } 1903 1904 static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 1905 { 1906 int err; 1907 1908 err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); 1909 if (err) 1910 return false; 1911 1912 err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); 1913 if (err) 1914 return false; 1915 1916 *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ 1917 *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ 1918 1919 return true; 1920 } 1921 1922 #define X86_MATCH(model) \ 1923 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, \ 1924 INTEL_FAM6_##model, X86_FEATURE_APERFMPERF, NULL) 1925 1926 static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { 1927 X86_MATCH(XEON_PHI_KNL), 1928 X86_MATCH(XEON_PHI_KNM), 1929 {} 1930 }; 1931 1932 static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { 1933 X86_MATCH(SKYLAKE_X), 1934 {} 1935 }; 1936 1937 static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { 1938 X86_MATCH(ATOM_GOLDMONT), 1939 X86_MATCH(ATOM_GOLDMONT_D), 1940 X86_MATCH(ATOM_GOLDMONT_PLUS), 1941 {} 1942 }; 1943 1944 static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, 1945 int num_delta_fratio) 1946 { 1947 int fratio, delta_fratio, found; 1948 int err, i; 1949 u64 msr; 1950 1951 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1952 if (err) 1953 return false; 1954 1955 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1956 1957 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 1958 if (err) 1959 return false; 1960 1961 fratio = (msr >> 8) & 0xFF; 1962 i = 16; 1963 found = 0; 1964 do { 1965 if (found >= num_delta_fratio) { 1966 *turbo_freq = fratio; 1967 return true; 1968 } 1969 1970 delta_fratio = (msr >> (i + 5)) & 0x7; 1971 1972 if (delta_fratio) { 1973 found += 1; 1974 fratio -= delta_fratio; 1975 } 1976 1977 i += 8; 1978 } while (i < 64); 1979 1980 return true; 1981 } 1982 1983 static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) 1984 { 1985 u64 ratios, counts; 1986 u32 group_size; 1987 int err, i; 1988 1989 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 1990 if (err) 1991 return false; 1992 1993 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 1994 1995 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); 1996 if (err) 1997 return false; 1998 1999 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); 2000 if (err) 2001 return false; 2002 2003 for (i = 0; i < 64; i += 8) { 2004 group_size = (counts >> i) & 0xFF; 2005 if (group_size >= size) { 2006 *turbo_freq = (ratios >> i) & 0xFF; 2007 return true; 2008 } 2009 } 2010 2011 return false; 2012 } 2013 2014 static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) 2015 { 2016 u64 msr; 2017 int err; 2018 2019 err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); 2020 if (err) 2021 return false; 2022 2023 err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); 2024 if (err) 2025 return false; 2026 2027 *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ 2028 *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */ 2029 2030 /* The CPU may have less than 4 cores */ 2031 if (!*turbo_freq) 2032 *turbo_freq = msr & 0xFF; /* 1C turbo */ 2033 2034 return true; 2035 } 2036 2037 static bool intel_set_max_freq_ratio(void) 2038 { 2039 u64 base_freq, turbo_freq; 2040 u64 turbo_ratio; 2041 2042 if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) 2043 goto out; 2044 2045 if (x86_match_cpu(has_glm_turbo_ratio_limits) && 2046 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 2047 goto out; 2048 2049 if (x86_match_cpu(has_knl_turbo_ratio_limits) && 2050 knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) 2051 goto out; 2052 2053 if (x86_match_cpu(has_skx_turbo_ratio_limits) && 2054 skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) 2055 goto out; 2056 2057 if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) 2058 goto out; 2059 2060 return false; 2061 2062 out: 2063 /* 2064 * Some hypervisors advertise X86_FEATURE_APERFMPERF 2065 * but then fill all MSR's with zeroes. 2066 * Some CPUs have turbo boost but don't declare any turbo ratio 2067 * in MSR_TURBO_RATIO_LIMIT. 2068 */ 2069 if (!base_freq || !turbo_freq) { 2070 pr_debug("Couldn't determine cpu base or turbo frequency, necessary for scale-invariant accounting.\n"); 2071 return false; 2072 } 2073 2074 turbo_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, base_freq); 2075 if (!turbo_ratio) { 2076 pr_debug("Non-zero turbo and base frequencies led to a 0 ratio.\n"); 2077 return false; 2078 } 2079 2080 arch_turbo_freq_ratio = turbo_ratio; 2081 arch_set_max_freq_ratio(turbo_disabled()); 2082 2083 return true; 2084 } 2085 2086 #ifdef CONFIG_ACPI_CPPC_LIB 2087 static bool amd_set_max_freq_ratio(void) 2088 { 2089 struct cppc_perf_caps perf_caps; 2090 u64 highest_perf, nominal_perf; 2091 u64 perf_ratio; 2092 int rc; 2093 2094 rc = cppc_get_perf_caps(0, &perf_caps); 2095 if (rc) { 2096 pr_debug("Could not retrieve perf counters (%d)\n", rc); 2097 return false; 2098 } 2099 2100 highest_perf = amd_get_highest_perf(); 2101 nominal_perf = perf_caps.nominal_perf; 2102 2103 if (!highest_perf || !nominal_perf) { 2104 pr_debug("Could not retrieve highest or nominal performance\n"); 2105 return false; 2106 } 2107 2108 perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf); 2109 /* midpoint between max_boost and max_P */ 2110 perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1; 2111 if (!perf_ratio) { 2112 pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n"); 2113 return false; 2114 } 2115 2116 arch_turbo_freq_ratio = perf_ratio; 2117 arch_set_max_freq_ratio(false); 2118 2119 return true; 2120 } 2121 #else 2122 static bool amd_set_max_freq_ratio(void) 2123 { 2124 return false; 2125 } 2126 #endif 2127 2128 static void init_counter_refs(void) 2129 { 2130 u64 aperf, mperf; 2131 2132 rdmsrl(MSR_IA32_APERF, aperf); 2133 rdmsrl(MSR_IA32_MPERF, mperf); 2134 2135 this_cpu_write(arch_prev_aperf, aperf); 2136 this_cpu_write(arch_prev_mperf, mperf); 2137 } 2138 2139 #ifdef CONFIG_PM_SLEEP 2140 static struct syscore_ops freq_invariance_syscore_ops = { 2141 .resume = init_counter_refs, 2142 }; 2143 2144 static void register_freq_invariance_syscore_ops(void) 2145 { 2146 /* Bail out if registered already. */ 2147 if (freq_invariance_syscore_ops.node.prev) 2148 return; 2149 2150 register_syscore_ops(&freq_invariance_syscore_ops); 2151 } 2152 #else 2153 static inline void register_freq_invariance_syscore_ops(void) {} 2154 #endif 2155 2156 static void init_freq_invariance(bool secondary, bool cppc_ready) 2157 { 2158 bool ret = false; 2159 2160 if (!boot_cpu_has(X86_FEATURE_APERFMPERF)) 2161 return; 2162 2163 if (secondary) { 2164 if (static_branch_likely(&arch_scale_freq_key)) { 2165 init_counter_refs(); 2166 } 2167 return; 2168 } 2169 2170 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) 2171 ret = intel_set_max_freq_ratio(); 2172 else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) { 2173 if (!cppc_ready) { 2174 return; 2175 } 2176 ret = amd_set_max_freq_ratio(); 2177 } 2178 2179 if (ret) { 2180 init_counter_refs(); 2181 static_branch_enable(&arch_scale_freq_key); 2182 register_freq_invariance_syscore_ops(); 2183 pr_info("Estimated ratio of average max frequency by base frequency (times 1024): %llu\n", arch_max_freq_ratio); 2184 } else { 2185 pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); 2186 } 2187 } 2188 2189 #ifdef CONFIG_ACPI_CPPC_LIB 2190 static DEFINE_MUTEX(freq_invariance_lock); 2191 2192 void init_freq_invariance_cppc(void) 2193 { 2194 static bool secondary; 2195 2196 mutex_lock(&freq_invariance_lock); 2197 2198 init_freq_invariance(secondary, true); 2199 secondary = true; 2200 2201 mutex_unlock(&freq_invariance_lock); 2202 } 2203 #endif 2204 2205 static void disable_freq_invariance_workfn(struct work_struct *work) 2206 { 2207 static_branch_disable(&arch_scale_freq_key); 2208 } 2209 2210 static DECLARE_WORK(disable_freq_invariance_work, 2211 disable_freq_invariance_workfn); 2212 2213 DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; 2214 2215 void arch_scale_freq_tick(void) 2216 { 2217 u64 freq_scale; 2218 u64 aperf, mperf; 2219 u64 acnt, mcnt; 2220 2221 if (!arch_scale_freq_invariant()) 2222 return; 2223 2224 rdmsrl(MSR_IA32_APERF, aperf); 2225 rdmsrl(MSR_IA32_MPERF, mperf); 2226 2227 acnt = aperf - this_cpu_read(arch_prev_aperf); 2228 mcnt = mperf - this_cpu_read(arch_prev_mperf); 2229 2230 this_cpu_write(arch_prev_aperf, aperf); 2231 this_cpu_write(arch_prev_mperf, mperf); 2232 2233 if (check_shl_overflow(acnt, 2*SCHED_CAPACITY_SHIFT, &acnt)) 2234 goto error; 2235 2236 if (check_mul_overflow(mcnt, arch_max_freq_ratio, &mcnt) || !mcnt) 2237 goto error; 2238 2239 freq_scale = div64_u64(acnt, mcnt); 2240 if (!freq_scale) 2241 goto error; 2242 2243 if (freq_scale > SCHED_CAPACITY_SCALE) 2244 freq_scale = SCHED_CAPACITY_SCALE; 2245 2246 this_cpu_write(arch_freq_scale, freq_scale); 2247 return; 2248 2249 error: 2250 pr_warn("Scheduler frequency invariance went wobbly, disabling!\n"); 2251 schedule_work(&disable_freq_invariance_work); 2252 } 2253 #else 2254 static inline void init_freq_invariance(bool secondary, bool cppc_ready) 2255 { 2256 } 2257 #endif /* CONFIG_X86_64 */ 2258