1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 /* representing HT, core, and die siblings of each logical CPU */ 100 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 101 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 102 103 /* Per CPU bogomips and other parameters */ 104 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 105 EXPORT_PER_CPU_SYMBOL(cpu_info); 106 107 /* CPUs which are the primary SMT threads */ 108 struct cpumask __cpu_primary_thread_mask __read_mostly; 109 110 /* Representing CPUs for which sibling maps can be computed */ 111 static cpumask_var_t cpu_sibling_setup_mask; 112 113 struct mwait_cpu_dead { 114 unsigned int control; 115 unsigned int status; 116 }; 117 118 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 119 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 120 121 /* 122 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 123 * that it's unlikely to be touched by other CPUs. 124 */ 125 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 126 127 /* Logical package management. We might want to allocate that dynamically */ 128 unsigned int __max_logical_packages __read_mostly; 129 EXPORT_SYMBOL(__max_logical_packages); 130 static unsigned int logical_packages __read_mostly; 131 static unsigned int logical_die __read_mostly; 132 133 /* Maximum number of SMT threads on any online core */ 134 int __read_mostly __max_smt_threads = 1; 135 136 /* Flag to indicate if a complete sched domain rebuild is required */ 137 bool x86_topology_update; 138 139 int arch_update_cpu_topology(void) 140 { 141 int retval = x86_topology_update; 142 143 x86_topology_update = false; 144 return retval; 145 } 146 147 static unsigned int smpboot_warm_reset_vector_count; 148 149 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&rtc_lock, flags); 154 if (!smpboot_warm_reset_vector_count++) { 155 CMOS_WRITE(0xa, 0xf); 156 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 157 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 158 } 159 spin_unlock_irqrestore(&rtc_lock, flags); 160 } 161 162 static inline void smpboot_restore_warm_reset_vector(void) 163 { 164 unsigned long flags; 165 166 /* 167 * Paranoid: Set warm reset code and vector here back 168 * to default values. 169 */ 170 spin_lock_irqsave(&rtc_lock, flags); 171 if (!--smpboot_warm_reset_vector_count) { 172 CMOS_WRITE(0, 0xf); 173 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 174 } 175 spin_unlock_irqrestore(&rtc_lock, flags); 176 177 } 178 179 /* Run the next set of setup steps for the upcoming CPU */ 180 static void ap_starting(void) 181 { 182 int cpuid = smp_processor_id(); 183 184 /* Mop up eventual mwait_play_dead() wreckage */ 185 this_cpu_write(mwait_cpu_dead.status, 0); 186 this_cpu_write(mwait_cpu_dead.control, 0); 187 188 /* 189 * If woken up by an INIT in an 82489DX configuration the alive 190 * synchronization guarantees that the CPU does not reach this 191 * point before an INIT_deassert IPI reaches the local APIC, so it 192 * is now safe to touch the local APIC. 193 * 194 * Set up this CPU, first the APIC, which is probably redundant on 195 * most boards. 196 */ 197 apic_ap_setup(); 198 199 /* Save the processor parameters. */ 200 smp_store_cpu_info(cpuid); 201 202 /* 203 * The topology information must be up to date before 204 * notify_cpu_starting(). 205 */ 206 set_cpu_sibling_map(cpuid); 207 208 ap_init_aperfmperf(); 209 210 pr_debug("Stack at about %p\n", &cpuid); 211 212 wmb(); 213 214 /* 215 * This runs the AP through all the cpuhp states to its target 216 * state CPUHP_ONLINE. 217 */ 218 notify_cpu_starting(cpuid); 219 } 220 221 static void ap_calibrate_delay(void) 222 { 223 /* 224 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 225 * smp_store_cpu_info() stored a value that is close but not as 226 * accurate as the value just calculated. 227 * 228 * As this is invoked after the TSC synchronization check, 229 * calibrate_delay_is_known() will skip the calibration routine 230 * when TSC is synchronized across sockets. 231 */ 232 calibrate_delay(); 233 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 234 } 235 236 /* 237 * Activate a secondary processor. 238 */ 239 static void notrace start_secondary(void *unused) 240 { 241 /* 242 * Don't put *anything* except direct CPU state initialization 243 * before cpu_init(), SMP booting is too fragile that we want to 244 * limit the things done here to the most necessary things. 245 */ 246 cr4_init(); 247 248 /* 249 * 32-bit specific. 64-bit reaches this code with the correct page 250 * table established. Yet another historical divergence. 251 */ 252 if (IS_ENABLED(CONFIG_X86_32)) { 253 /* switch away from the initial page table */ 254 load_cr3(swapper_pg_dir); 255 __flush_tlb_all(); 256 } 257 258 cpu_init_exception_handling(); 259 260 /* 261 * 32-bit systems load the microcode from the ASM startup code for 262 * historical reasons. 263 * 264 * On 64-bit systems load it before reaching the AP alive 265 * synchronization point below so it is not part of the full per 266 * CPU serialized bringup part when "parallel" bringup is enabled. 267 * 268 * That's even safe when hyperthreading is enabled in the CPU as 269 * the core code starts the primary threads first and leaves the 270 * secondary threads waiting for SIPI. Loading microcode on 271 * physical cores concurrently is a safe operation. 272 * 273 * This covers both the Intel specific issue that concurrent 274 * microcode loading on SMT siblings must be prohibited and the 275 * vendor independent issue`that microcode loading which changes 276 * CPUID, MSRs etc. must be strictly serialized to maintain 277 * software state correctness. 278 */ 279 if (IS_ENABLED(CONFIG_X86_64)) 280 load_ucode_ap(); 281 282 /* 283 * Synchronization point with the hotplug core. Sets this CPUs 284 * synchronization state to ALIVE and spin-waits for the control CPU to 285 * release this CPU for further bringup. 286 */ 287 cpuhp_ap_sync_alive(); 288 289 cpu_init(); 290 fpu__init_cpu(); 291 rcu_cpu_starting(raw_smp_processor_id()); 292 x86_cpuinit.early_percpu_clock_init(); 293 294 ap_starting(); 295 296 /* Check TSC synchronization with the control CPU. */ 297 check_tsc_sync_target(); 298 299 /* 300 * Calibrate the delay loop after the TSC synchronization check. 301 * This allows to skip the calibration when TSC is synchronized 302 * across sockets. 303 */ 304 ap_calibrate_delay(); 305 306 speculative_store_bypass_ht_init(); 307 308 /* 309 * Lock vector_lock, set CPU online and bring the vector 310 * allocator online. Online must be set with vector_lock held 311 * to prevent a concurrent irq setup/teardown from seeing a 312 * half valid vector space. 313 */ 314 lock_vector_lock(); 315 set_cpu_online(smp_processor_id(), true); 316 lapic_online(); 317 unlock_vector_lock(); 318 x86_platform.nmi_init(); 319 320 /* enable local interrupts */ 321 local_irq_enable(); 322 323 x86_cpuinit.setup_percpu_clockev(); 324 325 wmb(); 326 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 327 } 328 329 /** 330 * topology_smt_supported - Check whether SMT is supported by the CPUs 331 */ 332 bool topology_smt_supported(void) 333 { 334 return smp_num_siblings > 1; 335 } 336 337 /** 338 * topology_phys_to_logical_pkg - Map a physical package id to a logical 339 * @phys_pkg: The physical package id to map 340 * 341 * Returns logical package id or -1 if not found 342 */ 343 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 344 { 345 int cpu; 346 347 for_each_possible_cpu(cpu) { 348 struct cpuinfo_x86 *c = &cpu_data(cpu); 349 350 if (c->initialized && c->phys_proc_id == phys_pkg) 351 return c->logical_proc_id; 352 } 353 return -1; 354 } 355 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 356 357 /** 358 * topology_phys_to_logical_die - Map a physical die id to logical 359 * @die_id: The physical die id to map 360 * @cur_cpu: The CPU for which the mapping is done 361 * 362 * Returns logical die id or -1 if not found 363 */ 364 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 365 { 366 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 367 368 for_each_possible_cpu(cpu) { 369 struct cpuinfo_x86 *c = &cpu_data(cpu); 370 371 if (c->initialized && c->cpu_die_id == die_id && 372 c->phys_proc_id == proc_id) 373 return c->logical_die_id; 374 } 375 return -1; 376 } 377 378 /** 379 * topology_update_package_map - Update the physical to logical package map 380 * @pkg: The physical package id as retrieved via CPUID 381 * @cpu: The cpu for which this is updated 382 */ 383 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 384 { 385 int new; 386 387 /* Already available somewhere? */ 388 new = topology_phys_to_logical_pkg(pkg); 389 if (new >= 0) 390 goto found; 391 392 new = logical_packages++; 393 if (new != pkg) { 394 pr_info("CPU %u Converting physical %u to logical package %u\n", 395 cpu, pkg, new); 396 } 397 found: 398 cpu_data(cpu).logical_proc_id = new; 399 return 0; 400 } 401 /** 402 * topology_update_die_map - Update the physical to logical die map 403 * @die: The die id as retrieved via CPUID 404 * @cpu: The cpu for which this is updated 405 */ 406 int topology_update_die_map(unsigned int die, unsigned int cpu) 407 { 408 int new; 409 410 /* Already available somewhere? */ 411 new = topology_phys_to_logical_die(die, cpu); 412 if (new >= 0) 413 goto found; 414 415 new = logical_die++; 416 if (new != die) { 417 pr_info("CPU %u Converting physical %u to logical die %u\n", 418 cpu, die, new); 419 } 420 found: 421 cpu_data(cpu).logical_die_id = new; 422 return 0; 423 } 424 425 void __init smp_store_boot_cpu_info(void) 426 { 427 int id = 0; /* CPU 0 */ 428 struct cpuinfo_x86 *c = &cpu_data(id); 429 430 *c = boot_cpu_data; 431 c->cpu_index = id; 432 topology_update_package_map(c->phys_proc_id, id); 433 topology_update_die_map(c->cpu_die_id, id); 434 c->initialized = true; 435 } 436 437 /* 438 * The bootstrap kernel entry code has set these up. Save them for 439 * a given CPU 440 */ 441 void smp_store_cpu_info(int id) 442 { 443 struct cpuinfo_x86 *c = &cpu_data(id); 444 445 /* Copy boot_cpu_data only on the first bringup */ 446 if (!c->initialized) 447 *c = boot_cpu_data; 448 c->cpu_index = id; 449 /* 450 * During boot time, CPU0 has this setup already. Save the info when 451 * bringing up an AP. 452 */ 453 identify_secondary_cpu(c); 454 c->initialized = true; 455 } 456 457 static bool 458 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 459 { 460 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 461 462 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 463 } 464 465 static bool 466 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 467 { 468 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 469 470 return !WARN_ONCE(!topology_same_node(c, o), 471 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 472 "[node: %d != %d]. Ignoring dependency.\n", 473 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 474 } 475 476 #define link_mask(mfunc, c1, c2) \ 477 do { \ 478 cpumask_set_cpu((c1), mfunc(c2)); \ 479 cpumask_set_cpu((c2), mfunc(c1)); \ 480 } while (0) 481 482 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 483 { 484 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 485 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 486 487 if (c->phys_proc_id == o->phys_proc_id && 488 c->cpu_die_id == o->cpu_die_id && 489 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 490 if (c->cpu_core_id == o->cpu_core_id) 491 return topology_sane(c, o, "smt"); 492 493 if ((c->cu_id != 0xff) && 494 (o->cu_id != 0xff) && 495 (c->cu_id == o->cu_id)) 496 return topology_sane(c, o, "smt"); 497 } 498 499 } else if (c->phys_proc_id == o->phys_proc_id && 500 c->cpu_die_id == o->cpu_die_id && 501 c->cpu_core_id == o->cpu_core_id) { 502 return topology_sane(c, o, "smt"); 503 } 504 505 return false; 506 } 507 508 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 509 { 510 if (c->phys_proc_id == o->phys_proc_id && 511 c->cpu_die_id == o->cpu_die_id) 512 return true; 513 return false; 514 } 515 516 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 517 { 518 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 519 520 /* If the arch didn't set up l2c_id, fall back to SMT */ 521 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 522 return match_smt(c, o); 523 524 /* Do not match if L2 cache id does not match: */ 525 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 526 return false; 527 528 return topology_sane(c, o, "l2c"); 529 } 530 531 /* 532 * Unlike the other levels, we do not enforce keeping a 533 * multicore group inside a NUMA node. If this happens, we will 534 * discard the MC level of the topology later. 535 */ 536 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 537 { 538 if (c->phys_proc_id == o->phys_proc_id) 539 return true; 540 return false; 541 } 542 543 /* 544 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 545 * 546 * Any Intel CPU that has multiple nodes per package and does not 547 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 548 * 549 * When in SNC mode, these CPUs enumerate an LLC that is shared 550 * by multiple NUMA nodes. The LLC is shared for off-package data 551 * access but private to the NUMA node (half of the package) for 552 * on-package access. CPUID (the source of the information about 553 * the LLC) can only enumerate the cache as shared or unshared, 554 * but not this particular configuration. 555 */ 556 557 static const struct x86_cpu_id intel_cod_cpu[] = { 558 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 559 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 560 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 561 {} 562 }; 563 564 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 565 { 566 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 567 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 568 bool intel_snc = id && id->driver_data; 569 570 /* Do not match if we do not have a valid APICID for cpu: */ 571 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 572 return false; 573 574 /* Do not match if LLC id does not match: */ 575 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 576 return false; 577 578 /* 579 * Allow the SNC topology without warning. Return of false 580 * means 'c' does not share the LLC of 'o'. This will be 581 * reflected to userspace. 582 */ 583 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 584 return false; 585 586 return topology_sane(c, o, "llc"); 587 } 588 589 590 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 591 static inline int x86_sched_itmt_flags(void) 592 { 593 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 594 } 595 596 #ifdef CONFIG_SCHED_MC 597 static int x86_core_flags(void) 598 { 599 return cpu_core_flags() | x86_sched_itmt_flags(); 600 } 601 #endif 602 #ifdef CONFIG_SCHED_SMT 603 static int x86_smt_flags(void) 604 { 605 return cpu_smt_flags(); 606 } 607 #endif 608 #ifdef CONFIG_SCHED_CLUSTER 609 static int x86_cluster_flags(void) 610 { 611 return cpu_cluster_flags() | x86_sched_itmt_flags(); 612 } 613 #endif 614 #endif 615 616 /* 617 * Set if a package/die has multiple NUMA nodes inside. 618 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 619 * Sub-NUMA Clustering have this. 620 */ 621 static bool x86_has_numa_in_package; 622 623 static struct sched_domain_topology_level x86_topology[6]; 624 625 static void __init build_sched_topology(void) 626 { 627 int i = 0; 628 629 #ifdef CONFIG_SCHED_SMT 630 x86_topology[i++] = (struct sched_domain_topology_level){ 631 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 632 }; 633 #endif 634 #ifdef CONFIG_SCHED_CLUSTER 635 /* 636 * For now, skip the cluster domain on Hybrid. 637 */ 638 if (!cpu_feature_enabled(X86_FEATURE_HYBRID_CPU)) { 639 x86_topology[i++] = (struct sched_domain_topology_level){ 640 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 641 }; 642 } 643 #endif 644 #ifdef CONFIG_SCHED_MC 645 x86_topology[i++] = (struct sched_domain_topology_level){ 646 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 647 }; 648 #endif 649 /* 650 * When there is NUMA topology inside the package skip the DIE domain 651 * since the NUMA domains will auto-magically create the right spanning 652 * domains based on the SLIT. 653 */ 654 if (!x86_has_numa_in_package) { 655 x86_topology[i++] = (struct sched_domain_topology_level){ 656 cpu_cpu_mask, SD_INIT_NAME(DIE) 657 }; 658 } 659 660 /* 661 * There must be one trailing NULL entry left. 662 */ 663 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 664 665 set_sched_topology(x86_topology); 666 } 667 668 void set_cpu_sibling_map(int cpu) 669 { 670 bool has_smt = smp_num_siblings > 1; 671 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 672 struct cpuinfo_x86 *c = &cpu_data(cpu); 673 struct cpuinfo_x86 *o; 674 int i, threads; 675 676 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 677 678 if (!has_mp) { 679 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 680 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 681 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 682 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 683 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 684 c->booted_cores = 1; 685 return; 686 } 687 688 for_each_cpu(i, cpu_sibling_setup_mask) { 689 o = &cpu_data(i); 690 691 if (match_pkg(c, o) && !topology_same_node(c, o)) 692 x86_has_numa_in_package = true; 693 694 if ((i == cpu) || (has_smt && match_smt(c, o))) 695 link_mask(topology_sibling_cpumask, cpu, i); 696 697 if ((i == cpu) || (has_mp && match_llc(c, o))) 698 link_mask(cpu_llc_shared_mask, cpu, i); 699 700 if ((i == cpu) || (has_mp && match_l2c(c, o))) 701 link_mask(cpu_l2c_shared_mask, cpu, i); 702 703 if ((i == cpu) || (has_mp && match_die(c, o))) 704 link_mask(topology_die_cpumask, cpu, i); 705 } 706 707 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 708 if (threads > __max_smt_threads) 709 __max_smt_threads = threads; 710 711 for_each_cpu(i, topology_sibling_cpumask(cpu)) 712 cpu_data(i).smt_active = threads > 1; 713 714 /* 715 * This needs a separate iteration over the cpus because we rely on all 716 * topology_sibling_cpumask links to be set-up. 717 */ 718 for_each_cpu(i, cpu_sibling_setup_mask) { 719 o = &cpu_data(i); 720 721 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 722 link_mask(topology_core_cpumask, cpu, i); 723 724 /* 725 * Does this new cpu bringup a new core? 726 */ 727 if (threads == 1) { 728 /* 729 * for each core in package, increment 730 * the booted_cores for this new cpu 731 */ 732 if (cpumask_first( 733 topology_sibling_cpumask(i)) == i) 734 c->booted_cores++; 735 /* 736 * increment the core count for all 737 * the other cpus in this package 738 */ 739 if (i != cpu) 740 cpu_data(i).booted_cores++; 741 } else if (i != cpu && !c->booted_cores) 742 c->booted_cores = cpu_data(i).booted_cores; 743 } 744 } 745 } 746 747 /* maps the cpu to the sched domain representing multi-core */ 748 const struct cpumask *cpu_coregroup_mask(int cpu) 749 { 750 return cpu_llc_shared_mask(cpu); 751 } 752 753 const struct cpumask *cpu_clustergroup_mask(int cpu) 754 { 755 return cpu_l2c_shared_mask(cpu); 756 } 757 758 static void impress_friends(void) 759 { 760 int cpu; 761 unsigned long bogosum = 0; 762 /* 763 * Allow the user to impress friends. 764 */ 765 pr_debug("Before bogomips\n"); 766 for_each_online_cpu(cpu) 767 bogosum += cpu_data(cpu).loops_per_jiffy; 768 769 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 770 num_online_cpus(), 771 bogosum/(500000/HZ), 772 (bogosum/(5000/HZ))%100); 773 774 pr_debug("Before bogocount - setting activated=1\n"); 775 } 776 777 /* 778 * The Multiprocessor Specification 1.4 (1997) example code suggests 779 * that there should be a 10ms delay between the BSP asserting INIT 780 * and de-asserting INIT, when starting a remote processor. 781 * But that slows boot and resume on modern processors, which include 782 * many cores and don't require that delay. 783 * 784 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 785 * Modern processor families are quirked to remove the delay entirely. 786 */ 787 #define UDELAY_10MS_DEFAULT 10000 788 789 static unsigned int init_udelay = UINT_MAX; 790 791 static int __init cpu_init_udelay(char *str) 792 { 793 get_option(&str, &init_udelay); 794 795 return 0; 796 } 797 early_param("cpu_init_udelay", cpu_init_udelay); 798 799 static void __init smp_quirk_init_udelay(void) 800 { 801 /* if cmdline changed it from default, leave it alone */ 802 if (init_udelay != UINT_MAX) 803 return; 804 805 /* if modern processor, use no delay */ 806 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 807 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 808 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 809 init_udelay = 0; 810 return; 811 } 812 /* else, use legacy delay */ 813 init_udelay = UDELAY_10MS_DEFAULT; 814 } 815 816 /* 817 * Wake up AP by INIT, INIT, STARTUP sequence. 818 */ 819 static void send_init_sequence(int phys_apicid) 820 { 821 int maxlvt = lapic_get_maxlvt(); 822 823 /* Be paranoid about clearing APIC errors. */ 824 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 825 /* Due to the Pentium erratum 3AP. */ 826 if (maxlvt > 3) 827 apic_write(APIC_ESR, 0); 828 apic_read(APIC_ESR); 829 } 830 831 /* Assert INIT on the target CPU */ 832 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 833 safe_apic_wait_icr_idle(); 834 835 udelay(init_udelay); 836 837 /* Deassert INIT on the target CPU */ 838 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 839 safe_apic_wait_icr_idle(); 840 } 841 842 /* 843 * Wake up AP by INIT, INIT, STARTUP sequence. 844 */ 845 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 846 { 847 unsigned long send_status = 0, accept_status = 0; 848 int num_starts, j, maxlvt; 849 850 preempt_disable(); 851 maxlvt = lapic_get_maxlvt(); 852 send_init_sequence(phys_apicid); 853 854 mb(); 855 856 /* 857 * Should we send STARTUP IPIs ? 858 * 859 * Determine this based on the APIC version. 860 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 861 */ 862 if (APIC_INTEGRATED(boot_cpu_apic_version)) 863 num_starts = 2; 864 else 865 num_starts = 0; 866 867 /* 868 * Run STARTUP IPI loop. 869 */ 870 pr_debug("#startup loops: %d\n", num_starts); 871 872 for (j = 1; j <= num_starts; j++) { 873 pr_debug("Sending STARTUP #%d\n", j); 874 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 875 apic_write(APIC_ESR, 0); 876 apic_read(APIC_ESR); 877 pr_debug("After apic_write\n"); 878 879 /* 880 * STARTUP IPI 881 */ 882 883 /* Target chip */ 884 /* Boot on the stack */ 885 /* Kick the second */ 886 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 887 phys_apicid); 888 889 /* 890 * Give the other CPU some time to accept the IPI. 891 */ 892 if (init_udelay == 0) 893 udelay(10); 894 else 895 udelay(300); 896 897 pr_debug("Startup point 1\n"); 898 899 pr_debug("Waiting for send to finish...\n"); 900 send_status = safe_apic_wait_icr_idle(); 901 902 /* 903 * Give the other CPU some time to accept the IPI. 904 */ 905 if (init_udelay == 0) 906 udelay(10); 907 else 908 udelay(200); 909 910 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 911 apic_write(APIC_ESR, 0); 912 accept_status = (apic_read(APIC_ESR) & 0xEF); 913 if (send_status || accept_status) 914 break; 915 } 916 pr_debug("After Startup\n"); 917 918 if (send_status) 919 pr_err("APIC never delivered???\n"); 920 if (accept_status) 921 pr_err("APIC delivery error (%lx)\n", accept_status); 922 923 preempt_enable(); 924 return (send_status | accept_status); 925 } 926 927 /* reduce the number of lines printed when booting a large cpu count system */ 928 static void announce_cpu(int cpu, int apicid) 929 { 930 static int width, node_width, first = 1; 931 static int current_node = NUMA_NO_NODE; 932 int node = early_cpu_to_node(cpu); 933 934 if (!width) 935 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 936 937 if (!node_width) 938 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 939 940 if (system_state < SYSTEM_RUNNING) { 941 if (first) 942 pr_info("x86: Booting SMP configuration:\n"); 943 944 if (node != current_node) { 945 if (current_node > (-1)) 946 pr_cont("\n"); 947 current_node = node; 948 949 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 950 node_width - num_digits(node), " ", node); 951 } 952 953 /* Add padding for the BSP */ 954 if (first) 955 pr_cont("%*s", width + 1, " "); 956 first = 0; 957 958 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 959 } else 960 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 961 node, cpu, apicid); 962 } 963 964 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 965 { 966 int ret; 967 968 /* Just in case we booted with a single CPU. */ 969 alternatives_enable_smp(); 970 971 per_cpu(pcpu_hot.current_task, cpu) = idle; 972 cpu_init_stack_canary(cpu, idle); 973 974 /* Initialize the interrupt stack(s) */ 975 ret = irq_init_percpu_irqstack(cpu); 976 if (ret) 977 return ret; 978 979 #ifdef CONFIG_X86_32 980 /* Stack for startup_32 can be just as for start_secondary onwards */ 981 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 982 #endif 983 return 0; 984 } 985 986 /* 987 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 988 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 989 * Returns zero if startup was successfully sent, else error code from 990 * ->wakeup_secondary_cpu. 991 */ 992 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 993 { 994 unsigned long start_ip = real_mode_header->trampoline_start; 995 int ret; 996 997 #ifdef CONFIG_X86_64 998 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 999 if (apic->wakeup_secondary_cpu_64) 1000 start_ip = real_mode_header->trampoline_start64; 1001 #endif 1002 idle->thread.sp = (unsigned long)task_pt_regs(idle); 1003 initial_code = (unsigned long)start_secondary; 1004 1005 if (IS_ENABLED(CONFIG_X86_32)) { 1006 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 1007 initial_stack = idle->thread.sp; 1008 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 1009 smpboot_control = cpu; 1010 } 1011 1012 /* Enable the espfix hack for this CPU */ 1013 init_espfix_ap(cpu); 1014 1015 /* So we see what's up */ 1016 announce_cpu(cpu, apicid); 1017 1018 /* 1019 * This grunge runs the startup process for 1020 * the targeted processor. 1021 */ 1022 if (x86_platform.legacy.warm_reset) { 1023 1024 pr_debug("Setting warm reset code and vector.\n"); 1025 1026 smpboot_setup_warm_reset_vector(start_ip); 1027 /* 1028 * Be paranoid about clearing APIC errors. 1029 */ 1030 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1031 apic_write(APIC_ESR, 0); 1032 apic_read(APIC_ESR); 1033 } 1034 } 1035 1036 smp_mb(); 1037 1038 /* 1039 * Wake up a CPU in difference cases: 1040 * - Use a method from the APIC driver if one defined, with wakeup 1041 * straight to 64-bit mode preferred over wakeup to RM. 1042 * Otherwise, 1043 * - Use an INIT boot APIC message 1044 */ 1045 if (apic->wakeup_secondary_cpu_64) 1046 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1047 else if (apic->wakeup_secondary_cpu) 1048 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1049 else 1050 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1051 1052 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1053 if (ret) 1054 arch_cpuhp_cleanup_kick_cpu(cpu); 1055 return ret; 1056 } 1057 1058 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1059 { 1060 int apicid = apic->cpu_present_to_apicid(cpu); 1061 int err; 1062 1063 lockdep_assert_irqs_enabled(); 1064 1065 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1066 1067 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) || 1068 !apic_id_valid(apicid)) { 1069 pr_err("%s: bad cpu %d\n", __func__, cpu); 1070 return -EINVAL; 1071 } 1072 1073 /* 1074 * Save current MTRR state in case it was changed since early boot 1075 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1076 */ 1077 mtrr_save_state(); 1078 1079 /* the FPU context is blank, nobody can own it */ 1080 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1081 1082 err = common_cpu_up(cpu, tidle); 1083 if (err) 1084 return err; 1085 1086 err = do_boot_cpu(apicid, cpu, tidle); 1087 if (err) 1088 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1089 1090 return err; 1091 } 1092 1093 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1094 { 1095 return smp_ops.kick_ap_alive(cpu, tidle); 1096 } 1097 1098 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1099 { 1100 /* Cleanup possible dangling ends... */ 1101 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1102 smpboot_restore_warm_reset_vector(); 1103 } 1104 1105 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1106 { 1107 if (smp_ops.cleanup_dead_cpu) 1108 smp_ops.cleanup_dead_cpu(cpu); 1109 1110 if (system_state == SYSTEM_RUNNING) 1111 pr_info("CPU %u is now offline\n", cpu); 1112 } 1113 1114 void arch_cpuhp_sync_state_poll(void) 1115 { 1116 if (smp_ops.poll_sync_state) 1117 smp_ops.poll_sync_state(); 1118 } 1119 1120 /** 1121 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1122 */ 1123 void __init arch_disable_smp_support(void) 1124 { 1125 disable_ioapic_support(); 1126 } 1127 1128 /* 1129 * Fall back to non SMP mode after errors. 1130 * 1131 * RED-PEN audit/test this more. I bet there is more state messed up here. 1132 */ 1133 static __init void disable_smp(void) 1134 { 1135 pr_info("SMP disabled\n"); 1136 1137 disable_ioapic_support(); 1138 1139 init_cpu_present(cpumask_of(0)); 1140 init_cpu_possible(cpumask_of(0)); 1141 1142 if (smp_found_config) 1143 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1144 else 1145 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1146 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1147 cpumask_set_cpu(0, topology_core_cpumask(0)); 1148 cpumask_set_cpu(0, topology_die_cpumask(0)); 1149 } 1150 1151 static void __init smp_cpu_index_default(void) 1152 { 1153 int i; 1154 struct cpuinfo_x86 *c; 1155 1156 for_each_possible_cpu(i) { 1157 c = &cpu_data(i); 1158 /* mark all to hotplug */ 1159 c->cpu_index = nr_cpu_ids; 1160 } 1161 } 1162 1163 void __init smp_prepare_cpus_common(void) 1164 { 1165 unsigned int i; 1166 1167 smp_cpu_index_default(); 1168 1169 /* 1170 * Setup boot CPU information 1171 */ 1172 smp_store_boot_cpu_info(); /* Final full version of the data */ 1173 mb(); 1174 1175 for_each_possible_cpu(i) { 1176 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1177 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1178 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1179 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1180 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1181 } 1182 1183 set_cpu_sibling_map(0); 1184 } 1185 1186 #ifdef CONFIG_X86_64 1187 /* Establish whether parallel bringup can be supported. */ 1188 bool __init arch_cpuhp_init_parallel_bringup(void) 1189 { 1190 if (!x86_cpuinit.parallel_bringup) { 1191 pr_info("Parallel CPU startup disabled by the platform\n"); 1192 return false; 1193 } 1194 1195 smpboot_control = STARTUP_READ_APICID; 1196 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1197 return true; 1198 } 1199 #endif 1200 1201 /* 1202 * Prepare for SMP bootup. 1203 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1204 * for common interface support. 1205 */ 1206 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1207 { 1208 smp_prepare_cpus_common(); 1209 1210 switch (apic_intr_mode) { 1211 case APIC_PIC: 1212 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1213 disable_smp(); 1214 return; 1215 case APIC_SYMMETRIC_IO_NO_ROUTING: 1216 disable_smp(); 1217 /* Setup local timer */ 1218 x86_init.timers.setup_percpu_clockev(); 1219 return; 1220 case APIC_VIRTUAL_WIRE: 1221 case APIC_SYMMETRIC_IO: 1222 break; 1223 } 1224 1225 /* Setup local timer */ 1226 x86_init.timers.setup_percpu_clockev(); 1227 1228 pr_info("CPU0: "); 1229 print_cpu_info(&cpu_data(0)); 1230 1231 uv_system_init(); 1232 1233 smp_quirk_init_udelay(); 1234 1235 speculative_store_bypass_ht_init(); 1236 1237 snp_set_wakeup_secondary_cpu(); 1238 } 1239 1240 void arch_thaw_secondary_cpus_begin(void) 1241 { 1242 set_cache_aps_delayed_init(true); 1243 } 1244 1245 void arch_thaw_secondary_cpus_end(void) 1246 { 1247 cache_aps_init(); 1248 } 1249 1250 bool smp_park_other_cpus_in_init(void) 1251 { 1252 unsigned int cpu, this_cpu = smp_processor_id(); 1253 unsigned int apicid; 1254 1255 if (apic->wakeup_secondary_cpu_64 || apic->wakeup_secondary_cpu) 1256 return false; 1257 1258 /* 1259 * If this is a crash stop which does not execute on the boot CPU, 1260 * then this cannot use the INIT mechanism because INIT to the boot 1261 * CPU will reset the machine. 1262 */ 1263 if (this_cpu) 1264 return false; 1265 1266 for_each_present_cpu(cpu) { 1267 if (cpu == this_cpu) 1268 continue; 1269 apicid = apic->cpu_present_to_apicid(cpu); 1270 if (apicid == BAD_APICID) 1271 continue; 1272 send_init_sequence(apicid); 1273 } 1274 return true; 1275 } 1276 1277 /* 1278 * Early setup to make printk work. 1279 */ 1280 void __init native_smp_prepare_boot_cpu(void) 1281 { 1282 int me = smp_processor_id(); 1283 1284 /* SMP handles this from setup_per_cpu_areas() */ 1285 if (!IS_ENABLED(CONFIG_SMP)) 1286 switch_gdt_and_percpu_base(me); 1287 1288 native_pv_lock_init(); 1289 } 1290 1291 void __init calculate_max_logical_packages(void) 1292 { 1293 int ncpus; 1294 1295 /* 1296 * Today neither Intel nor AMD support heterogeneous systems so 1297 * extrapolate the boot cpu's data to all packages. 1298 */ 1299 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1300 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1301 pr_info("Max logical packages: %u\n", __max_logical_packages); 1302 } 1303 1304 void __init native_smp_cpus_done(unsigned int max_cpus) 1305 { 1306 pr_debug("Boot done\n"); 1307 1308 calculate_max_logical_packages(); 1309 build_sched_topology(); 1310 nmi_selftest(); 1311 impress_friends(); 1312 cache_aps_init(); 1313 } 1314 1315 static int __initdata setup_possible_cpus = -1; 1316 static int __init _setup_possible_cpus(char *str) 1317 { 1318 get_option(&str, &setup_possible_cpus); 1319 return 0; 1320 } 1321 early_param("possible_cpus", _setup_possible_cpus); 1322 1323 1324 /* 1325 * cpu_possible_mask should be static, it cannot change as cpu's 1326 * are onlined, or offlined. The reason is per-cpu data-structures 1327 * are allocated by some modules at init time, and don't expect to 1328 * do this dynamically on cpu arrival/departure. 1329 * cpu_present_mask on the other hand can change dynamically. 1330 * In case when cpu_hotplug is not compiled, then we resort to current 1331 * behaviour, which is cpu_possible == cpu_present. 1332 * - Ashok Raj 1333 * 1334 * Three ways to find out the number of additional hotplug CPUs: 1335 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1336 * - The user can overwrite it with possible_cpus=NUM 1337 * - Otherwise don't reserve additional CPUs. 1338 * We do this because additional CPUs waste a lot of memory. 1339 * -AK 1340 */ 1341 __init void prefill_possible_map(void) 1342 { 1343 int i, possible; 1344 1345 i = setup_max_cpus ?: 1; 1346 if (setup_possible_cpus == -1) { 1347 possible = num_processors; 1348 #ifdef CONFIG_HOTPLUG_CPU 1349 if (setup_max_cpus) 1350 possible += disabled_cpus; 1351 #else 1352 if (possible > i) 1353 possible = i; 1354 #endif 1355 } else 1356 possible = setup_possible_cpus; 1357 1358 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1359 1360 /* nr_cpu_ids could be reduced via nr_cpus= */ 1361 if (possible > nr_cpu_ids) { 1362 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1363 possible, nr_cpu_ids); 1364 possible = nr_cpu_ids; 1365 } 1366 1367 #ifdef CONFIG_HOTPLUG_CPU 1368 if (!setup_max_cpus) 1369 #endif 1370 if (possible > i) { 1371 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1372 possible, setup_max_cpus); 1373 possible = i; 1374 } 1375 1376 set_nr_cpu_ids(possible); 1377 1378 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1379 possible, max_t(int, possible - num_processors, 0)); 1380 1381 reset_cpu_possible_mask(); 1382 1383 for (i = 0; i < possible; i++) 1384 set_cpu_possible(i, true); 1385 } 1386 1387 /* correctly size the local cpu masks */ 1388 void __init setup_cpu_local_masks(void) 1389 { 1390 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1391 } 1392 1393 #ifdef CONFIG_HOTPLUG_CPU 1394 1395 /* Recompute SMT state for all CPUs on offline */ 1396 static void recompute_smt_state(void) 1397 { 1398 int max_threads, cpu; 1399 1400 max_threads = 0; 1401 for_each_online_cpu (cpu) { 1402 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1403 1404 if (threads > max_threads) 1405 max_threads = threads; 1406 } 1407 __max_smt_threads = max_threads; 1408 } 1409 1410 static void remove_siblinginfo(int cpu) 1411 { 1412 int sibling; 1413 struct cpuinfo_x86 *c = &cpu_data(cpu); 1414 1415 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1416 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1417 /*/ 1418 * last thread sibling in this cpu core going down 1419 */ 1420 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1421 cpu_data(sibling).booted_cores--; 1422 } 1423 1424 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1425 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1426 1427 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1428 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1429 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1430 cpu_data(sibling).smt_active = false; 1431 } 1432 1433 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1434 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1435 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1436 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1437 cpumask_clear(cpu_llc_shared_mask(cpu)); 1438 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1439 cpumask_clear(topology_sibling_cpumask(cpu)); 1440 cpumask_clear(topology_core_cpumask(cpu)); 1441 cpumask_clear(topology_die_cpumask(cpu)); 1442 c->cpu_core_id = 0; 1443 c->booted_cores = 0; 1444 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1445 recompute_smt_state(); 1446 } 1447 1448 static void remove_cpu_from_maps(int cpu) 1449 { 1450 set_cpu_online(cpu, false); 1451 numa_remove_cpu(cpu); 1452 } 1453 1454 void cpu_disable_common(void) 1455 { 1456 int cpu = smp_processor_id(); 1457 1458 remove_siblinginfo(cpu); 1459 1460 /* It's now safe to remove this processor from the online map */ 1461 lock_vector_lock(); 1462 remove_cpu_from_maps(cpu); 1463 unlock_vector_lock(); 1464 fixup_irqs(); 1465 lapic_offline(); 1466 } 1467 1468 int native_cpu_disable(void) 1469 { 1470 int ret; 1471 1472 ret = lapic_can_unplug_cpu(); 1473 if (ret) 1474 return ret; 1475 1476 cpu_disable_common(); 1477 1478 /* 1479 * Disable the local APIC. Otherwise IPI broadcasts will reach 1480 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1481 * messages. 1482 * 1483 * Disabling the APIC must happen after cpu_disable_common() 1484 * which invokes fixup_irqs(). 1485 * 1486 * Disabling the APIC preserves already set bits in IRR, but 1487 * an interrupt arriving after disabling the local APIC does not 1488 * set the corresponding IRR bit. 1489 * 1490 * fixup_irqs() scans IRR for set bits so it can raise a not 1491 * yet handled interrupt on the new destination CPU via an IPI 1492 * but obviously it can't do so for IRR bits which are not set. 1493 * IOW, interrupts arriving after disabling the local APIC will 1494 * be lost. 1495 */ 1496 apic_soft_disable(); 1497 1498 return 0; 1499 } 1500 1501 void play_dead_common(void) 1502 { 1503 idle_task_exit(); 1504 1505 cpuhp_ap_report_dead(); 1506 /* 1507 * With physical CPU hotplug, we should halt the cpu 1508 */ 1509 local_irq_disable(); 1510 } 1511 1512 /* 1513 * We need to flush the caches before going to sleep, lest we have 1514 * dirty data in our caches when we come back up. 1515 */ 1516 static inline void mwait_play_dead(void) 1517 { 1518 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1519 unsigned int eax, ebx, ecx, edx; 1520 unsigned int highest_cstate = 0; 1521 unsigned int highest_subcstate = 0; 1522 int i; 1523 1524 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1525 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1526 return; 1527 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1528 return; 1529 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1530 return; 1531 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1532 return; 1533 1534 eax = CPUID_MWAIT_LEAF; 1535 ecx = 0; 1536 native_cpuid(&eax, &ebx, &ecx, &edx); 1537 1538 /* 1539 * eax will be 0 if EDX enumeration is not valid. 1540 * Initialized below to cstate, sub_cstate value when EDX is valid. 1541 */ 1542 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1543 eax = 0; 1544 } else { 1545 edx >>= MWAIT_SUBSTATE_SIZE; 1546 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1547 if (edx & MWAIT_SUBSTATE_MASK) { 1548 highest_cstate = i; 1549 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1550 } 1551 } 1552 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1553 (highest_subcstate - 1); 1554 } 1555 1556 /* Set up state for the kexec() hack below */ 1557 md->status = CPUDEAD_MWAIT_WAIT; 1558 md->control = CPUDEAD_MWAIT_WAIT; 1559 1560 wbinvd(); 1561 1562 while (1) { 1563 /* 1564 * The CLFLUSH is a workaround for erratum AAI65 for 1565 * the Xeon 7400 series. It's not clear it is actually 1566 * needed, but it should be harmless in either case. 1567 * The WBINVD is insufficient due to the spurious-wakeup 1568 * case where we return around the loop. 1569 */ 1570 mb(); 1571 clflush(md); 1572 mb(); 1573 __monitor(md, 0, 0); 1574 mb(); 1575 __mwait(eax, 0); 1576 1577 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1578 /* 1579 * Kexec is about to happen. Don't go back into mwait() as 1580 * the kexec kernel might overwrite text and data including 1581 * page tables and stack. So mwait() would resume when the 1582 * monitor cache line is written to and then the CPU goes 1583 * south due to overwritten text, page tables and stack. 1584 * 1585 * Note: This does _NOT_ protect against a stray MCE, NMI, 1586 * SMI. They will resume execution at the instruction 1587 * following the HLT instruction and run into the problem 1588 * which this is trying to prevent. 1589 */ 1590 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1591 while(1) 1592 native_halt(); 1593 } 1594 } 1595 } 1596 1597 /* 1598 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1599 * mwait_play_dead(). 1600 */ 1601 void smp_kick_mwait_play_dead(void) 1602 { 1603 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1604 struct mwait_cpu_dead *md; 1605 unsigned int cpu, i; 1606 1607 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1608 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1609 1610 /* Does it sit in mwait_play_dead() ? */ 1611 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1612 continue; 1613 1614 /* Wait up to 5ms */ 1615 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1616 /* Bring it out of mwait */ 1617 WRITE_ONCE(md->control, newstate); 1618 udelay(5); 1619 } 1620 1621 if (READ_ONCE(md->status) != newstate) 1622 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1623 } 1624 } 1625 1626 void __noreturn hlt_play_dead(void) 1627 { 1628 if (__this_cpu_read(cpu_info.x86) >= 4) 1629 wbinvd(); 1630 1631 while (1) 1632 native_halt(); 1633 } 1634 1635 void native_play_dead(void) 1636 { 1637 play_dead_common(); 1638 tboot_shutdown(TB_SHUTDOWN_WFS); 1639 1640 mwait_play_dead(); 1641 if (cpuidle_play_dead()) 1642 hlt_play_dead(); 1643 } 1644 1645 #else /* ... !CONFIG_HOTPLUG_CPU */ 1646 int native_cpu_disable(void) 1647 { 1648 return -ENOSYS; 1649 } 1650 1651 void native_play_dead(void) 1652 { 1653 BUG(); 1654 } 1655 1656 #endif 1657