1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * x86 SMP booting functions 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * Copyright 2001 Andi Kleen, SuSE Labs. 8 * 9 * Much of the core SMP work is based on previous work by Thomas Radke, to 10 * whom a great many thanks are extended. 11 * 12 * Thanks to Intel for making available several different Pentium, 13 * Pentium Pro and Pentium-II/Xeon MP machines. 14 * Original development of Linux SMP code supported by Caldera. 15 * 16 * Fixes 17 * Felix Koop : NR_CPUS used properly 18 * Jose Renau : Handle single CPU case. 19 * Alan Cox : By repeated request 8) - Total BogoMIPS report. 20 * Greg Wright : Fix for kernel stacks panic. 21 * Erich Boleyn : MP v1.4 and additional changes. 22 * Matthias Sattler : Changes for 2.1 kernel map. 23 * Michel Lespinasse : Changes for 2.1 kernel map. 24 * Michael Chastain : Change trampoline.S to gnu as. 25 * Alan Cox : Dumb bug: 'B' step PPro's are fine 26 * Ingo Molnar : Added APIC timers, based on code 27 * from Jose Renau 28 * Ingo Molnar : various cleanups and rewrites 29 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. 30 * Maciej W. Rozycki : Bits for genuine 82489DX APICs 31 * Andi Kleen : Changed for SMP boot into long mode. 32 * Martin J. Bligh : Added support for multi-quad systems 33 * Dave Jones : Report invalid combinations of Athlon CPUs. 34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. 35 * Andi Kleen : Converted to new state machine. 36 * Ashok Raj : CPU hotplug support 37 * Glauber Costa : i386 and x86_64 integration 38 */ 39 40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 41 42 #include <linux/init.h> 43 #include <linux/smp.h> 44 #include <linux/export.h> 45 #include <linux/sched.h> 46 #include <linux/sched/topology.h> 47 #include <linux/sched/hotplug.h> 48 #include <linux/sched/task_stack.h> 49 #include <linux/percpu.h> 50 #include <linux/memblock.h> 51 #include <linux/err.h> 52 #include <linux/nmi.h> 53 #include <linux/tboot.h> 54 #include <linux/gfp.h> 55 #include <linux/cpuidle.h> 56 #include <linux/kexec.h> 57 #include <linux/numa.h> 58 #include <linux/pgtable.h> 59 #include <linux/overflow.h> 60 #include <linux/stackprotector.h> 61 #include <linux/cpuhotplug.h> 62 #include <linux/mc146818rtc.h> 63 64 #include <asm/acpi.h> 65 #include <asm/cacheinfo.h> 66 #include <asm/desc.h> 67 #include <asm/nmi.h> 68 #include <asm/irq.h> 69 #include <asm/realmode.h> 70 #include <asm/cpu.h> 71 #include <asm/numa.h> 72 #include <asm/tlbflush.h> 73 #include <asm/mtrr.h> 74 #include <asm/mwait.h> 75 #include <asm/apic.h> 76 #include <asm/io_apic.h> 77 #include <asm/fpu/api.h> 78 #include <asm/setup.h> 79 #include <asm/uv/uv.h> 80 #include <asm/microcode.h> 81 #include <asm/i8259.h> 82 #include <asm/misc.h> 83 #include <asm/qspinlock.h> 84 #include <asm/intel-family.h> 85 #include <asm/cpu_device_id.h> 86 #include <asm/spec-ctrl.h> 87 #include <asm/hw_irq.h> 88 #include <asm/stackprotector.h> 89 #include <asm/sev.h> 90 91 /* representing HT siblings of each logical CPU */ 92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); 93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); 94 95 /* representing HT and core siblings of each logical CPU */ 96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); 97 EXPORT_PER_CPU_SYMBOL(cpu_core_map); 98 99 /* representing HT, core, and die siblings of each logical CPU */ 100 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); 101 EXPORT_PER_CPU_SYMBOL(cpu_die_map); 102 103 /* Per CPU bogomips and other parameters */ 104 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); 105 EXPORT_PER_CPU_SYMBOL(cpu_info); 106 107 /* CPUs which are the primary SMT threads */ 108 struct cpumask __cpu_primary_thread_mask __read_mostly; 109 110 /* Representing CPUs for which sibling maps can be computed */ 111 static cpumask_var_t cpu_sibling_setup_mask; 112 113 struct mwait_cpu_dead { 114 unsigned int control; 115 unsigned int status; 116 }; 117 118 #define CPUDEAD_MWAIT_WAIT 0xDEADBEEF 119 #define CPUDEAD_MWAIT_KEXEC_HLT 0x4A17DEAD 120 121 /* 122 * Cache line aligned data for mwait_play_dead(). Separate on purpose so 123 * that it's unlikely to be touched by other CPUs. 124 */ 125 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead); 126 127 /* Logical package management. We might want to allocate that dynamically */ 128 unsigned int __max_logical_packages __read_mostly; 129 EXPORT_SYMBOL(__max_logical_packages); 130 static unsigned int logical_packages __read_mostly; 131 static unsigned int logical_die __read_mostly; 132 133 /* Maximum number of SMT threads on any online core */ 134 int __read_mostly __max_smt_threads = 1; 135 136 /* Flag to indicate if a complete sched domain rebuild is required */ 137 bool x86_topology_update; 138 139 int arch_update_cpu_topology(void) 140 { 141 int retval = x86_topology_update; 142 143 x86_topology_update = false; 144 return retval; 145 } 146 147 static unsigned int smpboot_warm_reset_vector_count; 148 149 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) 150 { 151 unsigned long flags; 152 153 spin_lock_irqsave(&rtc_lock, flags); 154 if (!smpboot_warm_reset_vector_count++) { 155 CMOS_WRITE(0xa, 0xf); 156 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4; 157 *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf; 158 } 159 spin_unlock_irqrestore(&rtc_lock, flags); 160 } 161 162 static inline void smpboot_restore_warm_reset_vector(void) 163 { 164 unsigned long flags; 165 166 /* 167 * Paranoid: Set warm reset code and vector here back 168 * to default values. 169 */ 170 spin_lock_irqsave(&rtc_lock, flags); 171 if (!--smpboot_warm_reset_vector_count) { 172 CMOS_WRITE(0, 0xf); 173 *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; 174 } 175 spin_unlock_irqrestore(&rtc_lock, flags); 176 177 } 178 179 /* Run the next set of setup steps for the upcoming CPU */ 180 static void ap_starting(void) 181 { 182 int cpuid = smp_processor_id(); 183 184 /* Mop up eventual mwait_play_dead() wreckage */ 185 this_cpu_write(mwait_cpu_dead.status, 0); 186 this_cpu_write(mwait_cpu_dead.control, 0); 187 188 /* 189 * If woken up by an INIT in an 82489DX configuration the alive 190 * synchronization guarantees that the CPU does not reach this 191 * point before an INIT_deassert IPI reaches the local APIC, so it 192 * is now safe to touch the local APIC. 193 * 194 * Set up this CPU, first the APIC, which is probably redundant on 195 * most boards. 196 */ 197 apic_ap_setup(); 198 199 /* Save the processor parameters. */ 200 smp_store_cpu_info(cpuid); 201 202 /* 203 * The topology information must be up to date before 204 * notify_cpu_starting(). 205 */ 206 set_cpu_sibling_map(cpuid); 207 208 ap_init_aperfmperf(); 209 210 pr_debug("Stack at about %p\n", &cpuid); 211 212 wmb(); 213 214 /* 215 * This runs the AP through all the cpuhp states to its target 216 * state CPUHP_ONLINE. 217 */ 218 notify_cpu_starting(cpuid); 219 } 220 221 static void ap_calibrate_delay(void) 222 { 223 /* 224 * Calibrate the delay loop and update loops_per_jiffy in cpu_data. 225 * smp_store_cpu_info() stored a value that is close but not as 226 * accurate as the value just calculated. 227 * 228 * As this is invoked after the TSC synchronization check, 229 * calibrate_delay_is_known() will skip the calibration routine 230 * when TSC is synchronized across sockets. 231 */ 232 calibrate_delay(); 233 cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy; 234 } 235 236 /* 237 * Activate a secondary processor. 238 */ 239 static void notrace start_secondary(void *unused) 240 { 241 /* 242 * Don't put *anything* except direct CPU state initialization 243 * before cpu_init(), SMP booting is too fragile that we want to 244 * limit the things done here to the most necessary things. 245 */ 246 cr4_init(); 247 248 /* 249 * 32-bit specific. 64-bit reaches this code with the correct page 250 * table established. Yet another historical divergence. 251 */ 252 if (IS_ENABLED(CONFIG_X86_32)) { 253 /* switch away from the initial page table */ 254 load_cr3(swapper_pg_dir); 255 __flush_tlb_all(); 256 } 257 258 cpu_init_exception_handling(); 259 260 /* 261 * 32-bit systems load the microcode from the ASM startup code for 262 * historical reasons. 263 * 264 * On 64-bit systems load it before reaching the AP alive 265 * synchronization point below so it is not part of the full per 266 * CPU serialized bringup part when "parallel" bringup is enabled. 267 * 268 * That's even safe when hyperthreading is enabled in the CPU as 269 * the core code starts the primary threads first and leaves the 270 * secondary threads waiting for SIPI. Loading microcode on 271 * physical cores concurrently is a safe operation. 272 * 273 * This covers both the Intel specific issue that concurrent 274 * microcode loading on SMT siblings must be prohibited and the 275 * vendor independent issue`that microcode loading which changes 276 * CPUID, MSRs etc. must be strictly serialized to maintain 277 * software state correctness. 278 */ 279 if (IS_ENABLED(CONFIG_X86_64)) 280 load_ucode_ap(); 281 282 /* 283 * Synchronization point with the hotplug core. Sets this CPUs 284 * synchronization state to ALIVE and spin-waits for the control CPU to 285 * release this CPU for further bringup. 286 */ 287 cpuhp_ap_sync_alive(); 288 289 cpu_init(); 290 fpu__init_cpu(); 291 rcu_cpu_starting(raw_smp_processor_id()); 292 x86_cpuinit.early_percpu_clock_init(); 293 294 ap_starting(); 295 296 /* Check TSC synchronization with the control CPU. */ 297 check_tsc_sync_target(); 298 299 /* 300 * Calibrate the delay loop after the TSC synchronization check. 301 * This allows to skip the calibration when TSC is synchronized 302 * across sockets. 303 */ 304 ap_calibrate_delay(); 305 306 speculative_store_bypass_ht_init(); 307 308 /* 309 * Lock vector_lock, set CPU online and bring the vector 310 * allocator online. Online must be set with vector_lock held 311 * to prevent a concurrent irq setup/teardown from seeing a 312 * half valid vector space. 313 */ 314 lock_vector_lock(); 315 set_cpu_online(smp_processor_id(), true); 316 lapic_online(); 317 unlock_vector_lock(); 318 x86_platform.nmi_init(); 319 320 /* enable local interrupts */ 321 local_irq_enable(); 322 323 x86_cpuinit.setup_percpu_clockev(); 324 325 wmb(); 326 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); 327 } 328 329 /** 330 * topology_phys_to_logical_pkg - Map a physical package id to a logical 331 * @phys_pkg: The physical package id to map 332 * 333 * Returns logical package id or -1 if not found 334 */ 335 int topology_phys_to_logical_pkg(unsigned int phys_pkg) 336 { 337 int cpu; 338 339 for_each_possible_cpu(cpu) { 340 struct cpuinfo_x86 *c = &cpu_data(cpu); 341 342 if (c->initialized && c->phys_proc_id == phys_pkg) 343 return c->logical_proc_id; 344 } 345 return -1; 346 } 347 EXPORT_SYMBOL(topology_phys_to_logical_pkg); 348 349 /** 350 * topology_phys_to_logical_die - Map a physical die id to logical 351 * @die_id: The physical die id to map 352 * @cur_cpu: The CPU for which the mapping is done 353 * 354 * Returns logical die id or -1 if not found 355 */ 356 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) 357 { 358 int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id; 359 360 for_each_possible_cpu(cpu) { 361 struct cpuinfo_x86 *c = &cpu_data(cpu); 362 363 if (c->initialized && c->cpu_die_id == die_id && 364 c->phys_proc_id == proc_id) 365 return c->logical_die_id; 366 } 367 return -1; 368 } 369 370 /** 371 * topology_update_package_map - Update the physical to logical package map 372 * @pkg: The physical package id as retrieved via CPUID 373 * @cpu: The cpu for which this is updated 374 */ 375 int topology_update_package_map(unsigned int pkg, unsigned int cpu) 376 { 377 int new; 378 379 /* Already available somewhere? */ 380 new = topology_phys_to_logical_pkg(pkg); 381 if (new >= 0) 382 goto found; 383 384 new = logical_packages++; 385 if (new != pkg) { 386 pr_info("CPU %u Converting physical %u to logical package %u\n", 387 cpu, pkg, new); 388 } 389 found: 390 cpu_data(cpu).logical_proc_id = new; 391 return 0; 392 } 393 /** 394 * topology_update_die_map - Update the physical to logical die map 395 * @die: The die id as retrieved via CPUID 396 * @cpu: The cpu for which this is updated 397 */ 398 int topology_update_die_map(unsigned int die, unsigned int cpu) 399 { 400 int new; 401 402 /* Already available somewhere? */ 403 new = topology_phys_to_logical_die(die, cpu); 404 if (new >= 0) 405 goto found; 406 407 new = logical_die++; 408 if (new != die) { 409 pr_info("CPU %u Converting physical %u to logical die %u\n", 410 cpu, die, new); 411 } 412 found: 413 cpu_data(cpu).logical_die_id = new; 414 return 0; 415 } 416 417 static void __init smp_store_boot_cpu_info(void) 418 { 419 int id = 0; /* CPU 0 */ 420 struct cpuinfo_x86 *c = &cpu_data(id); 421 422 *c = boot_cpu_data; 423 c->cpu_index = id; 424 topology_update_package_map(c->phys_proc_id, id); 425 topology_update_die_map(c->cpu_die_id, id); 426 c->initialized = true; 427 } 428 429 /* 430 * The bootstrap kernel entry code has set these up. Save them for 431 * a given CPU 432 */ 433 void smp_store_cpu_info(int id) 434 { 435 struct cpuinfo_x86 *c = &cpu_data(id); 436 437 /* Copy boot_cpu_data only on the first bringup */ 438 if (!c->initialized) 439 *c = boot_cpu_data; 440 c->cpu_index = id; 441 /* 442 * During boot time, CPU0 has this setup already. Save the info when 443 * bringing up an AP. 444 */ 445 identify_secondary_cpu(c); 446 c->initialized = true; 447 } 448 449 static bool 450 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 451 { 452 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 453 454 return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); 455 } 456 457 static bool 458 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) 459 { 460 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 461 462 return !WARN_ONCE(!topology_same_node(c, o), 463 "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " 464 "[node: %d != %d]. Ignoring dependency.\n", 465 cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); 466 } 467 468 #define link_mask(mfunc, c1, c2) \ 469 do { \ 470 cpumask_set_cpu((c1), mfunc(c2)); \ 471 cpumask_set_cpu((c2), mfunc(c1)); \ 472 } while (0) 473 474 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 475 { 476 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { 477 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 478 479 if (c->phys_proc_id == o->phys_proc_id && 480 c->cpu_die_id == o->cpu_die_id && 481 per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { 482 if (c->cpu_core_id == o->cpu_core_id) 483 return topology_sane(c, o, "smt"); 484 485 if ((c->cu_id != 0xff) && 486 (o->cu_id != 0xff) && 487 (c->cu_id == o->cu_id)) 488 return topology_sane(c, o, "smt"); 489 } 490 491 } else if (c->phys_proc_id == o->phys_proc_id && 492 c->cpu_die_id == o->cpu_die_id && 493 c->cpu_core_id == o->cpu_core_id) { 494 return topology_sane(c, o, "smt"); 495 } 496 497 return false; 498 } 499 500 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 501 { 502 if (c->phys_proc_id == o->phys_proc_id && 503 c->cpu_die_id == o->cpu_die_id) 504 return true; 505 return false; 506 } 507 508 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 509 { 510 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 511 512 /* If the arch didn't set up l2c_id, fall back to SMT */ 513 if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID) 514 return match_smt(c, o); 515 516 /* Do not match if L2 cache id does not match: */ 517 if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2)) 518 return false; 519 520 return topology_sane(c, o, "l2c"); 521 } 522 523 /* 524 * Unlike the other levels, we do not enforce keeping a 525 * multicore group inside a NUMA node. If this happens, we will 526 * discard the MC level of the topology later. 527 */ 528 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 529 { 530 if (c->phys_proc_id == o->phys_proc_id) 531 return true; 532 return false; 533 } 534 535 /* 536 * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs. 537 * 538 * Any Intel CPU that has multiple nodes per package and does not 539 * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology. 540 * 541 * When in SNC mode, these CPUs enumerate an LLC that is shared 542 * by multiple NUMA nodes. The LLC is shared for off-package data 543 * access but private to the NUMA node (half of the package) for 544 * on-package access. CPUID (the source of the information about 545 * the LLC) can only enumerate the cache as shared or unshared, 546 * but not this particular configuration. 547 */ 548 549 static const struct x86_cpu_id intel_cod_cpu[] = { 550 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0), /* COD */ 551 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0), /* COD */ 552 X86_MATCH_INTEL_FAM6_MODEL(ANY, 1), /* SNC */ 553 {} 554 }; 555 556 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) 557 { 558 const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu); 559 int cpu1 = c->cpu_index, cpu2 = o->cpu_index; 560 bool intel_snc = id && id->driver_data; 561 562 /* Do not match if we do not have a valid APICID for cpu: */ 563 if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) 564 return false; 565 566 /* Do not match if LLC id does not match: */ 567 if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) 568 return false; 569 570 /* 571 * Allow the SNC topology without warning. Return of false 572 * means 'c' does not share the LLC of 'o'. This will be 573 * reflected to userspace. 574 */ 575 if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc) 576 return false; 577 578 return topology_sane(c, o, "llc"); 579 } 580 581 582 #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_CLUSTER) || defined(CONFIG_SCHED_MC) 583 static inline int x86_sched_itmt_flags(void) 584 { 585 return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; 586 } 587 588 #ifdef CONFIG_SCHED_MC 589 static int x86_core_flags(void) 590 { 591 return cpu_core_flags() | x86_sched_itmt_flags(); 592 } 593 #endif 594 #ifdef CONFIG_SCHED_SMT 595 static int x86_smt_flags(void) 596 { 597 return cpu_smt_flags(); 598 } 599 #endif 600 #ifdef CONFIG_SCHED_CLUSTER 601 static int x86_cluster_flags(void) 602 { 603 return cpu_cluster_flags() | x86_sched_itmt_flags(); 604 } 605 #endif 606 #endif 607 608 /* 609 * Set if a package/die has multiple NUMA nodes inside. 610 * AMD Magny-Cours, Intel Cluster-on-Die, and Intel 611 * Sub-NUMA Clustering have this. 612 */ 613 static bool x86_has_numa_in_package; 614 615 static struct sched_domain_topology_level x86_topology[6]; 616 617 static void __init build_sched_topology(void) 618 { 619 int i = 0; 620 621 #ifdef CONFIG_SCHED_SMT 622 x86_topology[i++] = (struct sched_domain_topology_level){ 623 cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) 624 }; 625 #endif 626 #ifdef CONFIG_SCHED_CLUSTER 627 x86_topology[i++] = (struct sched_domain_topology_level){ 628 cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS) 629 }; 630 #endif 631 #ifdef CONFIG_SCHED_MC 632 x86_topology[i++] = (struct sched_domain_topology_level){ 633 cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) 634 }; 635 #endif 636 /* 637 * When there is NUMA topology inside the package skip the DIE domain 638 * since the NUMA domains will auto-magically create the right spanning 639 * domains based on the SLIT. 640 */ 641 if (!x86_has_numa_in_package) { 642 x86_topology[i++] = (struct sched_domain_topology_level){ 643 cpu_cpu_mask, SD_INIT_NAME(DIE) 644 }; 645 } 646 647 /* 648 * There must be one trailing NULL entry left. 649 */ 650 BUG_ON(i >= ARRAY_SIZE(x86_topology)-1); 651 652 set_sched_topology(x86_topology); 653 } 654 655 void set_cpu_sibling_map(int cpu) 656 { 657 bool has_smt = smp_num_siblings > 1; 658 bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; 659 struct cpuinfo_x86 *c = &cpu_data(cpu); 660 struct cpuinfo_x86 *o; 661 int i, threads; 662 663 cpumask_set_cpu(cpu, cpu_sibling_setup_mask); 664 665 if (!has_mp) { 666 cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); 667 cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); 668 cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu)); 669 cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); 670 cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); 671 c->booted_cores = 1; 672 return; 673 } 674 675 for_each_cpu(i, cpu_sibling_setup_mask) { 676 o = &cpu_data(i); 677 678 if (match_pkg(c, o) && !topology_same_node(c, o)) 679 x86_has_numa_in_package = true; 680 681 if ((i == cpu) || (has_smt && match_smt(c, o))) 682 link_mask(topology_sibling_cpumask, cpu, i); 683 684 if ((i == cpu) || (has_mp && match_llc(c, o))) 685 link_mask(cpu_llc_shared_mask, cpu, i); 686 687 if ((i == cpu) || (has_mp && match_l2c(c, o))) 688 link_mask(cpu_l2c_shared_mask, cpu, i); 689 690 if ((i == cpu) || (has_mp && match_die(c, o))) 691 link_mask(topology_die_cpumask, cpu, i); 692 } 693 694 threads = cpumask_weight(topology_sibling_cpumask(cpu)); 695 if (threads > __max_smt_threads) 696 __max_smt_threads = threads; 697 698 for_each_cpu(i, topology_sibling_cpumask(cpu)) 699 cpu_data(i).smt_active = threads > 1; 700 701 /* 702 * This needs a separate iteration over the cpus because we rely on all 703 * topology_sibling_cpumask links to be set-up. 704 */ 705 for_each_cpu(i, cpu_sibling_setup_mask) { 706 o = &cpu_data(i); 707 708 if ((i == cpu) || (has_mp && match_pkg(c, o))) { 709 link_mask(topology_core_cpumask, cpu, i); 710 711 /* 712 * Does this new cpu bringup a new core? 713 */ 714 if (threads == 1) { 715 /* 716 * for each core in package, increment 717 * the booted_cores for this new cpu 718 */ 719 if (cpumask_first( 720 topology_sibling_cpumask(i)) == i) 721 c->booted_cores++; 722 /* 723 * increment the core count for all 724 * the other cpus in this package 725 */ 726 if (i != cpu) 727 cpu_data(i).booted_cores++; 728 } else if (i != cpu && !c->booted_cores) 729 c->booted_cores = cpu_data(i).booted_cores; 730 } 731 } 732 } 733 734 /* maps the cpu to the sched domain representing multi-core */ 735 const struct cpumask *cpu_coregroup_mask(int cpu) 736 { 737 return cpu_llc_shared_mask(cpu); 738 } 739 740 const struct cpumask *cpu_clustergroup_mask(int cpu) 741 { 742 return cpu_l2c_shared_mask(cpu); 743 } 744 745 static void impress_friends(void) 746 { 747 int cpu; 748 unsigned long bogosum = 0; 749 /* 750 * Allow the user to impress friends. 751 */ 752 pr_debug("Before bogomips\n"); 753 for_each_online_cpu(cpu) 754 bogosum += cpu_data(cpu).loops_per_jiffy; 755 756 pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", 757 num_online_cpus(), 758 bogosum/(500000/HZ), 759 (bogosum/(5000/HZ))%100); 760 761 pr_debug("Before bogocount - setting activated=1\n"); 762 } 763 764 /* 765 * The Multiprocessor Specification 1.4 (1997) example code suggests 766 * that there should be a 10ms delay between the BSP asserting INIT 767 * and de-asserting INIT, when starting a remote processor. 768 * But that slows boot and resume on modern processors, which include 769 * many cores and don't require that delay. 770 * 771 * Cmdline "init_cpu_udelay=" is available to over-ride this delay. 772 * Modern processor families are quirked to remove the delay entirely. 773 */ 774 #define UDELAY_10MS_DEFAULT 10000 775 776 static unsigned int init_udelay = UINT_MAX; 777 778 static int __init cpu_init_udelay(char *str) 779 { 780 get_option(&str, &init_udelay); 781 782 return 0; 783 } 784 early_param("cpu_init_udelay", cpu_init_udelay); 785 786 static void __init smp_quirk_init_udelay(void) 787 { 788 /* if cmdline changed it from default, leave it alone */ 789 if (init_udelay != UINT_MAX) 790 return; 791 792 /* if modern processor, use no delay */ 793 if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || 794 ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || 795 ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { 796 init_udelay = 0; 797 return; 798 } 799 /* else, use legacy delay */ 800 init_udelay = UDELAY_10MS_DEFAULT; 801 } 802 803 /* 804 * Wake up AP by INIT, INIT, STARTUP sequence. 805 */ 806 static void send_init_sequence(int phys_apicid) 807 { 808 int maxlvt = lapic_get_maxlvt(); 809 810 /* Be paranoid about clearing APIC errors. */ 811 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 812 /* Due to the Pentium erratum 3AP. */ 813 if (maxlvt > 3) 814 apic_write(APIC_ESR, 0); 815 apic_read(APIC_ESR); 816 } 817 818 /* Assert INIT on the target CPU */ 819 apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); 820 safe_apic_wait_icr_idle(); 821 822 udelay(init_udelay); 823 824 /* Deassert INIT on the target CPU */ 825 apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); 826 safe_apic_wait_icr_idle(); 827 } 828 829 /* 830 * Wake up AP by INIT, INIT, STARTUP sequence. 831 */ 832 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) 833 { 834 unsigned long send_status = 0, accept_status = 0; 835 int num_starts, j, maxlvt; 836 837 preempt_disable(); 838 maxlvt = lapic_get_maxlvt(); 839 send_init_sequence(phys_apicid); 840 841 mb(); 842 843 /* 844 * Should we send STARTUP IPIs ? 845 * 846 * Determine this based on the APIC version. 847 * If we don't have an integrated APIC, don't send the STARTUP IPIs. 848 */ 849 if (APIC_INTEGRATED(boot_cpu_apic_version)) 850 num_starts = 2; 851 else 852 num_starts = 0; 853 854 /* 855 * Run STARTUP IPI loop. 856 */ 857 pr_debug("#startup loops: %d\n", num_starts); 858 859 for (j = 1; j <= num_starts; j++) { 860 pr_debug("Sending STARTUP #%d\n", j); 861 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 862 apic_write(APIC_ESR, 0); 863 apic_read(APIC_ESR); 864 pr_debug("After apic_write\n"); 865 866 /* 867 * STARTUP IPI 868 */ 869 870 /* Target chip */ 871 /* Boot on the stack */ 872 /* Kick the second */ 873 apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), 874 phys_apicid); 875 876 /* 877 * Give the other CPU some time to accept the IPI. 878 */ 879 if (init_udelay == 0) 880 udelay(10); 881 else 882 udelay(300); 883 884 pr_debug("Startup point 1\n"); 885 886 pr_debug("Waiting for send to finish...\n"); 887 send_status = safe_apic_wait_icr_idle(); 888 889 /* 890 * Give the other CPU some time to accept the IPI. 891 */ 892 if (init_udelay == 0) 893 udelay(10); 894 else 895 udelay(200); 896 897 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ 898 apic_write(APIC_ESR, 0); 899 accept_status = (apic_read(APIC_ESR) & 0xEF); 900 if (send_status || accept_status) 901 break; 902 } 903 pr_debug("After Startup\n"); 904 905 if (send_status) 906 pr_err("APIC never delivered???\n"); 907 if (accept_status) 908 pr_err("APIC delivery error (%lx)\n", accept_status); 909 910 preempt_enable(); 911 return (send_status | accept_status); 912 } 913 914 /* reduce the number of lines printed when booting a large cpu count system */ 915 static void announce_cpu(int cpu, int apicid) 916 { 917 static int width, node_width, first = 1; 918 static int current_node = NUMA_NO_NODE; 919 int node = early_cpu_to_node(cpu); 920 921 if (!width) 922 width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ 923 924 if (!node_width) 925 node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ 926 927 if (system_state < SYSTEM_RUNNING) { 928 if (first) 929 pr_info("x86: Booting SMP configuration:\n"); 930 931 if (node != current_node) { 932 if (current_node > (-1)) 933 pr_cont("\n"); 934 current_node = node; 935 936 printk(KERN_INFO ".... node %*s#%d, CPUs: ", 937 node_width - num_digits(node), " ", node); 938 } 939 940 /* Add padding for the BSP */ 941 if (first) 942 pr_cont("%*s", width + 1, " "); 943 first = 0; 944 945 pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); 946 } else 947 pr_info("Booting Node %d Processor %d APIC 0x%x\n", 948 node, cpu, apicid); 949 } 950 951 int common_cpu_up(unsigned int cpu, struct task_struct *idle) 952 { 953 int ret; 954 955 /* Just in case we booted with a single CPU. */ 956 alternatives_enable_smp(); 957 958 per_cpu(pcpu_hot.current_task, cpu) = idle; 959 cpu_init_stack_canary(cpu, idle); 960 961 /* Initialize the interrupt stack(s) */ 962 ret = irq_init_percpu_irqstack(cpu); 963 if (ret) 964 return ret; 965 966 #ifdef CONFIG_X86_32 967 /* Stack for startup_32 can be just as for start_secondary onwards */ 968 per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle); 969 #endif 970 return 0; 971 } 972 973 /* 974 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad 975 * (ie clustered apic addressing mode), this is a LOGICAL apic ID. 976 * Returns zero if startup was successfully sent, else error code from 977 * ->wakeup_secondary_cpu. 978 */ 979 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle) 980 { 981 unsigned long start_ip = real_mode_header->trampoline_start; 982 int ret; 983 984 #ifdef CONFIG_X86_64 985 /* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */ 986 if (apic->wakeup_secondary_cpu_64) 987 start_ip = real_mode_header->trampoline_start64; 988 #endif 989 idle->thread.sp = (unsigned long)task_pt_regs(idle); 990 initial_code = (unsigned long)start_secondary; 991 992 if (IS_ENABLED(CONFIG_X86_32)) { 993 early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); 994 initial_stack = idle->thread.sp; 995 } else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) { 996 smpboot_control = cpu; 997 } 998 999 /* Enable the espfix hack for this CPU */ 1000 init_espfix_ap(cpu); 1001 1002 /* So we see what's up */ 1003 announce_cpu(cpu, apicid); 1004 1005 /* 1006 * This grunge runs the startup process for 1007 * the targeted processor. 1008 */ 1009 if (x86_platform.legacy.warm_reset) { 1010 1011 pr_debug("Setting warm reset code and vector.\n"); 1012 1013 smpboot_setup_warm_reset_vector(start_ip); 1014 /* 1015 * Be paranoid about clearing APIC errors. 1016 */ 1017 if (APIC_INTEGRATED(boot_cpu_apic_version)) { 1018 apic_write(APIC_ESR, 0); 1019 apic_read(APIC_ESR); 1020 } 1021 } 1022 1023 smp_mb(); 1024 1025 /* 1026 * Wake up a CPU in difference cases: 1027 * - Use a method from the APIC driver if one defined, with wakeup 1028 * straight to 64-bit mode preferred over wakeup to RM. 1029 * Otherwise, 1030 * - Use an INIT boot APIC message 1031 */ 1032 if (apic->wakeup_secondary_cpu_64) 1033 ret = apic->wakeup_secondary_cpu_64(apicid, start_ip); 1034 else if (apic->wakeup_secondary_cpu) 1035 ret = apic->wakeup_secondary_cpu(apicid, start_ip); 1036 else 1037 ret = wakeup_secondary_cpu_via_init(apicid, start_ip); 1038 1039 /* If the wakeup mechanism failed, cleanup the warm reset vector */ 1040 if (ret) 1041 arch_cpuhp_cleanup_kick_cpu(cpu); 1042 return ret; 1043 } 1044 1045 int native_kick_ap(unsigned int cpu, struct task_struct *tidle) 1046 { 1047 int apicid = apic->cpu_present_to_apicid(cpu); 1048 int err; 1049 1050 lockdep_assert_irqs_enabled(); 1051 1052 pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); 1053 1054 if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) || 1055 !apic_id_valid(apicid)) { 1056 pr_err("%s: bad cpu %d\n", __func__, cpu); 1057 return -EINVAL; 1058 } 1059 1060 /* 1061 * Save current MTRR state in case it was changed since early boot 1062 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: 1063 */ 1064 mtrr_save_state(); 1065 1066 /* the FPU context is blank, nobody can own it */ 1067 per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; 1068 1069 err = common_cpu_up(cpu, tidle); 1070 if (err) 1071 return err; 1072 1073 err = do_boot_cpu(apicid, cpu, tidle); 1074 if (err) 1075 pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); 1076 1077 return err; 1078 } 1079 1080 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle) 1081 { 1082 return smp_ops.kick_ap_alive(cpu, tidle); 1083 } 1084 1085 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu) 1086 { 1087 /* Cleanup possible dangling ends... */ 1088 if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset) 1089 smpboot_restore_warm_reset_vector(); 1090 } 1091 1092 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu) 1093 { 1094 if (smp_ops.cleanup_dead_cpu) 1095 smp_ops.cleanup_dead_cpu(cpu); 1096 1097 if (system_state == SYSTEM_RUNNING) 1098 pr_info("CPU %u is now offline\n", cpu); 1099 } 1100 1101 void arch_cpuhp_sync_state_poll(void) 1102 { 1103 if (smp_ops.poll_sync_state) 1104 smp_ops.poll_sync_state(); 1105 } 1106 1107 /** 1108 * arch_disable_smp_support() - Disables SMP support for x86 at boottime 1109 */ 1110 void __init arch_disable_smp_support(void) 1111 { 1112 disable_ioapic_support(); 1113 } 1114 1115 /* 1116 * Fall back to non SMP mode after errors. 1117 * 1118 * RED-PEN audit/test this more. I bet there is more state messed up here. 1119 */ 1120 static __init void disable_smp(void) 1121 { 1122 pr_info("SMP disabled\n"); 1123 1124 disable_ioapic_support(); 1125 1126 init_cpu_present(cpumask_of(0)); 1127 init_cpu_possible(cpumask_of(0)); 1128 1129 if (smp_found_config) 1130 physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); 1131 else 1132 physid_set_mask_of_physid(0, &phys_cpu_present_map); 1133 cpumask_set_cpu(0, topology_sibling_cpumask(0)); 1134 cpumask_set_cpu(0, topology_core_cpumask(0)); 1135 cpumask_set_cpu(0, topology_die_cpumask(0)); 1136 } 1137 1138 static void __init smp_cpu_index_default(void) 1139 { 1140 int i; 1141 struct cpuinfo_x86 *c; 1142 1143 for_each_possible_cpu(i) { 1144 c = &cpu_data(i); 1145 /* mark all to hotplug */ 1146 c->cpu_index = nr_cpu_ids; 1147 } 1148 } 1149 1150 void __init smp_prepare_cpus_common(void) 1151 { 1152 unsigned int i; 1153 1154 smp_cpu_index_default(); 1155 1156 /* 1157 * Setup boot CPU information 1158 */ 1159 smp_store_boot_cpu_info(); /* Final full version of the data */ 1160 mb(); 1161 1162 for_each_possible_cpu(i) { 1163 zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); 1164 zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); 1165 zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); 1166 zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); 1167 zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL); 1168 } 1169 1170 set_cpu_sibling_map(0); 1171 } 1172 1173 #ifdef CONFIG_X86_64 1174 /* Establish whether parallel bringup can be supported. */ 1175 bool __init arch_cpuhp_init_parallel_bringup(void) 1176 { 1177 if (!x86_cpuinit.parallel_bringup) { 1178 pr_info("Parallel CPU startup disabled by the platform\n"); 1179 return false; 1180 } 1181 1182 smpboot_control = STARTUP_READ_APICID; 1183 pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control); 1184 return true; 1185 } 1186 #endif 1187 1188 /* 1189 * Prepare for SMP bootup. 1190 * @max_cpus: configured maximum number of CPUs, It is a legacy parameter 1191 * for common interface support. 1192 */ 1193 void __init native_smp_prepare_cpus(unsigned int max_cpus) 1194 { 1195 smp_prepare_cpus_common(); 1196 1197 switch (apic_intr_mode) { 1198 case APIC_PIC: 1199 case APIC_VIRTUAL_WIRE_NO_CONFIG: 1200 disable_smp(); 1201 return; 1202 case APIC_SYMMETRIC_IO_NO_ROUTING: 1203 disable_smp(); 1204 /* Setup local timer */ 1205 x86_init.timers.setup_percpu_clockev(); 1206 return; 1207 case APIC_VIRTUAL_WIRE: 1208 case APIC_SYMMETRIC_IO: 1209 break; 1210 } 1211 1212 /* Setup local timer */ 1213 x86_init.timers.setup_percpu_clockev(); 1214 1215 pr_info("CPU0: "); 1216 print_cpu_info(&cpu_data(0)); 1217 1218 uv_system_init(); 1219 1220 smp_quirk_init_udelay(); 1221 1222 speculative_store_bypass_ht_init(); 1223 1224 snp_set_wakeup_secondary_cpu(); 1225 } 1226 1227 void arch_thaw_secondary_cpus_begin(void) 1228 { 1229 set_cache_aps_delayed_init(true); 1230 } 1231 1232 void arch_thaw_secondary_cpus_end(void) 1233 { 1234 cache_aps_init(); 1235 } 1236 1237 bool smp_park_other_cpus_in_init(void) 1238 { 1239 unsigned int cpu, this_cpu = smp_processor_id(); 1240 unsigned int apicid; 1241 1242 if (apic->wakeup_secondary_cpu_64 || apic->wakeup_secondary_cpu) 1243 return false; 1244 1245 /* 1246 * If this is a crash stop which does not execute on the boot CPU, 1247 * then this cannot use the INIT mechanism because INIT to the boot 1248 * CPU will reset the machine. 1249 */ 1250 if (this_cpu) 1251 return false; 1252 1253 for_each_cpu_and(cpu, &cpus_booted_once_mask, cpu_present_mask) { 1254 if (cpu == this_cpu) 1255 continue; 1256 apicid = apic->cpu_present_to_apicid(cpu); 1257 if (apicid == BAD_APICID) 1258 continue; 1259 send_init_sequence(apicid); 1260 } 1261 return true; 1262 } 1263 1264 /* 1265 * Early setup to make printk work. 1266 */ 1267 void __init native_smp_prepare_boot_cpu(void) 1268 { 1269 int me = smp_processor_id(); 1270 1271 /* SMP handles this from setup_per_cpu_areas() */ 1272 if (!IS_ENABLED(CONFIG_SMP)) 1273 switch_gdt_and_percpu_base(me); 1274 1275 native_pv_lock_init(); 1276 } 1277 1278 void __init calculate_max_logical_packages(void) 1279 { 1280 int ncpus; 1281 1282 /* 1283 * Today neither Intel nor AMD support heterogeneous systems so 1284 * extrapolate the boot cpu's data to all packages. 1285 */ 1286 ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); 1287 __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); 1288 pr_info("Max logical packages: %u\n", __max_logical_packages); 1289 } 1290 1291 void __init native_smp_cpus_done(unsigned int max_cpus) 1292 { 1293 pr_debug("Boot done\n"); 1294 1295 calculate_max_logical_packages(); 1296 build_sched_topology(); 1297 nmi_selftest(); 1298 impress_friends(); 1299 cache_aps_init(); 1300 } 1301 1302 static int __initdata setup_possible_cpus = -1; 1303 static int __init _setup_possible_cpus(char *str) 1304 { 1305 get_option(&str, &setup_possible_cpus); 1306 return 0; 1307 } 1308 early_param("possible_cpus", _setup_possible_cpus); 1309 1310 1311 /* 1312 * cpu_possible_mask should be static, it cannot change as cpu's 1313 * are onlined, or offlined. The reason is per-cpu data-structures 1314 * are allocated by some modules at init time, and don't expect to 1315 * do this dynamically on cpu arrival/departure. 1316 * cpu_present_mask on the other hand can change dynamically. 1317 * In case when cpu_hotplug is not compiled, then we resort to current 1318 * behaviour, which is cpu_possible == cpu_present. 1319 * - Ashok Raj 1320 * 1321 * Three ways to find out the number of additional hotplug CPUs: 1322 * - If the BIOS specified disabled CPUs in ACPI/mptables use that. 1323 * - The user can overwrite it with possible_cpus=NUM 1324 * - Otherwise don't reserve additional CPUs. 1325 * We do this because additional CPUs waste a lot of memory. 1326 * -AK 1327 */ 1328 __init void prefill_possible_map(void) 1329 { 1330 int i, possible; 1331 1332 i = setup_max_cpus ?: 1; 1333 if (setup_possible_cpus == -1) { 1334 possible = num_processors; 1335 #ifdef CONFIG_HOTPLUG_CPU 1336 if (setup_max_cpus) 1337 possible += disabled_cpus; 1338 #else 1339 if (possible > i) 1340 possible = i; 1341 #endif 1342 } else 1343 possible = setup_possible_cpus; 1344 1345 total_cpus = max_t(int, possible, num_processors + disabled_cpus); 1346 1347 /* nr_cpu_ids could be reduced via nr_cpus= */ 1348 if (possible > nr_cpu_ids) { 1349 pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", 1350 possible, nr_cpu_ids); 1351 possible = nr_cpu_ids; 1352 } 1353 1354 #ifdef CONFIG_HOTPLUG_CPU 1355 if (!setup_max_cpus) 1356 #endif 1357 if (possible > i) { 1358 pr_warn("%d Processors exceeds max_cpus limit of %u\n", 1359 possible, setup_max_cpus); 1360 possible = i; 1361 } 1362 1363 set_nr_cpu_ids(possible); 1364 1365 pr_info("Allowing %d CPUs, %d hotplug CPUs\n", 1366 possible, max_t(int, possible - num_processors, 0)); 1367 1368 reset_cpu_possible_mask(); 1369 1370 for (i = 0; i < possible; i++) 1371 set_cpu_possible(i, true); 1372 } 1373 1374 /* correctly size the local cpu masks */ 1375 void __init setup_cpu_local_masks(void) 1376 { 1377 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask); 1378 } 1379 1380 #ifdef CONFIG_HOTPLUG_CPU 1381 1382 /* Recompute SMT state for all CPUs on offline */ 1383 static void recompute_smt_state(void) 1384 { 1385 int max_threads, cpu; 1386 1387 max_threads = 0; 1388 for_each_online_cpu (cpu) { 1389 int threads = cpumask_weight(topology_sibling_cpumask(cpu)); 1390 1391 if (threads > max_threads) 1392 max_threads = threads; 1393 } 1394 __max_smt_threads = max_threads; 1395 } 1396 1397 static void remove_siblinginfo(int cpu) 1398 { 1399 int sibling; 1400 struct cpuinfo_x86 *c = &cpu_data(cpu); 1401 1402 for_each_cpu(sibling, topology_core_cpumask(cpu)) { 1403 cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); 1404 /*/ 1405 * last thread sibling in this cpu core going down 1406 */ 1407 if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) 1408 cpu_data(sibling).booted_cores--; 1409 } 1410 1411 for_each_cpu(sibling, topology_die_cpumask(cpu)) 1412 cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); 1413 1414 for_each_cpu(sibling, topology_sibling_cpumask(cpu)) { 1415 cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); 1416 if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1) 1417 cpu_data(sibling).smt_active = false; 1418 } 1419 1420 for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) 1421 cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); 1422 for_each_cpu(sibling, cpu_l2c_shared_mask(cpu)) 1423 cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling)); 1424 cpumask_clear(cpu_llc_shared_mask(cpu)); 1425 cpumask_clear(cpu_l2c_shared_mask(cpu)); 1426 cpumask_clear(topology_sibling_cpumask(cpu)); 1427 cpumask_clear(topology_core_cpumask(cpu)); 1428 cpumask_clear(topology_die_cpumask(cpu)); 1429 c->cpu_core_id = 0; 1430 c->booted_cores = 0; 1431 cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); 1432 recompute_smt_state(); 1433 } 1434 1435 static void remove_cpu_from_maps(int cpu) 1436 { 1437 set_cpu_online(cpu, false); 1438 numa_remove_cpu(cpu); 1439 } 1440 1441 void cpu_disable_common(void) 1442 { 1443 int cpu = smp_processor_id(); 1444 1445 remove_siblinginfo(cpu); 1446 1447 /* It's now safe to remove this processor from the online map */ 1448 lock_vector_lock(); 1449 remove_cpu_from_maps(cpu); 1450 unlock_vector_lock(); 1451 fixup_irqs(); 1452 lapic_offline(); 1453 } 1454 1455 int native_cpu_disable(void) 1456 { 1457 int ret; 1458 1459 ret = lapic_can_unplug_cpu(); 1460 if (ret) 1461 return ret; 1462 1463 cpu_disable_common(); 1464 1465 /* 1466 * Disable the local APIC. Otherwise IPI broadcasts will reach 1467 * it. It still responds normally to INIT, NMI, SMI, and SIPI 1468 * messages. 1469 * 1470 * Disabling the APIC must happen after cpu_disable_common() 1471 * which invokes fixup_irqs(). 1472 * 1473 * Disabling the APIC preserves already set bits in IRR, but 1474 * an interrupt arriving after disabling the local APIC does not 1475 * set the corresponding IRR bit. 1476 * 1477 * fixup_irqs() scans IRR for set bits so it can raise a not 1478 * yet handled interrupt on the new destination CPU via an IPI 1479 * but obviously it can't do so for IRR bits which are not set. 1480 * IOW, interrupts arriving after disabling the local APIC will 1481 * be lost. 1482 */ 1483 apic_soft_disable(); 1484 1485 return 0; 1486 } 1487 1488 void play_dead_common(void) 1489 { 1490 idle_task_exit(); 1491 1492 cpuhp_ap_report_dead(); 1493 1494 local_irq_disable(); 1495 } 1496 1497 /* 1498 * We need to flush the caches before going to sleep, lest we have 1499 * dirty data in our caches when we come back up. 1500 */ 1501 static inline void mwait_play_dead(void) 1502 { 1503 struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead); 1504 unsigned int eax, ebx, ecx, edx; 1505 unsigned int highest_cstate = 0; 1506 unsigned int highest_subcstate = 0; 1507 int i; 1508 1509 if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || 1510 boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) 1511 return; 1512 if (!this_cpu_has(X86_FEATURE_MWAIT)) 1513 return; 1514 if (!this_cpu_has(X86_FEATURE_CLFLUSH)) 1515 return; 1516 if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) 1517 return; 1518 1519 eax = CPUID_MWAIT_LEAF; 1520 ecx = 0; 1521 native_cpuid(&eax, &ebx, &ecx, &edx); 1522 1523 /* 1524 * eax will be 0 if EDX enumeration is not valid. 1525 * Initialized below to cstate, sub_cstate value when EDX is valid. 1526 */ 1527 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { 1528 eax = 0; 1529 } else { 1530 edx >>= MWAIT_SUBSTATE_SIZE; 1531 for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { 1532 if (edx & MWAIT_SUBSTATE_MASK) { 1533 highest_cstate = i; 1534 highest_subcstate = edx & MWAIT_SUBSTATE_MASK; 1535 } 1536 } 1537 eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | 1538 (highest_subcstate - 1); 1539 } 1540 1541 /* Set up state for the kexec() hack below */ 1542 md->status = CPUDEAD_MWAIT_WAIT; 1543 md->control = CPUDEAD_MWAIT_WAIT; 1544 1545 wbinvd(); 1546 1547 while (1) { 1548 /* 1549 * The CLFLUSH is a workaround for erratum AAI65 for 1550 * the Xeon 7400 series. It's not clear it is actually 1551 * needed, but it should be harmless in either case. 1552 * The WBINVD is insufficient due to the spurious-wakeup 1553 * case where we return around the loop. 1554 */ 1555 mb(); 1556 clflush(md); 1557 mb(); 1558 __monitor(md, 0, 0); 1559 mb(); 1560 __mwait(eax, 0); 1561 1562 if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) { 1563 /* 1564 * Kexec is about to happen. Don't go back into mwait() as 1565 * the kexec kernel might overwrite text and data including 1566 * page tables and stack. So mwait() would resume when the 1567 * monitor cache line is written to and then the CPU goes 1568 * south due to overwritten text, page tables and stack. 1569 * 1570 * Note: This does _NOT_ protect against a stray MCE, NMI, 1571 * SMI. They will resume execution at the instruction 1572 * following the HLT instruction and run into the problem 1573 * which this is trying to prevent. 1574 */ 1575 WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT); 1576 while(1) 1577 native_halt(); 1578 } 1579 } 1580 } 1581 1582 /* 1583 * Kick all "offline" CPUs out of mwait on kexec(). See comment in 1584 * mwait_play_dead(). 1585 */ 1586 void smp_kick_mwait_play_dead(void) 1587 { 1588 u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT; 1589 struct mwait_cpu_dead *md; 1590 unsigned int cpu, i; 1591 1592 for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) { 1593 md = per_cpu_ptr(&mwait_cpu_dead, cpu); 1594 1595 /* Does it sit in mwait_play_dead() ? */ 1596 if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT) 1597 continue; 1598 1599 /* Wait up to 5ms */ 1600 for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) { 1601 /* Bring it out of mwait */ 1602 WRITE_ONCE(md->control, newstate); 1603 udelay(5); 1604 } 1605 1606 if (READ_ONCE(md->status) != newstate) 1607 pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu); 1608 } 1609 } 1610 1611 void __noreturn hlt_play_dead(void) 1612 { 1613 if (__this_cpu_read(cpu_info.x86) >= 4) 1614 wbinvd(); 1615 1616 while (1) 1617 native_halt(); 1618 } 1619 1620 void native_play_dead(void) 1621 { 1622 play_dead_common(); 1623 tboot_shutdown(TB_SHUTDOWN_WFS); 1624 1625 mwait_play_dead(); 1626 if (cpuidle_play_dead()) 1627 hlt_play_dead(); 1628 } 1629 1630 #else /* ... !CONFIG_HOTPLUG_CPU */ 1631 int native_cpu_disable(void) 1632 { 1633 return -ENOSYS; 1634 } 1635 1636 void native_play_dead(void) 1637 { 1638 BUG(); 1639 } 1640 1641 #endif 1642