xref: /openbmc/linux/arch/x86/kernel/smpboot.c (revision fbe1bf1e)
1 // SPDX-License-Identifier: GPL-2.0-or-later
2  /*
3  *	x86 SMP booting functions
4  *
5  *	(c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk>
6  *	(c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com>
7  *	Copyright 2001 Andi Kleen, SuSE Labs.
8  *
9  *	Much of the core SMP work is based on previous work by Thomas Radke, to
10  *	whom a great many thanks are extended.
11  *
12  *	Thanks to Intel for making available several different Pentium,
13  *	Pentium Pro and Pentium-II/Xeon MP machines.
14  *	Original development of Linux SMP code supported by Caldera.
15  *
16  *	Fixes
17  *		Felix Koop	:	NR_CPUS used properly
18  *		Jose Renau	:	Handle single CPU case.
19  *		Alan Cox	:	By repeated request 8) - Total BogoMIPS report.
20  *		Greg Wright	:	Fix for kernel stacks panic.
21  *		Erich Boleyn	:	MP v1.4 and additional changes.
22  *	Matthias Sattler	:	Changes for 2.1 kernel map.
23  *	Michel Lespinasse	:	Changes for 2.1 kernel map.
24  *	Michael Chastain	:	Change trampoline.S to gnu as.
25  *		Alan Cox	:	Dumb bug: 'B' step PPro's are fine
26  *		Ingo Molnar	:	Added APIC timers, based on code
27  *					from Jose Renau
28  *		Ingo Molnar	:	various cleanups and rewrites
29  *		Tigran Aivazian	:	fixed "0.00 in /proc/uptime on SMP" bug.
30  *	Maciej W. Rozycki	:	Bits for genuine 82489DX APICs
31  *	Andi Kleen		:	Changed for SMP boot into long mode.
32  *		Martin J. Bligh	: 	Added support for multi-quad systems
33  *		Dave Jones	:	Report invalid combinations of Athlon CPUs.
34  *		Rusty Russell	:	Hacked into shape for new "hotplug" boot process.
35  *      Andi Kleen              :       Converted to new state machine.
36  *	Ashok Raj		: 	CPU hotplug support
37  *	Glauber Costa		:	i386 and x86_64 integration
38  */
39 
40 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
41 
42 #include <linux/init.h>
43 #include <linux/smp.h>
44 #include <linux/export.h>
45 #include <linux/sched.h>
46 #include <linux/sched/topology.h>
47 #include <linux/sched/hotplug.h>
48 #include <linux/sched/task_stack.h>
49 #include <linux/percpu.h>
50 #include <linux/memblock.h>
51 #include <linux/err.h>
52 #include <linux/nmi.h>
53 #include <linux/tboot.h>
54 #include <linux/gfp.h>
55 #include <linux/cpuidle.h>
56 #include <linux/kexec.h>
57 #include <linux/numa.h>
58 #include <linux/pgtable.h>
59 #include <linux/overflow.h>
60 #include <linux/stackprotector.h>
61 #include <linux/cpuhotplug.h>
62 #include <linux/mc146818rtc.h>
63 
64 #include <asm/acpi.h>
65 #include <asm/cacheinfo.h>
66 #include <asm/desc.h>
67 #include <asm/nmi.h>
68 #include <asm/irq.h>
69 #include <asm/realmode.h>
70 #include <asm/cpu.h>
71 #include <asm/numa.h>
72 #include <asm/tlbflush.h>
73 #include <asm/mtrr.h>
74 #include <asm/mwait.h>
75 #include <asm/apic.h>
76 #include <asm/io_apic.h>
77 #include <asm/fpu/api.h>
78 #include <asm/setup.h>
79 #include <asm/uv/uv.h>
80 #include <asm/microcode.h>
81 #include <asm/i8259.h>
82 #include <asm/misc.h>
83 #include <asm/qspinlock.h>
84 #include <asm/intel-family.h>
85 #include <asm/cpu_device_id.h>
86 #include <asm/spec-ctrl.h>
87 #include <asm/hw_irq.h>
88 #include <asm/stackprotector.h>
89 #include <asm/sev.h>
90 
91 /* representing HT siblings of each logical CPU */
92 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map);
93 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
94 
95 /* representing HT and core siblings of each logical CPU */
96 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map);
97 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
98 
99 /* representing HT, core, and die siblings of each logical CPU */
100 DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map);
101 EXPORT_PER_CPU_SYMBOL(cpu_die_map);
102 
103 /* Per CPU bogomips and other parameters */
104 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
105 EXPORT_PER_CPU_SYMBOL(cpu_info);
106 
107 /* CPUs which are the primary SMT threads */
108 struct cpumask __cpu_primary_thread_mask __read_mostly;
109 
110 /* Representing CPUs for which sibling maps can be computed */
111 static cpumask_var_t cpu_sibling_setup_mask;
112 
113 struct mwait_cpu_dead {
114 	unsigned int	control;
115 	unsigned int	status;
116 };
117 
118 #define CPUDEAD_MWAIT_WAIT	0xDEADBEEF
119 #define CPUDEAD_MWAIT_KEXEC_HLT	0x4A17DEAD
120 
121 /*
122  * Cache line aligned data for mwait_play_dead(). Separate on purpose so
123  * that it's unlikely to be touched by other CPUs.
124  */
125 static DEFINE_PER_CPU_ALIGNED(struct mwait_cpu_dead, mwait_cpu_dead);
126 
127 /* Logical package management. We might want to allocate that dynamically */
128 unsigned int __max_logical_packages __read_mostly;
129 EXPORT_SYMBOL(__max_logical_packages);
130 static unsigned int logical_packages __read_mostly;
131 static unsigned int logical_die __read_mostly;
132 
133 /* Maximum number of SMT threads on any online core */
134 int __read_mostly __max_smt_threads = 1;
135 
136 /* Flag to indicate if a complete sched domain rebuild is required */
137 bool x86_topology_update;
138 
139 int arch_update_cpu_topology(void)
140 {
141 	int retval = x86_topology_update;
142 
143 	x86_topology_update = false;
144 	return retval;
145 }
146 
147 static unsigned int smpboot_warm_reset_vector_count;
148 
149 static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip)
150 {
151 	unsigned long flags;
152 
153 	spin_lock_irqsave(&rtc_lock, flags);
154 	if (!smpboot_warm_reset_vector_count++) {
155 		CMOS_WRITE(0xa, 0xf);
156 		*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = start_eip >> 4;
157 		*((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = start_eip & 0xf;
158 	}
159 	spin_unlock_irqrestore(&rtc_lock, flags);
160 }
161 
162 static inline void smpboot_restore_warm_reset_vector(void)
163 {
164 	unsigned long flags;
165 
166 	/*
167 	 * Paranoid:  Set warm reset code and vector here back
168 	 * to default values.
169 	 */
170 	spin_lock_irqsave(&rtc_lock, flags);
171 	if (!--smpboot_warm_reset_vector_count) {
172 		CMOS_WRITE(0, 0xf);
173 		*((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0;
174 	}
175 	spin_unlock_irqrestore(&rtc_lock, flags);
176 
177 }
178 
179 /* Run the next set of setup steps for the upcoming CPU */
180 static void ap_starting(void)
181 {
182 	int cpuid = smp_processor_id();
183 
184 	/* Mop up eventual mwait_play_dead() wreckage */
185 	this_cpu_write(mwait_cpu_dead.status, 0);
186 	this_cpu_write(mwait_cpu_dead.control, 0);
187 
188 	/*
189 	 * If woken up by an INIT in an 82489DX configuration the alive
190 	 * synchronization guarantees that the CPU does not reach this
191 	 * point before an INIT_deassert IPI reaches the local APIC, so it
192 	 * is now safe to touch the local APIC.
193 	 *
194 	 * Set up this CPU, first the APIC, which is probably redundant on
195 	 * most boards.
196 	 */
197 	apic_ap_setup();
198 
199 	/* Save the processor parameters. */
200 	smp_store_cpu_info(cpuid);
201 
202 	/*
203 	 * The topology information must be up to date before
204 	 * notify_cpu_starting().
205 	 */
206 	set_cpu_sibling_map(cpuid);
207 
208 	ap_init_aperfmperf();
209 
210 	pr_debug("Stack at about %p\n", &cpuid);
211 
212 	wmb();
213 
214 	/*
215 	 * This runs the AP through all the cpuhp states to its target
216 	 * state CPUHP_ONLINE.
217 	 */
218 	notify_cpu_starting(cpuid);
219 }
220 
221 static void ap_calibrate_delay(void)
222 {
223 	/*
224 	 * Calibrate the delay loop and update loops_per_jiffy in cpu_data.
225 	 * smp_store_cpu_info() stored a value that is close but not as
226 	 * accurate as the value just calculated.
227 	 *
228 	 * As this is invoked after the TSC synchronization check,
229 	 * calibrate_delay_is_known() will skip the calibration routine
230 	 * when TSC is synchronized across sockets.
231 	 */
232 	calibrate_delay();
233 	cpu_data(smp_processor_id()).loops_per_jiffy = loops_per_jiffy;
234 }
235 
236 /*
237  * Activate a secondary processor.
238  */
239 static void notrace start_secondary(void *unused)
240 {
241 	/*
242 	 * Don't put *anything* except direct CPU state initialization
243 	 * before cpu_init(), SMP booting is too fragile that we want to
244 	 * limit the things done here to the most necessary things.
245 	 */
246 	cr4_init();
247 
248 	/*
249 	 * 32-bit specific. 64-bit reaches this code with the correct page
250 	 * table established. Yet another historical divergence.
251 	 */
252 	if (IS_ENABLED(CONFIG_X86_32)) {
253 		/* switch away from the initial page table */
254 		load_cr3(swapper_pg_dir);
255 		__flush_tlb_all();
256 	}
257 
258 	cpu_init_exception_handling();
259 
260 	/*
261 	 * 32-bit systems load the microcode from the ASM startup code for
262 	 * historical reasons.
263 	 *
264 	 * On 64-bit systems load it before reaching the AP alive
265 	 * synchronization point below so it is not part of the full per
266 	 * CPU serialized bringup part when "parallel" bringup is enabled.
267 	 *
268 	 * That's even safe when hyperthreading is enabled in the CPU as
269 	 * the core code starts the primary threads first and leaves the
270 	 * secondary threads waiting for SIPI. Loading microcode on
271 	 * physical cores concurrently is a safe operation.
272 	 *
273 	 * This covers both the Intel specific issue that concurrent
274 	 * microcode loading on SMT siblings must be prohibited and the
275 	 * vendor independent issue`that microcode loading which changes
276 	 * CPUID, MSRs etc. must be strictly serialized to maintain
277 	 * software state correctness.
278 	 */
279 	if (IS_ENABLED(CONFIG_X86_64))
280 		load_ucode_ap();
281 
282 	/*
283 	 * Synchronization point with the hotplug core. Sets this CPUs
284 	 * synchronization state to ALIVE and spin-waits for the control CPU to
285 	 * release this CPU for further bringup.
286 	 */
287 	cpuhp_ap_sync_alive();
288 
289 	cpu_init();
290 	fpu__init_cpu();
291 	rcu_cpu_starting(raw_smp_processor_id());
292 	x86_cpuinit.early_percpu_clock_init();
293 
294 	ap_starting();
295 
296 	/* Check TSC synchronization with the control CPU. */
297 	check_tsc_sync_target();
298 
299 	/*
300 	 * Calibrate the delay loop after the TSC synchronization check.
301 	 * This allows to skip the calibration when TSC is synchronized
302 	 * across sockets.
303 	 */
304 	ap_calibrate_delay();
305 
306 	speculative_store_bypass_ht_init();
307 
308 	/*
309 	 * Lock vector_lock, set CPU online and bring the vector
310 	 * allocator online. Online must be set with vector_lock held
311 	 * to prevent a concurrent irq setup/teardown from seeing a
312 	 * half valid vector space.
313 	 */
314 	lock_vector_lock();
315 	set_cpu_online(smp_processor_id(), true);
316 	lapic_online();
317 	unlock_vector_lock();
318 	x86_platform.nmi_init();
319 
320 	/* enable local interrupts */
321 	local_irq_enable();
322 
323 	x86_cpuinit.setup_percpu_clockev();
324 
325 	wmb();
326 	cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
327 }
328 
329 /**
330  * topology_phys_to_logical_pkg - Map a physical package id to a logical
331  * @phys_pkg:	The physical package id to map
332  *
333  * Returns logical package id or -1 if not found
334  */
335 int topology_phys_to_logical_pkg(unsigned int phys_pkg)
336 {
337 	int cpu;
338 
339 	for_each_possible_cpu(cpu) {
340 		struct cpuinfo_x86 *c = &cpu_data(cpu);
341 
342 		if (c->initialized && c->phys_proc_id == phys_pkg)
343 			return c->logical_proc_id;
344 	}
345 	return -1;
346 }
347 EXPORT_SYMBOL(topology_phys_to_logical_pkg);
348 
349 /**
350  * topology_phys_to_logical_die - Map a physical die id to logical
351  * @die_id:	The physical die id to map
352  * @cur_cpu:	The CPU for which the mapping is done
353  *
354  * Returns logical die id or -1 if not found
355  */
356 static int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu)
357 {
358 	int cpu, proc_id = cpu_data(cur_cpu).phys_proc_id;
359 
360 	for_each_possible_cpu(cpu) {
361 		struct cpuinfo_x86 *c = &cpu_data(cpu);
362 
363 		if (c->initialized && c->cpu_die_id == die_id &&
364 		    c->phys_proc_id == proc_id)
365 			return c->logical_die_id;
366 	}
367 	return -1;
368 }
369 
370 /**
371  * topology_update_package_map - Update the physical to logical package map
372  * @pkg:	The physical package id as retrieved via CPUID
373  * @cpu:	The cpu for which this is updated
374  */
375 int topology_update_package_map(unsigned int pkg, unsigned int cpu)
376 {
377 	int new;
378 
379 	/* Already available somewhere? */
380 	new = topology_phys_to_logical_pkg(pkg);
381 	if (new >= 0)
382 		goto found;
383 
384 	new = logical_packages++;
385 	if (new != pkg) {
386 		pr_info("CPU %u Converting physical %u to logical package %u\n",
387 			cpu, pkg, new);
388 	}
389 found:
390 	cpu_data(cpu).logical_proc_id = new;
391 	return 0;
392 }
393 /**
394  * topology_update_die_map - Update the physical to logical die map
395  * @die:	The die id as retrieved via CPUID
396  * @cpu:	The cpu for which this is updated
397  */
398 int topology_update_die_map(unsigned int die, unsigned int cpu)
399 {
400 	int new;
401 
402 	/* Already available somewhere? */
403 	new = topology_phys_to_logical_die(die, cpu);
404 	if (new >= 0)
405 		goto found;
406 
407 	new = logical_die++;
408 	if (new != die) {
409 		pr_info("CPU %u Converting physical %u to logical die %u\n",
410 			cpu, die, new);
411 	}
412 found:
413 	cpu_data(cpu).logical_die_id = new;
414 	return 0;
415 }
416 
417 static void __init smp_store_boot_cpu_info(void)
418 {
419 	int id = 0; /* CPU 0 */
420 	struct cpuinfo_x86 *c = &cpu_data(id);
421 
422 	*c = boot_cpu_data;
423 	c->cpu_index = id;
424 	topology_update_package_map(c->phys_proc_id, id);
425 	topology_update_die_map(c->cpu_die_id, id);
426 	c->initialized = true;
427 }
428 
429 /*
430  * The bootstrap kernel entry code has set these up. Save them for
431  * a given CPU
432  */
433 void smp_store_cpu_info(int id)
434 {
435 	struct cpuinfo_x86 *c = &cpu_data(id);
436 
437 	/* Copy boot_cpu_data only on the first bringup */
438 	if (!c->initialized)
439 		*c = boot_cpu_data;
440 	c->cpu_index = id;
441 	/*
442 	 * During boot time, CPU0 has this setup already. Save the info when
443 	 * bringing up an AP.
444 	 */
445 	identify_secondary_cpu(c);
446 	c->initialized = true;
447 }
448 
449 static bool
450 topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
451 {
452 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
453 
454 	return (cpu_to_node(cpu1) == cpu_to_node(cpu2));
455 }
456 
457 static bool
458 topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name)
459 {
460 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
461 
462 	return !WARN_ONCE(!topology_same_node(c, o),
463 		"sched: CPU #%d's %s-sibling CPU #%d is not on the same node! "
464 		"[node: %d != %d]. Ignoring dependency.\n",
465 		cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2));
466 }
467 
468 #define link_mask(mfunc, c1, c2)					\
469 do {									\
470 	cpumask_set_cpu((c1), mfunc(c2));				\
471 	cpumask_set_cpu((c2), mfunc(c1));				\
472 } while (0)
473 
474 static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
475 {
476 	if (boot_cpu_has(X86_FEATURE_TOPOEXT)) {
477 		int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
478 
479 		if (c->phys_proc_id == o->phys_proc_id &&
480 		    c->cpu_die_id == o->cpu_die_id &&
481 		    per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) {
482 			if (c->cpu_core_id == o->cpu_core_id)
483 				return topology_sane(c, o, "smt");
484 
485 			if ((c->cu_id != 0xff) &&
486 			    (o->cu_id != 0xff) &&
487 			    (c->cu_id == o->cu_id))
488 				return topology_sane(c, o, "smt");
489 		}
490 
491 	} else if (c->phys_proc_id == o->phys_proc_id &&
492 		   c->cpu_die_id == o->cpu_die_id &&
493 		   c->cpu_core_id == o->cpu_core_id) {
494 		return topology_sane(c, o, "smt");
495 	}
496 
497 	return false;
498 }
499 
500 static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
501 {
502 	if (c->phys_proc_id == o->phys_proc_id &&
503 	    c->cpu_die_id == o->cpu_die_id)
504 		return true;
505 	return false;
506 }
507 
508 static bool match_l2c(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
509 {
510 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
511 
512 	/* If the arch didn't set up l2c_id, fall back to SMT */
513 	if (per_cpu(cpu_l2c_id, cpu1) == BAD_APICID)
514 		return match_smt(c, o);
515 
516 	/* Do not match if L2 cache id does not match: */
517 	if (per_cpu(cpu_l2c_id, cpu1) != per_cpu(cpu_l2c_id, cpu2))
518 		return false;
519 
520 	return topology_sane(c, o, "l2c");
521 }
522 
523 /*
524  * Unlike the other levels, we do not enforce keeping a
525  * multicore group inside a NUMA node.  If this happens, we will
526  * discard the MC level of the topology later.
527  */
528 static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
529 {
530 	if (c->phys_proc_id == o->phys_proc_id)
531 		return true;
532 	return false;
533 }
534 
535 /*
536  * Define intel_cod_cpu[] for Intel COD (Cluster-on-Die) CPUs.
537  *
538  * Any Intel CPU that has multiple nodes per package and does not
539  * match intel_cod_cpu[] has the SNC (Sub-NUMA Cluster) topology.
540  *
541  * When in SNC mode, these CPUs enumerate an LLC that is shared
542  * by multiple NUMA nodes. The LLC is shared for off-package data
543  * access but private to the NUMA node (half of the package) for
544  * on-package access. CPUID (the source of the information about
545  * the LLC) can only enumerate the cache as shared or unshared,
546  * but not this particular configuration.
547  */
548 
549 static const struct x86_cpu_id intel_cod_cpu[] = {
550 	X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, 0),	/* COD */
551 	X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, 0),	/* COD */
552 	X86_MATCH_INTEL_FAM6_MODEL(ANY, 1),		/* SNC */
553 	{}
554 };
555 
556 static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o)
557 {
558 	const struct x86_cpu_id *id = x86_match_cpu(intel_cod_cpu);
559 	int cpu1 = c->cpu_index, cpu2 = o->cpu_index;
560 	bool intel_snc = id && id->driver_data;
561 
562 	/* Do not match if we do not have a valid APICID for cpu: */
563 	if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID)
564 		return false;
565 
566 	/* Do not match if LLC id does not match: */
567 	if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2))
568 		return false;
569 
570 	/*
571 	 * Allow the SNC topology without warning. Return of false
572 	 * means 'c' does not share the LLC of 'o'. This will be
573 	 * reflected to userspace.
574 	 */
575 	if (match_pkg(c, o) && !topology_same_node(c, o) && intel_snc)
576 		return false;
577 
578 	return topology_sane(c, o, "llc");
579 }
580 
581 
582 static inline int x86_sched_itmt_flags(void)
583 {
584 	return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0;
585 }
586 
587 #ifdef CONFIG_SCHED_MC
588 static int x86_core_flags(void)
589 {
590 	return cpu_core_flags() | x86_sched_itmt_flags();
591 }
592 #endif
593 #ifdef CONFIG_SCHED_SMT
594 static int x86_smt_flags(void)
595 {
596 	return cpu_smt_flags();
597 }
598 #endif
599 #ifdef CONFIG_SCHED_CLUSTER
600 static int x86_cluster_flags(void)
601 {
602 	return cpu_cluster_flags() | x86_sched_itmt_flags();
603 }
604 #endif
605 
606 static int x86_die_flags(void)
607 {
608 	if (cpu_feature_enabled(X86_FEATURE_HYBRID_CPU))
609 	       return x86_sched_itmt_flags();
610 
611 	return 0;
612 }
613 
614 /*
615  * Set if a package/die has multiple NUMA nodes inside.
616  * AMD Magny-Cours, Intel Cluster-on-Die, and Intel
617  * Sub-NUMA Clustering have this.
618  */
619 static bool x86_has_numa_in_package;
620 
621 static struct sched_domain_topology_level x86_topology[6];
622 
623 static void __init build_sched_topology(void)
624 {
625 	int i = 0;
626 
627 #ifdef CONFIG_SCHED_SMT
628 	x86_topology[i++] = (struct sched_domain_topology_level){
629 		cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT)
630 	};
631 #endif
632 #ifdef CONFIG_SCHED_CLUSTER
633 	x86_topology[i++] = (struct sched_domain_topology_level){
634 		cpu_clustergroup_mask, x86_cluster_flags, SD_INIT_NAME(CLS)
635 	};
636 #endif
637 #ifdef CONFIG_SCHED_MC
638 	x86_topology[i++] = (struct sched_domain_topology_level){
639 		cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC)
640 	};
641 #endif
642 	/*
643 	 * When there is NUMA topology inside the package skip the DIE domain
644 	 * since the NUMA domains will auto-magically create the right spanning
645 	 * domains based on the SLIT.
646 	 */
647 	if (!x86_has_numa_in_package) {
648 		x86_topology[i++] = (struct sched_domain_topology_level){
649 			cpu_cpu_mask, x86_die_flags, SD_INIT_NAME(DIE)
650 		};
651 	}
652 
653 	/*
654 	 * There must be one trailing NULL entry left.
655 	 */
656 	BUG_ON(i >= ARRAY_SIZE(x86_topology)-1);
657 
658 	set_sched_topology(x86_topology);
659 }
660 
661 void set_cpu_sibling_map(int cpu)
662 {
663 	bool has_smt = smp_num_siblings > 1;
664 	bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1;
665 	struct cpuinfo_x86 *c = &cpu_data(cpu);
666 	struct cpuinfo_x86 *o;
667 	int i, threads;
668 
669 	cpumask_set_cpu(cpu, cpu_sibling_setup_mask);
670 
671 	if (!has_mp) {
672 		cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu));
673 		cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu));
674 		cpumask_set_cpu(cpu, cpu_l2c_shared_mask(cpu));
675 		cpumask_set_cpu(cpu, topology_core_cpumask(cpu));
676 		cpumask_set_cpu(cpu, topology_die_cpumask(cpu));
677 		c->booted_cores = 1;
678 		return;
679 	}
680 
681 	for_each_cpu(i, cpu_sibling_setup_mask) {
682 		o = &cpu_data(i);
683 
684 		if (match_pkg(c, o) && !topology_same_node(c, o))
685 			x86_has_numa_in_package = true;
686 
687 		if ((i == cpu) || (has_smt && match_smt(c, o)))
688 			link_mask(topology_sibling_cpumask, cpu, i);
689 
690 		if ((i == cpu) || (has_mp && match_llc(c, o)))
691 			link_mask(cpu_llc_shared_mask, cpu, i);
692 
693 		if ((i == cpu) || (has_mp && match_l2c(c, o)))
694 			link_mask(cpu_l2c_shared_mask, cpu, i);
695 
696 		if ((i == cpu) || (has_mp && match_die(c, o)))
697 			link_mask(topology_die_cpumask, cpu, i);
698 	}
699 
700 	threads = cpumask_weight(topology_sibling_cpumask(cpu));
701 	if (threads > __max_smt_threads)
702 		__max_smt_threads = threads;
703 
704 	for_each_cpu(i, topology_sibling_cpumask(cpu))
705 		cpu_data(i).smt_active = threads > 1;
706 
707 	/*
708 	 * This needs a separate iteration over the cpus because we rely on all
709 	 * topology_sibling_cpumask links to be set-up.
710 	 */
711 	for_each_cpu(i, cpu_sibling_setup_mask) {
712 		o = &cpu_data(i);
713 
714 		if ((i == cpu) || (has_mp && match_pkg(c, o))) {
715 			link_mask(topology_core_cpumask, cpu, i);
716 
717 			/*
718 			 *  Does this new cpu bringup a new core?
719 			 */
720 			if (threads == 1) {
721 				/*
722 				 * for each core in package, increment
723 				 * the booted_cores for this new cpu
724 				 */
725 				if (cpumask_first(
726 				    topology_sibling_cpumask(i)) == i)
727 					c->booted_cores++;
728 				/*
729 				 * increment the core count for all
730 				 * the other cpus in this package
731 				 */
732 				if (i != cpu)
733 					cpu_data(i).booted_cores++;
734 			} else if (i != cpu && !c->booted_cores)
735 				c->booted_cores = cpu_data(i).booted_cores;
736 		}
737 	}
738 }
739 
740 /* maps the cpu to the sched domain representing multi-core */
741 const struct cpumask *cpu_coregroup_mask(int cpu)
742 {
743 	return cpu_llc_shared_mask(cpu);
744 }
745 
746 const struct cpumask *cpu_clustergroup_mask(int cpu)
747 {
748 	return cpu_l2c_shared_mask(cpu);
749 }
750 
751 static void impress_friends(void)
752 {
753 	int cpu;
754 	unsigned long bogosum = 0;
755 	/*
756 	 * Allow the user to impress friends.
757 	 */
758 	pr_debug("Before bogomips\n");
759 	for_each_online_cpu(cpu)
760 		bogosum += cpu_data(cpu).loops_per_jiffy;
761 
762 	pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n",
763 		num_online_cpus(),
764 		bogosum/(500000/HZ),
765 		(bogosum/(5000/HZ))%100);
766 
767 	pr_debug("Before bogocount - setting activated=1\n");
768 }
769 
770 /*
771  * The Multiprocessor Specification 1.4 (1997) example code suggests
772  * that there should be a 10ms delay between the BSP asserting INIT
773  * and de-asserting INIT, when starting a remote processor.
774  * But that slows boot and resume on modern processors, which include
775  * many cores and don't require that delay.
776  *
777  * Cmdline "init_cpu_udelay=" is available to over-ride this delay.
778  * Modern processor families are quirked to remove the delay entirely.
779  */
780 #define UDELAY_10MS_DEFAULT 10000
781 
782 static unsigned int init_udelay = UINT_MAX;
783 
784 static int __init cpu_init_udelay(char *str)
785 {
786 	get_option(&str, &init_udelay);
787 
788 	return 0;
789 }
790 early_param("cpu_init_udelay", cpu_init_udelay);
791 
792 static void __init smp_quirk_init_udelay(void)
793 {
794 	/* if cmdline changed it from default, leave it alone */
795 	if (init_udelay != UINT_MAX)
796 		return;
797 
798 	/* if modern processor, use no delay */
799 	if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) ||
800 	    ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) ||
801 	    ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) {
802 		init_udelay = 0;
803 		return;
804 	}
805 	/* else, use legacy delay */
806 	init_udelay = UDELAY_10MS_DEFAULT;
807 }
808 
809 /*
810  * Wake up AP by INIT, INIT, STARTUP sequence.
811  */
812 static void send_init_sequence(int phys_apicid)
813 {
814 	int maxlvt = lapic_get_maxlvt();
815 
816 	/* Be paranoid about clearing APIC errors. */
817 	if (APIC_INTEGRATED(boot_cpu_apic_version)) {
818 		/* Due to the Pentium erratum 3AP.  */
819 		if (maxlvt > 3)
820 			apic_write(APIC_ESR, 0);
821 		apic_read(APIC_ESR);
822 	}
823 
824 	/* Assert INIT on the target CPU */
825 	apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid);
826 	safe_apic_wait_icr_idle();
827 
828 	udelay(init_udelay);
829 
830 	/* Deassert INIT on the target CPU */
831 	apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid);
832 	safe_apic_wait_icr_idle();
833 }
834 
835 /*
836  * Wake up AP by INIT, INIT, STARTUP sequence.
837  */
838 static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip)
839 {
840 	unsigned long send_status = 0, accept_status = 0;
841 	int num_starts, j, maxlvt;
842 
843 	preempt_disable();
844 	maxlvt = lapic_get_maxlvt();
845 	send_init_sequence(phys_apicid);
846 
847 	mb();
848 
849 	/*
850 	 * Should we send STARTUP IPIs ?
851 	 *
852 	 * Determine this based on the APIC version.
853 	 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
854 	 */
855 	if (APIC_INTEGRATED(boot_cpu_apic_version))
856 		num_starts = 2;
857 	else
858 		num_starts = 0;
859 
860 	/*
861 	 * Run STARTUP IPI loop.
862 	 */
863 	pr_debug("#startup loops: %d\n", num_starts);
864 
865 	for (j = 1; j <= num_starts; j++) {
866 		pr_debug("Sending STARTUP #%d\n", j);
867 		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
868 			apic_write(APIC_ESR, 0);
869 		apic_read(APIC_ESR);
870 		pr_debug("After apic_write\n");
871 
872 		/*
873 		 * STARTUP IPI
874 		 */
875 
876 		/* Target chip */
877 		/* Boot on the stack */
878 		/* Kick the second */
879 		apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12),
880 			       phys_apicid);
881 
882 		/*
883 		 * Give the other CPU some time to accept the IPI.
884 		 */
885 		if (init_udelay == 0)
886 			udelay(10);
887 		else
888 			udelay(300);
889 
890 		pr_debug("Startup point 1\n");
891 
892 		pr_debug("Waiting for send to finish...\n");
893 		send_status = safe_apic_wait_icr_idle();
894 
895 		/*
896 		 * Give the other CPU some time to accept the IPI.
897 		 */
898 		if (init_udelay == 0)
899 			udelay(10);
900 		else
901 			udelay(200);
902 
903 		if (maxlvt > 3)		/* Due to the Pentium erratum 3AP.  */
904 			apic_write(APIC_ESR, 0);
905 		accept_status = (apic_read(APIC_ESR) & 0xEF);
906 		if (send_status || accept_status)
907 			break;
908 	}
909 	pr_debug("After Startup\n");
910 
911 	if (send_status)
912 		pr_err("APIC never delivered???\n");
913 	if (accept_status)
914 		pr_err("APIC delivery error (%lx)\n", accept_status);
915 
916 	preempt_enable();
917 	return (send_status | accept_status);
918 }
919 
920 /* reduce the number of lines printed when booting a large cpu count system */
921 static void announce_cpu(int cpu, int apicid)
922 {
923 	static int width, node_width, first = 1;
924 	static int current_node = NUMA_NO_NODE;
925 	int node = early_cpu_to_node(cpu);
926 
927 	if (!width)
928 		width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */
929 
930 	if (!node_width)
931 		node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */
932 
933 	if (system_state < SYSTEM_RUNNING) {
934 		if (first)
935 			pr_info("x86: Booting SMP configuration:\n");
936 
937 		if (node != current_node) {
938 			if (current_node > (-1))
939 				pr_cont("\n");
940 			current_node = node;
941 
942 			printk(KERN_INFO ".... node %*s#%d, CPUs:  ",
943 			       node_width - num_digits(node), " ", node);
944 		}
945 
946 		/* Add padding for the BSP */
947 		if (first)
948 			pr_cont("%*s", width + 1, " ");
949 		first = 0;
950 
951 		pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu);
952 	} else
953 		pr_info("Booting Node %d Processor %d APIC 0x%x\n",
954 			node, cpu, apicid);
955 }
956 
957 int common_cpu_up(unsigned int cpu, struct task_struct *idle)
958 {
959 	int ret;
960 
961 	/* Just in case we booted with a single CPU. */
962 	alternatives_enable_smp();
963 
964 	per_cpu(pcpu_hot.current_task, cpu) = idle;
965 	cpu_init_stack_canary(cpu, idle);
966 
967 	/* Initialize the interrupt stack(s) */
968 	ret = irq_init_percpu_irqstack(cpu);
969 	if (ret)
970 		return ret;
971 
972 #ifdef CONFIG_X86_32
973 	/* Stack for startup_32 can be just as for start_secondary onwards */
974 	per_cpu(pcpu_hot.top_of_stack, cpu) = task_top_of_stack(idle);
975 #endif
976 	return 0;
977 }
978 
979 /*
980  * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
981  * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
982  * Returns zero if startup was successfully sent, else error code from
983  * ->wakeup_secondary_cpu.
984  */
985 static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle)
986 {
987 	unsigned long start_ip = real_mode_header->trampoline_start;
988 	int ret;
989 
990 #ifdef CONFIG_X86_64
991 	/* If 64-bit wakeup method exists, use the 64-bit mode trampoline IP */
992 	if (apic->wakeup_secondary_cpu_64)
993 		start_ip = real_mode_header->trampoline_start64;
994 #endif
995 	idle->thread.sp = (unsigned long)task_pt_regs(idle);
996 	initial_code = (unsigned long)start_secondary;
997 
998 	if (IS_ENABLED(CONFIG_X86_32)) {
999 		early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu);
1000 		initial_stack  = idle->thread.sp;
1001 	} else if (!(smpboot_control & STARTUP_PARALLEL_MASK)) {
1002 		smpboot_control = cpu;
1003 	}
1004 
1005 	/* Enable the espfix hack for this CPU */
1006 	init_espfix_ap(cpu);
1007 
1008 	/* So we see what's up */
1009 	announce_cpu(cpu, apicid);
1010 
1011 	/*
1012 	 * This grunge runs the startup process for
1013 	 * the targeted processor.
1014 	 */
1015 	if (x86_platform.legacy.warm_reset) {
1016 
1017 		pr_debug("Setting warm reset code and vector.\n");
1018 
1019 		smpboot_setup_warm_reset_vector(start_ip);
1020 		/*
1021 		 * Be paranoid about clearing APIC errors.
1022 		*/
1023 		if (APIC_INTEGRATED(boot_cpu_apic_version)) {
1024 			apic_write(APIC_ESR, 0);
1025 			apic_read(APIC_ESR);
1026 		}
1027 	}
1028 
1029 	smp_mb();
1030 
1031 	/*
1032 	 * Wake up a CPU in difference cases:
1033 	 * - Use a method from the APIC driver if one defined, with wakeup
1034 	 *   straight to 64-bit mode preferred over wakeup to RM.
1035 	 * Otherwise,
1036 	 * - Use an INIT boot APIC message
1037 	 */
1038 	if (apic->wakeup_secondary_cpu_64)
1039 		ret = apic->wakeup_secondary_cpu_64(apicid, start_ip);
1040 	else if (apic->wakeup_secondary_cpu)
1041 		ret = apic->wakeup_secondary_cpu(apicid, start_ip);
1042 	else
1043 		ret = wakeup_secondary_cpu_via_init(apicid, start_ip);
1044 
1045 	/* If the wakeup mechanism failed, cleanup the warm reset vector */
1046 	if (ret)
1047 		arch_cpuhp_cleanup_kick_cpu(cpu);
1048 	return ret;
1049 }
1050 
1051 int native_kick_ap(unsigned int cpu, struct task_struct *tidle)
1052 {
1053 	int apicid = apic->cpu_present_to_apicid(cpu);
1054 	int err;
1055 
1056 	lockdep_assert_irqs_enabled();
1057 
1058 	pr_debug("++++++++++++++++++++=_---CPU UP  %u\n", cpu);
1059 
1060 	if (apicid == BAD_APICID || !physid_isset(apicid, phys_cpu_present_map) ||
1061 	    !apic_id_valid(apicid)) {
1062 		pr_err("%s: bad cpu %d\n", __func__, cpu);
1063 		return -EINVAL;
1064 	}
1065 
1066 	/*
1067 	 * Save current MTRR state in case it was changed since early boot
1068 	 * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync:
1069 	 */
1070 	mtrr_save_state();
1071 
1072 	/* the FPU context is blank, nobody can own it */
1073 	per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL;
1074 
1075 	err = common_cpu_up(cpu, tidle);
1076 	if (err)
1077 		return err;
1078 
1079 	err = do_boot_cpu(apicid, cpu, tidle);
1080 	if (err)
1081 		pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu);
1082 
1083 	return err;
1084 }
1085 
1086 int arch_cpuhp_kick_ap_alive(unsigned int cpu, struct task_struct *tidle)
1087 {
1088 	return smp_ops.kick_ap_alive(cpu, tidle);
1089 }
1090 
1091 void arch_cpuhp_cleanup_kick_cpu(unsigned int cpu)
1092 {
1093 	/* Cleanup possible dangling ends... */
1094 	if (smp_ops.kick_ap_alive == native_kick_ap && x86_platform.legacy.warm_reset)
1095 		smpboot_restore_warm_reset_vector();
1096 }
1097 
1098 void arch_cpuhp_cleanup_dead_cpu(unsigned int cpu)
1099 {
1100 	if (smp_ops.cleanup_dead_cpu)
1101 		smp_ops.cleanup_dead_cpu(cpu);
1102 
1103 	if (system_state == SYSTEM_RUNNING)
1104 		pr_info("CPU %u is now offline\n", cpu);
1105 }
1106 
1107 void arch_cpuhp_sync_state_poll(void)
1108 {
1109 	if (smp_ops.poll_sync_state)
1110 		smp_ops.poll_sync_state();
1111 }
1112 
1113 /**
1114  * arch_disable_smp_support() - Disables SMP support for x86 at boottime
1115  */
1116 void __init arch_disable_smp_support(void)
1117 {
1118 	disable_ioapic_support();
1119 }
1120 
1121 /*
1122  * Fall back to non SMP mode after errors.
1123  *
1124  * RED-PEN audit/test this more. I bet there is more state messed up here.
1125  */
1126 static __init void disable_smp(void)
1127 {
1128 	pr_info("SMP disabled\n");
1129 
1130 	disable_ioapic_support();
1131 
1132 	init_cpu_present(cpumask_of(0));
1133 	init_cpu_possible(cpumask_of(0));
1134 
1135 	if (smp_found_config)
1136 		physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map);
1137 	else
1138 		physid_set_mask_of_physid(0, &phys_cpu_present_map);
1139 	cpumask_set_cpu(0, topology_sibling_cpumask(0));
1140 	cpumask_set_cpu(0, topology_core_cpumask(0));
1141 	cpumask_set_cpu(0, topology_die_cpumask(0));
1142 }
1143 
1144 static void __init smp_cpu_index_default(void)
1145 {
1146 	int i;
1147 	struct cpuinfo_x86 *c;
1148 
1149 	for_each_possible_cpu(i) {
1150 		c = &cpu_data(i);
1151 		/* mark all to hotplug */
1152 		c->cpu_index = nr_cpu_ids;
1153 	}
1154 }
1155 
1156 void __init smp_prepare_cpus_common(void)
1157 {
1158 	unsigned int i;
1159 
1160 	smp_cpu_index_default();
1161 
1162 	/*
1163 	 * Setup boot CPU information
1164 	 */
1165 	smp_store_boot_cpu_info(); /* Final full version of the data */
1166 	mb();
1167 
1168 	for_each_possible_cpu(i) {
1169 		zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL);
1170 		zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL);
1171 		zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL);
1172 		zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL);
1173 		zalloc_cpumask_var(&per_cpu(cpu_l2c_shared_map, i), GFP_KERNEL);
1174 	}
1175 
1176 	set_cpu_sibling_map(0);
1177 }
1178 
1179 #ifdef CONFIG_X86_64
1180 /* Establish whether parallel bringup can be supported. */
1181 bool __init arch_cpuhp_init_parallel_bringup(void)
1182 {
1183 	if (!x86_cpuinit.parallel_bringup) {
1184 		pr_info("Parallel CPU startup disabled by the platform\n");
1185 		return false;
1186 	}
1187 
1188 	smpboot_control = STARTUP_READ_APICID;
1189 	pr_debug("Parallel CPU startup enabled: 0x%08x\n", smpboot_control);
1190 	return true;
1191 }
1192 #endif
1193 
1194 /*
1195  * Prepare for SMP bootup.
1196  * @max_cpus: configured maximum number of CPUs, It is a legacy parameter
1197  *            for common interface support.
1198  */
1199 void __init native_smp_prepare_cpus(unsigned int max_cpus)
1200 {
1201 	smp_prepare_cpus_common();
1202 
1203 	switch (apic_intr_mode) {
1204 	case APIC_PIC:
1205 	case APIC_VIRTUAL_WIRE_NO_CONFIG:
1206 		disable_smp();
1207 		return;
1208 	case APIC_SYMMETRIC_IO_NO_ROUTING:
1209 		disable_smp();
1210 		/* Setup local timer */
1211 		x86_init.timers.setup_percpu_clockev();
1212 		return;
1213 	case APIC_VIRTUAL_WIRE:
1214 	case APIC_SYMMETRIC_IO:
1215 		break;
1216 	}
1217 
1218 	/* Setup local timer */
1219 	x86_init.timers.setup_percpu_clockev();
1220 
1221 	pr_info("CPU0: ");
1222 	print_cpu_info(&cpu_data(0));
1223 
1224 	uv_system_init();
1225 
1226 	smp_quirk_init_udelay();
1227 
1228 	speculative_store_bypass_ht_init();
1229 
1230 	snp_set_wakeup_secondary_cpu();
1231 }
1232 
1233 void arch_thaw_secondary_cpus_begin(void)
1234 {
1235 	set_cache_aps_delayed_init(true);
1236 }
1237 
1238 void arch_thaw_secondary_cpus_end(void)
1239 {
1240 	cache_aps_init();
1241 }
1242 
1243 /*
1244  * Early setup to make printk work.
1245  */
1246 void __init native_smp_prepare_boot_cpu(void)
1247 {
1248 	int me = smp_processor_id();
1249 
1250 	/* SMP handles this from setup_per_cpu_areas() */
1251 	if (!IS_ENABLED(CONFIG_SMP))
1252 		switch_gdt_and_percpu_base(me);
1253 
1254 	native_pv_lock_init();
1255 }
1256 
1257 void __init calculate_max_logical_packages(void)
1258 {
1259 	int ncpus;
1260 
1261 	/*
1262 	 * Today neither Intel nor AMD support heterogeneous systems so
1263 	 * extrapolate the boot cpu's data to all packages.
1264 	 */
1265 	ncpus = cpu_data(0).booted_cores * topology_max_smt_threads();
1266 	__max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus);
1267 	pr_info("Max logical packages: %u\n", __max_logical_packages);
1268 }
1269 
1270 void __init native_smp_cpus_done(unsigned int max_cpus)
1271 {
1272 	pr_debug("Boot done\n");
1273 
1274 	calculate_max_logical_packages();
1275 	build_sched_topology();
1276 	nmi_selftest();
1277 	impress_friends();
1278 	cache_aps_init();
1279 }
1280 
1281 static int __initdata setup_possible_cpus = -1;
1282 static int __init _setup_possible_cpus(char *str)
1283 {
1284 	get_option(&str, &setup_possible_cpus);
1285 	return 0;
1286 }
1287 early_param("possible_cpus", _setup_possible_cpus);
1288 
1289 
1290 /*
1291  * cpu_possible_mask should be static, it cannot change as cpu's
1292  * are onlined, or offlined. The reason is per-cpu data-structures
1293  * are allocated by some modules at init time, and don't expect to
1294  * do this dynamically on cpu arrival/departure.
1295  * cpu_present_mask on the other hand can change dynamically.
1296  * In case when cpu_hotplug is not compiled, then we resort to current
1297  * behaviour, which is cpu_possible == cpu_present.
1298  * - Ashok Raj
1299  *
1300  * Three ways to find out the number of additional hotplug CPUs:
1301  * - If the BIOS specified disabled CPUs in ACPI/mptables use that.
1302  * - The user can overwrite it with possible_cpus=NUM
1303  * - Otherwise don't reserve additional CPUs.
1304  * We do this because additional CPUs waste a lot of memory.
1305  * -AK
1306  */
1307 __init void prefill_possible_map(void)
1308 {
1309 	int i, possible;
1310 
1311 	i = setup_max_cpus ?: 1;
1312 	if (setup_possible_cpus == -1) {
1313 		possible = num_processors;
1314 #ifdef CONFIG_HOTPLUG_CPU
1315 		if (setup_max_cpus)
1316 			possible += disabled_cpus;
1317 #else
1318 		if (possible > i)
1319 			possible = i;
1320 #endif
1321 	} else
1322 		possible = setup_possible_cpus;
1323 
1324 	total_cpus = max_t(int, possible, num_processors + disabled_cpus);
1325 
1326 	/* nr_cpu_ids could be reduced via nr_cpus= */
1327 	if (possible > nr_cpu_ids) {
1328 		pr_warn("%d Processors exceeds NR_CPUS limit of %u\n",
1329 			possible, nr_cpu_ids);
1330 		possible = nr_cpu_ids;
1331 	}
1332 
1333 #ifdef CONFIG_HOTPLUG_CPU
1334 	if (!setup_max_cpus)
1335 #endif
1336 	if (possible > i) {
1337 		pr_warn("%d Processors exceeds max_cpus limit of %u\n",
1338 			possible, setup_max_cpus);
1339 		possible = i;
1340 	}
1341 
1342 	set_nr_cpu_ids(possible);
1343 
1344 	pr_info("Allowing %d CPUs, %d hotplug CPUs\n",
1345 		possible, max_t(int, possible - num_processors, 0));
1346 
1347 	reset_cpu_possible_mask();
1348 
1349 	for (i = 0; i < possible; i++)
1350 		set_cpu_possible(i, true);
1351 }
1352 
1353 /* correctly size the local cpu masks */
1354 void __init setup_cpu_local_masks(void)
1355 {
1356 	alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
1357 }
1358 
1359 #ifdef CONFIG_HOTPLUG_CPU
1360 
1361 /* Recompute SMT state for all CPUs on offline */
1362 static void recompute_smt_state(void)
1363 {
1364 	int max_threads, cpu;
1365 
1366 	max_threads = 0;
1367 	for_each_online_cpu (cpu) {
1368 		int threads = cpumask_weight(topology_sibling_cpumask(cpu));
1369 
1370 		if (threads > max_threads)
1371 			max_threads = threads;
1372 	}
1373 	__max_smt_threads = max_threads;
1374 }
1375 
1376 static void remove_siblinginfo(int cpu)
1377 {
1378 	int sibling;
1379 	struct cpuinfo_x86 *c = &cpu_data(cpu);
1380 
1381 	for_each_cpu(sibling, topology_core_cpumask(cpu)) {
1382 		cpumask_clear_cpu(cpu, topology_core_cpumask(sibling));
1383 		/*/
1384 		 * last thread sibling in this cpu core going down
1385 		 */
1386 		if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1)
1387 			cpu_data(sibling).booted_cores--;
1388 	}
1389 
1390 	for_each_cpu(sibling, topology_die_cpumask(cpu))
1391 		cpumask_clear_cpu(cpu, topology_die_cpumask(sibling));
1392 
1393 	for_each_cpu(sibling, topology_sibling_cpumask(cpu)) {
1394 		cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling));
1395 		if (cpumask_weight(topology_sibling_cpumask(sibling)) == 1)
1396 			cpu_data(sibling).smt_active = false;
1397 	}
1398 
1399 	for_each_cpu(sibling, cpu_llc_shared_mask(cpu))
1400 		cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling));
1401 	for_each_cpu(sibling, cpu_l2c_shared_mask(cpu))
1402 		cpumask_clear_cpu(cpu, cpu_l2c_shared_mask(sibling));
1403 	cpumask_clear(cpu_llc_shared_mask(cpu));
1404 	cpumask_clear(cpu_l2c_shared_mask(cpu));
1405 	cpumask_clear(topology_sibling_cpumask(cpu));
1406 	cpumask_clear(topology_core_cpumask(cpu));
1407 	cpumask_clear(topology_die_cpumask(cpu));
1408 	c->cpu_core_id = 0;
1409 	c->booted_cores = 0;
1410 	cpumask_clear_cpu(cpu, cpu_sibling_setup_mask);
1411 	recompute_smt_state();
1412 }
1413 
1414 static void remove_cpu_from_maps(int cpu)
1415 {
1416 	set_cpu_online(cpu, false);
1417 	numa_remove_cpu(cpu);
1418 }
1419 
1420 void cpu_disable_common(void)
1421 {
1422 	int cpu = smp_processor_id();
1423 
1424 	remove_siblinginfo(cpu);
1425 
1426 	/* It's now safe to remove this processor from the online map */
1427 	lock_vector_lock();
1428 	remove_cpu_from_maps(cpu);
1429 	unlock_vector_lock();
1430 	fixup_irqs();
1431 	lapic_offline();
1432 }
1433 
1434 int native_cpu_disable(void)
1435 {
1436 	int ret;
1437 
1438 	ret = lapic_can_unplug_cpu();
1439 	if (ret)
1440 		return ret;
1441 
1442 	cpu_disable_common();
1443 
1444         /*
1445          * Disable the local APIC. Otherwise IPI broadcasts will reach
1446          * it. It still responds normally to INIT, NMI, SMI, and SIPI
1447          * messages.
1448          *
1449          * Disabling the APIC must happen after cpu_disable_common()
1450          * which invokes fixup_irqs().
1451          *
1452          * Disabling the APIC preserves already set bits in IRR, but
1453          * an interrupt arriving after disabling the local APIC does not
1454          * set the corresponding IRR bit.
1455          *
1456          * fixup_irqs() scans IRR for set bits so it can raise a not
1457          * yet handled interrupt on the new destination CPU via an IPI
1458          * but obviously it can't do so for IRR bits which are not set.
1459          * IOW, interrupts arriving after disabling the local APIC will
1460          * be lost.
1461          */
1462 	apic_soft_disable();
1463 
1464 	return 0;
1465 }
1466 
1467 void play_dead_common(void)
1468 {
1469 	idle_task_exit();
1470 
1471 	cpuhp_ap_report_dead();
1472 
1473 	local_irq_disable();
1474 }
1475 
1476 /*
1477  * We need to flush the caches before going to sleep, lest we have
1478  * dirty data in our caches when we come back up.
1479  */
1480 static inline void mwait_play_dead(void)
1481 {
1482 	struct mwait_cpu_dead *md = this_cpu_ptr(&mwait_cpu_dead);
1483 	unsigned int eax, ebx, ecx, edx;
1484 	unsigned int highest_cstate = 0;
1485 	unsigned int highest_subcstate = 0;
1486 	int i;
1487 
1488 	if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD ||
1489 	    boot_cpu_data.x86_vendor == X86_VENDOR_HYGON)
1490 		return;
1491 	if (!this_cpu_has(X86_FEATURE_MWAIT))
1492 		return;
1493 	if (!this_cpu_has(X86_FEATURE_CLFLUSH))
1494 		return;
1495 	if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF)
1496 		return;
1497 
1498 	eax = CPUID_MWAIT_LEAF;
1499 	ecx = 0;
1500 	native_cpuid(&eax, &ebx, &ecx, &edx);
1501 
1502 	/*
1503 	 * eax will be 0 if EDX enumeration is not valid.
1504 	 * Initialized below to cstate, sub_cstate value when EDX is valid.
1505 	 */
1506 	if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) {
1507 		eax = 0;
1508 	} else {
1509 		edx >>= MWAIT_SUBSTATE_SIZE;
1510 		for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) {
1511 			if (edx & MWAIT_SUBSTATE_MASK) {
1512 				highest_cstate = i;
1513 				highest_subcstate = edx & MWAIT_SUBSTATE_MASK;
1514 			}
1515 		}
1516 		eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) |
1517 			(highest_subcstate - 1);
1518 	}
1519 
1520 	/* Set up state for the kexec() hack below */
1521 	md->status = CPUDEAD_MWAIT_WAIT;
1522 	md->control = CPUDEAD_MWAIT_WAIT;
1523 
1524 	wbinvd();
1525 
1526 	while (1) {
1527 		/*
1528 		 * The CLFLUSH is a workaround for erratum AAI65 for
1529 		 * the Xeon 7400 series.  It's not clear it is actually
1530 		 * needed, but it should be harmless in either case.
1531 		 * The WBINVD is insufficient due to the spurious-wakeup
1532 		 * case where we return around the loop.
1533 		 */
1534 		mb();
1535 		clflush(md);
1536 		mb();
1537 		__monitor(md, 0, 0);
1538 		mb();
1539 		__mwait(eax, 0);
1540 
1541 		if (READ_ONCE(md->control) == CPUDEAD_MWAIT_KEXEC_HLT) {
1542 			/*
1543 			 * Kexec is about to happen. Don't go back into mwait() as
1544 			 * the kexec kernel might overwrite text and data including
1545 			 * page tables and stack. So mwait() would resume when the
1546 			 * monitor cache line is written to and then the CPU goes
1547 			 * south due to overwritten text, page tables and stack.
1548 			 *
1549 			 * Note: This does _NOT_ protect against a stray MCE, NMI,
1550 			 * SMI. They will resume execution at the instruction
1551 			 * following the HLT instruction and run into the problem
1552 			 * which this is trying to prevent.
1553 			 */
1554 			WRITE_ONCE(md->status, CPUDEAD_MWAIT_KEXEC_HLT);
1555 			while(1)
1556 				native_halt();
1557 		}
1558 	}
1559 }
1560 
1561 /*
1562  * Kick all "offline" CPUs out of mwait on kexec(). See comment in
1563  * mwait_play_dead().
1564  */
1565 void smp_kick_mwait_play_dead(void)
1566 {
1567 	u32 newstate = CPUDEAD_MWAIT_KEXEC_HLT;
1568 	struct mwait_cpu_dead *md;
1569 	unsigned int cpu, i;
1570 
1571 	for_each_cpu_andnot(cpu, cpu_present_mask, cpu_online_mask) {
1572 		md = per_cpu_ptr(&mwait_cpu_dead, cpu);
1573 
1574 		/* Does it sit in mwait_play_dead() ? */
1575 		if (READ_ONCE(md->status) != CPUDEAD_MWAIT_WAIT)
1576 			continue;
1577 
1578 		/* Wait up to 5ms */
1579 		for (i = 0; READ_ONCE(md->status) != newstate && i < 1000; i++) {
1580 			/* Bring it out of mwait */
1581 			WRITE_ONCE(md->control, newstate);
1582 			udelay(5);
1583 		}
1584 
1585 		if (READ_ONCE(md->status) != newstate)
1586 			pr_err_once("CPU%u is stuck in mwait_play_dead()\n", cpu);
1587 	}
1588 }
1589 
1590 void __noreturn hlt_play_dead(void)
1591 {
1592 	if (__this_cpu_read(cpu_info.x86) >= 4)
1593 		wbinvd();
1594 
1595 	while (1)
1596 		native_halt();
1597 }
1598 
1599 void native_play_dead(void)
1600 {
1601 	play_dead_common();
1602 	tboot_shutdown(TB_SHUTDOWN_WFS);
1603 
1604 	mwait_play_dead();
1605 	if (cpuidle_play_dead())
1606 		hlt_play_dead();
1607 }
1608 
1609 #else /* ... !CONFIG_HOTPLUG_CPU */
1610 int native_cpu_disable(void)
1611 {
1612 	return -ENOSYS;
1613 }
1614 
1615 void native_play_dead(void)
1616 {
1617 	BUG();
1618 }
1619 
1620 #endif
1621