1 /* 2 * Intel SMP support routines. 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * (c) 2002,2003 Andi Kleen, SuSE Labs. 7 * 8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> 9 * 10 * This code is released under the GNU General Public License version 2 or 11 * later. 12 */ 13 14 #include <linux/init.h> 15 16 #include <linux/mm.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/cache.h> 22 #include <linux/interrupt.h> 23 #include <linux/cpu.h> 24 25 #include <asm/mtrr.h> 26 #include <asm/tlbflush.h> 27 #include <asm/mmu_context.h> 28 #include <asm/proto.h> 29 #include <asm/apic.h> 30 /* 31 * Some notes on x86 processor bugs affecting SMP operation: 32 * 33 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. 34 * The Linux implications for SMP are handled as follows: 35 * 36 * Pentium III / [Xeon] 37 * None of the E1AP-E3AP errata are visible to the user. 38 * 39 * E1AP. see PII A1AP 40 * E2AP. see PII A2AP 41 * E3AP. see PII A3AP 42 * 43 * Pentium II / [Xeon] 44 * None of the A1AP-A3AP errata are visible to the user. 45 * 46 * A1AP. see PPro 1AP 47 * A2AP. see PPro 2AP 48 * A3AP. see PPro 7AP 49 * 50 * Pentium Pro 51 * None of 1AP-9AP errata are visible to the normal user, 52 * except occasional delivery of 'spurious interrupt' as trap #15. 53 * This is very rare and a non-problem. 54 * 55 * 1AP. Linux maps APIC as non-cacheable 56 * 2AP. worked around in hardware 57 * 3AP. fixed in C0 and above steppings microcode update. 58 * Linux does not use excessive STARTUP_IPIs. 59 * 4AP. worked around in hardware 60 * 5AP. symmetric IO mode (normal Linux operation) not affected. 61 * 'noapic' mode has vector 0xf filled out properly. 62 * 6AP. 'noapic' mode might be affected - fixed in later steppings 63 * 7AP. We do not assume writes to the LVT deassering IRQs 64 * 8AP. We do not enable low power mode (deep sleep) during MP bootup 65 * 9AP. We do not use mixed mode 66 * 67 * Pentium 68 * There is a marginal case where REP MOVS on 100MHz SMP 69 * machines with B stepping processors can fail. XXX should provide 70 * an L1cache=Writethrough or L1cache=off option. 71 * 72 * B stepping CPUs may hang. There are hardware work arounds 73 * for this. We warn about it in case your board doesn't have the work 74 * arounds. Basically that's so I can tell anyone with a B stepping 75 * CPU and SMP problems "tough". 76 * 77 * Specific items [From Pentium Processor Specification Update] 78 * 79 * 1AP. Linux doesn't use remote read 80 * 2AP. Linux doesn't trust APIC errors 81 * 3AP. We work around this 82 * 4AP. Linux never generated 3 interrupts of the same priority 83 * to cause a lost local interrupt. 84 * 5AP. Remote read is never used 85 * 6AP. not affected - worked around in hardware 86 * 7AP. not affected - worked around in hardware 87 * 8AP. worked around in hardware - we get explicit CS errors if not 88 * 9AP. only 'noapic' mode affected. Might generate spurious 89 * interrupts, we log only the first one and count the 90 * rest silently. 91 * 10AP. not affected - worked around in hardware 92 * 11AP. Linux reads the APIC between writes to avoid this, as per 93 * the documentation. Make sure you preserve this as it affects 94 * the C stepping chips too. 95 * 12AP. not affected - worked around in hardware 96 * 13AP. not affected - worked around in hardware 97 * 14AP. we always deassert INIT during bootup 98 * 15AP. not affected - worked around in hardware 99 * 16AP. not affected - worked around in hardware 100 * 17AP. not affected - worked around in hardware 101 * 18AP. not affected - worked around in hardware 102 * 19AP. not affected - worked around in BIOS 103 * 104 * If this sounds worrying believe me these bugs are either ___RARE___, 105 * or are signal timing bugs worked around in hardware and there's 106 * about nothing of note with C stepping upwards. 107 */ 108 109 /* 110 * this function sends a 'reschedule' IPI to another CPU. 111 * it goes straight through and wastes no time serializing 112 * anything. Worst case is that we lose a reschedule ... 113 */ 114 static void native_smp_send_reschedule(int cpu) 115 { 116 if (unlikely(cpu_is_offline(cpu))) { 117 WARN_ON(1); 118 return; 119 } 120 apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR); 121 } 122 123 void native_send_call_func_single_ipi(int cpu) 124 { 125 apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR); 126 } 127 128 void native_send_call_func_ipi(const struct cpumask *mask) 129 { 130 cpumask_var_t allbutself; 131 132 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) { 133 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 134 return; 135 } 136 137 cpumask_copy(allbutself, cpu_online_mask); 138 cpumask_clear_cpu(smp_processor_id(), allbutself); 139 140 if (cpumask_equal(mask, allbutself) && 141 cpumask_equal(cpu_online_mask, cpu_callout_mask)) 142 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); 143 else 144 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 145 146 free_cpumask_var(allbutself); 147 } 148 149 /* 150 * this function calls the 'stop' function on all other CPUs in the system. 151 */ 152 153 asmlinkage void smp_reboot_interrupt(void) 154 { 155 ack_APIC_irq(); 156 irq_enter(); 157 stop_this_cpu(NULL); 158 irq_exit(); 159 } 160 161 static void native_smp_send_stop(void) 162 { 163 unsigned long flags; 164 unsigned long wait; 165 166 if (reboot_force) 167 return; 168 169 /* 170 * Use an own vector here because smp_call_function 171 * does lots of things not suitable in a panic situation. 172 * On most systems we could also use an NMI here, 173 * but there are a few systems around where NMI 174 * is problematic so stay with an non NMI for now 175 * (this implies we cannot stop CPUs spinning with irq off 176 * currently) 177 */ 178 if (num_online_cpus() > 1) { 179 apic->send_IPI_allbutself(REBOOT_VECTOR); 180 181 /* Don't wait longer than a second */ 182 wait = USEC_PER_SEC; 183 while (num_online_cpus() > 1 && wait--) 184 udelay(1); 185 } 186 187 local_irq_save(flags); 188 disable_local_APIC(); 189 local_irq_restore(flags); 190 } 191 192 /* 193 * Reschedule call back. Nothing to do, 194 * all the work is done automatically when 195 * we return from the interrupt. 196 */ 197 void smp_reschedule_interrupt(struct pt_regs *regs) 198 { 199 ack_APIC_irq(); 200 inc_irq_stat(irq_resched_count); 201 /* 202 * KVM uses this interrupt to force a cpu out of guest mode 203 */ 204 } 205 206 void smp_call_function_interrupt(struct pt_regs *regs) 207 { 208 ack_APIC_irq(); 209 irq_enter(); 210 generic_smp_call_function_interrupt(); 211 inc_irq_stat(irq_call_count); 212 irq_exit(); 213 } 214 215 void smp_call_function_single_interrupt(struct pt_regs *regs) 216 { 217 ack_APIC_irq(); 218 irq_enter(); 219 generic_smp_call_function_single_interrupt(); 220 inc_irq_stat(irq_call_count); 221 irq_exit(); 222 } 223 224 struct smp_ops smp_ops = { 225 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 226 .smp_prepare_cpus = native_smp_prepare_cpus, 227 .smp_cpus_done = native_smp_cpus_done, 228 229 .smp_send_stop = native_smp_send_stop, 230 .smp_send_reschedule = native_smp_send_reschedule, 231 232 .cpu_up = native_cpu_up, 233 .cpu_die = native_cpu_die, 234 .cpu_disable = native_cpu_disable, 235 .play_dead = native_play_dead, 236 237 .send_call_func_ipi = native_send_call_func_ipi, 238 .send_call_func_single_ipi = native_send_call_func_single_ipi, 239 }; 240 EXPORT_SYMBOL_GPL(smp_ops); 241