1 /* 2 * Intel SMP support routines. 3 * 4 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 5 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> 6 * (c) 2002,2003 Andi Kleen, SuSE Labs. 7 * 8 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> 9 * 10 * This code is released under the GNU General Public License version 2 or 11 * later. 12 */ 13 14 #include <linux/init.h> 15 16 #include <linux/mm.h> 17 #include <linux/delay.h> 18 #include <linux/spinlock.h> 19 #include <linux/kernel_stat.h> 20 #include <linux/mc146818rtc.h> 21 #include <linux/cache.h> 22 #include <linux/interrupt.h> 23 #include <linux/cpu.h> 24 #include <linux/gfp.h> 25 26 #include <asm/mtrr.h> 27 #include <asm/tlbflush.h> 28 #include <asm/mmu_context.h> 29 #include <asm/proto.h> 30 #include <asm/apic.h> 31 /* 32 * Some notes on x86 processor bugs affecting SMP operation: 33 * 34 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. 35 * The Linux implications for SMP are handled as follows: 36 * 37 * Pentium III / [Xeon] 38 * None of the E1AP-E3AP errata are visible to the user. 39 * 40 * E1AP. see PII A1AP 41 * E2AP. see PII A2AP 42 * E3AP. see PII A3AP 43 * 44 * Pentium II / [Xeon] 45 * None of the A1AP-A3AP errata are visible to the user. 46 * 47 * A1AP. see PPro 1AP 48 * A2AP. see PPro 2AP 49 * A3AP. see PPro 7AP 50 * 51 * Pentium Pro 52 * None of 1AP-9AP errata are visible to the normal user, 53 * except occasional delivery of 'spurious interrupt' as trap #15. 54 * This is very rare and a non-problem. 55 * 56 * 1AP. Linux maps APIC as non-cacheable 57 * 2AP. worked around in hardware 58 * 3AP. fixed in C0 and above steppings microcode update. 59 * Linux does not use excessive STARTUP_IPIs. 60 * 4AP. worked around in hardware 61 * 5AP. symmetric IO mode (normal Linux operation) not affected. 62 * 'noapic' mode has vector 0xf filled out properly. 63 * 6AP. 'noapic' mode might be affected - fixed in later steppings 64 * 7AP. We do not assume writes to the LVT deassering IRQs 65 * 8AP. We do not enable low power mode (deep sleep) during MP bootup 66 * 9AP. We do not use mixed mode 67 * 68 * Pentium 69 * There is a marginal case where REP MOVS on 100MHz SMP 70 * machines with B stepping processors can fail. XXX should provide 71 * an L1cache=Writethrough or L1cache=off option. 72 * 73 * B stepping CPUs may hang. There are hardware work arounds 74 * for this. We warn about it in case your board doesn't have the work 75 * arounds. Basically that's so I can tell anyone with a B stepping 76 * CPU and SMP problems "tough". 77 * 78 * Specific items [From Pentium Processor Specification Update] 79 * 80 * 1AP. Linux doesn't use remote read 81 * 2AP. Linux doesn't trust APIC errors 82 * 3AP. We work around this 83 * 4AP. Linux never generated 3 interrupts of the same priority 84 * to cause a lost local interrupt. 85 * 5AP. Remote read is never used 86 * 6AP. not affected - worked around in hardware 87 * 7AP. not affected - worked around in hardware 88 * 8AP. worked around in hardware - we get explicit CS errors if not 89 * 9AP. only 'noapic' mode affected. Might generate spurious 90 * interrupts, we log only the first one and count the 91 * rest silently. 92 * 10AP. not affected - worked around in hardware 93 * 11AP. Linux reads the APIC between writes to avoid this, as per 94 * the documentation. Make sure you preserve this as it affects 95 * the C stepping chips too. 96 * 12AP. not affected - worked around in hardware 97 * 13AP. not affected - worked around in hardware 98 * 14AP. we always deassert INIT during bootup 99 * 15AP. not affected - worked around in hardware 100 * 16AP. not affected - worked around in hardware 101 * 17AP. not affected - worked around in hardware 102 * 18AP. not affected - worked around in hardware 103 * 19AP. not affected - worked around in BIOS 104 * 105 * If this sounds worrying believe me these bugs are either ___RARE___, 106 * or are signal timing bugs worked around in hardware and there's 107 * about nothing of note with C stepping upwards. 108 */ 109 110 /* 111 * this function sends a 'reschedule' IPI to another CPU. 112 * it goes straight through and wastes no time serializing 113 * anything. Worst case is that we lose a reschedule ... 114 */ 115 static void native_smp_send_reschedule(int cpu) 116 { 117 if (unlikely(cpu_is_offline(cpu))) { 118 WARN_ON(1); 119 return; 120 } 121 apic->send_IPI_mask(cpumask_of(cpu), RESCHEDULE_VECTOR); 122 } 123 124 void native_send_call_func_single_ipi(int cpu) 125 { 126 apic->send_IPI_mask(cpumask_of(cpu), CALL_FUNCTION_SINGLE_VECTOR); 127 } 128 129 void native_send_call_func_ipi(const struct cpumask *mask) 130 { 131 cpumask_var_t allbutself; 132 133 if (!alloc_cpumask_var(&allbutself, GFP_ATOMIC)) { 134 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 135 return; 136 } 137 138 cpumask_copy(allbutself, cpu_online_mask); 139 cpumask_clear_cpu(smp_processor_id(), allbutself); 140 141 if (cpumask_equal(mask, allbutself) && 142 cpumask_equal(cpu_online_mask, cpu_callout_mask)) 143 apic->send_IPI_allbutself(CALL_FUNCTION_VECTOR); 144 else 145 apic->send_IPI_mask(mask, CALL_FUNCTION_VECTOR); 146 147 free_cpumask_var(allbutself); 148 } 149 150 /* 151 * this function calls the 'stop' function on all other CPUs in the system. 152 */ 153 154 asmlinkage void smp_reboot_interrupt(void) 155 { 156 ack_APIC_irq(); 157 irq_enter(); 158 stop_this_cpu(NULL); 159 irq_exit(); 160 } 161 162 static void native_stop_other_cpus(int wait) 163 { 164 unsigned long flags; 165 unsigned long timeout; 166 167 if (reboot_force) 168 return; 169 170 /* 171 * Use an own vector here because smp_call_function 172 * does lots of things not suitable in a panic situation. 173 * On most systems we could also use an NMI here, 174 * but there are a few systems around where NMI 175 * is problematic so stay with an non NMI for now 176 * (this implies we cannot stop CPUs spinning with irq off 177 * currently) 178 */ 179 if (num_online_cpus() > 1) { 180 apic->send_IPI_allbutself(REBOOT_VECTOR); 181 182 /* 183 * Don't wait longer than a second if the caller 184 * didn't ask us to wait. 185 */ 186 timeout = USEC_PER_SEC; 187 while (num_online_cpus() > 1 && (wait || timeout--)) 188 udelay(1); 189 } 190 191 local_irq_save(flags); 192 disable_local_APIC(); 193 local_irq_restore(flags); 194 } 195 196 /* 197 * Reschedule call back. Nothing to do, 198 * all the work is done automatically when 199 * we return from the interrupt. 200 */ 201 void smp_reschedule_interrupt(struct pt_regs *regs) 202 { 203 ack_APIC_irq(); 204 inc_irq_stat(irq_resched_count); 205 /* 206 * KVM uses this interrupt to force a cpu out of guest mode 207 */ 208 } 209 210 void smp_call_function_interrupt(struct pt_regs *regs) 211 { 212 ack_APIC_irq(); 213 irq_enter(); 214 generic_smp_call_function_interrupt(); 215 inc_irq_stat(irq_call_count); 216 irq_exit(); 217 } 218 219 void smp_call_function_single_interrupt(struct pt_regs *regs) 220 { 221 ack_APIC_irq(); 222 irq_enter(); 223 generic_smp_call_function_single_interrupt(); 224 inc_irq_stat(irq_call_count); 225 irq_exit(); 226 } 227 228 struct smp_ops smp_ops = { 229 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 230 .smp_prepare_cpus = native_smp_prepare_cpus, 231 .smp_cpus_done = native_smp_cpus_done, 232 233 .stop_other_cpus = native_stop_other_cpus, 234 .smp_send_reschedule = native_smp_send_reschedule, 235 236 .cpu_up = native_cpu_up, 237 .cpu_die = native_cpu_die, 238 .cpu_disable = native_cpu_disable, 239 .play_dead = native_play_dead, 240 241 .send_call_func_ipi = native_send_call_func_ipi, 242 .send_call_func_single_ipi = native_send_call_func_single_ipi, 243 }; 244 EXPORT_SYMBOL_GPL(smp_ops); 245