1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Intel SMP support routines. 4 * 5 * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> 6 * (c) 1998-99, 2000, 2009 Ingo Molnar <mingo@redhat.com> 7 * (c) 2002,2003 Andi Kleen, SuSE Labs. 8 * 9 * i386 and x86_64 integration by Glauber Costa <gcosta@redhat.com> 10 */ 11 12 #include <linux/init.h> 13 14 #include <linux/mm.h> 15 #include <linux/delay.h> 16 #include <linux/spinlock.h> 17 #include <linux/export.h> 18 #include <linux/kernel_stat.h> 19 #include <linux/mc146818rtc.h> 20 #include <linux/cache.h> 21 #include <linux/interrupt.h> 22 #include <linux/cpu.h> 23 #include <linux/gfp.h> 24 #include <linux/kexec.h> 25 26 #include <asm/mtrr.h> 27 #include <asm/tlbflush.h> 28 #include <asm/mmu_context.h> 29 #include <asm/proto.h> 30 #include <asm/apic.h> 31 #include <asm/cpu.h> 32 #include <asm/idtentry.h> 33 #include <asm/nmi.h> 34 #include <asm/mce.h> 35 #include <asm/trace/irq_vectors.h> 36 #include <asm/kexec.h> 37 #include <asm/reboot.h> 38 39 /* 40 * Some notes on x86 processor bugs affecting SMP operation: 41 * 42 * Pentium, Pentium Pro, II, III (and all CPUs) have bugs. 43 * The Linux implications for SMP are handled as follows: 44 * 45 * Pentium III / [Xeon] 46 * None of the E1AP-E3AP errata are visible to the user. 47 * 48 * E1AP. see PII A1AP 49 * E2AP. see PII A2AP 50 * E3AP. see PII A3AP 51 * 52 * Pentium II / [Xeon] 53 * None of the A1AP-A3AP errata are visible to the user. 54 * 55 * A1AP. see PPro 1AP 56 * A2AP. see PPro 2AP 57 * A3AP. see PPro 7AP 58 * 59 * Pentium Pro 60 * None of 1AP-9AP errata are visible to the normal user, 61 * except occasional delivery of 'spurious interrupt' as trap #15. 62 * This is very rare and a non-problem. 63 * 64 * 1AP. Linux maps APIC as non-cacheable 65 * 2AP. worked around in hardware 66 * 3AP. fixed in C0 and above steppings microcode update. 67 * Linux does not use excessive STARTUP_IPIs. 68 * 4AP. worked around in hardware 69 * 5AP. symmetric IO mode (normal Linux operation) not affected. 70 * 'noapic' mode has vector 0xf filled out properly. 71 * 6AP. 'noapic' mode might be affected - fixed in later steppings 72 * 7AP. We do not assume writes to the LVT deasserting IRQs 73 * 8AP. We do not enable low power mode (deep sleep) during MP bootup 74 * 9AP. We do not use mixed mode 75 * 76 * Pentium 77 * There is a marginal case where REP MOVS on 100MHz SMP 78 * machines with B stepping processors can fail. XXX should provide 79 * an L1cache=Writethrough or L1cache=off option. 80 * 81 * B stepping CPUs may hang. There are hardware work arounds 82 * for this. We warn about it in case your board doesn't have the work 83 * arounds. Basically that's so I can tell anyone with a B stepping 84 * CPU and SMP problems "tough". 85 * 86 * Specific items [From Pentium Processor Specification Update] 87 * 88 * 1AP. Linux doesn't use remote read 89 * 2AP. Linux doesn't trust APIC errors 90 * 3AP. We work around this 91 * 4AP. Linux never generated 3 interrupts of the same priority 92 * to cause a lost local interrupt. 93 * 5AP. Remote read is never used 94 * 6AP. not affected - worked around in hardware 95 * 7AP. not affected - worked around in hardware 96 * 8AP. worked around in hardware - we get explicit CS errors if not 97 * 9AP. only 'noapic' mode affected. Might generate spurious 98 * interrupts, we log only the first one and count the 99 * rest silently. 100 * 10AP. not affected - worked around in hardware 101 * 11AP. Linux reads the APIC between writes to avoid this, as per 102 * the documentation. Make sure you preserve this as it affects 103 * the C stepping chips too. 104 * 12AP. not affected - worked around in hardware 105 * 13AP. not affected - worked around in hardware 106 * 14AP. we always deassert INIT during bootup 107 * 15AP. not affected - worked around in hardware 108 * 16AP. not affected - worked around in hardware 109 * 17AP. not affected - worked around in hardware 110 * 18AP. not affected - worked around in hardware 111 * 19AP. not affected - worked around in BIOS 112 * 113 * If this sounds worrying believe me these bugs are either ___RARE___, 114 * or are signal timing bugs worked around in hardware and there's 115 * about nothing of note with C stepping upwards. 116 */ 117 118 static atomic_t stopping_cpu = ATOMIC_INIT(-1); 119 static bool smp_no_nmi_ipi = false; 120 121 static int smp_stop_nmi_callback(unsigned int val, struct pt_regs *regs) 122 { 123 /* We are registered on stopping cpu too, avoid spurious NMI */ 124 if (raw_smp_processor_id() == atomic_read(&stopping_cpu)) 125 return NMI_HANDLED; 126 127 cpu_emergency_disable_virtualization(); 128 stop_this_cpu(NULL); 129 130 return NMI_HANDLED; 131 } 132 133 /* 134 * Disable virtualization, APIC etc. and park the CPU in a HLT loop 135 */ 136 DEFINE_IDTENTRY_SYSVEC(sysvec_reboot) 137 { 138 ack_APIC_irq(); 139 cpu_emergency_disable_virtualization(); 140 stop_this_cpu(NULL); 141 } 142 143 static int register_stop_handler(void) 144 { 145 return register_nmi_handler(NMI_LOCAL, smp_stop_nmi_callback, 146 NMI_FLAG_FIRST, "smp_stop"); 147 } 148 149 static void native_stop_other_cpus(int wait) 150 { 151 unsigned int cpu = smp_processor_id(); 152 unsigned long flags, timeout; 153 154 if (reboot_force) 155 return; 156 157 /* Only proceed if this is the first CPU to reach this code */ 158 if (atomic_cmpxchg(&stopping_cpu, -1, cpu) != -1) 159 return; 160 161 /* For kexec, ensure that offline CPUs are out of MWAIT and in HLT */ 162 if (kexec_in_progress) 163 smp_kick_mwait_play_dead(); 164 165 /* 166 * 1) Send an IPI on the reboot vector to all other CPUs. 167 * 168 * The other CPUs should react on it after leaving critical 169 * sections and re-enabling interrupts. They might still hold 170 * locks, but there is nothing which can be done about that. 171 * 172 * 2) Wait for all other CPUs to report that they reached the 173 * HLT loop in stop_this_cpu() 174 * 175 * 3) If the system uses INIT/STARTUP for CPU bringup, then 176 * send all present CPUs an INIT vector, which brings them 177 * completely out of the way. 178 * 179 * 4) If #3 is not possible and #2 timed out send an NMI to the 180 * CPUs which did not yet report 181 * 182 * 5) Wait for all other CPUs to report that they reached the 183 * HLT loop in stop_this_cpu() 184 * 185 * #4 can obviously race against a CPU reaching the HLT loop late. 186 * That CPU will have reported already and the "have all CPUs 187 * reached HLT" condition will be true despite the fact that the 188 * other CPU is still handling the NMI. Again, there is no 189 * protection against that as "disabled" APICs still respond to 190 * NMIs. 191 */ 192 cpumask_copy(&cpus_stop_mask, cpu_online_mask); 193 cpumask_clear_cpu(cpu, &cpus_stop_mask); 194 195 if (!cpumask_empty(&cpus_stop_mask)) { 196 apic_send_IPI_allbutself(REBOOT_VECTOR); 197 198 /* 199 * Don't wait longer than a second for IPI completion. The 200 * wait request is not checked here because that would 201 * prevent an NMI/INIT shutdown in case that not all 202 * CPUs reach shutdown state. 203 */ 204 timeout = USEC_PER_SEC; 205 while (!cpumask_empty(&cpus_stop_mask) && timeout--) 206 udelay(1); 207 } 208 209 /* 210 * Park all other CPUs in INIT including "offline" CPUs, if 211 * possible. That's a safe place where they can't resume execution 212 * of HLT and then execute the HLT loop from overwritten text or 213 * page tables. 214 * 215 * The only downside is a broadcast MCE, but up to the point where 216 * the kexec() kernel brought all APs online again an MCE will just 217 * make HLT resume and handle the MCE. The machine crashes and burns 218 * due to overwritten text, page tables and data. So there is a 219 * choice between fire and frying pan. The result is pretty much 220 * the same. Chose frying pan until x86 provides a sane mechanism 221 * to park a CPU. 222 */ 223 if (smp_park_other_cpus_in_init()) 224 goto done; 225 226 /* 227 * If park with INIT was not possible and the REBOOT_VECTOR didn't 228 * take all secondary CPUs offline, try with the NMI. 229 */ 230 if (!cpumask_empty(&cpus_stop_mask)) { 231 /* 232 * If NMI IPI is enabled, try to register the stop handler 233 * and send the IPI. In any case try to wait for the other 234 * CPUs to stop. 235 */ 236 if (!smp_no_nmi_ipi && !register_stop_handler()) { 237 pr_emerg("Shutting down cpus with NMI\n"); 238 239 for_each_cpu(cpu, &cpus_stop_mask) 240 apic->send_IPI(cpu, NMI_VECTOR); 241 } 242 /* 243 * Don't wait longer than 10 ms if the caller didn't 244 * request it. If wait is true, the machine hangs here if 245 * one or more CPUs do not reach shutdown state. 246 */ 247 timeout = USEC_PER_MSEC * 10; 248 while (!cpumask_empty(&cpus_stop_mask) && (wait || timeout--)) 249 udelay(1); 250 } 251 252 done: 253 local_irq_save(flags); 254 disable_local_APIC(); 255 mcheck_cpu_clear(this_cpu_ptr(&cpu_info)); 256 local_irq_restore(flags); 257 258 /* 259 * Ensure that the cpus_stop_mask cache lines are invalidated on 260 * the other CPUs. See comment vs. SME in stop_this_cpu(). 261 */ 262 cpumask_clear(&cpus_stop_mask); 263 } 264 265 /* 266 * Reschedule call back. KVM uses this interrupt to force a cpu out of 267 * guest mode. 268 */ 269 DEFINE_IDTENTRY_SYSVEC_SIMPLE(sysvec_reschedule_ipi) 270 { 271 ack_APIC_irq(); 272 trace_reschedule_entry(RESCHEDULE_VECTOR); 273 inc_irq_stat(irq_resched_count); 274 scheduler_ipi(); 275 trace_reschedule_exit(RESCHEDULE_VECTOR); 276 } 277 278 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function) 279 { 280 ack_APIC_irq(); 281 trace_call_function_entry(CALL_FUNCTION_VECTOR); 282 inc_irq_stat(irq_call_count); 283 generic_smp_call_function_interrupt(); 284 trace_call_function_exit(CALL_FUNCTION_VECTOR); 285 } 286 287 DEFINE_IDTENTRY_SYSVEC(sysvec_call_function_single) 288 { 289 ack_APIC_irq(); 290 trace_call_function_single_entry(CALL_FUNCTION_SINGLE_VECTOR); 291 inc_irq_stat(irq_call_count); 292 generic_smp_call_function_single_interrupt(); 293 trace_call_function_single_exit(CALL_FUNCTION_SINGLE_VECTOR); 294 } 295 296 static int __init nonmi_ipi_setup(char *str) 297 { 298 smp_no_nmi_ipi = true; 299 return 1; 300 } 301 302 __setup("nonmi_ipi", nonmi_ipi_setup); 303 304 struct smp_ops smp_ops = { 305 .smp_prepare_boot_cpu = native_smp_prepare_boot_cpu, 306 .smp_prepare_cpus = native_smp_prepare_cpus, 307 .smp_cpus_done = native_smp_cpus_done, 308 309 .stop_other_cpus = native_stop_other_cpus, 310 #if defined(CONFIG_KEXEC_CORE) 311 .crash_stop_other_cpus = kdump_nmi_shootdown_cpus, 312 #endif 313 .smp_send_reschedule = native_smp_send_reschedule, 314 315 .kick_ap_alive = native_kick_ap, 316 .cpu_disable = native_cpu_disable, 317 .play_dead = native_play_dead, 318 319 .send_call_func_ipi = native_send_call_func_ipi, 320 .send_call_func_single_ipi = native_send_call_func_single_ipi, 321 }; 322 EXPORT_SYMBOL_GPL(smp_ops); 323