1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * AMD Memory Encryption Support 4 * 5 * Copyright (C) 2019 SUSE 6 * 7 * Author: Joerg Roedel <jroedel@suse.de> 8 */ 9 10 #define pr_fmt(fmt) "SEV: " fmt 11 12 #include <linux/sched/debug.h> /* For show_regs() */ 13 #include <linux/percpu-defs.h> 14 #include <linux/cc_platform.h> 15 #include <linux/printk.h> 16 #include <linux/mm_types.h> 17 #include <linux/set_memory.h> 18 #include <linux/memblock.h> 19 #include <linux/kernel.h> 20 #include <linux/mm.h> 21 #include <linux/cpumask.h> 22 #include <linux/efi.h> 23 #include <linux/platform_device.h> 24 #include <linux/io.h> 25 26 #include <asm/cpu_entry_area.h> 27 #include <asm/stacktrace.h> 28 #include <asm/sev.h> 29 #include <asm/insn-eval.h> 30 #include <asm/fpu/xcr.h> 31 #include <asm/processor.h> 32 #include <asm/realmode.h> 33 #include <asm/setup.h> 34 #include <asm/traps.h> 35 #include <asm/svm.h> 36 #include <asm/smp.h> 37 #include <asm/cpu.h> 38 #include <asm/apic.h> 39 #include <asm/cpuid.h> 40 #include <asm/cmdline.h> 41 42 #define DR7_RESET_VALUE 0x400 43 44 /* AP INIT values as documented in the APM2 section "Processor Initialization State" */ 45 #define AP_INIT_CS_LIMIT 0xffff 46 #define AP_INIT_DS_LIMIT 0xffff 47 #define AP_INIT_LDTR_LIMIT 0xffff 48 #define AP_INIT_GDTR_LIMIT 0xffff 49 #define AP_INIT_IDTR_LIMIT 0xffff 50 #define AP_INIT_TR_LIMIT 0xffff 51 #define AP_INIT_RFLAGS_DEFAULT 0x2 52 #define AP_INIT_DR6_DEFAULT 0xffff0ff0 53 #define AP_INIT_GPAT_DEFAULT 0x0007040600070406ULL 54 #define AP_INIT_XCR0_DEFAULT 0x1 55 #define AP_INIT_X87_FTW_DEFAULT 0x5555 56 #define AP_INIT_X87_FCW_DEFAULT 0x0040 57 #define AP_INIT_CR0_DEFAULT 0x60000010 58 #define AP_INIT_MXCSR_DEFAULT 0x1f80 59 60 /* For early boot hypervisor communication in SEV-ES enabled guests */ 61 static struct ghcb boot_ghcb_page __bss_decrypted __aligned(PAGE_SIZE); 62 63 /* 64 * Needs to be in the .data section because we need it NULL before bss is 65 * cleared 66 */ 67 static struct ghcb *boot_ghcb __section(".data"); 68 69 /* Bitmap of SEV features supported by the hypervisor */ 70 static u64 sev_hv_features __ro_after_init; 71 72 /* #VC handler runtime per-CPU data */ 73 struct sev_es_runtime_data { 74 struct ghcb ghcb_page; 75 76 /* 77 * Reserve one page per CPU as backup storage for the unencrypted GHCB. 78 * It is needed when an NMI happens while the #VC handler uses the real 79 * GHCB, and the NMI handler itself is causing another #VC exception. In 80 * that case the GHCB content of the first handler needs to be backed up 81 * and restored. 82 */ 83 struct ghcb backup_ghcb; 84 85 /* 86 * Mark the per-cpu GHCBs as in-use to detect nested #VC exceptions. 87 * There is no need for it to be atomic, because nothing is written to 88 * the GHCB between the read and the write of ghcb_active. So it is safe 89 * to use it when a nested #VC exception happens before the write. 90 * 91 * This is necessary for example in the #VC->NMI->#VC case when the NMI 92 * happens while the first #VC handler uses the GHCB. When the NMI code 93 * raises a second #VC handler it might overwrite the contents of the 94 * GHCB written by the first handler. To avoid this the content of the 95 * GHCB is saved and restored when the GHCB is detected to be in use 96 * already. 97 */ 98 bool ghcb_active; 99 bool backup_ghcb_active; 100 101 /* 102 * Cached DR7 value - write it on DR7 writes and return it on reads. 103 * That value will never make it to the real hardware DR7 as debugging 104 * is currently unsupported in SEV-ES guests. 105 */ 106 unsigned long dr7; 107 }; 108 109 struct ghcb_state { 110 struct ghcb *ghcb; 111 }; 112 113 static DEFINE_PER_CPU(struct sev_es_runtime_data*, runtime_data); 114 DEFINE_STATIC_KEY_FALSE(sev_es_enable_key); 115 116 static DEFINE_PER_CPU(struct sev_es_save_area *, sev_vmsa); 117 118 struct sev_config { 119 __u64 debug : 1, 120 __reserved : 63; 121 }; 122 123 static struct sev_config sev_cfg __read_mostly; 124 125 static __always_inline bool on_vc_stack(struct pt_regs *regs) 126 { 127 unsigned long sp = regs->sp; 128 129 /* User-mode RSP is not trusted */ 130 if (user_mode(regs)) 131 return false; 132 133 /* SYSCALL gap still has user-mode RSP */ 134 if (ip_within_syscall_gap(regs)) 135 return false; 136 137 return ((sp >= __this_cpu_ist_bottom_va(VC)) && (sp < __this_cpu_ist_top_va(VC))); 138 } 139 140 /* 141 * This function handles the case when an NMI is raised in the #VC 142 * exception handler entry code, before the #VC handler has switched off 143 * its IST stack. In this case, the IST entry for #VC must be adjusted, 144 * so that any nested #VC exception will not overwrite the stack 145 * contents of the interrupted #VC handler. 146 * 147 * The IST entry is adjusted unconditionally so that it can be also be 148 * unconditionally adjusted back in __sev_es_ist_exit(). Otherwise a 149 * nested sev_es_ist_exit() call may adjust back the IST entry too 150 * early. 151 * 152 * The __sev_es_ist_enter() and __sev_es_ist_exit() functions always run 153 * on the NMI IST stack, as they are only called from NMI handling code 154 * right now. 155 */ 156 void noinstr __sev_es_ist_enter(struct pt_regs *regs) 157 { 158 unsigned long old_ist, new_ist; 159 160 /* Read old IST entry */ 161 new_ist = old_ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]); 162 163 /* 164 * If NMI happened while on the #VC IST stack, set the new IST 165 * value below regs->sp, so that the interrupted stack frame is 166 * not overwritten by subsequent #VC exceptions. 167 */ 168 if (on_vc_stack(regs)) 169 new_ist = regs->sp; 170 171 /* 172 * Reserve additional 8 bytes and store old IST value so this 173 * adjustment can be unrolled in __sev_es_ist_exit(). 174 */ 175 new_ist -= sizeof(old_ist); 176 *(unsigned long *)new_ist = old_ist; 177 178 /* Set new IST entry */ 179 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], new_ist); 180 } 181 182 void noinstr __sev_es_ist_exit(void) 183 { 184 unsigned long ist; 185 186 /* Read IST entry */ 187 ist = __this_cpu_read(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC]); 188 189 if (WARN_ON(ist == __this_cpu_ist_top_va(VC))) 190 return; 191 192 /* Read back old IST entry and write it to the TSS */ 193 this_cpu_write(cpu_tss_rw.x86_tss.ist[IST_INDEX_VC], *(unsigned long *)ist); 194 } 195 196 /* 197 * Nothing shall interrupt this code path while holding the per-CPU 198 * GHCB. The backup GHCB is only for NMIs interrupting this path. 199 * 200 * Callers must disable local interrupts around it. 201 */ 202 static noinstr struct ghcb *__sev_get_ghcb(struct ghcb_state *state) 203 { 204 struct sev_es_runtime_data *data; 205 struct ghcb *ghcb; 206 207 WARN_ON(!irqs_disabled()); 208 209 data = this_cpu_read(runtime_data); 210 ghcb = &data->ghcb_page; 211 212 if (unlikely(data->ghcb_active)) { 213 /* GHCB is already in use - save its contents */ 214 215 if (unlikely(data->backup_ghcb_active)) { 216 /* 217 * Backup-GHCB is also already in use. There is no way 218 * to continue here so just kill the machine. To make 219 * panic() work, mark GHCBs inactive so that messages 220 * can be printed out. 221 */ 222 data->ghcb_active = false; 223 data->backup_ghcb_active = false; 224 225 instrumentation_begin(); 226 panic("Unable to handle #VC exception! GHCB and Backup GHCB are already in use"); 227 instrumentation_end(); 228 } 229 230 /* Mark backup_ghcb active before writing to it */ 231 data->backup_ghcb_active = true; 232 233 state->ghcb = &data->backup_ghcb; 234 235 /* Backup GHCB content */ 236 *state->ghcb = *ghcb; 237 } else { 238 state->ghcb = NULL; 239 data->ghcb_active = true; 240 } 241 242 return ghcb; 243 } 244 245 static inline u64 sev_es_rd_ghcb_msr(void) 246 { 247 return __rdmsr(MSR_AMD64_SEV_ES_GHCB); 248 } 249 250 static __always_inline void sev_es_wr_ghcb_msr(u64 val) 251 { 252 u32 low, high; 253 254 low = (u32)(val); 255 high = (u32)(val >> 32); 256 257 native_wrmsr(MSR_AMD64_SEV_ES_GHCB, low, high); 258 } 259 260 static int vc_fetch_insn_kernel(struct es_em_ctxt *ctxt, 261 unsigned char *buffer) 262 { 263 return copy_from_kernel_nofault(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE); 264 } 265 266 static enum es_result __vc_decode_user_insn(struct es_em_ctxt *ctxt) 267 { 268 char buffer[MAX_INSN_SIZE]; 269 int insn_bytes; 270 271 insn_bytes = insn_fetch_from_user_inatomic(ctxt->regs, buffer); 272 if (insn_bytes == 0) { 273 /* Nothing could be copied */ 274 ctxt->fi.vector = X86_TRAP_PF; 275 ctxt->fi.error_code = X86_PF_INSTR | X86_PF_USER; 276 ctxt->fi.cr2 = ctxt->regs->ip; 277 return ES_EXCEPTION; 278 } else if (insn_bytes == -EINVAL) { 279 /* Effective RIP could not be calculated */ 280 ctxt->fi.vector = X86_TRAP_GP; 281 ctxt->fi.error_code = 0; 282 ctxt->fi.cr2 = 0; 283 return ES_EXCEPTION; 284 } 285 286 if (!insn_decode_from_regs(&ctxt->insn, ctxt->regs, buffer, insn_bytes)) 287 return ES_DECODE_FAILED; 288 289 if (ctxt->insn.immediate.got) 290 return ES_OK; 291 else 292 return ES_DECODE_FAILED; 293 } 294 295 static enum es_result __vc_decode_kern_insn(struct es_em_ctxt *ctxt) 296 { 297 char buffer[MAX_INSN_SIZE]; 298 int res, ret; 299 300 res = vc_fetch_insn_kernel(ctxt, buffer); 301 if (res) { 302 ctxt->fi.vector = X86_TRAP_PF; 303 ctxt->fi.error_code = X86_PF_INSTR; 304 ctxt->fi.cr2 = ctxt->regs->ip; 305 return ES_EXCEPTION; 306 } 307 308 ret = insn_decode(&ctxt->insn, buffer, MAX_INSN_SIZE, INSN_MODE_64); 309 if (ret < 0) 310 return ES_DECODE_FAILED; 311 else 312 return ES_OK; 313 } 314 315 static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt) 316 { 317 if (user_mode(ctxt->regs)) 318 return __vc_decode_user_insn(ctxt); 319 else 320 return __vc_decode_kern_insn(ctxt); 321 } 322 323 static enum es_result vc_write_mem(struct es_em_ctxt *ctxt, 324 char *dst, char *buf, size_t size) 325 { 326 unsigned long error_code = X86_PF_PROT | X86_PF_WRITE; 327 328 /* 329 * This function uses __put_user() independent of whether kernel or user 330 * memory is accessed. This works fine because __put_user() does no 331 * sanity checks of the pointer being accessed. All that it does is 332 * to report when the access failed. 333 * 334 * Also, this function runs in atomic context, so __put_user() is not 335 * allowed to sleep. The page-fault handler detects that it is running 336 * in atomic context and will not try to take mmap_sem and handle the 337 * fault, so additional pagefault_enable()/disable() calls are not 338 * needed. 339 * 340 * The access can't be done via copy_to_user() here because 341 * vc_write_mem() must not use string instructions to access unsafe 342 * memory. The reason is that MOVS is emulated by the #VC handler by 343 * splitting the move up into a read and a write and taking a nested #VC 344 * exception on whatever of them is the MMIO access. Using string 345 * instructions here would cause infinite nesting. 346 */ 347 switch (size) { 348 case 1: { 349 u8 d1; 350 u8 __user *target = (u8 __user *)dst; 351 352 memcpy(&d1, buf, 1); 353 if (__put_user(d1, target)) 354 goto fault; 355 break; 356 } 357 case 2: { 358 u16 d2; 359 u16 __user *target = (u16 __user *)dst; 360 361 memcpy(&d2, buf, 2); 362 if (__put_user(d2, target)) 363 goto fault; 364 break; 365 } 366 case 4: { 367 u32 d4; 368 u32 __user *target = (u32 __user *)dst; 369 370 memcpy(&d4, buf, 4); 371 if (__put_user(d4, target)) 372 goto fault; 373 break; 374 } 375 case 8: { 376 u64 d8; 377 u64 __user *target = (u64 __user *)dst; 378 379 memcpy(&d8, buf, 8); 380 if (__put_user(d8, target)) 381 goto fault; 382 break; 383 } 384 default: 385 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size); 386 return ES_UNSUPPORTED; 387 } 388 389 return ES_OK; 390 391 fault: 392 if (user_mode(ctxt->regs)) 393 error_code |= X86_PF_USER; 394 395 ctxt->fi.vector = X86_TRAP_PF; 396 ctxt->fi.error_code = error_code; 397 ctxt->fi.cr2 = (unsigned long)dst; 398 399 return ES_EXCEPTION; 400 } 401 402 static enum es_result vc_read_mem(struct es_em_ctxt *ctxt, 403 char *src, char *buf, size_t size) 404 { 405 unsigned long error_code = X86_PF_PROT; 406 407 /* 408 * This function uses __get_user() independent of whether kernel or user 409 * memory is accessed. This works fine because __get_user() does no 410 * sanity checks of the pointer being accessed. All that it does is 411 * to report when the access failed. 412 * 413 * Also, this function runs in atomic context, so __get_user() is not 414 * allowed to sleep. The page-fault handler detects that it is running 415 * in atomic context and will not try to take mmap_sem and handle the 416 * fault, so additional pagefault_enable()/disable() calls are not 417 * needed. 418 * 419 * The access can't be done via copy_from_user() here because 420 * vc_read_mem() must not use string instructions to access unsafe 421 * memory. The reason is that MOVS is emulated by the #VC handler by 422 * splitting the move up into a read and a write and taking a nested #VC 423 * exception on whatever of them is the MMIO access. Using string 424 * instructions here would cause infinite nesting. 425 */ 426 switch (size) { 427 case 1: { 428 u8 d1; 429 u8 __user *s = (u8 __user *)src; 430 431 if (__get_user(d1, s)) 432 goto fault; 433 memcpy(buf, &d1, 1); 434 break; 435 } 436 case 2: { 437 u16 d2; 438 u16 __user *s = (u16 __user *)src; 439 440 if (__get_user(d2, s)) 441 goto fault; 442 memcpy(buf, &d2, 2); 443 break; 444 } 445 case 4: { 446 u32 d4; 447 u32 __user *s = (u32 __user *)src; 448 449 if (__get_user(d4, s)) 450 goto fault; 451 memcpy(buf, &d4, 4); 452 break; 453 } 454 case 8: { 455 u64 d8; 456 u64 __user *s = (u64 __user *)src; 457 if (__get_user(d8, s)) 458 goto fault; 459 memcpy(buf, &d8, 8); 460 break; 461 } 462 default: 463 WARN_ONCE(1, "%s: Invalid size: %zu\n", __func__, size); 464 return ES_UNSUPPORTED; 465 } 466 467 return ES_OK; 468 469 fault: 470 if (user_mode(ctxt->regs)) 471 error_code |= X86_PF_USER; 472 473 ctxt->fi.vector = X86_TRAP_PF; 474 ctxt->fi.error_code = error_code; 475 ctxt->fi.cr2 = (unsigned long)src; 476 477 return ES_EXCEPTION; 478 } 479 480 static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt, 481 unsigned long vaddr, phys_addr_t *paddr) 482 { 483 unsigned long va = (unsigned long)vaddr; 484 unsigned int level; 485 phys_addr_t pa; 486 pgd_t *pgd; 487 pte_t *pte; 488 489 pgd = __va(read_cr3_pa()); 490 pgd = &pgd[pgd_index(va)]; 491 pte = lookup_address_in_pgd(pgd, va, &level); 492 if (!pte) { 493 ctxt->fi.vector = X86_TRAP_PF; 494 ctxt->fi.cr2 = vaddr; 495 ctxt->fi.error_code = 0; 496 497 if (user_mode(ctxt->regs)) 498 ctxt->fi.error_code |= X86_PF_USER; 499 500 return ES_EXCEPTION; 501 } 502 503 if (WARN_ON_ONCE(pte_val(*pte) & _PAGE_ENC)) 504 /* Emulated MMIO to/from encrypted memory not supported */ 505 return ES_UNSUPPORTED; 506 507 pa = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT; 508 pa |= va & ~page_level_mask(level); 509 510 *paddr = pa; 511 512 return ES_OK; 513 } 514 515 /* Include code shared with pre-decompression boot stage */ 516 #include "sev-shared.c" 517 518 static noinstr void __sev_put_ghcb(struct ghcb_state *state) 519 { 520 struct sev_es_runtime_data *data; 521 struct ghcb *ghcb; 522 523 WARN_ON(!irqs_disabled()); 524 525 data = this_cpu_read(runtime_data); 526 ghcb = &data->ghcb_page; 527 528 if (state->ghcb) { 529 /* Restore GHCB from Backup */ 530 *ghcb = *state->ghcb; 531 data->backup_ghcb_active = false; 532 state->ghcb = NULL; 533 } else { 534 /* 535 * Invalidate the GHCB so a VMGEXIT instruction issued 536 * from userspace won't appear to be valid. 537 */ 538 vc_ghcb_invalidate(ghcb); 539 data->ghcb_active = false; 540 } 541 } 542 543 void noinstr __sev_es_nmi_complete(void) 544 { 545 struct ghcb_state state; 546 struct ghcb *ghcb; 547 548 ghcb = __sev_get_ghcb(&state); 549 550 vc_ghcb_invalidate(ghcb); 551 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_NMI_COMPLETE); 552 ghcb_set_sw_exit_info_1(ghcb, 0); 553 ghcb_set_sw_exit_info_2(ghcb, 0); 554 555 sev_es_wr_ghcb_msr(__pa_nodebug(ghcb)); 556 VMGEXIT(); 557 558 __sev_put_ghcb(&state); 559 } 560 561 static u64 get_jump_table_addr(void) 562 { 563 struct ghcb_state state; 564 unsigned long flags; 565 struct ghcb *ghcb; 566 u64 ret = 0; 567 568 local_irq_save(flags); 569 570 ghcb = __sev_get_ghcb(&state); 571 572 vc_ghcb_invalidate(ghcb); 573 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_JUMP_TABLE); 574 ghcb_set_sw_exit_info_1(ghcb, SVM_VMGEXIT_GET_AP_JUMP_TABLE); 575 ghcb_set_sw_exit_info_2(ghcb, 0); 576 577 sev_es_wr_ghcb_msr(__pa(ghcb)); 578 VMGEXIT(); 579 580 if (ghcb_sw_exit_info_1_is_valid(ghcb) && 581 ghcb_sw_exit_info_2_is_valid(ghcb)) 582 ret = ghcb->save.sw_exit_info_2; 583 584 __sev_put_ghcb(&state); 585 586 local_irq_restore(flags); 587 588 return ret; 589 } 590 591 static void pvalidate_pages(unsigned long vaddr, unsigned int npages, bool validate) 592 { 593 unsigned long vaddr_end; 594 int rc; 595 596 vaddr = vaddr & PAGE_MASK; 597 vaddr_end = vaddr + (npages << PAGE_SHIFT); 598 599 while (vaddr < vaddr_end) { 600 rc = pvalidate(vaddr, RMP_PG_SIZE_4K, validate); 601 if (WARN(rc, "Failed to validate address 0x%lx ret %d", vaddr, rc)) 602 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PVALIDATE); 603 604 vaddr = vaddr + PAGE_SIZE; 605 } 606 } 607 608 static void __init early_set_pages_state(unsigned long paddr, unsigned int npages, enum psc_op op) 609 { 610 unsigned long paddr_end; 611 u64 val; 612 613 paddr = paddr & PAGE_MASK; 614 paddr_end = paddr + (npages << PAGE_SHIFT); 615 616 while (paddr < paddr_end) { 617 /* 618 * Use the MSR protocol because this function can be called before 619 * the GHCB is established. 620 */ 621 sev_es_wr_ghcb_msr(GHCB_MSR_PSC_REQ_GFN(paddr >> PAGE_SHIFT, op)); 622 VMGEXIT(); 623 624 val = sev_es_rd_ghcb_msr(); 625 626 if (WARN(GHCB_RESP_CODE(val) != GHCB_MSR_PSC_RESP, 627 "Wrong PSC response code: 0x%x\n", 628 (unsigned int)GHCB_RESP_CODE(val))) 629 goto e_term; 630 631 if (WARN(GHCB_MSR_PSC_RESP_VAL(val), 632 "Failed to change page state to '%s' paddr 0x%lx error 0x%llx\n", 633 op == SNP_PAGE_STATE_PRIVATE ? "private" : "shared", 634 paddr, GHCB_MSR_PSC_RESP_VAL(val))) 635 goto e_term; 636 637 paddr = paddr + PAGE_SIZE; 638 } 639 640 return; 641 642 e_term: 643 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); 644 } 645 646 void __init early_snp_set_memory_private(unsigned long vaddr, unsigned long paddr, 647 unsigned int npages) 648 { 649 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 650 return; 651 652 /* 653 * Ask the hypervisor to mark the memory pages as private in the RMP 654 * table. 655 */ 656 early_set_pages_state(paddr, npages, SNP_PAGE_STATE_PRIVATE); 657 658 /* Validate the memory pages after they've been added in the RMP table. */ 659 pvalidate_pages(vaddr, npages, true); 660 } 661 662 void __init early_snp_set_memory_shared(unsigned long vaddr, unsigned long paddr, 663 unsigned int npages) 664 { 665 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 666 return; 667 668 /* Invalidate the memory pages before they are marked shared in the RMP table. */ 669 pvalidate_pages(vaddr, npages, false); 670 671 /* Ask hypervisor to mark the memory pages shared in the RMP table. */ 672 early_set_pages_state(paddr, npages, SNP_PAGE_STATE_SHARED); 673 } 674 675 void __init snp_prep_memory(unsigned long paddr, unsigned int sz, enum psc_op op) 676 { 677 unsigned long vaddr, npages; 678 679 vaddr = (unsigned long)__va(paddr); 680 npages = PAGE_ALIGN(sz) >> PAGE_SHIFT; 681 682 if (op == SNP_PAGE_STATE_PRIVATE) 683 early_snp_set_memory_private(vaddr, paddr, npages); 684 else if (op == SNP_PAGE_STATE_SHARED) 685 early_snp_set_memory_shared(vaddr, paddr, npages); 686 else 687 WARN(1, "invalid memory op %d\n", op); 688 } 689 690 static int vmgexit_psc(struct snp_psc_desc *desc) 691 { 692 int cur_entry, end_entry, ret = 0; 693 struct snp_psc_desc *data; 694 struct ghcb_state state; 695 struct es_em_ctxt ctxt; 696 unsigned long flags; 697 struct ghcb *ghcb; 698 699 /* 700 * __sev_get_ghcb() needs to run with IRQs disabled because it is using 701 * a per-CPU GHCB. 702 */ 703 local_irq_save(flags); 704 705 ghcb = __sev_get_ghcb(&state); 706 if (!ghcb) { 707 ret = 1; 708 goto out_unlock; 709 } 710 711 /* Copy the input desc into GHCB shared buffer */ 712 data = (struct snp_psc_desc *)ghcb->shared_buffer; 713 memcpy(ghcb->shared_buffer, desc, min_t(int, GHCB_SHARED_BUF_SIZE, sizeof(*desc))); 714 715 /* 716 * As per the GHCB specification, the hypervisor can resume the guest 717 * before processing all the entries. Check whether all the entries 718 * are processed. If not, then keep retrying. Note, the hypervisor 719 * will update the data memory directly to indicate the status, so 720 * reference the data->hdr everywhere. 721 * 722 * The strategy here is to wait for the hypervisor to change the page 723 * state in the RMP table before guest accesses the memory pages. If the 724 * page state change was not successful, then later memory access will 725 * result in a crash. 726 */ 727 cur_entry = data->hdr.cur_entry; 728 end_entry = data->hdr.end_entry; 729 730 while (data->hdr.cur_entry <= data->hdr.end_entry) { 731 ghcb_set_sw_scratch(ghcb, (u64)__pa(data)); 732 733 /* This will advance the shared buffer data points to. */ 734 ret = sev_es_ghcb_hv_call(ghcb, true, &ctxt, SVM_VMGEXIT_PSC, 0, 0); 735 736 /* 737 * Page State Change VMGEXIT can pass error code through 738 * exit_info_2. 739 */ 740 if (WARN(ret || ghcb->save.sw_exit_info_2, 741 "SNP: PSC failed ret=%d exit_info_2=%llx\n", 742 ret, ghcb->save.sw_exit_info_2)) { 743 ret = 1; 744 goto out; 745 } 746 747 /* Verify that reserved bit is not set */ 748 if (WARN(data->hdr.reserved, "Reserved bit is set in the PSC header\n")) { 749 ret = 1; 750 goto out; 751 } 752 753 /* 754 * Sanity check that entry processing is not going backwards. 755 * This will happen only if hypervisor is tricking us. 756 */ 757 if (WARN(data->hdr.end_entry > end_entry || cur_entry > data->hdr.cur_entry, 758 "SNP: PSC processing going backward, end_entry %d (got %d) cur_entry %d (got %d)\n", 759 end_entry, data->hdr.end_entry, cur_entry, data->hdr.cur_entry)) { 760 ret = 1; 761 goto out; 762 } 763 } 764 765 out: 766 __sev_put_ghcb(&state); 767 768 out_unlock: 769 local_irq_restore(flags); 770 771 return ret; 772 } 773 774 static void __set_pages_state(struct snp_psc_desc *data, unsigned long vaddr, 775 unsigned long vaddr_end, int op) 776 { 777 struct psc_hdr *hdr; 778 struct psc_entry *e; 779 unsigned long pfn; 780 int i; 781 782 hdr = &data->hdr; 783 e = data->entries; 784 785 memset(data, 0, sizeof(*data)); 786 i = 0; 787 788 while (vaddr < vaddr_end) { 789 if (is_vmalloc_addr((void *)vaddr)) 790 pfn = vmalloc_to_pfn((void *)vaddr); 791 else 792 pfn = __pa(vaddr) >> PAGE_SHIFT; 793 794 e->gfn = pfn; 795 e->operation = op; 796 hdr->end_entry = i; 797 798 /* 799 * Current SNP implementation doesn't keep track of the RMP page 800 * size so use 4K for simplicity. 801 */ 802 e->pagesize = RMP_PG_SIZE_4K; 803 804 vaddr = vaddr + PAGE_SIZE; 805 e++; 806 i++; 807 } 808 809 if (vmgexit_psc(data)) 810 sev_es_terminate(SEV_TERM_SET_LINUX, GHCB_TERM_PSC); 811 } 812 813 static void set_pages_state(unsigned long vaddr, unsigned int npages, int op) 814 { 815 unsigned long vaddr_end, next_vaddr; 816 struct snp_psc_desc *desc; 817 818 desc = kmalloc(sizeof(*desc), GFP_KERNEL_ACCOUNT); 819 if (!desc) 820 panic("SNP: failed to allocate memory for PSC descriptor\n"); 821 822 vaddr = vaddr & PAGE_MASK; 823 vaddr_end = vaddr + (npages << PAGE_SHIFT); 824 825 while (vaddr < vaddr_end) { 826 /* Calculate the last vaddr that fits in one struct snp_psc_desc. */ 827 next_vaddr = min_t(unsigned long, vaddr_end, 828 (VMGEXIT_PSC_MAX_ENTRY * PAGE_SIZE) + vaddr); 829 830 __set_pages_state(desc, vaddr, next_vaddr, op); 831 832 vaddr = next_vaddr; 833 } 834 835 kfree(desc); 836 } 837 838 void snp_set_memory_shared(unsigned long vaddr, unsigned int npages) 839 { 840 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 841 return; 842 843 pvalidate_pages(vaddr, npages, false); 844 845 set_pages_state(vaddr, npages, SNP_PAGE_STATE_SHARED); 846 } 847 848 void snp_set_memory_private(unsigned long vaddr, unsigned int npages) 849 { 850 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 851 return; 852 853 set_pages_state(vaddr, npages, SNP_PAGE_STATE_PRIVATE); 854 855 pvalidate_pages(vaddr, npages, true); 856 } 857 858 static int snp_set_vmsa(void *va, bool vmsa) 859 { 860 u64 attrs; 861 862 /* 863 * Running at VMPL0 allows the kernel to change the VMSA bit for a page 864 * using the RMPADJUST instruction. However, for the instruction to 865 * succeed it must target the permissions of a lesser privileged 866 * (higher numbered) VMPL level, so use VMPL1 (refer to the RMPADJUST 867 * instruction in the AMD64 APM Volume 3). 868 */ 869 attrs = 1; 870 if (vmsa) 871 attrs |= RMPADJUST_VMSA_PAGE_BIT; 872 873 return rmpadjust((unsigned long)va, RMP_PG_SIZE_4K, attrs); 874 } 875 876 #define __ATTR_BASE (SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK) 877 #define INIT_CS_ATTRIBS (__ATTR_BASE | SVM_SELECTOR_READ_MASK | SVM_SELECTOR_CODE_MASK) 878 #define INIT_DS_ATTRIBS (__ATTR_BASE | SVM_SELECTOR_WRITE_MASK) 879 880 #define INIT_LDTR_ATTRIBS (SVM_SELECTOR_P_MASK | 2) 881 #define INIT_TR_ATTRIBS (SVM_SELECTOR_P_MASK | 3) 882 883 static void *snp_alloc_vmsa_page(void) 884 { 885 struct page *p; 886 887 /* 888 * Allocate VMSA page to work around the SNP erratum where the CPU will 889 * incorrectly signal an RMP violation #PF if a large page (2MB or 1GB) 890 * collides with the RMP entry of VMSA page. The recommended workaround 891 * is to not use a large page. 892 * 893 * Allocate an 8k page which is also 8k-aligned. 894 */ 895 p = alloc_pages(GFP_KERNEL_ACCOUNT | __GFP_ZERO, 1); 896 if (!p) 897 return NULL; 898 899 split_page(p, 1); 900 901 /* Free the first 4k. This page may be 2M/1G aligned and cannot be used. */ 902 __free_page(p); 903 904 return page_address(p + 1); 905 } 906 907 static void snp_cleanup_vmsa(struct sev_es_save_area *vmsa) 908 { 909 int err; 910 911 err = snp_set_vmsa(vmsa, false); 912 if (err) 913 pr_err("clear VMSA page failed (%u), leaking page\n", err); 914 else 915 free_page((unsigned long)vmsa); 916 } 917 918 static int wakeup_cpu_via_vmgexit(int apic_id, unsigned long start_ip) 919 { 920 struct sev_es_save_area *cur_vmsa, *vmsa; 921 struct ghcb_state state; 922 unsigned long flags; 923 struct ghcb *ghcb; 924 u8 sipi_vector; 925 int cpu, ret; 926 u64 cr4; 927 928 /* 929 * The hypervisor SNP feature support check has happened earlier, just check 930 * the AP_CREATION one here. 931 */ 932 if (!(sev_hv_features & GHCB_HV_FT_SNP_AP_CREATION)) 933 return -EOPNOTSUPP; 934 935 /* 936 * Verify the desired start IP against the known trampoline start IP 937 * to catch any future new trampolines that may be introduced that 938 * would require a new protected guest entry point. 939 */ 940 if (WARN_ONCE(start_ip != real_mode_header->trampoline_start, 941 "Unsupported SNP start_ip: %lx\n", start_ip)) 942 return -EINVAL; 943 944 /* Override start_ip with known protected guest start IP */ 945 start_ip = real_mode_header->sev_es_trampoline_start; 946 947 /* Find the logical CPU for the APIC ID */ 948 for_each_present_cpu(cpu) { 949 if (arch_match_cpu_phys_id(cpu, apic_id)) 950 break; 951 } 952 if (cpu >= nr_cpu_ids) 953 return -EINVAL; 954 955 cur_vmsa = per_cpu(sev_vmsa, cpu); 956 957 /* 958 * A new VMSA is created each time because there is no guarantee that 959 * the current VMSA is the kernels or that the vCPU is not running. If 960 * an attempt was done to use the current VMSA with a running vCPU, a 961 * #VMEXIT of that vCPU would wipe out all of the settings being done 962 * here. 963 */ 964 vmsa = (struct sev_es_save_area *)snp_alloc_vmsa_page(); 965 if (!vmsa) 966 return -ENOMEM; 967 968 /* CR4 should maintain the MCE value */ 969 cr4 = native_read_cr4() & X86_CR4_MCE; 970 971 /* Set the CS value based on the start_ip converted to a SIPI vector */ 972 sipi_vector = (start_ip >> 12); 973 vmsa->cs.base = sipi_vector << 12; 974 vmsa->cs.limit = AP_INIT_CS_LIMIT; 975 vmsa->cs.attrib = INIT_CS_ATTRIBS; 976 vmsa->cs.selector = sipi_vector << 8; 977 978 /* Set the RIP value based on start_ip */ 979 vmsa->rip = start_ip & 0xfff; 980 981 /* Set AP INIT defaults as documented in the APM */ 982 vmsa->ds.limit = AP_INIT_DS_LIMIT; 983 vmsa->ds.attrib = INIT_DS_ATTRIBS; 984 vmsa->es = vmsa->ds; 985 vmsa->fs = vmsa->ds; 986 vmsa->gs = vmsa->ds; 987 vmsa->ss = vmsa->ds; 988 989 vmsa->gdtr.limit = AP_INIT_GDTR_LIMIT; 990 vmsa->ldtr.limit = AP_INIT_LDTR_LIMIT; 991 vmsa->ldtr.attrib = INIT_LDTR_ATTRIBS; 992 vmsa->idtr.limit = AP_INIT_IDTR_LIMIT; 993 vmsa->tr.limit = AP_INIT_TR_LIMIT; 994 vmsa->tr.attrib = INIT_TR_ATTRIBS; 995 996 vmsa->cr4 = cr4; 997 vmsa->cr0 = AP_INIT_CR0_DEFAULT; 998 vmsa->dr7 = DR7_RESET_VALUE; 999 vmsa->dr6 = AP_INIT_DR6_DEFAULT; 1000 vmsa->rflags = AP_INIT_RFLAGS_DEFAULT; 1001 vmsa->g_pat = AP_INIT_GPAT_DEFAULT; 1002 vmsa->xcr0 = AP_INIT_XCR0_DEFAULT; 1003 vmsa->mxcsr = AP_INIT_MXCSR_DEFAULT; 1004 vmsa->x87_ftw = AP_INIT_X87_FTW_DEFAULT; 1005 vmsa->x87_fcw = AP_INIT_X87_FCW_DEFAULT; 1006 1007 /* SVME must be set. */ 1008 vmsa->efer = EFER_SVME; 1009 1010 /* 1011 * Set the SNP-specific fields for this VMSA: 1012 * VMPL level 1013 * SEV_FEATURES (matches the SEV STATUS MSR right shifted 2 bits) 1014 */ 1015 vmsa->vmpl = 0; 1016 vmsa->sev_features = sev_status >> 2; 1017 1018 /* Switch the page over to a VMSA page now that it is initialized */ 1019 ret = snp_set_vmsa(vmsa, true); 1020 if (ret) { 1021 pr_err("set VMSA page failed (%u)\n", ret); 1022 free_page((unsigned long)vmsa); 1023 1024 return -EINVAL; 1025 } 1026 1027 /* Issue VMGEXIT AP Creation NAE event */ 1028 local_irq_save(flags); 1029 1030 ghcb = __sev_get_ghcb(&state); 1031 1032 vc_ghcb_invalidate(ghcb); 1033 ghcb_set_rax(ghcb, vmsa->sev_features); 1034 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_CREATION); 1035 ghcb_set_sw_exit_info_1(ghcb, ((u64)apic_id << 32) | SVM_VMGEXIT_AP_CREATE); 1036 ghcb_set_sw_exit_info_2(ghcb, __pa(vmsa)); 1037 1038 sev_es_wr_ghcb_msr(__pa(ghcb)); 1039 VMGEXIT(); 1040 1041 if (!ghcb_sw_exit_info_1_is_valid(ghcb) || 1042 lower_32_bits(ghcb->save.sw_exit_info_1)) { 1043 pr_err("SNP AP Creation error\n"); 1044 ret = -EINVAL; 1045 } 1046 1047 __sev_put_ghcb(&state); 1048 1049 local_irq_restore(flags); 1050 1051 /* Perform cleanup if there was an error */ 1052 if (ret) { 1053 snp_cleanup_vmsa(vmsa); 1054 vmsa = NULL; 1055 } 1056 1057 /* Free up any previous VMSA page */ 1058 if (cur_vmsa) 1059 snp_cleanup_vmsa(cur_vmsa); 1060 1061 /* Record the current VMSA page */ 1062 per_cpu(sev_vmsa, cpu) = vmsa; 1063 1064 return ret; 1065 } 1066 1067 void snp_set_wakeup_secondary_cpu(void) 1068 { 1069 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 1070 return; 1071 1072 /* 1073 * Always set this override if SNP is enabled. This makes it the 1074 * required method to start APs under SNP. If the hypervisor does 1075 * not support AP creation, then no APs will be started. 1076 */ 1077 apic->wakeup_secondary_cpu = wakeup_cpu_via_vmgexit; 1078 } 1079 1080 int sev_es_setup_ap_jump_table(struct real_mode_header *rmh) 1081 { 1082 u16 startup_cs, startup_ip; 1083 phys_addr_t jump_table_pa; 1084 u64 jump_table_addr; 1085 u16 __iomem *jump_table; 1086 1087 jump_table_addr = get_jump_table_addr(); 1088 1089 /* On UP guests there is no jump table so this is not a failure */ 1090 if (!jump_table_addr) 1091 return 0; 1092 1093 /* Check if AP Jump Table is page-aligned */ 1094 if (jump_table_addr & ~PAGE_MASK) 1095 return -EINVAL; 1096 1097 jump_table_pa = jump_table_addr & PAGE_MASK; 1098 1099 startup_cs = (u16)(rmh->trampoline_start >> 4); 1100 startup_ip = (u16)(rmh->sev_es_trampoline_start - 1101 rmh->trampoline_start); 1102 1103 jump_table = ioremap_encrypted(jump_table_pa, PAGE_SIZE); 1104 if (!jump_table) 1105 return -EIO; 1106 1107 writew(startup_ip, &jump_table[0]); 1108 writew(startup_cs, &jump_table[1]); 1109 1110 iounmap(jump_table); 1111 1112 return 0; 1113 } 1114 1115 /* 1116 * This is needed by the OVMF UEFI firmware which will use whatever it finds in 1117 * the GHCB MSR as its GHCB to talk to the hypervisor. So make sure the per-cpu 1118 * runtime GHCBs used by the kernel are also mapped in the EFI page-table. 1119 */ 1120 int __init sev_es_efi_map_ghcbs(pgd_t *pgd) 1121 { 1122 struct sev_es_runtime_data *data; 1123 unsigned long address, pflags; 1124 int cpu; 1125 u64 pfn; 1126 1127 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) 1128 return 0; 1129 1130 pflags = _PAGE_NX | _PAGE_RW; 1131 1132 for_each_possible_cpu(cpu) { 1133 data = per_cpu(runtime_data, cpu); 1134 1135 address = __pa(&data->ghcb_page); 1136 pfn = address >> PAGE_SHIFT; 1137 1138 if (kernel_map_pages_in_pgd(pgd, pfn, address, 1, pflags)) 1139 return 1; 1140 } 1141 1142 return 0; 1143 } 1144 1145 static enum es_result vc_handle_msr(struct ghcb *ghcb, struct es_em_ctxt *ctxt) 1146 { 1147 struct pt_regs *regs = ctxt->regs; 1148 enum es_result ret; 1149 u64 exit_info_1; 1150 1151 /* Is it a WRMSR? */ 1152 exit_info_1 = (ctxt->insn.opcode.bytes[1] == 0x30) ? 1 : 0; 1153 1154 ghcb_set_rcx(ghcb, regs->cx); 1155 if (exit_info_1) { 1156 ghcb_set_rax(ghcb, regs->ax); 1157 ghcb_set_rdx(ghcb, regs->dx); 1158 } 1159 1160 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_MSR, 1161 exit_info_1, 0); 1162 1163 if ((ret == ES_OK) && (!exit_info_1)) { 1164 regs->ax = ghcb->save.rax; 1165 regs->dx = ghcb->save.rdx; 1166 } 1167 1168 return ret; 1169 } 1170 1171 static void snp_register_per_cpu_ghcb(void) 1172 { 1173 struct sev_es_runtime_data *data; 1174 struct ghcb *ghcb; 1175 1176 data = this_cpu_read(runtime_data); 1177 ghcb = &data->ghcb_page; 1178 1179 snp_register_ghcb_early(__pa(ghcb)); 1180 } 1181 1182 void setup_ghcb(void) 1183 { 1184 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) 1185 return; 1186 1187 /* First make sure the hypervisor talks a supported protocol. */ 1188 if (!sev_es_negotiate_protocol()) 1189 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); 1190 1191 /* 1192 * Check whether the runtime #VC exception handler is active. It uses 1193 * the per-CPU GHCB page which is set up by sev_es_init_vc_handling(). 1194 * 1195 * If SNP is active, register the per-CPU GHCB page so that the runtime 1196 * exception handler can use it. 1197 */ 1198 if (initial_vc_handler == (unsigned long)kernel_exc_vmm_communication) { 1199 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 1200 snp_register_per_cpu_ghcb(); 1201 1202 return; 1203 } 1204 1205 /* 1206 * Clear the boot_ghcb. The first exception comes in before the bss 1207 * section is cleared. 1208 */ 1209 memset(&boot_ghcb_page, 0, PAGE_SIZE); 1210 1211 /* Alright - Make the boot-ghcb public */ 1212 boot_ghcb = &boot_ghcb_page; 1213 1214 /* SNP guest requires that GHCB GPA must be registered. */ 1215 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 1216 snp_register_ghcb_early(__pa(&boot_ghcb_page)); 1217 } 1218 1219 #ifdef CONFIG_HOTPLUG_CPU 1220 static void sev_es_ap_hlt_loop(void) 1221 { 1222 struct ghcb_state state; 1223 struct ghcb *ghcb; 1224 1225 ghcb = __sev_get_ghcb(&state); 1226 1227 while (true) { 1228 vc_ghcb_invalidate(ghcb); 1229 ghcb_set_sw_exit_code(ghcb, SVM_VMGEXIT_AP_HLT_LOOP); 1230 ghcb_set_sw_exit_info_1(ghcb, 0); 1231 ghcb_set_sw_exit_info_2(ghcb, 0); 1232 1233 sev_es_wr_ghcb_msr(__pa(ghcb)); 1234 VMGEXIT(); 1235 1236 /* Wakeup signal? */ 1237 if (ghcb_sw_exit_info_2_is_valid(ghcb) && 1238 ghcb->save.sw_exit_info_2) 1239 break; 1240 } 1241 1242 __sev_put_ghcb(&state); 1243 } 1244 1245 /* 1246 * Play_dead handler when running under SEV-ES. This is needed because 1247 * the hypervisor can't deliver an SIPI request to restart the AP. 1248 * Instead the kernel has to issue a VMGEXIT to halt the VCPU until the 1249 * hypervisor wakes it up again. 1250 */ 1251 static void sev_es_play_dead(void) 1252 { 1253 play_dead_common(); 1254 1255 /* IRQs now disabled */ 1256 1257 sev_es_ap_hlt_loop(); 1258 1259 /* 1260 * If we get here, the VCPU was woken up again. Jump to CPU 1261 * startup code to get it back online. 1262 */ 1263 start_cpu0(); 1264 } 1265 #else /* CONFIG_HOTPLUG_CPU */ 1266 #define sev_es_play_dead native_play_dead 1267 #endif /* CONFIG_HOTPLUG_CPU */ 1268 1269 #ifdef CONFIG_SMP 1270 static void __init sev_es_setup_play_dead(void) 1271 { 1272 smp_ops.play_dead = sev_es_play_dead; 1273 } 1274 #else 1275 static inline void sev_es_setup_play_dead(void) { } 1276 #endif 1277 1278 static void __init alloc_runtime_data(int cpu) 1279 { 1280 struct sev_es_runtime_data *data; 1281 1282 data = memblock_alloc(sizeof(*data), PAGE_SIZE); 1283 if (!data) 1284 panic("Can't allocate SEV-ES runtime data"); 1285 1286 per_cpu(runtime_data, cpu) = data; 1287 } 1288 1289 static void __init init_ghcb(int cpu) 1290 { 1291 struct sev_es_runtime_data *data; 1292 int err; 1293 1294 data = per_cpu(runtime_data, cpu); 1295 1296 err = early_set_memory_decrypted((unsigned long)&data->ghcb_page, 1297 sizeof(data->ghcb_page)); 1298 if (err) 1299 panic("Can't map GHCBs unencrypted"); 1300 1301 memset(&data->ghcb_page, 0, sizeof(data->ghcb_page)); 1302 1303 data->ghcb_active = false; 1304 data->backup_ghcb_active = false; 1305 } 1306 1307 void __init sev_es_init_vc_handling(void) 1308 { 1309 int cpu; 1310 1311 BUILD_BUG_ON(offsetof(struct sev_es_runtime_data, ghcb_page) % PAGE_SIZE); 1312 1313 if (!cc_platform_has(CC_ATTR_GUEST_STATE_ENCRYPT)) 1314 return; 1315 1316 if (!sev_es_check_cpu_features()) 1317 panic("SEV-ES CPU Features missing"); 1318 1319 /* 1320 * SNP is supported in v2 of the GHCB spec which mandates support for HV 1321 * features. 1322 */ 1323 if (cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) { 1324 sev_hv_features = get_hv_features(); 1325 1326 if (!(sev_hv_features & GHCB_HV_FT_SNP)) 1327 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); 1328 } 1329 1330 /* Enable SEV-ES special handling */ 1331 static_branch_enable(&sev_es_enable_key); 1332 1333 /* Initialize per-cpu GHCB pages */ 1334 for_each_possible_cpu(cpu) { 1335 alloc_runtime_data(cpu); 1336 init_ghcb(cpu); 1337 } 1338 1339 sev_es_setup_play_dead(); 1340 1341 /* Secondary CPUs use the runtime #VC handler */ 1342 initial_vc_handler = (unsigned long)kernel_exc_vmm_communication; 1343 } 1344 1345 static void __init vc_early_forward_exception(struct es_em_ctxt *ctxt) 1346 { 1347 int trapnr = ctxt->fi.vector; 1348 1349 if (trapnr == X86_TRAP_PF) 1350 native_write_cr2(ctxt->fi.cr2); 1351 1352 ctxt->regs->orig_ax = ctxt->fi.error_code; 1353 do_early_exception(ctxt->regs, trapnr); 1354 } 1355 1356 static long *vc_insn_get_rm(struct es_em_ctxt *ctxt) 1357 { 1358 long *reg_array; 1359 int offset; 1360 1361 reg_array = (long *)ctxt->regs; 1362 offset = insn_get_modrm_rm_off(&ctxt->insn, ctxt->regs); 1363 1364 if (offset < 0) 1365 return NULL; 1366 1367 offset /= sizeof(long); 1368 1369 return reg_array + offset; 1370 } 1371 static enum es_result vc_do_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt, 1372 unsigned int bytes, bool read) 1373 { 1374 u64 exit_code, exit_info_1, exit_info_2; 1375 unsigned long ghcb_pa = __pa(ghcb); 1376 enum es_result res; 1377 phys_addr_t paddr; 1378 void __user *ref; 1379 1380 ref = insn_get_addr_ref(&ctxt->insn, ctxt->regs); 1381 if (ref == (void __user *)-1L) 1382 return ES_UNSUPPORTED; 1383 1384 exit_code = read ? SVM_VMGEXIT_MMIO_READ : SVM_VMGEXIT_MMIO_WRITE; 1385 1386 res = vc_slow_virt_to_phys(ghcb, ctxt, (unsigned long)ref, &paddr); 1387 if (res != ES_OK) { 1388 if (res == ES_EXCEPTION && !read) 1389 ctxt->fi.error_code |= X86_PF_WRITE; 1390 1391 return res; 1392 } 1393 1394 exit_info_1 = paddr; 1395 /* Can never be greater than 8 */ 1396 exit_info_2 = bytes; 1397 1398 ghcb_set_sw_scratch(ghcb, ghcb_pa + offsetof(struct ghcb, shared_buffer)); 1399 1400 return sev_es_ghcb_hv_call(ghcb, true, ctxt, exit_code, exit_info_1, exit_info_2); 1401 } 1402 1403 /* 1404 * The MOVS instruction has two memory operands, which raises the 1405 * problem that it is not known whether the access to the source or the 1406 * destination caused the #VC exception (and hence whether an MMIO read 1407 * or write operation needs to be emulated). 1408 * 1409 * Instead of playing games with walking page-tables and trying to guess 1410 * whether the source or destination is an MMIO range, split the move 1411 * into two operations, a read and a write with only one memory operand. 1412 * This will cause a nested #VC exception on the MMIO address which can 1413 * then be handled. 1414 * 1415 * This implementation has the benefit that it also supports MOVS where 1416 * source _and_ destination are MMIO regions. 1417 * 1418 * It will slow MOVS on MMIO down a lot, but in SEV-ES guests it is a 1419 * rare operation. If it turns out to be a performance problem the split 1420 * operations can be moved to memcpy_fromio() and memcpy_toio(). 1421 */ 1422 static enum es_result vc_handle_mmio_movs(struct es_em_ctxt *ctxt, 1423 unsigned int bytes) 1424 { 1425 unsigned long ds_base, es_base; 1426 unsigned char *src, *dst; 1427 unsigned char buffer[8]; 1428 enum es_result ret; 1429 bool rep; 1430 int off; 1431 1432 ds_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_DS); 1433 es_base = insn_get_seg_base(ctxt->regs, INAT_SEG_REG_ES); 1434 1435 if (ds_base == -1L || es_base == -1L) { 1436 ctxt->fi.vector = X86_TRAP_GP; 1437 ctxt->fi.error_code = 0; 1438 return ES_EXCEPTION; 1439 } 1440 1441 src = ds_base + (unsigned char *)ctxt->regs->si; 1442 dst = es_base + (unsigned char *)ctxt->regs->di; 1443 1444 ret = vc_read_mem(ctxt, src, buffer, bytes); 1445 if (ret != ES_OK) 1446 return ret; 1447 1448 ret = vc_write_mem(ctxt, dst, buffer, bytes); 1449 if (ret != ES_OK) 1450 return ret; 1451 1452 if (ctxt->regs->flags & X86_EFLAGS_DF) 1453 off = -bytes; 1454 else 1455 off = bytes; 1456 1457 ctxt->regs->si += off; 1458 ctxt->regs->di += off; 1459 1460 rep = insn_has_rep_prefix(&ctxt->insn); 1461 if (rep) 1462 ctxt->regs->cx -= 1; 1463 1464 if (!rep || ctxt->regs->cx == 0) 1465 return ES_OK; 1466 else 1467 return ES_RETRY; 1468 } 1469 1470 static enum es_result vc_handle_mmio(struct ghcb *ghcb, struct es_em_ctxt *ctxt) 1471 { 1472 struct insn *insn = &ctxt->insn; 1473 unsigned int bytes = 0; 1474 enum mmio_type mmio; 1475 enum es_result ret; 1476 u8 sign_byte; 1477 long *reg_data; 1478 1479 mmio = insn_decode_mmio(insn, &bytes); 1480 if (mmio == MMIO_DECODE_FAILED) 1481 return ES_DECODE_FAILED; 1482 1483 if (mmio != MMIO_WRITE_IMM && mmio != MMIO_MOVS) { 1484 reg_data = insn_get_modrm_reg_ptr(insn, ctxt->regs); 1485 if (!reg_data) 1486 return ES_DECODE_FAILED; 1487 } 1488 1489 switch (mmio) { 1490 case MMIO_WRITE: 1491 memcpy(ghcb->shared_buffer, reg_data, bytes); 1492 ret = vc_do_mmio(ghcb, ctxt, bytes, false); 1493 break; 1494 case MMIO_WRITE_IMM: 1495 memcpy(ghcb->shared_buffer, insn->immediate1.bytes, bytes); 1496 ret = vc_do_mmio(ghcb, ctxt, bytes, false); 1497 break; 1498 case MMIO_READ: 1499 ret = vc_do_mmio(ghcb, ctxt, bytes, true); 1500 if (ret) 1501 break; 1502 1503 /* Zero-extend for 32-bit operation */ 1504 if (bytes == 4) 1505 *reg_data = 0; 1506 1507 memcpy(reg_data, ghcb->shared_buffer, bytes); 1508 break; 1509 case MMIO_READ_ZERO_EXTEND: 1510 ret = vc_do_mmio(ghcb, ctxt, bytes, true); 1511 if (ret) 1512 break; 1513 1514 /* Zero extend based on operand size */ 1515 memset(reg_data, 0, insn->opnd_bytes); 1516 memcpy(reg_data, ghcb->shared_buffer, bytes); 1517 break; 1518 case MMIO_READ_SIGN_EXTEND: 1519 ret = vc_do_mmio(ghcb, ctxt, bytes, true); 1520 if (ret) 1521 break; 1522 1523 if (bytes == 1) { 1524 u8 *val = (u8 *)ghcb->shared_buffer; 1525 1526 sign_byte = (*val & 0x80) ? 0xff : 0x00; 1527 } else { 1528 u16 *val = (u16 *)ghcb->shared_buffer; 1529 1530 sign_byte = (*val & 0x8000) ? 0xff : 0x00; 1531 } 1532 1533 /* Sign extend based on operand size */ 1534 memset(reg_data, sign_byte, insn->opnd_bytes); 1535 memcpy(reg_data, ghcb->shared_buffer, bytes); 1536 break; 1537 case MMIO_MOVS: 1538 ret = vc_handle_mmio_movs(ctxt, bytes); 1539 break; 1540 default: 1541 ret = ES_UNSUPPORTED; 1542 break; 1543 } 1544 1545 return ret; 1546 } 1547 1548 static enum es_result vc_handle_dr7_write(struct ghcb *ghcb, 1549 struct es_em_ctxt *ctxt) 1550 { 1551 struct sev_es_runtime_data *data = this_cpu_read(runtime_data); 1552 long val, *reg = vc_insn_get_rm(ctxt); 1553 enum es_result ret; 1554 1555 if (!reg) 1556 return ES_DECODE_FAILED; 1557 1558 val = *reg; 1559 1560 /* Upper 32 bits must be written as zeroes */ 1561 if (val >> 32) { 1562 ctxt->fi.vector = X86_TRAP_GP; 1563 ctxt->fi.error_code = 0; 1564 return ES_EXCEPTION; 1565 } 1566 1567 /* Clear out other reserved bits and set bit 10 */ 1568 val = (val & 0xffff23ffL) | BIT(10); 1569 1570 /* Early non-zero writes to DR7 are not supported */ 1571 if (!data && (val & ~DR7_RESET_VALUE)) 1572 return ES_UNSUPPORTED; 1573 1574 /* Using a value of 0 for ExitInfo1 means RAX holds the value */ 1575 ghcb_set_rax(ghcb, val); 1576 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WRITE_DR7, 0, 0); 1577 if (ret != ES_OK) 1578 return ret; 1579 1580 if (data) 1581 data->dr7 = val; 1582 1583 return ES_OK; 1584 } 1585 1586 static enum es_result vc_handle_dr7_read(struct ghcb *ghcb, 1587 struct es_em_ctxt *ctxt) 1588 { 1589 struct sev_es_runtime_data *data = this_cpu_read(runtime_data); 1590 long *reg = vc_insn_get_rm(ctxt); 1591 1592 if (!reg) 1593 return ES_DECODE_FAILED; 1594 1595 if (data) 1596 *reg = data->dr7; 1597 else 1598 *reg = DR7_RESET_VALUE; 1599 1600 return ES_OK; 1601 } 1602 1603 static enum es_result vc_handle_wbinvd(struct ghcb *ghcb, 1604 struct es_em_ctxt *ctxt) 1605 { 1606 return sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_WBINVD, 0, 0); 1607 } 1608 1609 static enum es_result vc_handle_rdpmc(struct ghcb *ghcb, struct es_em_ctxt *ctxt) 1610 { 1611 enum es_result ret; 1612 1613 ghcb_set_rcx(ghcb, ctxt->regs->cx); 1614 1615 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_RDPMC, 0, 0); 1616 if (ret != ES_OK) 1617 return ret; 1618 1619 if (!(ghcb_rax_is_valid(ghcb) && ghcb_rdx_is_valid(ghcb))) 1620 return ES_VMM_ERROR; 1621 1622 ctxt->regs->ax = ghcb->save.rax; 1623 ctxt->regs->dx = ghcb->save.rdx; 1624 1625 return ES_OK; 1626 } 1627 1628 static enum es_result vc_handle_monitor(struct ghcb *ghcb, 1629 struct es_em_ctxt *ctxt) 1630 { 1631 /* 1632 * Treat it as a NOP and do not leak a physical address to the 1633 * hypervisor. 1634 */ 1635 return ES_OK; 1636 } 1637 1638 static enum es_result vc_handle_mwait(struct ghcb *ghcb, 1639 struct es_em_ctxt *ctxt) 1640 { 1641 /* Treat the same as MONITOR/MONITORX */ 1642 return ES_OK; 1643 } 1644 1645 static enum es_result vc_handle_vmmcall(struct ghcb *ghcb, 1646 struct es_em_ctxt *ctxt) 1647 { 1648 enum es_result ret; 1649 1650 ghcb_set_rax(ghcb, ctxt->regs->ax); 1651 ghcb_set_cpl(ghcb, user_mode(ctxt->regs) ? 3 : 0); 1652 1653 if (x86_platform.hyper.sev_es_hcall_prepare) 1654 x86_platform.hyper.sev_es_hcall_prepare(ghcb, ctxt->regs); 1655 1656 ret = sev_es_ghcb_hv_call(ghcb, true, ctxt, SVM_EXIT_VMMCALL, 0, 0); 1657 if (ret != ES_OK) 1658 return ret; 1659 1660 if (!ghcb_rax_is_valid(ghcb)) 1661 return ES_VMM_ERROR; 1662 1663 ctxt->regs->ax = ghcb->save.rax; 1664 1665 /* 1666 * Call sev_es_hcall_finish() after regs->ax is already set. 1667 * This allows the hypervisor handler to overwrite it again if 1668 * necessary. 1669 */ 1670 if (x86_platform.hyper.sev_es_hcall_finish && 1671 !x86_platform.hyper.sev_es_hcall_finish(ghcb, ctxt->regs)) 1672 return ES_VMM_ERROR; 1673 1674 return ES_OK; 1675 } 1676 1677 static enum es_result vc_handle_trap_ac(struct ghcb *ghcb, 1678 struct es_em_ctxt *ctxt) 1679 { 1680 /* 1681 * Calling ecx_alignment_check() directly does not work, because it 1682 * enables IRQs and the GHCB is active. Forward the exception and call 1683 * it later from vc_forward_exception(). 1684 */ 1685 ctxt->fi.vector = X86_TRAP_AC; 1686 ctxt->fi.error_code = 0; 1687 return ES_EXCEPTION; 1688 } 1689 1690 static enum es_result vc_handle_exitcode(struct es_em_ctxt *ctxt, 1691 struct ghcb *ghcb, 1692 unsigned long exit_code) 1693 { 1694 enum es_result result; 1695 1696 switch (exit_code) { 1697 case SVM_EXIT_READ_DR7: 1698 result = vc_handle_dr7_read(ghcb, ctxt); 1699 break; 1700 case SVM_EXIT_WRITE_DR7: 1701 result = vc_handle_dr7_write(ghcb, ctxt); 1702 break; 1703 case SVM_EXIT_EXCP_BASE + X86_TRAP_AC: 1704 result = vc_handle_trap_ac(ghcb, ctxt); 1705 break; 1706 case SVM_EXIT_RDTSC: 1707 case SVM_EXIT_RDTSCP: 1708 result = vc_handle_rdtsc(ghcb, ctxt, exit_code); 1709 break; 1710 case SVM_EXIT_RDPMC: 1711 result = vc_handle_rdpmc(ghcb, ctxt); 1712 break; 1713 case SVM_EXIT_INVD: 1714 pr_err_ratelimited("#VC exception for INVD??? Seriously???\n"); 1715 result = ES_UNSUPPORTED; 1716 break; 1717 case SVM_EXIT_CPUID: 1718 result = vc_handle_cpuid(ghcb, ctxt); 1719 break; 1720 case SVM_EXIT_IOIO: 1721 result = vc_handle_ioio(ghcb, ctxt); 1722 break; 1723 case SVM_EXIT_MSR: 1724 result = vc_handle_msr(ghcb, ctxt); 1725 break; 1726 case SVM_EXIT_VMMCALL: 1727 result = vc_handle_vmmcall(ghcb, ctxt); 1728 break; 1729 case SVM_EXIT_WBINVD: 1730 result = vc_handle_wbinvd(ghcb, ctxt); 1731 break; 1732 case SVM_EXIT_MONITOR: 1733 result = vc_handle_monitor(ghcb, ctxt); 1734 break; 1735 case SVM_EXIT_MWAIT: 1736 result = vc_handle_mwait(ghcb, ctxt); 1737 break; 1738 case SVM_EXIT_NPF: 1739 result = vc_handle_mmio(ghcb, ctxt); 1740 break; 1741 default: 1742 /* 1743 * Unexpected #VC exception 1744 */ 1745 result = ES_UNSUPPORTED; 1746 } 1747 1748 return result; 1749 } 1750 1751 static __always_inline void vc_forward_exception(struct es_em_ctxt *ctxt) 1752 { 1753 long error_code = ctxt->fi.error_code; 1754 int trapnr = ctxt->fi.vector; 1755 1756 ctxt->regs->orig_ax = ctxt->fi.error_code; 1757 1758 switch (trapnr) { 1759 case X86_TRAP_GP: 1760 exc_general_protection(ctxt->regs, error_code); 1761 break; 1762 case X86_TRAP_UD: 1763 exc_invalid_op(ctxt->regs); 1764 break; 1765 case X86_TRAP_PF: 1766 write_cr2(ctxt->fi.cr2); 1767 exc_page_fault(ctxt->regs, error_code); 1768 break; 1769 case X86_TRAP_AC: 1770 exc_alignment_check(ctxt->regs, error_code); 1771 break; 1772 default: 1773 pr_emerg("Unsupported exception in #VC instruction emulation - can't continue\n"); 1774 BUG(); 1775 } 1776 } 1777 1778 static __always_inline bool is_vc2_stack(unsigned long sp) 1779 { 1780 return (sp >= __this_cpu_ist_bottom_va(VC2) && sp < __this_cpu_ist_top_va(VC2)); 1781 } 1782 1783 static __always_inline bool vc_from_invalid_context(struct pt_regs *regs) 1784 { 1785 unsigned long sp, prev_sp; 1786 1787 sp = (unsigned long)regs; 1788 prev_sp = regs->sp; 1789 1790 /* 1791 * If the code was already executing on the VC2 stack when the #VC 1792 * happened, let it proceed to the normal handling routine. This way the 1793 * code executing on the VC2 stack can cause #VC exceptions to get handled. 1794 */ 1795 return is_vc2_stack(sp) && !is_vc2_stack(prev_sp); 1796 } 1797 1798 static bool vc_raw_handle_exception(struct pt_regs *regs, unsigned long error_code) 1799 { 1800 struct ghcb_state state; 1801 struct es_em_ctxt ctxt; 1802 enum es_result result; 1803 struct ghcb *ghcb; 1804 bool ret = true; 1805 1806 ghcb = __sev_get_ghcb(&state); 1807 1808 vc_ghcb_invalidate(ghcb); 1809 result = vc_init_em_ctxt(&ctxt, regs, error_code); 1810 1811 if (result == ES_OK) 1812 result = vc_handle_exitcode(&ctxt, ghcb, error_code); 1813 1814 __sev_put_ghcb(&state); 1815 1816 /* Done - now check the result */ 1817 switch (result) { 1818 case ES_OK: 1819 vc_finish_insn(&ctxt); 1820 break; 1821 case ES_UNSUPPORTED: 1822 pr_err_ratelimited("Unsupported exit-code 0x%02lx in #VC exception (IP: 0x%lx)\n", 1823 error_code, regs->ip); 1824 ret = false; 1825 break; 1826 case ES_VMM_ERROR: 1827 pr_err_ratelimited("Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n", 1828 error_code, regs->ip); 1829 ret = false; 1830 break; 1831 case ES_DECODE_FAILED: 1832 pr_err_ratelimited("Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n", 1833 error_code, regs->ip); 1834 ret = false; 1835 break; 1836 case ES_EXCEPTION: 1837 vc_forward_exception(&ctxt); 1838 break; 1839 case ES_RETRY: 1840 /* Nothing to do */ 1841 break; 1842 default: 1843 pr_emerg("Unknown result in %s():%d\n", __func__, result); 1844 /* 1845 * Emulating the instruction which caused the #VC exception 1846 * failed - can't continue so print debug information 1847 */ 1848 BUG(); 1849 } 1850 1851 return ret; 1852 } 1853 1854 static __always_inline bool vc_is_db(unsigned long error_code) 1855 { 1856 return error_code == SVM_EXIT_EXCP_BASE + X86_TRAP_DB; 1857 } 1858 1859 /* 1860 * Runtime #VC exception handler when raised from kernel mode. Runs in NMI mode 1861 * and will panic when an error happens. 1862 */ 1863 DEFINE_IDTENTRY_VC_KERNEL(exc_vmm_communication) 1864 { 1865 irqentry_state_t irq_state; 1866 1867 /* 1868 * With the current implementation it is always possible to switch to a 1869 * safe stack because #VC exceptions only happen at known places, like 1870 * intercepted instructions or accesses to MMIO areas/IO ports. They can 1871 * also happen with code instrumentation when the hypervisor intercepts 1872 * #DB, but the critical paths are forbidden to be instrumented, so #DB 1873 * exceptions currently also only happen in safe places. 1874 * 1875 * But keep this here in case the noinstr annotations are violated due 1876 * to bug elsewhere. 1877 */ 1878 if (unlikely(vc_from_invalid_context(regs))) { 1879 instrumentation_begin(); 1880 panic("Can't handle #VC exception from unsupported context\n"); 1881 instrumentation_end(); 1882 } 1883 1884 /* 1885 * Handle #DB before calling into !noinstr code to avoid recursive #DB. 1886 */ 1887 if (vc_is_db(error_code)) { 1888 exc_debug(regs); 1889 return; 1890 } 1891 1892 irq_state = irqentry_nmi_enter(regs); 1893 1894 instrumentation_begin(); 1895 1896 if (!vc_raw_handle_exception(regs, error_code)) { 1897 /* Show some debug info */ 1898 show_regs(regs); 1899 1900 /* Ask hypervisor to sev_es_terminate */ 1901 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); 1902 1903 /* If that fails and we get here - just panic */ 1904 panic("Returned from Terminate-Request to Hypervisor\n"); 1905 } 1906 1907 instrumentation_end(); 1908 irqentry_nmi_exit(regs, irq_state); 1909 } 1910 1911 /* 1912 * Runtime #VC exception handler when raised from user mode. Runs in IRQ mode 1913 * and will kill the current task with SIGBUS when an error happens. 1914 */ 1915 DEFINE_IDTENTRY_VC_USER(exc_vmm_communication) 1916 { 1917 /* 1918 * Handle #DB before calling into !noinstr code to avoid recursive #DB. 1919 */ 1920 if (vc_is_db(error_code)) { 1921 noist_exc_debug(regs); 1922 return; 1923 } 1924 1925 irqentry_enter_from_user_mode(regs); 1926 instrumentation_begin(); 1927 1928 if (!vc_raw_handle_exception(regs, error_code)) { 1929 /* 1930 * Do not kill the machine if user-space triggered the 1931 * exception. Send SIGBUS instead and let user-space deal with 1932 * it. 1933 */ 1934 force_sig_fault(SIGBUS, BUS_OBJERR, (void __user *)0); 1935 } 1936 1937 instrumentation_end(); 1938 irqentry_exit_to_user_mode(regs); 1939 } 1940 1941 bool __init handle_vc_boot_ghcb(struct pt_regs *regs) 1942 { 1943 unsigned long exit_code = regs->orig_ax; 1944 struct es_em_ctxt ctxt; 1945 enum es_result result; 1946 1947 vc_ghcb_invalidate(boot_ghcb); 1948 1949 result = vc_init_em_ctxt(&ctxt, regs, exit_code); 1950 if (result == ES_OK) 1951 result = vc_handle_exitcode(&ctxt, boot_ghcb, exit_code); 1952 1953 /* Done - now check the result */ 1954 switch (result) { 1955 case ES_OK: 1956 vc_finish_insn(&ctxt); 1957 break; 1958 case ES_UNSUPPORTED: 1959 early_printk("PANIC: Unsupported exit-code 0x%02lx in early #VC exception (IP: 0x%lx)\n", 1960 exit_code, regs->ip); 1961 goto fail; 1962 case ES_VMM_ERROR: 1963 early_printk("PANIC: Failure in communication with VMM (exit-code 0x%02lx IP: 0x%lx)\n", 1964 exit_code, regs->ip); 1965 goto fail; 1966 case ES_DECODE_FAILED: 1967 early_printk("PANIC: Failed to decode instruction (exit-code 0x%02lx IP: 0x%lx)\n", 1968 exit_code, regs->ip); 1969 goto fail; 1970 case ES_EXCEPTION: 1971 vc_early_forward_exception(&ctxt); 1972 break; 1973 case ES_RETRY: 1974 /* Nothing to do */ 1975 break; 1976 default: 1977 BUG(); 1978 } 1979 1980 return true; 1981 1982 fail: 1983 show_regs(regs); 1984 1985 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SEV_ES_GEN_REQ); 1986 } 1987 1988 /* 1989 * Initial set up of SNP relies on information provided by the 1990 * Confidential Computing blob, which can be passed to the kernel 1991 * in the following ways, depending on how it is booted: 1992 * 1993 * - when booted via the boot/decompress kernel: 1994 * - via boot_params 1995 * 1996 * - when booted directly by firmware/bootloader (e.g. CONFIG_PVH): 1997 * - via a setup_data entry, as defined by the Linux Boot Protocol 1998 * 1999 * Scan for the blob in that order. 2000 */ 2001 static __init struct cc_blob_sev_info *find_cc_blob(struct boot_params *bp) 2002 { 2003 struct cc_blob_sev_info *cc_info; 2004 2005 /* Boot kernel would have passed the CC blob via boot_params. */ 2006 if (bp->cc_blob_address) { 2007 cc_info = (struct cc_blob_sev_info *)(unsigned long)bp->cc_blob_address; 2008 goto found_cc_info; 2009 } 2010 2011 /* 2012 * If kernel was booted directly, without the use of the 2013 * boot/decompression kernel, the CC blob may have been passed via 2014 * setup_data instead. 2015 */ 2016 cc_info = find_cc_blob_setup_data(bp); 2017 if (!cc_info) 2018 return NULL; 2019 2020 found_cc_info: 2021 if (cc_info->magic != CC_BLOB_SEV_HDR_MAGIC) 2022 snp_abort(); 2023 2024 return cc_info; 2025 } 2026 2027 bool __init snp_init(struct boot_params *bp) 2028 { 2029 struct cc_blob_sev_info *cc_info; 2030 2031 if (!bp) 2032 return false; 2033 2034 cc_info = find_cc_blob(bp); 2035 if (!cc_info) 2036 return false; 2037 2038 setup_cpuid_table(cc_info); 2039 2040 /* 2041 * The CC blob will be used later to access the secrets page. Cache 2042 * it here like the boot kernel does. 2043 */ 2044 bp->cc_blob_address = (u32)(unsigned long)cc_info; 2045 2046 return true; 2047 } 2048 2049 void __init snp_abort(void) 2050 { 2051 sev_es_terminate(SEV_TERM_SET_GEN, GHCB_SNP_UNSUPPORTED); 2052 } 2053 2054 static void dump_cpuid_table(void) 2055 { 2056 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table(); 2057 int i = 0; 2058 2059 pr_info("count=%d reserved=0x%x reserved2=0x%llx\n", 2060 cpuid_table->count, cpuid_table->__reserved1, cpuid_table->__reserved2); 2061 2062 for (i = 0; i < SNP_CPUID_COUNT_MAX; i++) { 2063 const struct snp_cpuid_fn *fn = &cpuid_table->fn[i]; 2064 2065 pr_info("index=%3d fn=0x%08x subfn=0x%08x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x xcr0_in=0x%016llx xss_in=0x%016llx reserved=0x%016llx\n", 2066 i, fn->eax_in, fn->ecx_in, fn->eax, fn->ebx, fn->ecx, 2067 fn->edx, fn->xcr0_in, fn->xss_in, fn->__reserved); 2068 } 2069 } 2070 2071 /* 2072 * It is useful from an auditing/testing perspective to provide an easy way 2073 * for the guest owner to know that the CPUID table has been initialized as 2074 * expected, but that initialization happens too early in boot to print any 2075 * sort of indicator, and there's not really any other good place to do it, 2076 * so do it here. 2077 */ 2078 static int __init report_cpuid_table(void) 2079 { 2080 const struct snp_cpuid_table *cpuid_table = snp_cpuid_get_table(); 2081 2082 if (!cpuid_table->count) 2083 return 0; 2084 2085 pr_info("Using SNP CPUID table, %d entries present.\n", 2086 cpuid_table->count); 2087 2088 if (sev_cfg.debug) 2089 dump_cpuid_table(); 2090 2091 return 0; 2092 } 2093 arch_initcall(report_cpuid_table); 2094 2095 static int __init init_sev_config(char *str) 2096 { 2097 char *s; 2098 2099 while ((s = strsep(&str, ","))) { 2100 if (!strcmp(s, "debug")) { 2101 sev_cfg.debug = true; 2102 continue; 2103 } 2104 2105 pr_info("SEV command-line option '%s' was not recognized\n", s); 2106 } 2107 2108 return 1; 2109 } 2110 __setup("sev=", init_sev_config); 2111 2112 int snp_issue_guest_request(u64 exit_code, struct snp_req_data *input, unsigned long *fw_err) 2113 { 2114 struct ghcb_state state; 2115 struct es_em_ctxt ctxt; 2116 unsigned long flags; 2117 struct ghcb *ghcb; 2118 int ret; 2119 2120 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 2121 return -ENODEV; 2122 2123 if (!fw_err) 2124 return -EINVAL; 2125 2126 /* 2127 * __sev_get_ghcb() needs to run with IRQs disabled because it is using 2128 * a per-CPU GHCB. 2129 */ 2130 local_irq_save(flags); 2131 2132 ghcb = __sev_get_ghcb(&state); 2133 if (!ghcb) { 2134 ret = -EIO; 2135 goto e_restore_irq; 2136 } 2137 2138 vc_ghcb_invalidate(ghcb); 2139 2140 if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST) { 2141 ghcb_set_rax(ghcb, input->data_gpa); 2142 ghcb_set_rbx(ghcb, input->data_npages); 2143 } 2144 2145 ret = sev_es_ghcb_hv_call(ghcb, true, &ctxt, exit_code, input->req_gpa, input->resp_gpa); 2146 if (ret) 2147 goto e_put; 2148 2149 if (ghcb->save.sw_exit_info_2) { 2150 /* Number of expected pages are returned in RBX */ 2151 if (exit_code == SVM_VMGEXIT_EXT_GUEST_REQUEST && 2152 ghcb->save.sw_exit_info_2 == SNP_GUEST_REQ_INVALID_LEN) 2153 input->data_npages = ghcb_get_rbx(ghcb); 2154 2155 *fw_err = ghcb->save.sw_exit_info_2; 2156 2157 ret = -EIO; 2158 } 2159 2160 e_put: 2161 __sev_put_ghcb(&state); 2162 e_restore_irq: 2163 local_irq_restore(flags); 2164 2165 return ret; 2166 } 2167 EXPORT_SYMBOL_GPL(snp_issue_guest_request); 2168 2169 static struct platform_device sev_guest_device = { 2170 .name = "sev-guest", 2171 .id = -1, 2172 }; 2173 2174 static u64 get_secrets_page(void) 2175 { 2176 u64 pa_data = boot_params.cc_blob_address; 2177 struct cc_blob_sev_info info; 2178 void *map; 2179 2180 /* 2181 * The CC blob contains the address of the secrets page, check if the 2182 * blob is present. 2183 */ 2184 if (!pa_data) 2185 return 0; 2186 2187 map = early_memremap(pa_data, sizeof(info)); 2188 memcpy(&info, map, sizeof(info)); 2189 early_memunmap(map, sizeof(info)); 2190 2191 /* smoke-test the secrets page passed */ 2192 if (!info.secrets_phys || info.secrets_len != PAGE_SIZE) 2193 return 0; 2194 2195 return info.secrets_phys; 2196 } 2197 2198 static int __init snp_init_platform_device(void) 2199 { 2200 struct sev_guest_platform_data data; 2201 u64 gpa; 2202 2203 if (!cc_platform_has(CC_ATTR_GUEST_SEV_SNP)) 2204 return -ENODEV; 2205 2206 gpa = get_secrets_page(); 2207 if (!gpa) 2208 return -ENODEV; 2209 2210 data.secrets_gpa = gpa; 2211 if (platform_device_add_data(&sev_guest_device, &data, sizeof(data))) 2212 return -ENODEV; 2213 2214 if (platform_device_register(&sev_guest_device)) 2215 return -ENODEV; 2216 2217 pr_info("SNP guest platform device initialized.\n"); 2218 return 0; 2219 } 2220 device_initcall(snp_init_platform_device); 2221