1 /* 2 * Copyright (C) 1995 Linus Torvalds 3 * 4 * Pentium III FXSR, SSE support 5 * Gareth Hughes <gareth@valinux.com>, May 2000 6 * 7 * X86-64 port 8 * Andi Kleen. 9 * 10 * CPU hotplug support - ashok.raj@intel.com 11 */ 12 13 /* 14 * This file handles the architecture-dependent parts of process handling.. 15 */ 16 17 #include <linux/cpu.h> 18 #include <linux/errno.h> 19 #include <linux/sched.h> 20 #include <linux/sched/task.h> 21 #include <linux/sched/task_stack.h> 22 #include <linux/fs.h> 23 #include <linux/kernel.h> 24 #include <linux/mm.h> 25 #include <linux/elfcore.h> 26 #include <linux/smp.h> 27 #include <linux/slab.h> 28 #include <linux/user.h> 29 #include <linux/interrupt.h> 30 #include <linux/delay.h> 31 #include <linux/export.h> 32 #include <linux/ptrace.h> 33 #include <linux/notifier.h> 34 #include <linux/kprobes.h> 35 #include <linux/kdebug.h> 36 #include <linux/prctl.h> 37 #include <linux/uaccess.h> 38 #include <linux/io.h> 39 #include <linux/ftrace.h> 40 #include <linux/syscalls.h> 41 42 #include <asm/pgtable.h> 43 #include <asm/processor.h> 44 #include <asm/fpu/internal.h> 45 #include <asm/mmu_context.h> 46 #include <asm/prctl.h> 47 #include <asm/desc.h> 48 #include <asm/proto.h> 49 #include <asm/ia32.h> 50 #include <asm/syscalls.h> 51 #include <asm/debugreg.h> 52 #include <asm/switch_to.h> 53 #include <asm/xen/hypervisor.h> 54 #include <asm/vdso.h> 55 #include <asm/intel_rdt_sched.h> 56 #include <asm/unistd.h> 57 #ifdef CONFIG_IA32_EMULATION 58 /* Not included via unistd.h */ 59 #include <asm/unistd_32_ia32.h> 60 #endif 61 62 __visible DEFINE_PER_CPU(unsigned long, rsp_scratch); 63 64 /* Prints also some state that isn't saved in the pt_regs */ 65 void __show_regs(struct pt_regs *regs, int all) 66 { 67 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L, fs, gs, shadowgs; 68 unsigned long d0, d1, d2, d3, d6, d7; 69 unsigned int fsindex, gsindex; 70 unsigned int ds, cs, es; 71 72 show_iret_regs(regs); 73 74 if (regs->orig_ax != -1) 75 pr_cont(" ORIG_RAX: %016lx\n", regs->orig_ax); 76 else 77 pr_cont("\n"); 78 79 printk(KERN_DEFAULT "RAX: %016lx RBX: %016lx RCX: %016lx\n", 80 regs->ax, regs->bx, regs->cx); 81 printk(KERN_DEFAULT "RDX: %016lx RSI: %016lx RDI: %016lx\n", 82 regs->dx, regs->si, regs->di); 83 printk(KERN_DEFAULT "RBP: %016lx R08: %016lx R09: %016lx\n", 84 regs->bp, regs->r8, regs->r9); 85 printk(KERN_DEFAULT "R10: %016lx R11: %016lx R12: %016lx\n", 86 regs->r10, regs->r11, regs->r12); 87 printk(KERN_DEFAULT "R13: %016lx R14: %016lx R15: %016lx\n", 88 regs->r13, regs->r14, regs->r15); 89 90 if (!all) 91 return; 92 93 asm("movl %%ds,%0" : "=r" (ds)); 94 asm("movl %%cs,%0" : "=r" (cs)); 95 asm("movl %%es,%0" : "=r" (es)); 96 asm("movl %%fs,%0" : "=r" (fsindex)); 97 asm("movl %%gs,%0" : "=r" (gsindex)); 98 99 rdmsrl(MSR_FS_BASE, fs); 100 rdmsrl(MSR_GS_BASE, gs); 101 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); 102 103 cr0 = read_cr0(); 104 cr2 = read_cr2(); 105 cr3 = __read_cr3(); 106 cr4 = __read_cr4(); 107 108 printk(KERN_DEFAULT "FS: %016lx(%04x) GS:%016lx(%04x) knlGS:%016lx\n", 109 fs, fsindex, gs, gsindex, shadowgs); 110 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds, 111 es, cr0); 112 printk(KERN_DEFAULT "CR2: %016lx CR3: %016lx CR4: %016lx\n", cr2, cr3, 113 cr4); 114 115 get_debugreg(d0, 0); 116 get_debugreg(d1, 1); 117 get_debugreg(d2, 2); 118 get_debugreg(d3, 3); 119 get_debugreg(d6, 6); 120 get_debugreg(d7, 7); 121 122 /* Only print out debug registers if they are in their non-default state. */ 123 if (!((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) && 124 (d6 == DR6_RESERVED) && (d7 == 0x400))) { 125 printk(KERN_DEFAULT "DR0: %016lx DR1: %016lx DR2: %016lx\n", 126 d0, d1, d2); 127 printk(KERN_DEFAULT "DR3: %016lx DR6: %016lx DR7: %016lx\n", 128 d3, d6, d7); 129 } 130 131 if (boot_cpu_has(X86_FEATURE_OSPKE)) 132 printk(KERN_DEFAULT "PKRU: %08x\n", read_pkru()); 133 } 134 135 void release_thread(struct task_struct *dead_task) 136 { 137 if (dead_task->mm) { 138 #ifdef CONFIG_MODIFY_LDT_SYSCALL 139 if (dead_task->mm->context.ldt) { 140 pr_warn("WARNING: dead process %s still has LDT? <%p/%d>\n", 141 dead_task->comm, 142 dead_task->mm->context.ldt->entries, 143 dead_task->mm->context.ldt->nr_entries); 144 BUG(); 145 } 146 #endif 147 } 148 } 149 150 enum which_selector { 151 FS, 152 GS 153 }; 154 155 /* 156 * Saves the FS or GS base for an outgoing thread if FSGSBASE extensions are 157 * not available. The goal is to be reasonably fast on non-FSGSBASE systems. 158 * It's forcibly inlined because it'll generate better code and this function 159 * is hot. 160 */ 161 static __always_inline void save_base_legacy(struct task_struct *prev_p, 162 unsigned short selector, 163 enum which_selector which) 164 { 165 if (likely(selector == 0)) { 166 /* 167 * On Intel (without X86_BUG_NULL_SEG), the segment base could 168 * be the pre-existing saved base or it could be zero. On AMD 169 * (with X86_BUG_NULL_SEG), the segment base could be almost 170 * anything. 171 * 172 * This branch is very hot (it's hit twice on almost every 173 * context switch between 64-bit programs), and avoiding 174 * the RDMSR helps a lot, so we just assume that whatever 175 * value is already saved is correct. This matches historical 176 * Linux behavior, so it won't break existing applications. 177 * 178 * To avoid leaking state, on non-X86_BUG_NULL_SEG CPUs, if we 179 * report that the base is zero, it needs to actually be zero: 180 * see the corresponding logic in load_seg_legacy. 181 */ 182 } else { 183 /* 184 * If the selector is 1, 2, or 3, then the base is zero on 185 * !X86_BUG_NULL_SEG CPUs and could be anything on 186 * X86_BUG_NULL_SEG CPUs. In the latter case, Linux 187 * has never attempted to preserve the base across context 188 * switches. 189 * 190 * If selector > 3, then it refers to a real segment, and 191 * saving the base isn't necessary. 192 */ 193 if (which == FS) 194 prev_p->thread.fsbase = 0; 195 else 196 prev_p->thread.gsbase = 0; 197 } 198 } 199 200 static __always_inline void save_fsgs(struct task_struct *task) 201 { 202 savesegment(fs, task->thread.fsindex); 203 savesegment(gs, task->thread.gsindex); 204 save_base_legacy(task, task->thread.fsindex, FS); 205 save_base_legacy(task, task->thread.gsindex, GS); 206 } 207 208 static __always_inline void loadseg(enum which_selector which, 209 unsigned short sel) 210 { 211 if (which == FS) 212 loadsegment(fs, sel); 213 else 214 load_gs_index(sel); 215 } 216 217 static __always_inline void load_seg_legacy(unsigned short prev_index, 218 unsigned long prev_base, 219 unsigned short next_index, 220 unsigned long next_base, 221 enum which_selector which) 222 { 223 if (likely(next_index <= 3)) { 224 /* 225 * The next task is using 64-bit TLS, is not using this 226 * segment at all, or is having fun with arcane CPU features. 227 */ 228 if (next_base == 0) { 229 /* 230 * Nasty case: on AMD CPUs, we need to forcibly zero 231 * the base. 232 */ 233 if (static_cpu_has_bug(X86_BUG_NULL_SEG)) { 234 loadseg(which, __USER_DS); 235 loadseg(which, next_index); 236 } else { 237 /* 238 * We could try to exhaustively detect cases 239 * under which we can skip the segment load, 240 * but there's really only one case that matters 241 * for performance: if both the previous and 242 * next states are fully zeroed, we can skip 243 * the load. 244 * 245 * (This assumes that prev_base == 0 has no 246 * false positives. This is the case on 247 * Intel-style CPUs.) 248 */ 249 if (likely(prev_index | next_index | prev_base)) 250 loadseg(which, next_index); 251 } 252 } else { 253 if (prev_index != next_index) 254 loadseg(which, next_index); 255 wrmsrl(which == FS ? MSR_FS_BASE : MSR_KERNEL_GS_BASE, 256 next_base); 257 } 258 } else { 259 /* 260 * The next task is using a real segment. Loading the selector 261 * is sufficient. 262 */ 263 loadseg(which, next_index); 264 } 265 } 266 267 int copy_thread_tls(unsigned long clone_flags, unsigned long sp, 268 unsigned long arg, struct task_struct *p, unsigned long tls) 269 { 270 int err; 271 struct pt_regs *childregs; 272 struct fork_frame *fork_frame; 273 struct inactive_task_frame *frame; 274 struct task_struct *me = current; 275 276 childregs = task_pt_regs(p); 277 fork_frame = container_of(childregs, struct fork_frame, regs); 278 frame = &fork_frame->frame; 279 frame->bp = 0; 280 frame->ret_addr = (unsigned long) ret_from_fork; 281 p->thread.sp = (unsigned long) fork_frame; 282 p->thread.io_bitmap_ptr = NULL; 283 284 savesegment(gs, p->thread.gsindex); 285 p->thread.gsbase = p->thread.gsindex ? 0 : me->thread.gsbase; 286 savesegment(fs, p->thread.fsindex); 287 p->thread.fsbase = p->thread.fsindex ? 0 : me->thread.fsbase; 288 savesegment(es, p->thread.es); 289 savesegment(ds, p->thread.ds); 290 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps)); 291 292 if (unlikely(p->flags & PF_KTHREAD)) { 293 /* kernel thread */ 294 memset(childregs, 0, sizeof(struct pt_regs)); 295 frame->bx = sp; /* function */ 296 frame->r12 = arg; 297 return 0; 298 } 299 frame->bx = 0; 300 *childregs = *current_pt_regs(); 301 302 childregs->ax = 0; 303 if (sp) 304 childregs->sp = sp; 305 306 err = -ENOMEM; 307 if (unlikely(test_tsk_thread_flag(me, TIF_IO_BITMAP))) { 308 p->thread.io_bitmap_ptr = kmemdup(me->thread.io_bitmap_ptr, 309 IO_BITMAP_BYTES, GFP_KERNEL); 310 if (!p->thread.io_bitmap_ptr) { 311 p->thread.io_bitmap_max = 0; 312 return -ENOMEM; 313 } 314 set_tsk_thread_flag(p, TIF_IO_BITMAP); 315 } 316 317 /* 318 * Set a new TLS for the child thread? 319 */ 320 if (clone_flags & CLONE_SETTLS) { 321 #ifdef CONFIG_IA32_EMULATION 322 if (in_ia32_syscall()) 323 err = do_set_thread_area(p, -1, 324 (struct user_desc __user *)tls, 0); 325 else 326 #endif 327 err = do_arch_prctl_64(p, ARCH_SET_FS, tls); 328 if (err) 329 goto out; 330 } 331 err = 0; 332 out: 333 if (err && p->thread.io_bitmap_ptr) { 334 kfree(p->thread.io_bitmap_ptr); 335 p->thread.io_bitmap_max = 0; 336 } 337 338 return err; 339 } 340 341 static void 342 start_thread_common(struct pt_regs *regs, unsigned long new_ip, 343 unsigned long new_sp, 344 unsigned int _cs, unsigned int _ss, unsigned int _ds) 345 { 346 WARN_ON_ONCE(regs != current_pt_regs()); 347 348 if (static_cpu_has(X86_BUG_NULL_SEG)) { 349 /* Loading zero below won't clear the base. */ 350 loadsegment(fs, __USER_DS); 351 load_gs_index(__USER_DS); 352 } 353 354 loadsegment(fs, 0); 355 loadsegment(es, _ds); 356 loadsegment(ds, _ds); 357 load_gs_index(0); 358 359 regs->ip = new_ip; 360 regs->sp = new_sp; 361 regs->cs = _cs; 362 regs->ss = _ss; 363 regs->flags = X86_EFLAGS_IF; 364 force_iret(); 365 } 366 367 void 368 start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp) 369 { 370 start_thread_common(regs, new_ip, new_sp, 371 __USER_CS, __USER_DS, 0); 372 } 373 374 #ifdef CONFIG_COMPAT 375 void compat_start_thread(struct pt_regs *regs, u32 new_ip, u32 new_sp) 376 { 377 start_thread_common(regs, new_ip, new_sp, 378 test_thread_flag(TIF_X32) 379 ? __USER_CS : __USER32_CS, 380 __USER_DS, __USER_DS); 381 } 382 #endif 383 384 /* 385 * switch_to(x,y) should switch tasks from x to y. 386 * 387 * This could still be optimized: 388 * - fold all the options into a flag word and test it with a single test. 389 * - could test fs/gs bitsliced 390 * 391 * Kprobes not supported here. Set the probe on schedule instead. 392 * Function graph tracer not supported too. 393 */ 394 __visible __notrace_funcgraph struct task_struct * 395 __switch_to(struct task_struct *prev_p, struct task_struct *next_p) 396 { 397 struct thread_struct *prev = &prev_p->thread; 398 struct thread_struct *next = &next_p->thread; 399 struct fpu *prev_fpu = &prev->fpu; 400 struct fpu *next_fpu = &next->fpu; 401 int cpu = smp_processor_id(); 402 struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu); 403 404 WARN_ON_ONCE(IS_ENABLED(CONFIG_DEBUG_ENTRY) && 405 this_cpu_read(irq_count) != -1); 406 407 switch_fpu_prepare(prev_fpu, cpu); 408 409 /* We must save %fs and %gs before load_TLS() because 410 * %fs and %gs may be cleared by load_TLS(). 411 * 412 * (e.g. xen_load_tls()) 413 */ 414 save_fsgs(prev_p); 415 416 /* 417 * Load TLS before restoring any segments so that segment loads 418 * reference the correct GDT entries. 419 */ 420 load_TLS(next, cpu); 421 422 /* 423 * Leave lazy mode, flushing any hypercalls made here. This 424 * must be done after loading TLS entries in the GDT but before 425 * loading segments that might reference them, and and it must 426 * be done before fpu__restore(), so the TS bit is up to 427 * date. 428 */ 429 arch_end_context_switch(next_p); 430 431 /* Switch DS and ES. 432 * 433 * Reading them only returns the selectors, but writing them (if 434 * nonzero) loads the full descriptor from the GDT or LDT. The 435 * LDT for next is loaded in switch_mm, and the GDT is loaded 436 * above. 437 * 438 * We therefore need to write new values to the segment 439 * registers on every context switch unless both the new and old 440 * values are zero. 441 * 442 * Note that we don't need to do anything for CS and SS, as 443 * those are saved and restored as part of pt_regs. 444 */ 445 savesegment(es, prev->es); 446 if (unlikely(next->es | prev->es)) 447 loadsegment(es, next->es); 448 449 savesegment(ds, prev->ds); 450 if (unlikely(next->ds | prev->ds)) 451 loadsegment(ds, next->ds); 452 453 load_seg_legacy(prev->fsindex, prev->fsbase, 454 next->fsindex, next->fsbase, FS); 455 load_seg_legacy(prev->gsindex, prev->gsbase, 456 next->gsindex, next->gsbase, GS); 457 458 switch_fpu_finish(next_fpu, cpu); 459 460 /* 461 * Switch the PDA and FPU contexts. 462 */ 463 this_cpu_write(current_task, next_p); 464 this_cpu_write(cpu_current_top_of_stack, task_top_of_stack(next_p)); 465 466 /* Reload sp0. */ 467 update_sp0(next_p); 468 469 /* 470 * Now maybe reload the debug registers and handle I/O bitmaps 471 */ 472 if (unlikely(task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT || 473 task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV)) 474 __switch_to_xtra(prev_p, next_p, tss); 475 476 #ifdef CONFIG_XEN_PV 477 /* 478 * On Xen PV, IOPL bits in pt_regs->flags have no effect, and 479 * current_pt_regs()->flags may not match the current task's 480 * intended IOPL. We need to switch it manually. 481 */ 482 if (unlikely(static_cpu_has(X86_FEATURE_XENPV) && 483 prev->iopl != next->iopl)) 484 xen_set_iopl_mask(next->iopl); 485 #endif 486 487 if (static_cpu_has_bug(X86_BUG_SYSRET_SS_ATTRS)) { 488 /* 489 * AMD CPUs have a misfeature: SYSRET sets the SS selector but 490 * does not update the cached descriptor. As a result, if we 491 * do SYSRET while SS is NULL, we'll end up in user mode with 492 * SS apparently equal to __USER_DS but actually unusable. 493 * 494 * The straightforward workaround would be to fix it up just 495 * before SYSRET, but that would slow down the system call 496 * fast paths. Instead, we ensure that SS is never NULL in 497 * system call context. We do this by replacing NULL SS 498 * selectors at every context switch. SYSCALL sets up a valid 499 * SS, so the only way to get NULL is to re-enter the kernel 500 * from CPL 3 through an interrupt. Since that can't happen 501 * in the same task as a running syscall, we are guaranteed to 502 * context switch between every interrupt vector entry and a 503 * subsequent SYSRET. 504 * 505 * We read SS first because SS reads are much faster than 506 * writes. Out of caution, we force SS to __KERNEL_DS even if 507 * it previously had a different non-NULL value. 508 */ 509 unsigned short ss_sel; 510 savesegment(ss, ss_sel); 511 if (ss_sel != __KERNEL_DS) 512 loadsegment(ss, __KERNEL_DS); 513 } 514 515 /* Load the Intel cache allocation PQR MSR. */ 516 intel_rdt_sched_in(); 517 518 return prev_p; 519 } 520 521 void set_personality_64bit(void) 522 { 523 /* inherit personality from parent */ 524 525 /* Make sure to be in 64bit mode */ 526 clear_thread_flag(TIF_IA32); 527 clear_thread_flag(TIF_ADDR32); 528 clear_thread_flag(TIF_X32); 529 /* Pretend that this comes from a 64bit execve */ 530 task_pt_regs(current)->orig_ax = __NR_execve; 531 532 /* Ensure the corresponding mm is not marked. */ 533 if (current->mm) 534 current->mm->context.ia32_compat = 0; 535 536 /* TBD: overwrites user setup. Should have two bits. 537 But 64bit processes have always behaved this way, 538 so it's not too bad. The main problem is just that 539 32bit childs are affected again. */ 540 current->personality &= ~READ_IMPLIES_EXEC; 541 } 542 543 static void __set_personality_x32(void) 544 { 545 #ifdef CONFIG_X86_X32 546 clear_thread_flag(TIF_IA32); 547 set_thread_flag(TIF_X32); 548 if (current->mm) 549 current->mm->context.ia32_compat = TIF_X32; 550 current->personality &= ~READ_IMPLIES_EXEC; 551 /* 552 * in_compat_syscall() uses the presence of the x32 syscall bit 553 * flag to determine compat status. The x86 mmap() code relies on 554 * the syscall bitness so set x32 syscall bit right here to make 555 * in_compat_syscall() work during exec(). 556 * 557 * Pretend to come from a x32 execve. 558 */ 559 task_pt_regs(current)->orig_ax = __NR_x32_execve | __X32_SYSCALL_BIT; 560 current->thread.status &= ~TS_COMPAT; 561 #endif 562 } 563 564 static void __set_personality_ia32(void) 565 { 566 #ifdef CONFIG_IA32_EMULATION 567 set_thread_flag(TIF_IA32); 568 clear_thread_flag(TIF_X32); 569 if (current->mm) 570 current->mm->context.ia32_compat = TIF_IA32; 571 current->personality |= force_personality32; 572 /* Prepare the first "return" to user space */ 573 task_pt_regs(current)->orig_ax = __NR_ia32_execve; 574 current->thread.status |= TS_COMPAT; 575 #endif 576 } 577 578 void set_personality_ia32(bool x32) 579 { 580 /* Make sure to be in 32bit mode */ 581 set_thread_flag(TIF_ADDR32); 582 583 if (x32) 584 __set_personality_x32(); 585 else 586 __set_personality_ia32(); 587 } 588 EXPORT_SYMBOL_GPL(set_personality_ia32); 589 590 #ifdef CONFIG_CHECKPOINT_RESTORE 591 static long prctl_map_vdso(const struct vdso_image *image, unsigned long addr) 592 { 593 int ret; 594 595 ret = map_vdso_once(image, addr); 596 if (ret) 597 return ret; 598 599 return (long)image->size; 600 } 601 #endif 602 603 long do_arch_prctl_64(struct task_struct *task, int option, unsigned long arg2) 604 { 605 int ret = 0; 606 int doit = task == current; 607 int cpu; 608 609 switch (option) { 610 case ARCH_SET_GS: 611 if (arg2 >= TASK_SIZE_MAX) 612 return -EPERM; 613 cpu = get_cpu(); 614 task->thread.gsindex = 0; 615 task->thread.gsbase = arg2; 616 if (doit) { 617 load_gs_index(0); 618 ret = wrmsrl_safe(MSR_KERNEL_GS_BASE, arg2); 619 } 620 put_cpu(); 621 break; 622 case ARCH_SET_FS: 623 /* Not strictly needed for fs, but do it for symmetry 624 with gs */ 625 if (arg2 >= TASK_SIZE_MAX) 626 return -EPERM; 627 cpu = get_cpu(); 628 task->thread.fsindex = 0; 629 task->thread.fsbase = arg2; 630 if (doit) { 631 /* set the selector to 0 to not confuse __switch_to */ 632 loadsegment(fs, 0); 633 ret = wrmsrl_safe(MSR_FS_BASE, arg2); 634 } 635 put_cpu(); 636 break; 637 case ARCH_GET_FS: { 638 unsigned long base; 639 640 if (doit) 641 rdmsrl(MSR_FS_BASE, base); 642 else 643 base = task->thread.fsbase; 644 ret = put_user(base, (unsigned long __user *)arg2); 645 break; 646 } 647 case ARCH_GET_GS: { 648 unsigned long base; 649 650 if (doit) 651 rdmsrl(MSR_KERNEL_GS_BASE, base); 652 else 653 base = task->thread.gsbase; 654 ret = put_user(base, (unsigned long __user *)arg2); 655 break; 656 } 657 658 #ifdef CONFIG_CHECKPOINT_RESTORE 659 # ifdef CONFIG_X86_X32_ABI 660 case ARCH_MAP_VDSO_X32: 661 return prctl_map_vdso(&vdso_image_x32, arg2); 662 # endif 663 # if defined CONFIG_X86_32 || defined CONFIG_IA32_EMULATION 664 case ARCH_MAP_VDSO_32: 665 return prctl_map_vdso(&vdso_image_32, arg2); 666 # endif 667 case ARCH_MAP_VDSO_64: 668 return prctl_map_vdso(&vdso_image_64, arg2); 669 #endif 670 671 default: 672 ret = -EINVAL; 673 break; 674 } 675 676 return ret; 677 } 678 679 SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2) 680 { 681 long ret; 682 683 ret = do_arch_prctl_64(current, option, arg2); 684 if (ret == -EINVAL) 685 ret = do_arch_prctl_common(current, option, arg2); 686 687 return ret; 688 } 689 690 #ifdef CONFIG_IA32_EMULATION 691 COMPAT_SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2) 692 { 693 return do_arch_prctl_common(current, option, arg2); 694 } 695 #endif 696 697 unsigned long KSTK_ESP(struct task_struct *task) 698 { 699 return task_pt_regs(task)->sp; 700 } 701